AND8112/D
A Quasi−Resonant SPICE
Model Eases Feedback
Loop Designs
Prepared by: Christophe Basso
Prepared by: Joel Turchi
ON Semiconductor
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Within the wide family of Switch Mode Power Supplies
(SMPS), the Flyback converters represent the structure of
choice for use in small and medium power applications. For
compact designs and radio−frequency sensitive
applications, e.g. TV sets or set−top boxes, Quasi− Resonant
power supplies start to take a significant market share over
the traditional fixed frequency topology. However, if the
feedback loop control is well understood with this latter, for
instance via a comprehensive literature and SPICE models,
the situation differs for self−oscillating variable switching
frequency structures where no model still exists. This article
will show how a simple large−signal averaged SPICE model
can be derived and used to ease the design work during
stability analysis.
Leakage Inductance
Plateau:
(Vout + Vf)/N
Vin
ON
SON LP
Figure 1. A Typical FLYBACK Drain−Source
Waveform
Ipeak
Soff = (V + Vf) / (LP x N)
Son = Vg/LP
ON
(V Vf)
N LP
October, 2003 − Rev. 1
IP = 0, Reset
0
Figure 2. The Primary Current Ramps Up and Down
to Zero in DCM
When the primary current reaches zero, the transformer
core is fully demagnetized: we are in Discontinuous
Conduction Mode (DCM). The primary inductance LP
together with all the surrounding capacitive elements Ctot
create a LC filter. When the secondary diode stops conducting
at IP = 0, the drain branch is left floating since the MOSFET
is already open. As a result, a natural oscillation occurs,
exhibiting the following frequency value:
(eq. 2)
Figure 2 zooms on the simulated primary current (actually
circulating in the magnetizing inductor), showing how it
moves over one switching cycle.
Semiconductor Components Industries, LLC, 2003
OFF
(eq. 1)
When the controller instructs the switch opening, the
drain−source quickly rises and the energy transfer between
primary and secondary takes place: the secondary diode
conducts and the output voltage flies back on the primary
side, over LP. This “Flyback” plateau is equal to Vg + (V +
Vf) / N, where N is the secondary to primary turn ratio, V the
output voltage and Vf the diode forward voltage drop.
During this time, the primary current decreases with a slope
now imposed by the reflected voltage
SOFF OFF
Valleys
Quasi−Resonant Operation
It is difficult to abruptly dig into the analytical analysis
without giving a basic idea of the operation of a converter
working in Quasi−Resonance (QR). Figure 1 depicts a
typical FLYBACK converter drain−source waveform as you
probably have already observed. When the switch is closed,
the drain−source voltage VDS is near 0 V and the input
voltage Vg appears across the primary inductance LP: the
current inside LP ramps up with a slope of
Vg
Core is Reset
Fring 1
1
2 LP Ctot
(eq. 3)
Publication Order Number:
AND8112/D
AND8112/D
As in any sinusoidal signal, there are peaks and valleys. When you re−start the switch in one valley, where the voltage is
minimum, the MOSFET is no longer the seat of heavy turn−on losses engendered by capacitive effects: this is the so−called
Quasi−Resonance operation where the switching frequency depends on the peak current, the various slopes ON and OFF and
the number of valleys you choose after the core reset. In our study, we will first concentrate on a simplified SPICE version where
the power switch is actuated right after the reset detection point (parasitic ringings are neglected) and later on, a more
sophisticated declination will incorporate parasitic delays.
Modeling the Switch Network
Figure 3 depicts a Flyback topology where the switching
elements generating the above waveforms have been
highlighted: the power switch (usually a MOSFET
transistor) and a diode, performing a rectification job.
During the converter operation, the Pulse Width Modulator
controller (PWM) instructs the transistor to turn ON, in
order to store energy in the primary side. The primary
current builds up until the setpoint imposed by the feedback
loop is reached. At this time, the controller toggles the
transistor to the OFF state and energy transfers to the
secondary side. If the ON and OFF states can be described
by a set of linear equations, there exists a discontinuity
linking these two events. Despite the presence of linear
elements in the converter (capacitors, inductors and
resistors), the presence of the commuting switch clearly
introduces the non−linearity that prevents us from directly
writing the small−signal equations…
When learning electronic circuits at school, there were
some exercises in which we were asked to reveal the transfer
function of bipolar amplifiers. At that time, we learned to
replace the transistor symbol by its equivalent small−signal
model: the schematic turned into the simple association of
current and voltage sources that greatly simplified the
analysis. In the average circuit modeling technique, we also
follow the same philosophy: the exercise lies in isolating and
replacing the switch network with a set of current and
voltage sources whose electrical architecture do not vary
with time. Therefore, plugging the equivalent model back
into the converter of interest allows us to resolve its transfer
characteristics.
IL(t)
IP
IL(t)
Vg
LP
V
N LP
IP
I1(t)
(V(LP)
Vg
Vg
LP
I2(t)
V1(t)
IP/N
V
N 2 LP
V
N
V
Vg
N
d TS
V2(t)
N Vg V
d TS
TS
Figure 4. and Individual Signals Separately Plotted.
Deriving Equations
The object of deriving a model consists in writing the
equations that describe the switch network averaged input
and output quantities that a) depend from each other b) obey
to the control input. Let us draw the various waveforms
before starting any line of algebra (Figure 4). From this
picture, we can develop equations that will finally describe
the averaged evolution of the values of interest, the input /
output voltage and current of our switch network:
I
I1(t) P d
2
1:N
I2(t) 1
V1(t) Vg
I2(t)
I1(t)
a
d
2
V2(t)
s
k
5
C
Control
R
V N Vg
(eq. 5)
d
(eq. 6)
V2(t) [V N Vg] d
(eq. 7)
N
where: V is the output voltage, Vg the input voltage, IP the
primary peak current, N the NS / NP turn ratio and d the
duty−cycle (d′ = 1 –d).
Please note that in this first approach, we do not consider
any delay occurring at the switch opening or induced by
equation 3. These events will considered later on, in a more
complex model.
3
V1(t)
(eq. 4)
IP
d
2N
LP
+
TS
V(t)
Figure 3. A Flyback Power Supply where Switches
have been Isolated
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AND8112/D
Averaging Input / Output Voltages
From the inductor volt−second balance approximation, we know that the average voltage across an inductor operated in a
steady−state converter is null. By looking at the V(LP) sketch, we obtain the following equation:
V(LP) d(t) Vg(t) d(t) V(t) (1 d(t)) V(t) d(t) Vg(t) 0
N
N
(eq. 8)
which lets us extract the classical output / input voltage ratio
d(t)
V(t) N
(1 d(t))
Vg(t) (eq. 9)
and as a result, the duty−cycle expression:
d(t) V
V(t) (t) N Vg(t) (eq. 10)
Now, by plugging equation 10 in equation 6, we obtain the average voltage across the primary switch terminal: <V1(t)> =
V(t) N Vg(t) N
(1 d(t)) V(t) N Vg(t) N
1
(eq. 11)
V(t) Vg(t) V(t) N Vg(t) which agrees with the inductor volt−second balance approximation (from Figure 1 since, by definition, <V(LP)> = 0, then Vg
appears across the switch terminals).
To reveal <V2(t)>, let us plug equation 10 into 7: <V2(t)> =
[ V(t) N Vg(t) ] d(t) [ V(t) N Vg(t) ] V(t) V(t) V(t) N Vg(t) (eq. 12)
which again could be deduced from Figure 3 since the average voltage across the secondary inductance is zero…
Averaging Input / Output Currents
The peak inductor current depends on the time during
which Vg is applied over LP. If we recall that this time
(actually ton ) is d x TS, then:
Vg
IP d TS
LP
TS
I2(t) 1
TS
I2(t) d.TS
Vg(t) d(t) (1 d(t)) TS
2 N LP
V1(t) d(t) (1 d(t)) TS
2 N LP
d(t) TS d(t) LP
(eq. 14)
Vg(t) d(t) 2 TS
(eq. 17)
A 100% Efficiency Power Transfer…
Assuming that 100% of the primary stored energy is
released to the secondary side, then we can use equations 11
and 12 to write:
2 LP
however, from equation 11, we know that <V1(t)> = <Vg(t)>
thus equation 14 turns into:
V1(t) d(t) 2 TS
2 LP
(eq. 16)
plugging equation 13 in 16 leads to:
Vg(t) I1(t) I
I2(t) dt 1 P d(t)
2
N
(eq. 13)
From Figure 4, the average current <I1(t)> can be obtained
by evaluating the triangular area (charge in Coulomb) and
dividing by the switching period. This is expressed by
equation 4. Now plugging equation 13 in 4, we obtain:
I1(t) 1 2
<P(t)> = <V1(t)> X <I1(t)> = <V2(t)> X <I2(t)>
(eq. 18)
From equation 15, we can see that a current is generated
by a voltage multiplied by a term. This term is obviously
homogenous to the inverse of an impedance. By
re−arranging equation 15, we obtain:
(eq. 15)
Applying the same technique to the secondary current
I2(t), leads to:
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AND8112/D
Re(d) V1(t) 2 LP
I1(t) d(t) 2 TS
Our switch network can thus modeled according to the
so−called loss−free network where all the power developed
across an input resistance transfers to the output without any
loss (Figure 6) [1].
(eq. 19)
where the input impedance depends on the duty−cycle d(t).
However, in quasi−resonant converters, the power transfer
adjusts by varying the peak current IP which finally imposes
the operating frequency. Since by definition ton = d x TS, we
can re−arrange equation 9 to reveal
TS ton (N Vg) V
V
A More Complex Model Including Parasitic Effects
The above simplified model assumes that there are no
transient times between the conduction and
demagnetization phases. A more precise modelling
approach requires that the two following delays t1 and t2
are taken into account, as highlighted by Figure 7 and 8:
(eq. 20)
By finally plugging equation 10 and 20 into 19, we obtain
a ton −dependent input effective resistance definition:
Re(ton) 2 LP (V N Vg)
ton V
Core Is Reset!
(eq. 21)
that Figure 5 portrays:
<I1(t)>
Re(ton)
<V1(t)>
t1
t2
Figure 5.
Figure 7.
The average input waveforms of the switch can be modeled via
the above equivalent network.
The presence of a capacitive node slows−down the VDS rising
and makes the drain sinusoidally ring at the core reset…
<I1(t)>
<I2(t)>
1. At the end of the ON−time, the power switch
opens but the energy transfer to the secondary side
does not start immediately. The primary inductor
current (IP) that cannot flow through the power
switch, charges the surrounding capacitive
elements (Ctot) until Ctot voltage exceeds
<P(t)>
<V1(t)>
Re(ton)
<V2(t)>
Vg V
N
Figure 6.
At that moment, the secondary diode starts to
conduct and current feeds the output capacitor. One
can assume that the Ctot charging time (t1) is short
enough to consider that the primary inductor current
stays equal to IP during this interval. Then, t1 is the
time necessary to charge the capacitor Ctot with a
current IP from zero to
The two−port loss−free network where all the input power transforms into output power.
As reference [1] details, the apparent power consumed by
Re, Pin, is entirely transmitted to the output since we assume
a 100% efficiency. Therefore, equation 19 can be re−written
by:
P(t) V1(t) I1(t) V1(t) 2
V2(t) I2(t) Re(ton)
(eq. 23)
Vg V
N
(eq. 22)
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, i.e.: t1 Ctot Vg NV
IP
(eq. 24)
AND8112/D
D1
Vg
V
+
Vg
1
8
2
7
3
6
4
5
Cout
<=>
Ctot
Ctot
NCP1207
Figure 8.
When the power switch turns off, the primary inductor behaves like a current source that charges the Ctot capacitor. This sequence ends
when voltage developed across Ctot exceeds [Vg+(V+Vf)/N], that is when the secondary diode D1 starts to conduct.
replacing d′(t) by its novel value as expressed by
equation (27):
2. At the end of the core reset, both switches (power
switch and secondary diode) are off. The primary
inductor LP together with Ctot form a LC network.
Ctot voltage (and thus the drain source voltage of
the power switch) oscillates around the input
voltage Vg between a peak value (the initial level:
V(LP) d Vg d
effects being neglected. To benefit from the quasi−
resonant mode, it is recommended to turn the power
switch on in the valley, where the drain−source
voltage is minimized. This naturally reduces the
dV/dt and switching losses to a minimum (in
practice, an appropriate delay inserted after the core
reset detection provides an effective method to
synchronize the power switch turn on with the valley
event). A simple look at Figure 7 shows that the
valley occurs at half the oscillation period.
Therefore, the delay t2 between the core reset
completion and the optimal turn on time is given by
the following equation:
N
Vg ton
S
(eq. 29)
(N Vg) V
(eq. 30)
The time tdemag can be easily deducted from the Figure 4
sketch. Since the core reset is the time necessary to discharge
the primary inductor from IP to zero with a (V+Vf)/N slope,
it comes:
N Vg
L IP
tdemag P
ton
V
VN
(eq. 31)
Substitution of equation (31) into (eq. 30), leads to the
following expression where TS is a function of ton :
TS t1 t2 [(N Vg) V] ton
N
(eq. 32)
Equation (15) that defines the average input current as a
function of the input voltage, the duty cycle, the inductor
value and the switching period, still holds. Substitution of
equation (29) into equation (15) leads to:
I1(t) (eq. 26)
Vg 1 V ton
2 LP [(N Vg) V]
t1t2
TS
(eq. 33)
Replacing TS by its equation 32 expression, it comes:
If (d′ x TS) depicts the core reset time, t1 and t2 times
require to change (d′=1−d) into:
t2
d 1 d t1
TS
1 t1Tt2 V
TS ton tdemag t1 t2
Once these delays are defined, it is about time to revise the
previous equations in order to include t1 and t2 effects.
The main parameters of interest are the average input and
output currents, the equivalent resistance and the switching
period. If we combine equations 24 and 13 that express IP as
a function of the input voltage, the inductor value and the
ON−time leads to:
t1 LP Ctot N
(eq. 28)
0
The switching period is the sum of the on−time, the core
reset time (tdemag), t1 and t2:
(eq. 25)
Vg V
S
Re−arranging equation (28), one can unveil the duty cycle
expression:
Vg V ) and a valley value Vg V , the damping
N
N
t2 LP Ctot
1 d t1Tt2 V
Vg (eq. 27)
I1(t) The inductor volt−second balance approximation of
equation 8 still holds. However, it must be revised by
1
t1t2
t1t2
(NVg)Vton
V
5
V ton
2 LP [(N Vg) V]
Re−arranging this equation, one can obtain:
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(eq. 34)
AND8112/D
(eq. 35)
I1(t) Vg ton 2
2 LP t1 t2 (NVg)Vton
V
Substitution of equation (32) giving TS into equation (37),
leads to: <I2(t)> =
Vg ton
2 LP
Similarly to the simplified model analysis, one can note
that the average input current is proportional to the input
voltage. The effective resistance Re is thus: Re(ton) =
[(N Vg) V] ton
2 LP
t1 t2 2
V
ton
ton
t1 t2 (NVg)Vton
Vg
V
(eq. 38)
V
This expression can be simplified as follows: <I2(t)> =
Vg
Vg
Vg
I1(t) Re(ton) V Vf
V Vf
(eq. 36)
(eq. 39)
The model assumes a 100% efficiency power transfer. To
better stick to reality, the above expression should be
multiplied by the estimated efficiency to obtain the final
<I2(t)> equation:
It is pleasant to confirm that if t1=t2=0, the Re(ton )
expression reduces to equation 21…
Then, the equivalent circuit depicted in Figure 6 and based
on the loss−free resistor Re(ton ) can be applied. To complete
the model, let’s calculate <I2(t)> by combining equations
(17) where d′ is taken equal to (tdemag/TS), (13) and (31):
Vg ton ton N Vg
I2(t) 1 2 LP
V
N
TS
I2(t) I1(t) where eff is the efficiency.
(eq. 37)
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Vg
V Vf
eff
(eq. 40)
AND8112/D
The following table summarizes the main equations upon which our model is based:
Delay between the power switch opening and the start of the energy transfer to secondary side:
t1 LP Ctot t2 LP Ctot
Delay between the core reset completion and the next turn on of
the power switch (Note 1):
[(N Vg) V] ton
2 LP
Re(ton) t1 t2 V
ton 2
Equivalent input resistance:
Switching Frequency:
fSW 1
t1 t2 (NVg)Vton
V
I1(t) VgRe(ton)
Average input current:
Average output current:
I2(t) NOTE: : even if the proposed value appears to us as the
optimal one, SMPS designers might make a
different choice for t2. That is why, if the model
Et I1 Gd
I1(t) eff
2 LP (V N Vg)
ton V
(eq. 41)
(eq. 42)
Rin(eq) i1 2
2 LP (V N Vg) i1 2
I2 v2
v2
ton V
Also, one can introduce the efficiency by simply
multiplying the I2 current source by {eff}, where eff is a
parameter entered by the user in the model. Hence, I2 can be
written as:
I2 I2
Et
V
where ton is an input port of the model, imposed by the
control loop. In the final model, this value will be derived
from LP and the peak current given by the error voltage
divided by Rsense, where V, Vg and N are to be passed or
sensed by the model.
The output current source together with V2 shall deliver
the output power as imposed by equation 22. Thus, i2
generation shall follow:
Implementing the SPICE Model with the
Loss−Free Network
As exemplified by Figure 6, the model shall emulate an
input resistor being ton dependent and then transmit a power
following equation 23. Different ways exist to implement
this topology in Spice. INTUSOFT’s IsSpice authorizes
behavioral resistors, e.g. following any particular ohmic
evolution with time, voltage, current etc. For instance, the
following code would be accepted by the simulator:
R1 1 2 R = 2.0 * v(1)^0.5 + 3.0*v(2)*time + v(2)*sqrt(temp)
Unfortunately, despite its obvious interest, this code is not
very portable and would constrain the model usage to
IsSpice only. Figure 9 offers a more practical association
using behavioral voltage and current sources [2]:
I1
Vg
The input voltage source being supposed to emulate a
resistance, its expression shall be in the form of:
Et = I1 x Re where Re is simply equation 22, thus:
proposes t2 LP Ctot as default
value, you can modify this simulation parameter
to stick to your application in case valley
switching is not considered.
V1
Vg NV
Vg ton
2 LP (V N Vg)
V2
Figure 9. Implementing the DCM Model via Two
Controlled Elements
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ton V
i 2
1 eff
v2
(eq. 43)
AND8112/D
Operating Parameter Calculation
ton
errint
FB
R9
1 Meg
System Parameter calculation
toff
IP
BIp
Voltage
V(ton)*V(13)/{Lp}
1
1
VI1
7
Bton
Voltage
V(errint)*{Lp}/({Rs}*V(13))
B8
Voltage
V(FB)/3 > 1 ? 1 : V(FB)/3 < 10 m
? 10m : V(FB)/3
Bclamp
Current
I(VI1)>0 ?
I(VI1) :
0
13
Lm
{Lp}
Bfreq
Voltage
(1/(V(ton)+V(toff)))/1 k
12
Rs
{Rlf}
3
1
3
4
V6
BGd
Current
(((2*{Lp}*(V(3)+{N}*V(13))/(V(ton)*V(3)+1u))*I(V6)^2)/(V(3,4)+1u))*{eff}
BEt
Voltage
(2*{Lp}*(V(3)+{N}*V(13))/(V(ton)*V(3)+1u))*I(V6)
Gnd
13
FSW
BToff
Voltage
{Lp}*V(Ip)*{N}/V(3)
20
X2
XFMR
RATIO = N
4
4
Figure 10. The final simplified model implementation where added sources reveal operating parameters
such as Ton, FSW and the peak current IP
Figure 10 portrays the final simplified model subcircuit where all relevant sources appear, among them, the switching
frequency, peak current and Ton calculations. For the extended model, only BGd and BEt sources need to be changed. As you
can see, there are plenty denominator expressions where a variable such as Ton appears. If during the bias point calculation
SPICE Ton starts or goes close to zero, the simulator can fail to converge (or find a wrong bias point which is worse). To avoid
this potential problem, a trick consists in inserting a fixed value, small enough like 1 or less, to clamp the maximum value
the source can take if Ton becomes null. To the opposite, the frequency expression modeled by a voltage source can deliver
kV to express kilo Hz. The simulator dynamic being bounded, mixing values of a few mV with sources delivering kV can puzzle
the bias point calculation. Again, a division by 1000 will limit the range. The FB pin undergoes a division by 3 to be further
clamp by a 1 V limiter, a classical circuitry found in most PWM controllers (IP max = 1 V / Rsense).
DC−bias calculation always represents a difficult task for SPICE simulators running averaged models. In order to enhance
the extended model robustness (the one including parasitic effects), we have constrained the BGd source to be positive only
by using a simple in−line equation that differs depending on the simulator syntax:
IsSpice
BGd 4 3 I= ((2*{Lp}/V(ton)) * ( ({N}*V(13)+V(3))/(V(3)+1u) + {DEL}/V(ton) +
+({Lp}*{Ctot}/V(ton))*(1+(V(3)/{N})/V(13)) ) * I(V6)^2)/(V(3,4)+1u)*{EFF} < 10m ? 10m :
+((2*{Lp}/V(ton)) * ( ({N}*V(13)+V(3))/(V(3)+1u) + {DEL}/V(ton) +
+({Lp}*{Ctot}/V(ton))*(1+(V(3)/{N})/V(13)) ) * I(V6)^2)/(V(3,4)+1u)*{EFF}
PSpice
Gd 4 3 TABLE { ((2*{Lp}/(V(ton)+10n)) * ( ({N}*V(13)+V(3))/(V(3)+1u) + {DEL}/(V(ton)+10n) +
+({Lp}*{Ctot}/(V(ton)+10 n))*(1+(V(3)/{N})/V(13)) )
+ * I(V6)^2)/(V(3,4) + 1u)*{EFF} } ( (10m,10m) (1000,1000) )
Finally, the model comes with two different names:
.SUBCKT QuasiFly 13 FB GND 3 IP Ton FSW params: LP = 3.22 m RS = 0.5 N = 0.06 eff = 0.86
the simplified model version
QuasiFlyDel 13 FB GND 3 IP Ton FSW params: LP = 3.22 m RS = 0.8 N = 0.06 eff = 0.86 Ctot = 100 p
the complete model including parasitic effects
Passed parameters are:
Ctot, the lump parasitic component present on the drain.
LP, the primary inductance
Rlf, the ohmic losses of the primary winding
N, the NP : NS ratio with NP=1
Eff, the circuit estimated efficiency
Please note that for the sake of simplicity, both models do not account for the secondary rectifier forward drop Vf whose effect
is nevertheless negligible in our approach.
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AND8112/D
Putting the Model to Work
Different ways exist to test the validity of a model. The
first one is by using SPICE only, where one can compare the
transient response of the averaged model versus that of the
equivalent cycle−by−cycle. The other one implies the
comparison of the averaged model results versus a real board
measurement. In this paper, we will depict both approaches,
using our simplified cycle−by−cycle transient model.
The averaged template is depicted by Figure 11 where
Figure 10 sources have been pushed into a single graphic
8.68 ton
0.868
iP
80.7
fSW
IP
ton fSW (kHz)
Flyback FreeRunning
Averaged model
OUT
IN
Vin
120
FB
X2
QuasiFly
LP = 1.2 m
RS = 0.5
N = 0.06
eff = 0.91
Rlf = 0.5
Vout
R6
10 m
24
L3
2.2 16.8
GND
9
Vg
120
AC =
symbol. The symbol must be fed by Lp, Efficiency, Rsense,
transformer turn ratio and the primary inductance ohmic
loss. The FB pin goes to a component arrangement particular
to the NCP1207 series from ON Semiconductor where the
optocoupler collector is internally pulled−up to a reference
voltage.
R7
150 m
R8
60 m
17
16.8
FB
16.8
16.8
3
Vout
16.8
C3
1 mF
IC = 16
Rload
8.5
25
C4
220 IC =
Vout
FB
V9
4.8
6
Fb
R10
20 k
R1
1k
1.30
16.7
C5
1n
15.8
4.80
1
X1
SFH615AGR
2
D4
BV = 15.6
Figure 11. Averaged Model Template
The averaged model template featuring DC bias points which confirms the correct bias point calculation
Figure 13 reveals the good agreement between the averaged
response and the cycle−by−cycle one. The next experience
will step load the converter output from light to heavy load
in a few s. Figure 14 testifies for the right behavior on both
configuration, average or cycle−by−cycle.
On the static point of view, the following data compare
numbers given by the averaged model and the
cycle−by−cycle one:
IP AVG = 868 mA / IP TRAN = 858 mA
Ton AVG = 8.68 s / Ton TRAN = 8.78 s
FSW AVG = 80.7 kHz / FSW AVG = 77.8 kHz
In Figure 11, once the simulation has been done, DC
points are reflected to the schematic and confirm the validity
of the original calculation. The feedback loop is made of a
simple Zener diode to avoid any long feedback time
constants as with a standard TL431. The cycle−by−cycle
circuitry uses our simplified QR transient model which
emulates
a
free−running
controller
such
as
ON Semiconductor NCP1207 or NCP1205 [3] (Figure 12).
The output stage and feedback configuration conforms to
Figure 11 in order to compare similar topologies. The first
test consists in testing the input audio susceptibility by
stepping the input voltage from 200 V to 350 VDC.
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AND8112/D
21
9
dem
R6
100
C6
100 p
Lleak
1p
FreeRun
4
8
1
fb
31
IDiode
dem
2
7
3
6
4
5
R7
150 m
Cout1
1 mF
IC = 16.5
16
V1
X3
PSW1
Rled
1k
fb
3
24
IReso
X2
PSW1
17
X5
SFH615AGR
C5
1n
Creso
10 p
1
Simplified simulation of a
NCP1207−based board
C1
220 IC = 16.5
Feedback
+
ID
X1
FreeRunDT
toff(min) = 1 7
Vout
6
Vdrain
Vout
15
14
5
R1
1k
Vout
Resr1
60 m
Lprim
1.2 m
V3
120
AC =
R5
10 m
13
12
Icoil
11
L3
2.2 +
Rprim
0.5
VCoil
Iout
X4
XFMR−AUX
D1
RATIO_POW = −0.06
RATIO_AUX = −0.06 MBR20100CT
Rsense
0.5
18
D4
BV = 15.6
Figure 12. This Simplified Transient Model Will Help to Check the Averaged Results
Real World Confrontation
Even if the above paragraph gives us the assumption that
our model sticks to reality quite well, nothing replaces a real
board measurement with a network analyzer. However, on
the NCP1207, the collector of the optocoupler is directly
internally pulled−up to a reference via a resistor, it thus
becomes difficult to open the loop via the series transformer
method. We thus went back to a simple open−loop
configuration where a DC source fixes the expected
operating point. It does not cause any problem in our case
since the overall gain Vcontrol to Vout is low. The AC
injection is then made via a 1000 F capacitor. Figure 15
depicts the adopted configuration on the bench, but also
replicated on the averaged model.
16.88
16.86
16.84
16.82
Averaged Vout
Cycle−by−Cycle Vout
16.80
2.57 m
3.11 m
3.65 m
4.19 m
4.73 m
Figure 13. Audio Susceptibility with a Line Step
(200 to 350 V)
Averaged Vout
16.95
4
1
8
2
7
3
6
4
5
5
16.85
C1
1000 = 20 mV
16.75
Vstim
AC = 1
R3
1k
3
NCP1207
1
Rsense
Vbias
1.57
16.65 Cycle−by−Cycle Vout
Figure 15.
16.55
2.48 m
3.04 m
3.60 m
4.16 m
The AC measurement is obtained once the proper
operating point is reached by adjusting Vbias. The gain being
low, there is no problem of output runaway as long as Vbias
is slowly increased.
4.72 m
Figure 14. and Load Step Response
Comparison Between Models (50 to 0.5 )
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AND8112/D
The bandwidth measurement has been carried on a board further to a 15 mn warm−up. This board does not use any clamping
network but a 800 V MOSFET instead and a large capacitor connected between drain and ground Figure 16 and 17 compare
the obtained results with the averaged model including valley and turn−off delays:
Phase (°)
Mag (dB)
180
20
135
10
High Line
90
0
Low Line
45
−10
F0 dB = 49 Hz
−20
0
−30
−45
−40
−90
−135
−50
High Line
−180
−60
Low Line
1
10
100
1k
10 k
Figure 16. Bode Plot Captured with a Network Analyzer
20.0
180
Open−loop Gain:
High Line
Low Line
0
90.0
F0 dB = 46 Hz
−20.0
0
−40.0 −90.0
Open−loop Phase:
High Line
Low Line
−60.0 −180
1
10
100
1k
10 k
100 k
Figure 17. Bode Plot Obtained with the Averaged Model
Finally, a step−load response was performed on a real
board fed back by a TL−431 network and compared to our
SPICE model, also implementing the same control loop
structure. Results prove that the proposed model accuracy is
acceptable to predict board stability and final transient
response:
One can detect a slight gain difference (around 3.5 dB) in
DC but the overall simulated shape stays in good agreement
with the real measurement. The phase dips are imputed to
the presence of the LC network whose cut−off frequency
obviously affects the results. The small−signal analysis
details are available in [5].
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AND8112/D
Conclusion
A SPICE model dedicated to the AC analysis of
free−running topologies was missing. The simple model
presented in this article shows that loop stabilization of QR
converters becomes easy thanks to the simulation.
Furthermore, the good agreement between simulated results
and hardware measurements will surely diminish the
prototype development time. As usual, the application
templates of the paper examples are available to download
from the author’s website [5] in both Intusoft’s IsSpice and
OrCAD’s PSpice.
16.93
16.87
30 ms/div
16.81
16.75
2 ms/div
16.69
4.50 m
8.50 m
12.5 m
16.5 m
References:
1. B. Erickson, D. Maksimovic, “Fundamentals of
Power Electronics”, Kluwers Academic
Publishers, ISBN 0−7923−7270−0
2. B. Erickson, D. Maksimovic, Advances in
Averaged Switch Modeling and Simulation”,
CoPEC.
http://schof.Colorado.EDU/~pwrelect/publications
.html
3. C. Basso, “Determining the Free−Running
Frequency for QR Systems”, ON Semiconductor,
AND8089/D
4. J. Chen, B. Erickson, D. Maksimovic, “Averaged
Switch Modeling of Boundary Conduction Mode
Dc−to−Dc converters”, the 27th Annual
Conference of the IEEE Industrial Electronics
Society.
5. http://perso.wanadoo.fr/cbasso/Spice.htm
20.5 m
Figure 18. The Simulated Step−Load Response On
a TL431−based Feedback Loop
Figure 19. versus Real Board Oscilloscope Shot
ON Semiconductor and
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