AND8240 Designing NCP1381 and NCP1382 in High Power AC-DC Adapters Nicolas Cyr ON Semiconductor http://onsemi.com The NCP1381 and NCP1382 are valley−switching controllers offering various features making it ideal to build efficient High Power AC−DC adapters. For instance, it has the capability to control the activity of the Power Factor Correction (PFC) front stage that highly simplifies PFC implementation. More generally, the NCP1381/82 incorporates all the major up−to−date functions (most of them programmable) to ease the optimization of any specific application and the compliance to the specifications of modern power supplies, including reliability and standby efficiency. Main features • Current−Mode Operation with Quasi−Resonant Operation: Implementing peak current mode control, NCP1381/82 • • • • • • • waits until the voltage across the external switching device crosses a minimum level. This is the quasi−resonance approach, minimizing both EMI radiations and capacitive losses. Over Power Protection: Using a current image of the bulk level (via the brown−out divider), it is easy to create an offset on top of the current sense information by inserting a series resistor, providing an efficient line compensation method. Frequency Clamp: The controller monitors the sum of tON and tOFF, providing a real frequency clamp. Also the tON maximum duration is safely limited to 45 ms in case the peak current information is lost. If the maximum tON limit is reached, then the controller stops all pulses and enters a safe auto−recovery burst mode. Blanking Time: to prevent false tripping with energetic leakage spikes, the controllers includes a 3 ms blanking time after the TOFF event. Go−to−Standby Signal for PFC Front Stage: NCP1381/82 includes an internal low impedance switch connected between Pin 10 (VCC) and Pin 11 (GTS). The signal delivered by Pin 11 being of low impedance, it becomes possible to connect PFC’s VCC directly to this pin and thus avoid any complicated interface circuitry between the PWM controller and the PFC front−end section. In normal operation, Pin 11 routes the PWM auxiliary VCC to the PFC circuit which is thus directly supplied by the auxiliary winding. When the SMPS enters skip−cycle at low output power levels, the controller detects and confirms the presence of the skip activity by monitoring the signal applied on its pin ADJ_GTS (typically a portion of FB signal) and opens Pin 11, shutting down the front−end PFC stage. When this signal level increases, e.g. when the SMPS goes back to a normal output power, Pin 11 immediately (without delay) goes back to a low impedance state. Finally, in short−circuit conditions, the PFC is disabled to lower the stress applied to the PWM main switch. Low Startup−Current: Reaching a low no−load standby power represents a difficult exercise when the controller requires an external lossy resistor connected to the bulk capacitor. Due to a novel silicon architecture, the startup current is guaranteed to be less than 15 mA maximum, helping to reach a low standby power level. Skip−Cycle Capability: A continuous flow of pulses is not compatible with no−load standby power requirements. Slicing the switching pattern in bunch of pulses drastically reduces overall losses but can, in certain cases, bring acoustic noise in the transformer. Due to a skip operation taking place at low peak currents only, no mechanical noise appears in the transformer. This is further strengthened by ON Semiconductor soft skip technique, which forces the peak current in skip to gradually increase. In case the default skip value would be too large, connecting a resistor to the Pin 6 will reduce or increase the skip cycle level. Adjusting the skip level also adjusts the maximum switching frequency before skip occurs. Soft−Start: A circuitry provides a soft−start sequence which precludes the main power switch from being stressed upon startup. This soft−start is internal and reaches 5 ms typical. © Semiconductor Components Industries, LLC, 2008 September, 2008 − Rev. 1 1 Publication Order Number: AND8240/D AND8240 • Overvoltage Protection: By sensing the plateau level after the power switch has opened, the controller can detect an • • • over voltage condition through the auxiliary reflection of the output voltage. If an OVP is sensed, the controller stops all pulses and permanently stays latched until the VCC is cycled down below 4 V. External Latch Input: By permanently monitoring Pin 5, the controller detects when its level rises above 3.5 V, e.g. in presence of a fault condition like an OTP. This fault is permanently latched−off and needs the VCC to go down below 4 V to reset, for instance when the user un−plugs the SMPS. Brown−Out Detection: By monitoring the level on pin 2 during normal operation, the controller protects the SMPS against low mains condition. When the Pin 2 level falls below 240 mV, the controllers stops pulsing until this level goes back to 500 mV to prevent any instability. During brown−out conditions, the PFC is not activated. Short−Circuit Protection: Short−circuit and especially over−load protection is difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the auxiliary winding level does not properly collapse in presence of an output short−circuit). In NCP1381/82, every time the internal 0.8 V maximum peak current limit is activated, an error flag is asserted and a time period starts, due to an external timing capacitor. If voltage on the capacitor reaches 4 V (after 90 ms for a 220 nF capacitor) while the error flag is still present, the controller stops the pulses and goes into a latchoff phase, operating in a low−frequency burst−mode. As soon as the fault disappears, the SMPS resumes its operation. The latchoff phase can also be initiated, more classically, when VCC drops below VCCmin (10 V typical). Typical Application The above features makes NCP1381/82 well suited for medium to high power offline applications. Its typical application is a 75 W to 200 W AC−DC power supply such as a notebook adapter. HV PFC Stage + + To PFC’s VCC OVP NCP1381/82 GTS_ADJ BO DMG Skip GTS_ADJ 1 14 2 13 3 4 5 12 11 10 6 9 7 8 + Vref + OPP Figure 1. NCP1381/82 Typical Application Example http://onsemi.com 2 Vout AND8240 PIN−BY−PIN IMPLEMENTATION Pin 1: “ADJ_GTS” Pin This pin offers a comparator with adjustable hysteresis to define the turning ON and OFF conditions of the PFC controller. It is primarily intended to be connected to a portion of the FB voltage, but any other signal could be used as well (such as a rectified and averaged image of the DRV pin for instance). The purpose is to define the output power level at which the front−end PFC turns ON and OFF, in order to reduce the standby consumption of the application. It consists in a simple comparator with fixed 250 mV reference: when the voltage applied on the pin is higher than 250 mV, GTS signal can turn on; and when it is lower than 250 mV, GTS signal is low. Additionally, when output of the comparator is high an internal current source delivers 5 mA to the pin, allowing the creation of an offset on top of the signal applied: as this offset disappears when the comparator turns off, it plays the same role as an hysteresis. VDD 5 mA Ext. Signal (FB, Aux.) RUP Rhyst + GTS OK − + 250 mV RLOW Figure 2. Internal Configuration of ADJ_GTS Pin Design Steps (Considering RHYST = 0) • Choose the input signal levels at which GTS must turn on and off: VON and VOFF • Find the division ratio of the input resistor divider based on the turn−on level (case where the internal 5 mA current source is off): h+ 0.25 (eq. 1) VON • Find the equivalent resistance seen from the pin according to the turn−off level (case where the internal 5 mA current source is on): 0.25 + h @ V OFF ) 5 @ 10 *6 @ R EQ å R EQ + 0.25 * h @ V OFF Knowing that h+ 5@ R LOW R UP ) R LOW (eq. 2) 10 *6 , and R EQ + R UP @ R LOW R UP ) R LOW , it may be deduced R UP + R EQ h (V ON * V OFF) h 4 + 2 @ 10 5 @ (V ON * V OFF) and R LOW + 1 * h @ R UP + 5 @ 10 @ (V * 0.25) (eq. 3) ON • An additional constraint if the signal used is FB, is that RUP + RLOW must be greater than 20 kW in order not to disturb FB behavior. If a smaller value is obtained, restart calculations with different VON and VOFF. http://onsemi.com 3 AND8240 Pin 2: “BO” Pin SMPS are designed for a given input range. When the input voltage is too low, the power supply tends to compensate by sinking more current from the line to deliver the same output power. As a result, the power components may suffer from an excessive heating and ultimately the SMPS may be destroyed. Another consequence is that as when the electricity network weakens, its voltage tends to decrease, and as in this case SMPS tend to sink more current, electricity network gets weaker and weaker and eventually collapses (it is the reason why this protection is called ‘brown−out’ protection). A simple solution to protect at the same time the power supply and the network is to stop the SMPS controller when the input voltage is too low. For this purpose Pin 2 offers a comparator with hysteresis able to stop the controller if the voltage applied is too low. By applying an image of the input voltage on the pin, it becomes possible to authorize operation above a certain level of mains only. The controller monitors this voltage and when the Pin 2 voltage is too low (i.e., when Vpin2 is below 240 mV), the controller stops pulsing and keeps disabled until this level exceeds 500 mV. The 260 mV hysteresis prevents the instabilities that could result from the input voltage ripple. The brown−out protection is not latched: when the input voltage (VIN) is below the target, the controller stops pulsing but it recovers operation as soon as (VIN) goes back within the acceptable range. Input Voltage CMP RBO1 CMP 5 Driver + − RBO2 + Driver is off as long as CMP is LOW 500 mV if CMP is LOW 240 mV if CMP is HIGH VPin5 0.24 V Figure 3. Internal Configuration of BO Pin http://onsemi.com 4 0.5 V AND8240 Which Input Voltage Should be Monitored? • The PFC stage output voltage (“VBULK” − bulk voltage). • “VSIN”, the PFC stage input voltage. Figures 4 and 5 depict the two techniques. VSIN Vbulk To Converter PFC Preconverter RBO1 Input Filtering Capacitor AC Line Cbulk + 2 RBO2 CBO1 Figure 4. Brown−Out Detection on VSIN VSIN Vbulk To Converter PFC Preconverter RBO1 AC Line Input Filtering Capacitor Cbulk + 2 RBO2 CBO1 Figure 5. Brown−Out Detection on VBULK We will focus on VSIN monitoring as this solution protects both PFC and SMPS stages. Figure 6 depicts VSIN behavior when PFC stage starts. 400 200 0 Figure 6. Voltage Across the Input Diodes Bridge (VSIN) at PFC Startup http://onsemi.com 5 AND8240 We clearly see two phases: • The input voltage VSIN is a substantially constant voltage when the PFC stage is off. The input bridge acting as a peak detector, the input voltage is flat and equates the AC line amplitude: V IN + Ǹ2 @ V AC (eq. 4) Where VAC is the RMS voltage of the line. Hence, the voltage applied to BO pin is: V BO + Ǹ2 @ V AC @ R BO2 (eq. 5) R BO1 ) R BO2 This is the situation anytime when the PFC stage is off. • The input voltage VSIN is a rectified sinewave when the PFC stage operates. If CBO1 is large enough to suppress the AC component of BO voltage, pin 2 voltage is the following portion of the average value of VSIN: V BO + 2 @ Ǹ2 @ V AC p @ R BO2 R BO1 ) R BO2 (eq. 6) i.e. about 64% of the previous value. Therefore, the same line magnitude leads to a BO voltage that is 36% lower when the PFC is working compared to the pin 2 level when it is off. That is why the NCP1381/82 features a 48% hysteresis (VBOlow = 0.48 x VBOhigh). When the PFC stage starts operation, the input voltage equates the AC line peak. That is why the initial threshold of the brown−out comparator is its upper one (VBO = VBOhigh = 500 mV when the NCP1381/82 starts operation). Design Steps: RBO1 and RBO2 can be calculated by using the following procedure: 1. Fix the current drawn by RBO1 and RBO2 so that it is compatible with the standby requirements. For instance, choose 50 mA consumed when VBO reaches the 500 mV VBOhigh threshold. 2. Evaluate RBO2 by: R BO2 + 0.5 50 @ 10 *6 + 10 kW (eq. 7) 3. Calculate RBO1 by: V BO + 2 @ Ǹ2 @ VAC 50 @ 10 *6 [ Ǹ2 @ V AChigh 50 @ 10 *6 (eq. 8) Where VAChigh is the AC line RMS voltage above which the circuit enters operation. For instance, if the desired threshold is 85 Vac, RBO1 = 2.39 MW. The threshold at which the power supply stops (VAClow) depends on the capacitor CBO1. If CBO1 is infinite, it fully suppresses the AC component of the input voltage portion that is monitored. Hence, VBO is proportional to the average of the rectified AC line voltage: V BOlow + 2 @ Ǹ2 @ V AClow p As V AChigh + V BOhigh @ @ R BO2 R BO1 ) R BO2 å V AClow + p @ V BOlow 2@ @ R BO1 ) R BO2 Ǹ2 @ R BO2 . (eq. 9) B BOlow R BO1 ) R BO2 we can deduce, i.e. V AClow + p @ @ V AChigh, i.e. Ǹ2 @ R 2 V BOhigh BO2 VAClow = VAChigh x 75.4%. That means that if VAChigh = 85 V, VAClow = 64 V. If VAClow is too low, reducing CBO1 will increase the ripple injected to BO pin, and as a result decrease the hysteresis. Using a simple simulation circuit (as proposed in Figure 7) rapidly gives the right value for CBO1 and the desired VAClow. The simulation result of Figure 8 gives the VBO ripple as a function of CBO1 in the case where: V SIN + Ǹ2 @ 80 sin(w @ t) (eq. 10) To the light of this study, CBO1 = 470 nF is the capacitance necessary to have VAClow = 80 V. http://onsemi.com 6 AND8240 VSIN B1 Voltage VAC + + VPin5 R1 2390 k − V1 440 m 400 VSIN 340m 300 VPin5 V(VAC) > 0 ? V(VAC): −V(VAC) 240m 200 R2 10 k C1 470 n 140m 100 Figure 7. Brown−Out Detection Simulation Circuit 40m 0 890m 895m 900m 905m 910m TIME (s) Figure 8. Results of the Simulation for Circuit of Figure 7 Without simulation tools, the procedure consist in implementing a large CBO1 value (leading to a time constant RBO2 ⋅ CBO1 in the range of 20 ms in 50 Hz or 60 Hz line conditions) and decreasing it until VAClow reaches the wished value. To Summarize • Select RBO2 in the range of 10 kW (in order to limit the leakage current generated by the brown−out sensing network • around 50 mA). Compute: R BO1 + R BO2 @ ǒ Ǹ2 @ V AChigh 0.5 Ǔ *1 (eq. 11) • Implement CBO1 so that (RBO2⋅CBO1) is in the range of 20ms. Then measure VAClow and adjust CBO1 until VAClow has the right value, knowing that reducing CBO1 increases VAClow. We will see later that Overpower Protection is dependent on VBO voltage: to have an accurate protection, VBO should be proportional to the input voltage of the SMPS stage, i.e. VBULK. But once PFC has started, VBULK is not any more an image of the mains voltage: it means that even if VSIN goes below VAClow, PFC stage will still try to maintain VBULK high, and the brown−out protection is not effective. So connecting VBO to VSIN is recommended, even if overpower protection is less accurate. A solution to improve this protection is to use a “follower boost” type of PFC in which the output follows the input. Pin 3: “DMG” Pin In order to perform valley switching operation, NCP1381/82 monitors an auxiliary winding that gives an image of the voltage appearing on the drain of the switching MOSFET (Figure 9). Each time the decreasing voltage on DMG pin crosses 0 V, an internal comparator gives a clock signal to the internal latch that delivers the gate signal for the switching MOSFET (Figure 10). The signal applied on DMG pin must be lower than 3.7 V in order not to activate the overvoltage protection, and the current flowing in the negative clamping protection diode must be kept below 3 mA. Internal circuitry is depicted in Figure 11. VDRAIN(t) VDRAIN(t) TW Leakage Ringing 3.0 1.0 1st Valley 0 0 Possible Restart 2.0 tOFF VIN VPLATEAU tON Figure 9. Voltage Appearing on the Drain of the Switching MOSFET 45 mV 0V Figure 10. Corresponding Voltage Appearing on Pin DMG http://onsemi.com 7 AND8240 + DMG 30k 10 V − DMG Comp. 45 mV + 10 V Latch Input + Vlatchdem 4V + DRV Logic − 4 ms Mono Stable DRV Figure 11. Internal Circuitry of DMG Pin Design Steps: • Knowing the plateau voltage VPLATEAU appearing on the auxiliary winding, calculate RDMG taking into account the internal 30 kW pulldown resistor: R DMG w 3 @ 10 4 @ V PLATEAU * 3.7 (eq. 12) 3.7 Verify that the current flowing through RDMG when ESD clamping diode is activated (+10 V during tOFF, −0.7V during tON) is within specification (+/−3mA). If not, choose RDMG according to this maximum current, and then add an external resistor between DMG pin and ground (in parallel to the internal 30 kW resistor) to ensure VDMG < 3.7 V during normal operation. • Add a capacitor CDMG between DMG pin and ground in order to delay the turn−on to the exact valley of the Drain signal. A first approximation for CDMG consists in measuring the period of the oscillation (due to LP the primary inductance and CDRAIN the total capacitance on MOSFETs drain) appearing on the drain after demagnetization, or estimate it by: T OSC + 2 @ p @ Ǹ L P @ C DRAIN (eq. 13) The time Tdelay between the zero crossing and the exact valley is one fourth this period, minus the roughly 200 ns inherent propagation delay of the controller: T delay + p Ǹ @ L P @ C DRAIN * 2 @ 10 *7 2 (eq. 14) Eventually choose CDMG so that (RDMG⋅CDMG) is in the range of Tdelay, and adjust it until the valley switching is correct. Pin 4: “TIMER” Pin The capacitor connected to this pin sets the duration of the fault timer, i.e. the delay after which the controller enters protection mode after detecting an overload condition. Its main purpose is to allow the cold startup (during which, by definition, the output is overloaded until the regulation level is reached), and to prevent any false triggering of the protection in a noisy environment. This timer is also used to prevent PFC shutoff during transient activation of the skip mode. It is built around an internal 10 mA current source that charges the external capacitor until a 4 V comparator toggles (See Figure 12). http://onsemi.com 8 AND8240 VDD 10 mA Timer + FAULT − Reset Timer + 4V Figure 12. Internal Circuitry of TIMER Pin Design Steps: Once the VCC capacitor is set (see VCC section below), it gives the minimum time duration TFAULT during which the controller must deliver power in overload condition during start−up. CTIMER can then be estimated by: C TIMER w T FAULT @ 10 @ 10 *6 4 , i.e. (eq. 15) C TIMER w T FAULT @ 25 @ 10 *7. For instance if TFAULT must be at least 80ms, CTIMER should be greater than 200nF. Pin 5: “SKIP / OVP” Pin This pin performs two functions: it allows the setting of the FB pin level at which the controller starts to skip pulses in order to lower standby consumption, and at the same time provides a comparator to stop and latch the controller by any external condition (See Figure 13). FB + − Skip Comp. DRV Logic VDD 32 mA Latchoff Comp. SKIP/OVP + − + Latch Input 3.5 V 25k Figure 13. Internal Circuitry of Skip/OVP Pin Design Steps: • By default, skip level is set to 800 mV (32 mA through a 25 kW resistor), corresponding to 25% of maximum FB • • voltage (See FB Pin Section). Adding an external resistor to ground allows decreasing skip level, while adding a resistor from REF pin to Skip/OVP pin allows the increase of this level. This pin being at rather high impedance, it is necessary to add a filtering capacitor, which value depends on the amount of noise of the environment: a value from 100 nF to 1 mF is usually sufficient. To perform a latch function, the best way is to drive the REF signal to Skip/OVP Pin through an optocoupler or a simple bipolar transistor as exemplified in Figure 14. http://onsemi.com 9 AND8240 Vref Vref OVP OVP SKIP + + Latch − − Latch SKIP SKIP NTC + + Vlatch Vlatch Vmax < 5 V! Figure 14. Possible use of the Latch Function of Skip/OVP Pin Pin 6: “FB” Pin The voltage on FB pin is divided by 4 and compared to CS Pin voltage to elaborate the tON duration (NCP1381/82 is a current−mode controller): it serves as a reference for the current sense comparator (See Figure 15). To simplify the connection of an optocoupler, an internal 10 kW pullup resistor is provided: optocoupler transistor can thus directly be plugged between FB pin and ground. LEB CS Comparator 7 CS 6 FB VDD + − 10k /4 0.8 V IP Flag Figure 15. Internal Circuitry of FB Pin Maximum CS pin voltage VCSmax is 0.8 V, corresponding to a maximum FB voltage of 3.2 V: when voltage on FB pin is higher than 3.2 V, internal flag IP flag is raised and fault timer is started. If IPflag is still asserted when TIMER pin voltage reaches 4 V, FAULT is detected and the controller enters protection mode: pulses are stopped, and VCC capacitor is discharged at a constant 1.4 mA current down to 7 V. Then a new start−up phase takes place, leading to a low−frequency burst mode safe for the power supply if the overload is still present. When the faulty condition disappears, the controller resumes normal operation after the next restart attempt (See Figure 16). If a resistive load is connected to FB pin (to generate ADJ_GTS signal for instance), it must be greater than 20 kW in order to allow the voltage on FB pin being greater than 3.2 V in overload conditions. http://onsemi.com 10 AND8240 VCC VCCON VCCmin VCCLatch Overload FB Max IP Flag TIMER Figure 16. Typical Behavior in Overload Conditions Pin 7: “CS” Pin This pin performs two distinct functions: primary peak current reading and compensation for overpower protection. Peak Current Reading It is classically performed through the reading of the voltage appearing through a sense resistor connected between switching MOSFETs source and ground. The internal maximum current sense level VCSmax is 0.8 V, so RSENSE must be calculated by: R SENSE + 0.8 I pkmax , (eq. 16) With Ipkmax the maximum peak primary current at the lowest input voltage and maximum output load. A leading edge blanking (LEB) prevents any spike appearing during the first 350 ns after tON to toggle falsely the internal current sense comparator. This LEB is usually enough, but if for some reasons an additional filtering is necessary, it is still possible to add externally an RC filter. Overpower Compensation In the quasi−resonant mode of operation, the slope of the current during ON time is (VIN B LP), and is (N ⋅ VOUT) B (LP) during OFF time. Thus for a given peak current Ipk, tON is shorter at high VIN than at low VIN, and tOFF is constant: so the switching frequency FSW is higher at high VIN (See Figure 17). http://onsemi.com 11 AND8240 Figure 17. tON Behavior at a Given Ipk for Different VIN Knowing that: P OUT + h @ P IN + h @ 1 @ L P @ I pk2 @ F SW (with h the efficiency), 2 (eq. 17) It is clear that for a given Ipk, POUT is higher at high VIN than at low VIN. So for a constant output power, the peak current is lower at high VIN than at low VIN (See Figure 18). Figure 18. Ipk Behavior at a Given POUT for Different VIN As the overload detection of NCP1381/82 is based on peak current detection, if an overpower protection is needed the voltage applied on CS Pin at POUTmax must be the same at high VIN and low VIN. The solution consists in adding a compensation offset proportional to VIN to the voltage sensed across the sense resistor. NCP1381/82 offers the possibility to easily create this offset by activating an internal current source proportional to VBO during tON: this current flows out of pin CS and create an offset proportional to VBO (which is proportional to VIN) through a series resistor (See Figure 19). http://onsemi.com 12 AND8240 VIN NCP1381/82 BO TO BO Comparator 2 CS Comparator I/V 85 mS − ROPP CS + LEB 7 RSENSE Figure 19. Internal Overpower Compensation Circuitry on CS Pin Design Steps: • Estimate peak current Ipk values at low VIN and high VIN for the maximum output power allowed. By neglecting the delay between core reset and the real valley (it is small compared to the switching period at high output power), we can estimate Ipk at a given VIN by: I pk + 2 @ P OUT h @ ǒV1 ) N @ 1V Ǔ IN (eq. 18) OUT Thus calculate IpkmaxLV and IpkmaxHV, respectively max peak currents at low and high input voltages. • In the case where no offset is added, we saw that: R SENSE + 0.8 I pkmax If an offset is added, we have at a given VIN: R SENSE + 0.8 * V offset I pkmax As we know what is the value of VBO for a given VIN, we can calculate V offset + R OPP @ V BO @ 85 @ 10 *6 Some lines of math eventually give: R OPP + 0.8 85 @ 10 *6 @ I pkmaxLV * I pkmaxHV V BOHV @ I pkmaxLV * V BOLV @ I pkmaxHV • Finally calculate RSENSE by using: R SENSE + 0.8 * R OPP @ V BOLV @ 85 @ 10 *6 (eq. 19) I pkmaxLV Pin 8: “GND” pin Reference ground for the controller. Pin 9: “DRV” pin By offering up to +500 mA/−800 mA peak, this pin allows to drive large QG MOSFETs without adding any additional components. http://onsemi.com 13 AND8240 Pin 10: “VCC” pin This is the supply pin for the controller. It must be connected through a resistor to VBULK for start−up supply, and to an auxiliary voltage for normal operation. Design steps: • Calculate VCC capacitor: it must be able to supply the controller during start−up before the auxiliary voltage is high enough to take the hand, i.e. before the output reaches regulation. Startup VCC voltage is 15 V, and minimum operating VCC is 10 V: the maximum voltage drop on VCC capacitor is thus 5 V. The current needed by the controller can be estimated by ICC1 (for NCP1381/82 internal supply) added to the current necessary to drive the switching MOSFET, given by the gate charge QG and the switching frequency FSW: I DRV + Q G @ F SW (eq. 20) To simplify the calculation, an average frequency of 60 kHz can be used as a rather good estimation. If we call TREG the time before the output reaches regulation, VCC capacitor must deliver ICC1 + IDRV during TREG without dropping more than 5 V. Thus calculate: C VCC u (I CC1 ) I DRV) @ T REG (eq. 21) 5 • Calculate the start−up resistor RSTART in order to fulfil the start−up time (TSTART) requirement: T START + C VCC @ VCC ON (eq. 22) I START ISTART = (VBULK − VCC) B (RSTART) is minimum at low VIN when VCC reaches VCCON, thus: R START t T START C VCC @ V BULKmin * VCC ON (eq. 23) VCC ON • Dissipated power in the start−up resistor at high input voltage is: P START+ ǒV BULKmax * VCC minǓ 2 (eq. 24) R START This value will greatly contribute to the no−load standby power of the complete power supply. To reduce this wasted power, several possibilities exist, for instance: allow longer startup time, allow higher maximum output power to reach earlier output regulation, increase auxiliary voltage to supply VCC before reaching regulation (but voltage on VCC Pin must stay below 20 V). A too big VCC capacitor leads to a too long start−up time, or to a too high standby power. But it is sometimes needed to keep on supplying NCP1381/82 in no−load condition, where the power delivered by the auxiliary supply is very low. In this case, it is possible to have a separate tank capacitor, different from the VCC capacitor (See Figure 20). VBULK RSTART 1M VCC CVCC 10 m + Ctank 100 m 18 V + AUX Figure 20. Split Capacitor on VCC Pin Pin 11: “GTS” Pin VCC is applied to GTS through an internal low−resistance switch. It is intended to be connected directly to supply pin of the front−end PFC controller. Pin 12: “REF” Pin A 5 V/10 mA reference voltage is available on pin REF. A filtering capacitor must be connected to this pin: 100 nF to 1 mF (depending on the noisiness of the environment) is usually enough. http://onsemi.com 14 AND8240 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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