AND8322 Four Key Steps to Design a Continuous Conduction Mode PFC Stage Using the NCP1654 http://onsemi.com Prepared by: Patrick Wang ON Semiconductor This paper proposes the key steps to rapidly design a Continuous Conduction Mode (CCM) PFC stage driven by the NCP1654. The process is illustrated by the following practical application: − Maximum output power: 300 W − Input voltage range: from 85 Vrms to 265 Vrms − Regulation output voltage: 390 V − Switching frequency: 65 kHz − INTRODUCTION − The NCP1654 is a controller for Continuous Conduction Mode (CCM) Power Factor Correction step−up pre−converters. It controls the power switch conduction time (PWM) in a fixed frequency mode and in dependence on the instantaneous coil current. Housed in a SO8 package, the circuit minimizes the number of external components and drastically simplifies the PFC implementation. It also integrates high safety protection features that make the NCP1654 a driver for robust and compact PFC stages like an effective input power runaway clamping circuitry. Generally, the NCP1654 is an ideal candidate in systems where cost−effectiveness, reliability and high power factor are the key parameters. It incorporates all the necessary features to build a compact and rugged PFC stage: • Compactness and Flexibility: Easy to implement, the NCP1654 yields near−unity power factor in a simple and robust manner. Despite the low external components count it requires, the circuit sacrifices neither performance nor flexibility. Instead, by simply adjusting an external resistor, you can even choose to have the circuit operated in traditional or follower boost mode (Note 1). • Low Consumption and shutdown Capability: The NCP1654 particularly, minimizes its consumption during the startup phase and in shutdown mode. Hence, the PFC stage losses are extremely low when the circuit is off. This feature helps meet the more stringent standby low power specifications. Grounding the Feedback pin (pin 6) forces the NCP1654 in shutdown mode. • Safety Protections: The NCP1654 permanently monitors the input and output voltages, the coil current and the die © Semiconductor Components Industries, LLC, 2009 July, 2009 − Rev. 2 − − − − temperature to protect the system from possible over−stresses. More specifically, the following protections make the PFC stage extremely robust and reliable: Maximum Current Limit: The circuit immediately turns off the MOSFET if the coil current exceeds the maximum permissible level. The NCP1654 also prevents any turn on of the power switch as long as the coil currents is not below this limit. This feature protects the PFC stage during the startup phase when large in−rush currents charge the output capacitor. Under Voltage Protection/Shutdown: The circuit keeps in shutdown mode as long as the feedback voltage indicates that the output voltage is lower than 8% its regulation level. In this case, the NCP1654 consumption is very low (<400 mA). This feature protects the PFC stage from starting operation in case of a failure in the feedback network (e.g., bad connection). Brown−Out Detection: The circuit detects the AC line voltage via the resistor divider. In case of too low AC line conditions, the circuit keeps in shutdown mode. Over Voltage Protection: Given the low bandwidth of the regulation block, PFC stages may exhibit dangerous output voltage overshoots because of abrupt load or input voltage variations (e.g. at startup). Over Voltage Protection (OVP) turns off the Power Switch as soon as Vout exceeds the OVP threshold (105% of the regulation level). Over Power Limitation: The NCP1654 senses the coil current and the input voltage and based on these information, the circuit is able to detect excessive power levels. In this case, it turns off the MOSFET. Thermal Shutdown: An internal thermal circuitry forces the power switch off when the junction temperature exceeds 150°C typically. The circuit resumes operation once the temperature drops below about 120°C (30°C hysteresis). 1. The “Follower Boost” mode makes the pre−converter output voltage stabilize at a level that varies linearly versus the AC line amplitude. This technique aims at reducing the difference between the output and input voltages to optimize the boost efficiency and minimize the cost of the PFC stage (refer to MC33260 and NCP1654 datasheet at www.onsemi.com) 1 Publication Order Number: AND8322/D AND8322 Vin VOUT D1 L1 + + IN Cfilter Q1 − RSENSE RboU1 EMI Filter RCS RboU2 2 3 4 RboL L CBO CM − RfbU2 10 NCP1654 1 + Cbulk RfbU1 10 k GND DRV VM VCC CS FB BO Vcontrol VCC 8 7 6 RfbL 5 RZ CP RM CZ CVcc CFB N Figure 1. PFC STAGE DIMENSIONING − Generic Schematic Step 1: Power Components Selection Basically, the coil, the bulk capacitor and the power silicon devices are dimensioned “as usually”, that is, as done with any other CCM PFC. This section does not detail this process, but simply states some key points. Therefore if we target a ±18% ripple at low line, i.e. Icoil,pp is 36%, the coil inductance, L, is given by the following equation: ǒ 1. Coil Selection L+ (eq. 1) Ǹ2 @ 300 ń (0.92 @ 85) Ǔ ǒ Ǔ Ǹ2 V h @ V acLL 2 acLL 1* V out 0.36 @ f sw @ P out,max I coil,rms + that is 5.4 A. On the other hand, one could show that at the sinusoid top, the peak−to−peak ripple of the coil current, is given by the following equation: ǒ Ǹ2 P out,max h @ V acLL (eq. 3) (eq. 4) The combination of 390 V for the output voltage (Vout) and 65 kHz for the switching frequency, leads to a coil inductance in the range of 655 mH. In practice, we have chosen 650 mH that more specifically, leads to about a 36% peak−to−peak ripple. Finally, if one neglects the switching ripple of the coil current, its rms value equates the rms AC line current. In other words: where Pout,max is the maximum output power, η the efficiency and VacLL the AC line lowest level. Consequently, if we assume a 92% efficiency, our 300 W application leads to the following maximum AC line peak current: Ǹ2 V Ǹ2 V ac ac 1* V out L @ f sw + 36% Hence, the coil inductance is: One generally selects the coil to limit the current ripple below a certain pre−determined level, for instance ±15% when the input current is maximum. The input current amplitude, Iin, is maximum at low line and high power. Hence, Ǹ2 P out,max I in,max + h @ V acLL Ǔ Ǹ2 V Ǹ2 V acLL acLL 1* V out L @ f sw P out h @ V ac (eq. 5) The maximum RMS current of the coil is then: I coil,rms,max + P out,max h @ V acLL (eq. 6) The coil specification is then: − L = 650 mH − Icoil,max = 6.4 A (maximum amplitude of the AC line current + ripple) − Icoil,rms = 3.8 A (eq. 2) where fsw is the operating frequency. Typically, one targets the peak−to−peak ripple between 10 and 50% of the AC line current maximum amplitude, Iin,max. http://onsemi.com 2 AND8322 2. Power Silicon Devices C bulk u Generally, the diode bridge, the power MOSFET and the output diode will be placed on the same heatsink. As a rule of the thumb, one can estimate that the heatsink will have to dissipate around: − 6% of the output power in wide mains applications (92% being generally the targeted minimum efficiency) − 3% of the output power in European mains applications Among the sources of losses that contribute to this heating, one can list: − The diodes bridge conduction losses that can be estimated by the following equation: V f P out 4 Ǹ2 V f P out P bridge + p h [ 1.8 V h V acLL C bulk u (eq. 7) acLL P on,max + R DS(on) @ ǒ V acLL Ǔ ǒ 2 @ (eq. 9) where dVpp,max is the maximum permissible peak−to−peak voltage ripple and w is the AC line angular frequency. In the NCP1654, Over Voltage Protection (OVP) is 105% of regulation level, which tolerance is from 103% to 107%. This function should be activated only during load or line change. To avoid OVP from being activated in normal operation, the voltage ripple on the bulk capacitor should be chosen below ± 3% (dVpp,max = 6% Vout). This requirement leads to the following bulk capacitance: 300 [ 105 mF 6% @ 100p @ 390 2 (eq. 10) Hold−up Time Requirement: If some hold−time requirement was specified, this would lead to the following additional constraint: where Vf is the forward voltage of the ridge diodes. − The MOSFET conduction losses, that if one neglects the current ripple, are given by: P in,max P out dV pp,max @ w @ V out Ǔ C bulk u 8 Ǹ2 V acLL 1* (eq. 8) 3pV out 2P out @ t HOLD V out1 2 * V out2 2 where Vout1 is the nominal output voltage (390 V in this case), Vout2 is the minimum acceptable level of Vout, and tHOLD is the hold−up time. For example, tHOLD = 20 ms and Vout2 = 250 V lead to Cbulk > 134 mF. The Cbulk capacitance should be higher than the calculated value from above two requirements. Considering the tolerance of capacitance, 180 mF is chosen here. Bulk Capacitor Heating: It must also be checked that the ESR is low enough to prevent the rms current that flows through it, from overheating the bulk capacitor. This rms current depending on the input impedance of the downstream converter, is not computed here. − The output diode conduction losses: (Iout ⋅ Vf), where Iout is the load current and Vf is the diode forward voltage. The maximum output current being nearly 0.77 A (= 300 W / 390 V), the diode conduction losses are in the range of 0.77 W (assuming Vf = 1.0 V). In our case, we have: − Pbridge = 6.9 W, assuming that Vf is 1.0 V. − Pon,max = 10.8 ⋅ RDS(on). In our application, a low RDS(on) MOSFET (0.19 W) is implemented to avoid excessive MOSFET losses. Assuming that RDS(on) doubles at the high temperatures, the maximum conduction losses are about 4.1 W. − Pdiode = 0.77 W. The diode and MOSFET switching losses are highly dependent on the diode choice, on the MOSFET drive speed and on the possible presence of some snubbering circuitry. Hence, their prediction is a tough and inaccurate exercise that will not be made in this paper. Instead, they are just assumed to be part of the power budget initially specified for the heatsink (6% of Pout in our case). Experimental tests will ensure that the estimation is correct. Step 2: Feedback Arrangement As shown by Figure 1, the feedback arrangement consists of: − CFB, a filtering capacitor to avoid that some switching noise may be injected into FB pin. A capacitor ranging from 100 pF to 1 nF is traditionally implemented. − RfbU1, RfbU2, and RfbL set output voltage. In practice, one generally implements more resistors as upper side feedback loop for safety consideration. Refer to Figure 1, given that Vout is a high voltage, an accidental shortage of the feedback resistor would destroy the controller. That is why it is better to have several series resistors instead of only one. 3. Output Bulk Capacitor The bulk capacitance had to satisfy two requirements, which are the output double line frequency ripple and hold−up time. Output Voltage Ripple Requirement: The bulk capacitance always presents the voltage ripple of double line frequency (100 or 120 Hz ripple exhibited by the bulk voltage (Note 2). The voltage ripple constraint requires that 2. The input current and voltage being sinusoidal, PFC stages deliver a squared sinusoidal power that matches the load power demand in average only. When the power fed to the load is lower than the load demand, the output capacitor discharges while it charges when the supplied power exceeds the load consumption. As a consequence, the output voltage exhibits a ripple (e.g., 100 Hz ripple in Europe or 120 Hz in USA) that is inherent to the PFC function. http://onsemi.com 3 AND8322 First, choose the value of the lower resistor, RfbL. There is a trade−off between the noise immunity and the power losses when choosing RfbL. In this application, we select 23.2 kW as RfbL that leads a 108 mA feedback current and 42 mW losses. The value of upper resistor RfbU is then given by V out * V REF R fbL V REF R fbU + − RboU (= RboU1 + RboU2 in Figure 1) and RboL are dimensioned to adjust the threshold of brown out protection. Because of the safety consideration, it is recommended to split this upper side brown out resistor into 2 or more resistors. − CBO that forms a low pass filtering together with RboL to get the average value of input signal. A time constant in the range of around 5 times the Vin period should be targeted to make Vbo substantially constant and proportional to the mean input voltage as the rule of thumb: (eq. 11) where: − VREF is the internal reference voltage for Vout feedback (2.5 V typical). − RfbU = RfbU1 + RfbU2 is the total feedback resistor placed between Vout and FB pin. In this case, Vout is 390 V and RfbL is 23.2 kW, one must then select the following RfbU resistance: R fbU + 390 * 2.5 @ 23.2 kW + 3.596 MW 2.5 V bo + Before device operates V control R @ G EAR Z 1 ) sR ZC Z + fbL @ V out R fbL ) R fbU sR ZC Z(1 ) sR ZC P) Vac After device operates + Vin + IN − RboU Vbo 4 (eq. 13) RboL where GEA is the error amplifier gain. Then this comp− ensation provides one original pole, one low frequency zero CBO + BO VboH / VboL VboH = 1.3 V, VboL = 0.7 V Figure 2. Brown−Out Protection 1 2p @ R Z @ C Z The NCP1654 starts to operate as Vbo exceeds 1.3 V and keeps operating until VBO goes below 0.7 V. The 600 mV hysteresis prevents the system from oscillating. As shown in Figure 2, before the device operates, Vin is kept at peak value of the input ac line sinusoid, Vac, that is, Ǹ2 V ac , which leads to: and one high frequency pole fP + (eq. 14) (eq. 12) One can approximately obtain 3.596 MW resistance by implementing: RfbU1 = RfbU2 = 1.8 MW. These normalized values precisely give RfbU = 3.6 MW, that is: 390 V as the regulation level. − CP, CZ, and RZ connected to Vcontrol pin acts as a type−2 compensation loop to set the regulation bandwidth (Note 3). It is recommended to set the bandwidth below 20 Hz for an effective filtering of the 100 or 120 Hz ripple. If CZ is >> CP, the transformer of Vout to Vcontrol is fZ + R boL tV in u R boL ) R boU 1 2p @ R Z @ C P In this application, we choose CP = 0.22 mF, CZ = 2.2 mF, and RZ = 12 kW, which leads to one zero at 6 Hz and one pole at 329 Hz. Finally: RfbU1 RfbU2 RfbL CFB 3.6 MW 3.6 MW 23.2 kW 100 pF CP CZ RZ 0.22 mF 2.2 mF 12 kW (eq. 15) R boL R boL Ǹ2 V V bo + tV in u+ ac R boL ) R boU R boL ) R boU After the device operates, Vin is the rectified sinusoidal input voltage, which average value becomes 2 Ǹ2 , which leads to: p V ac R boL 2 Ǹ2 V bo + V R boL ) R boU p ac Step 3: Input Voltage Sensing Refer to Figure 2, the NCP1654 monitors the input voltage, Vin, which is the rectified AC line sinusoid for brown−out, over−power limitation (OPL), and PFC duty cycle modulation. This sensing circuit consists of: (eq. 16) 3. Regarding how to design the compensation in NCP1654, please refer to application note: AND8321, “Compensation of a PFC stage driven by the NCP1654/5”, in www.onsemi.com or the book “Switch−Mode Power Supplies: SPICE Simulations and Practical Designs” written by Christophe Basso. http://onsemi.com 4 AND8322 First, select RboL. RboL should be relatively high impedance to limit the current within RboL and RboL and the associated losses. Please note however that given the bias current of the brown−out comparator (0.5 mA maximum), it is recommended to set the current flowing through RboU and RboL to be in the range or higher than 5 mA at low line. In this application, we use 82.5 kW for RfbL, which leads to a bias current of: Hence we can get V ac,off + Here RboU is split into 2 parts, RboU1 and RboU2 both equal to 3.3 MW for a global 6.6 MW resistance. Third, select CBO to make the time constant be around 5 times TVin, the cycle time of Vin by 5 @ T Vin R boL (eq. 18) Ǔ (eq. 19) line R boL R boU ) R boL Ǔ line + V BOL 40.0 Vin −40.0 Vbo 720m −120 700m −200 Vbo,min = 0.7 V 8.606 8.610 8.614 time in seconds 8.618 RboU1 RboU2 RboL CBO 3.3 MW 3.3 MW 82.5 kW 0.47 mF Like with the NCP1653, you are free to implement the current sense resistor, RSENSE, of your choice. Practically, losses considerations dictate its value. Once, you have selected the RSENSE resistor without other constraint that the best trade off between losses and noise immunity, you just have to choose a second resistor RCS to adjust the over−current threshold. fline is the line frequency, i.e. 50 Hz or 60 Hz. The brown−out function turning off the device is when (eq.19) equal to VBOL, the threshold voltage of brown out comparator, which leads to: ǒ 760m RSENSE R boL ) R boU 2p @ R boL @ R boU @ C BO f 2 Ǹ2 K BO @ p V ac,off @ 1 * BO 3@f + 64.8 Vac Step 4: Current Sense Network The current sense circuitry consists of: A current sense resistor RSENSE. A resistor RCS that sets the current limit threshold. A resistor RM that adjusts the PFC stage power capability. A capacitor CM. CS pin sources a current, Ics, that is proportional to the coil current. CM must filter the coil current ripple so that Ics is actually proportional to the input current, and makes the PFC stage operate at average current mode. fBO is the corner frequency of the BO filter: f BO + Ǔ Figure 3. Ripple on Vbo Where KBO is the scaling down factor of the BO network: K BO + Ǔ Finally Here 0.47 mF is selected because it is the closest normalized value. Fourthly, check Vac,off, the PFC brown−out off threshold of AC input voltage. As shown in Figure 3, because of the ripple voltage on Vbo, the minimum value of Vbo is around ǒ ǒ 8.602 5 @ 10 ms + 0.6 mF 82.5 kW f 2 Ǹ2 V bo + K BO @ p V ac @ 1 * BO 3@f 120 740m Where TVin is the duration of an input voltage cycle, that is, half the line period.. In this application, TVin is 10 ms since the ac input line is 50 Hz. So C BO [ 0.7 4.2 Hz 2Ǹ2 0.0123 @ p @ 1 * 3@50 Hz 780m vbo in volts Ǹ2 @ 75 V * 1.3 V R boU + @ 82.5 kW [ 6.65 MW 1.3 V vin in volts (eq. 17) In this application, 75 Vac is targeted as Vac,on. Hence, C BO [ line (eq. 21) which seems acceptable. By reducing CBO, one can increase this level and vice versa. Note that this calculation result is just a reference since it doesn’t include the voltage drop on the current loop, i.e. EMI filter and bridge diode etc. Second, select RboU according to Vac,on, the minimum AC input voltage to start PFC, which comes from (eq. 15): Ǹ2 V ac,on * V BOH R boL V BOH ǒ f 2Ǹ2 K BO @ p @ 1 * BO 3@f In this application, 0.7 V + 8.5 mA 82.5 k R boU + V BOL V ac,off + (eq. 20) http://onsemi.com 5 AND8322 This flexibility in the current sense resistor, leads to a significant reduction of the losses. Practically, compared to circuits featuring a traditional constant 1 V over−current threshold, you can easily improve the efficiency of your PFC stage (up to almost 1%, in a wide mains application). If one neglects the ripple current, maximum RSENSE losses can be estimated by the following equation: ǒ Ǔ P out,max PR ,max + R SENSE @ h @ V acLL SENSE where: − DVCONTROL is the operating range of Vcontrol (3 V). − VREF is the internal voltage reference (2.5 V) − VacLL is the lowest level of the AC line rms voltage. − Pout,max is the maximum output power. − η is the efficiency @ VacLL and Pout,max. − KBO is the scale down factor betweenVin and VBO, ǒ 2 (eq. 22) (h @ V acLL) 2 P out,max (eq. 23) In this application, solving of the precedent equation gives: R SENSE v 102 mW 70% @ 0.92 @ 2p @ 3.6 kW @ 3 V @ 2.5 V Hence, 0.1 W is chosen as RSENSE that would spend about 1.47 W. Ǹ2 @ 0.1 W @ 82.5 kW @ 390 V @ 300 W 6.6 MW)82.5 kW @ 85 Vac + 45.4 kW RCS Let’s take a normalized 47 kW resistor as RM. For a correct filtering of Ics, the time constant (RM ⋅ CM) should be taken in the range of 5 times the operating cycle period, i.e. 5 ⋅ 1/fsw. This time constant is large enough to filter the switching ripple and low enough not to distort the low frequency component, that is the 100 or 120 Hz rectified sinusoid. In this application, 65 kHz operating frequency of NCP1654 is chosen, which operating cycle period is 15.4 ms. So the time constant (RM ⋅ CM) should be in the range of 77 ms. Hence Simply select RCS in order to set the desired over−current limit: R CS + R SENSE @ I coil,max I S(OCP) (eq. 24) where: Icoil,max is the maximum coil current IS(OCP) is the internal over−current protection threshold (200 mA typical). To keep the design margin, it is recommended to use the minimum value of IS(OCP), 185 mA to design RCS. As the step 1 indicates that the maximum coil current is 6.4 A and RSENSE is 0.1 W, RCS is CM [ 0.1 W @ 6.4 A + 3.46 kW 185 mA 77 ms + 1.6 nF RM Let’s take CM = 1 nF. Finally Choose 3.6 kW as RCS as it is the closest higher normalized value in practical. RM and CM RM adjusts the maximum power the PFC stage can supply given the chosen output voltage level. By choosing RM high enough, you can force the “Follower Boost Operation” (Note 4). Use the following equation to select RM: R M + 70% @ h Ǔ R boL R boU ) R boL − VoutLL is the output voltage corresponding to VacLL in full load conditions. In traditional mode, VoutLL is the targeted regulation level (390 V in general). In Follower Boost, you can choose a lower value. − 70% is to take into account the im dispersion. Our application is a traditional one (constant output voltage). Hence, VoutLL equates 390 V and RM is: As a rule of the thumb, one can choose RSENSE so that its dissipation does not exceed 0.5% of Pout,max. This criterion leads to R SENSE v 0.5% @ K BO + RSENSE RCS RM CM 0.1 W 3.6 kW 47 kW 1 nF 4. The “Follower Boost” mode makes the pre−converter output voltage stabilize at a level that varies linearly versus the AC line amplitude. This technique aims at reducing the difference between the output and input voltages to optimize the boost efficiency and minimize the cost of the PFC stage (refer to MC33260 and NCP1654 datasheet at www.onsemi.com). 2pR CS @ DV CONTROL @ V REF (eq. 25) @ V acLL Ǹ2 R K V P SENSE BO outLL out,max http://onsemi.com 6 AND8322 CONSIDERATIONS REGARDING 200 kHz APPLICATIONS − DESIGN TIP AT HIGH LINE Please refer to Figures 5 and 4. As the operating frequency is 200 kHz and Vout is set at 390 Vdc, the input current is not smooth even at full load. By following above 4 steps, one can get the PFC converter done easily. However, there is a special situation needing the designer’s care, which is when the input is at high line and the operating frequency is 200 kHz. Ch1: Vin Ch2: DRV Ch3: Vout Ch4: Iin Figure 5. The Waveforms at 265 Vac, 300 W as Controlled by 200 kHz NCP1654 Ch1: Vin Ch2: VM Ch3: DRV Ch4: Iin Figure 4. Zoom−in with Waveforms at Peak of 265 Vac controller, the turn−off delay of MOSFET itself, and the delay caused by driver circuit etc. Depending on the design, the delay to turn off MOSFET could be in the range of 0.2 ms to 0.4 ms. As indicated in Figure 4, the PFC may operate at skip mode even at full load, which might produce audible noise. The skip mode at peak of the sinusoidal 265 Vac is caused by the fact that it exists several delay to turn off the power MOSFET, which include the propagation delay inside the http://onsemi.com 7 AND8322 If Vout is set at 390 V and the high line is 265 Vac, which is the existing design for most of cases, then the duty at peak of the sinusoidal input is: D+1* V in V out +1* 265 @ Ǹ2 390 + 3.9% of pulse width. It softens the skip mode operation reduces the audible noise. (eq. 26) RM2 When the operating frequency is 200 kHz, the on time at the peak of sinusoidal input is 0.2 ms. It is shorter than the total delay−off of MOSFET! In the end, PFC will go to the skip mode and might produce audible noise. To solve the audible noise, there are 2 possible ways: • Increase Vout and make the on time of MOSFET is above total delay−off of MOSFET. By solution 1, one can design the Vout by modifying the duty equation as follows: V out + + V in 1*D + RM1 t delay_off @ f op 265 @ Ǹ2 1 * 0.4 m @ 200k CM1 Optional Figure 6. Modified VM Pin Structure The design steps of the modified VM pin structure are proposed as follows: 1. Keep the total value of RM1 and RM2 equal to the original RM value. 2. Trim RM2 value in the range of 20% to 100% of RM1 to adjust the skip mode performance at high line. 3. Add CM2 about 10% of CM1 for filtering the signal of VM if needed. 4. Double check the performance at input ranging from 230 Vac to high line. Figure 7 shows the result after modification. It is denoted that there is still skip mode at peak of the sinusoidal input, but the audible noise is well−limited. V in 1 CM2 (eq. 27) + 407 V And then the PFC will keep operating continuously. The drawback of this solution is that there is less voltage margin concerning the bulk capacitor and the power devices. • Modify the skip mode operation, which can help reducing the audible noise. Refer to Figure 6, the modified VM pin structure. By inserting the RM2, part of the ripple on the inductor current join the modulation Ch1: Vin Ch2: DRV Ch4: Iin Figure 7. The Waveforms after Modifying the VM Pin Structure http://onsemi.com 8 AND8322 Summary Steps Components Formula 300 W Application Step 1: Coil Inductance, Bulk Capacitor and Power Silicon Select the maximum switching peak to peak ripple of the coil current Choose a value between 10 and 50% r = 36% r+ Coil inductance (L) L+ Bulk Capacitor (ripple voltage consideration) ǒ I coil,rms,max + ǒ C bulk u C bulk u Step 3: Input Voltage Sensing RboU1 + RboU2 + RboL RSENSE V out * V REF R fbL V REF Icoil,max = 6.4 A 180 mF / 450 V RfbL = 23.2 kW RfbU1 = 1.8 MW RfbU2 = 1.8 MW CFB = 100 pF V control R @ G EAR Z 1 ) sR ZC Z + fbL @ V out R fbL ) R fbU sR ZC Z(1 ) sR ZC P) CP = 0.22 mF CZ = 2.2 mF RZ = 12 kW Ǹ2 V ac,on * V BOH (R boU1 ) R boU2) + R boL V BOH Vac,on = 75 Vac RboL = 82.5 kW RboU1 = 3.3 MW RboU2 = 3.3 MW C BO [ 5 @ T Vin R boL Choose RSENSE so that its dissipation keeps reasonable, e.g. select RSENSE so that PRsense is less than 0.5% ⋅ Pout,max. R SENSE v 0.5% @ RCS RM Icoil,rms,max = 3.8 A CFB = 100 pF ~ 1 nF CBO Step 4: Current Sense Network Ǔ L = 650 mH 2P out @ t HOLD V out1 2 * V out2 2 (R fbU1 ) R fbU2) + CFB r P out,max 2 h @ V acLL P out dV pp,max @ w @ V out RfbU1 + RfbU2 + RfbL CP, CZ, RZ Ǔ P out,max h @ V acLL I coil,max + Ǹ2 1 ) Bulk Capacitor (Hold up time consideration) Step 2: Feedback Arrangement I in,max Ǹ2 V h @ V acLL 2 acLL 1* V out r @ f sw @ P out,max Maximum rms coil current Maximum coil current DI coil,pp R CS + R M + 70% @ h CM 9 RCS = 3.6 kW 185 mA 2pR CS @ DV CONTROL @ V REF @ V acLL Ǹ2 R SENSEK BOV outLLP out,max http://onsemi.com RSENSE = 0.1 W / 3 W (h @ V acLL) 2 P out,max R SENSE @ I coil,max CM [ 5 @ CBO = 0.47 mF 1 R Mf sw RM = 47 kW CM = 1 nF AND8322 TB2 1 390 V 2 C4 180 mF, 450 V + D1 TB3 1 MSR860G 2 SPP20N60S5 Q1 R1 C9 D2 10 k R2 C8 + +15 V 1N4148 R4 1.8 M 1.8 M R5 22 mF 0.1 mF 10 C10 100 pF R3 8 R6 R12 C12 12 k C5 5 220 nF NCP1654 IC1 0.1 2 2 VM GND 1 3 4 BO 650 mH 6 CS L1 7 Vcontrol 5 FB DRV VCC 23.2 k 2.2 mF R8 47 k R7 1 nF 3.6 k 0.1 mF GBU8J 600 V + 8A DB1 R9 R13 R10 R11 3.3 M 3.3 M 0 82.5 k C7 C3 0.47 mF − C2 0.47 mF L2 L3 2 x 6.8 mH 150 mH C1 0.47 mF 5 A Fuse F1 1 2 L AC Inlet C6 3 N TB1 Figure 8. 300 W Application Schematic http://onsemi.com 10 AND8322 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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