MC3423 Overvoltage Crowbar Sensing Circuit This overvoltage protection circuit (OVP) protects sensitive electronic circuitry from overvoltage transients or regulator failures when used in conjunction with an external “crowbar” SCR. The device senses the overvoltage condition and quickly “crowbars” or short circuits the supply, forcing the supply into current limiting or opening the fuse or circuit breaker. The protection voltage threshold is adjustable and the MC3423 can be programmed for minimum duration of overvoltage condition before tripping, thus supplying noise immunity. The MC3423 is essentially a “two terminal” system, therefore it can be used with either positive or negative supplies. http://onsemi.com MARKING DIAGRAMS 8 PDIP−8 P1 SUFFIX PLASTIC PACKAGE CASE 626 1 MC3423P1 AWL YYWW Features • Pb−Free Package is Available MC3423P1 = Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week MAXIMUM RATINGS Rating Differential Power Supply Voltage Sense Voltage (1) Sense Voltage (2) Symbol Value Unit VCC−VEE 40 Vdc VSense1 6.5 Vdc VSense2 6.5 Vact 7.0 Vdc Output Current IO 300 mA Operating Ambient Temperature Range TA 0 to +70 °C Operating Junction Temperature TJ 125 °C Tstg −65 to +150 °C Remote Activation Input Voltage Storage Temperature Range Vdc Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 8 8 1 SOIC−8 D SUFFIX PLASTIC PACKAGE CASE 751 3423 A L Y W 3423 ALYW 1 = Device Code = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS Vout Vin Current Limited DC Power Supply + Cout O. V. P. MC3423 VCC 1 8 Drive Output Sense 1 2 7 VEE Sense 2 3 6 Indicator Output Current 4 Source 5 Remote Activation (Top View) Figure 1. Simplified Application ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 5 1 Publication Order Number: MC3423/D MC3423 ELECTRICAL CHARACTERISTICS (5.0 V ≤ VCC − VEE ≤ 36 V, Tlow < TA , Thigh, unless otherwise noted.) Characteristics Supply Voltage Range Symbol Min Typ Max Unit VCC−VEE 4.5 − 40 Vdc Output Voltage (IO = 100 mA) VO VCC−2.2 VCC−1.8 − Vdc Indicator Output Voltage (IO(Ind) = 1.6 mA) VOL(Ind) − 0.1 0.4 Vdc Sense Trip Voltage (TA = 25°C) VSense1, VSense2 2.45 2.6 2.75 Vdc TCVS1 − 0.06 − %/°C IIH IIL − − 5.0 −120 40 −180 Temperature Coefficient of VSense1 (Figure 2) A Remote Activation Input Current (VIH = 2.0 V, VCC − VEE = 5.0 V) (VIL = 0.8 V, VCC − VEE = 5.0 V) Source Current ISource 0.1 0.2 0.3 mA Output Current Risetime (TA = 25°C) tr − 400 − mA/s Propagation Delay Time (TA = 25°C) tpd − 0.5 − s Supply Current ID − 6.0 10 mA NOTES: Tlow to Thigh = 0° to +70°C VCC 1 ISource 2 Sense 1 Vref 2.6V − 4 Current Source − + + − 8 + Output 7 VEE 3 Sense 2 5 6 Remote Activation Indicator Output Figure 2. Representative Block Diagram VCC 1 Switch 1 (A) 2 3 (B) Switch 2 VI 8 MC3423 4 7 Switch 1 Switch 2 VSense 1 Position A Closed VSense 2 Position B Open V 5 Ramp VI until output goes high; this is the VSense threshold. Figure 3. Sense Voltage Test Circuit http://onsemi.com 2 MC3423 * + F1 (+ Sense Lead) R1 Power Supply R2 Vtrip Vref 1 R1 2.6 V 1 R1 R2 R2 1 2 3 MC3423 4 7 5 R2 ≤ 10 k for minimum drift 8 To Load RG For minimum value of RG, see Figure 9. S1* *See text for explanation. (− Sense Lead) − Figure 4. Basic Circuit Configuration + C1 > (+ Sense Lead) RS VS–10 k 25 Vtrip Vref 1 R1 2.6 V 1 R R2 R RS R1 Q1 1 8 Power Supply MC3423 1N4740 10V + To Load 2 VS 3 4 10F 15V 7 5 RS (R1 + R2) 10F R1R2 C1 *R2 (− Sense Lead) *R2 ≤ 10 k Q1: Q1: Q1: Q1: Q1: Q1: VS ≤ 50 V; 2N6504 or equivalent VS ≤ 100 V; 2N6505 or equivalent VS ≤ 200 V; 2N6506 or equivalent VS ≤ 400 V; 2N6507 or equivalent VS ≤ 600 V; 2N6508 or equivalent VS ≤ 800 V; 2N6509 or equivalent − Figure 5. Circuit Configuration for Supply Voltage Above 36 V VCC Vtrip +VCC 0 R3 R1 1 2 Power Supply 6 MC3423 4 R2 VC 3 V10 Indication 8 Out VC Vref 0 RG VO 5 7 C VO 0 td VIO R3 ≥ Vtrip 10 mA td = Vref × C ≈ [12 × 103] C (See Figure 10) Isource Figure 6. Basic Configuration for Programmable Duration of Overvoltage Condition Before Trip http://onsemi.com 3 MC3423 APPLICATION INFORMATION Basic Circuit Configuration (+ Sense Lead) The basic circuit configuration of the MC3423 OVP is shown in Figure 3 for supply voltages from 4.5 V to 36 V, and in Figure 4 for trip voltages above 36 V. The threshold or trip voltage at which the MC3423 will trigger and supply gate drive to the crowbar SCR, Q1, is determined by the selection of R1 and R2. Their values can be determined by the equation given in Figures 3 and 4, or by the graph shown in Figure 8. The minimum value of the gate current limiting resistor, RG, is given in Figure 9. Using this value of RG, the SCR, Q1, will receive the greatest gate current possible without damaging the MC3423. If lower output currents are required, RG can be increased in value. The switch, S1, shown in Figure 3 may be used to reset the crowbar. Otherwise, the power supply, across which the SCR is connected, must be shut down to reset the crowbar. If a non current−limited supply is used, a fuse or circuit breaker, F1, should be used to protect the SCR and/or the load. The circuit configurations shown in Figures 3 and 4 will have a typical propagating delay of 1.0 s. If faster operation is desired, Pin 3 may be connected to Pin 2 with Pin 4 left floating. This will result in decreasing the propagating delay to approximately 0.5 s at the expense of a slightly increased TC for the trip voltage value. + 1 R1 Z1 Power Supply R2 2 MC3423 8 RG 5 4 3 1k 7 C (− Sense Lead) − Figure 7. Configuration for Programmable Duration of Overvoltage Condition Before Trip/With Immediate Trip at High Overvoltages Additional Features 1. Activation Indication Output An additional output for use as an indicator of OVP activation is provided by the MC3423. This output is an open collector transistor which saturates when the OVP is activated. In addition, it can be used to clock an edge triggered flip−flop whose output inhibits or shuts down the power supply when the OVP trips. This reduces or eliminates the heatsinking requirements for the crowbar SCR. Configuration for Programmable Minimum Duration of Overvoltage Condition Before Tripping In many instances, the MC3423 OVP will be used in a noise environment. To prevent false tripping of the OVP circuit by noise which would not normally harm the load, MC3423 has a programmable delay feature. To implement this feature, the circuit configuration of Figure 5 is used. In this configuration, a capacitor is connected from Pin 3 to VEE. The value of this capacitor determines the minimum duration of the overvoltage condition which is necessary to trip the OVP. The value of C can be found from Figure 10. The circuit operates in the following manner: When VCC rises above the trip point set by R1 and R2, an internal current source (Pin 4) begins charging the capacitor, C, connected to Pin 3. If the overvoltage condition disappears before this occurs, the capacitor is discharged at a rate ≅ 10 times faster than the charging rate, resetting the timing feature until the next overvoltage condition occurs. Occasionally, it is desired that immediate crowbarring of the supply occur when a high overvoltage condition occurs, while retaining the false tripping immunity of Figure 5. In this case, the circuit of Figure 6 can be used. The circuit will operate as previously described for small overvoltages, but will immediately trip if the power supply voltage exceeds VZ1 + 1.4 V. 2. Remote Activation Input Another feature of the MC3423 is its remote activation input, Pin 5. If the voltage on this CMOS/TTL compatible input is held below 0.8 V, the MC3423 operates normally. However, if it is raised to a voltage above 2.0 V, the OVP output is activated independent of whether or not an overvoltage condition is present. It should be noted that Pin 5 has an internal pullup current source. This feature can be used to accomplish an orderly and sequenced shutdown of system power supplies during a system fault condition. In addition, the activation indication output of one MC3423 can be used to activate another MC3423 if a single transistor inverter is used to interface the former’s indication output to the latter ’s remote activation input, as shown in Figure 7. In this circuit, the indication output (Pin 6) of the MC3423 on power supply 1 is used to activate the MC3423 associated with power supply 2. Q1 is any small PNP with adequate voltage rating. http://onsemi.com 4 MC3423 + 30 1 Power Supply #1 Typ 6 − R1 10k + 1 R2 = 2.7 k R1, RESISTANCE (k) Ω 7 Max 20 Min 10 Q1 Power Supply #2 5 0 0 5.0 10 15 20 VT, TRIP VOLTAGE (V) 1.0k 7 − 25 30 Figure 9. R1 versus Trip Voltage Figure 8. Circuit Configuration for Activating One MC3423 from Another 35 VCC , SUPPLY VOLTAGE (V) Note that both supplies have their negative output leads tied together (i.e., both are positive supplies). If their positive leads are common (two negative supplies) the emitter of Q1 would be moved to the positive lead of supply 1 and R1 would therefore have to be resized to deliver the appropriate drive to Q1. Crowbar SCR Considerations Referring to Figure 11, it can be seen that the crowbar SCR, when activated, is subject to a large current surge from the output capacitance, Cout. This capacitance consists of the power supply output caps, the load’s decoupling caps, and in the case of Figure 11A, the supply’s input filter caps. This surge current is illustrated in Figure 12, and can cause SCR failure or degradation by any one of three mechanisms: di/dt, absolute peak surge, or I2t. The interrelationship of these failure methods and the breadth of the applications make specification of the SCR by the semiconductor manufacturer difficult and expensive. Therefore, the designer must empirically determine the SCR and circuit elements which result in reliable and effective OVP operation. However, an understanding of the factors which influence the SCR’s di/dt and surge capabilities simplifies this task. RG(min) = 0 if VCC < 11 V 30 25 20 15 10 0 10 20 30 40 50 60 70 RG, GATE CURRENT LIMITING RESISTOR () 80 Figure 10. Minimum RG versus Supply Voltage C, CAPACITANCE (F) µ 1.0 1 2 3 5 7 1 0.1 0.01 0.001 di/dt As the gate region of the SCR is driven on, its area of conduction takes a finite amount of time to grow, starting as a very small region and gradually spreading. Since the anode current flows through this turned−on gate region, very high current densities can occur in the gate region if high anode currents appear quickly (di/dt). This can result in immediate destruction of the SCR or gradual degradation of its forward blocking voltage capabilities − depending on the severity of the occasion. 0.0001 0.001 1 5 2 1 0.01 0.1 td, DELAY TIME (ms) 1.0 Figure 11. Capacitance versus Minimum Overvoltage Duration http://onsemi.com 5 10 MC3423 (11A) Vin DC Power Supply + Cout OV Sense (11B) Vin Vout * DC Power Supply + Cout gate drive signal. A center−gate−fire SCR has more di/dt capability than a corner−gate−fire type, and heavily overdriving (3 to 5 times IGT) the SCR gate with a fast <1.0 s rise time signal will maximize its di/dt capability. A typical maximum number in phase control SCRs of less than 50 A(RMS) rating might be 200 A/s, assuming a gate current of five times IGT and < 1.0 s rise time. If having done this, a di/dt problem is seen to still exist, the designer can also decrease the di/dt of the current waveform by adding inductance in series with the SCR, as shown in Figure 13. Of course, this reduces the circuit’s ability to rapidly reduce the DC bus voltage and a tradeoff must be made between speedy voltage reduction and di/dt. Vout OV Sense *Needed if supply not current limited Figure 12. Typical Crowbar OVP Circuit Configurations l Surge Current If the peak current and/or the duration of the surge is excessive, immediate destruction due to device overheating will result. The surge capability of the SCR is directly proportional to its die area. If the surge current cannot be reduced (by adding series resistance − see Figure 13) to a safe level which is consistent with the systems requirements for speedy bus voltage reduction, the designer must use a higher current SCR. This may result in the average current capability of the SCR exceeding the steady state current requirements imposed by the DC power supply. lpk di dt Surge Due to Output Capacitor Current Limited Supply Output t A WORD ABOUT FUSING Before leaving the subject of the crowbar SCR, a few words about fuse protection are in order. Referring back to Figure 11A, it will be seen that a fuse is necessary if the power supply to be protected is not output current limited. This fuse is not meant to prevent SCR failure but rather to prevent a fire! In order to protect the SCR, the fuse would have to possess an I2t rating less than that of the SCR and yet have a high enough continuous current rating to survive normal supply output currents. In addition, it must be capable of successfully clearing the high short circuit currents from the supply. Such a fuse as this is quite expensive, and may not even be available. Figure 13. Crowbar SCR Surge Current Waveform RLead LLead ESR ESL Output Cap R L To MC3423 R & L EMPIRICALLY DETERMINED! Figure 14. Circuit Elements Affecting SCR Surge and di/dt CROWBAR SCR SELECTION GUIDE As an aid in selecting an SCR for crowbar use, the following selection guide is presented. The usual design compromise then is to use a garden variety fuse (3AG or 3AB style) which cannot be relied on to blow before the thyristor does, and trust that if the SCR does fail, it will fail short circuit. In the majority of the designs, this will be the case, though this is difficult to guarantee. Of course, a sufficiently high surge will cause an open. These comments also apply to the fuse in Figure 11B. The value of di/dt that an SCR can safely handle is influenced by its construction and the characteristics of the Device 2N6400 Series 2N6504 Series 2N1842 Series 2N2573 Series 2N681 Series MCR3935−1 Series MCR81−5 Series http://onsemi.com 6 IRMS IFSM Package 16 A 25 A 16 A 25 A 25 A 35 A 80 A 160 A 160 A 125 A 260 A 200 A 350 A 1000 A TO−220 Plastic TO−220 Plastic Metal Stud Metal TO−3 Type Metal Stud Metal Stud Metal Stud MC3423 ORDERING INFORMATION Device Operating Temperature Range MC3423D Package Shipping† SOIC−8 98 Units / Rail MC3423DG SOIC−8 (Pb−Free) 98 Units / Rail MC3423DR2 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel PDIP−8 1000 Units / Rail PDIP−8 (Pb−Free) 1000 Units / Rail MC3423DR2G TA = 0° to +70°C MC3423P1 MC3423P1G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 MC3423 PACKAGE DIMENSIONS PDIP−8 P1 SUFFIX CASE 626−05 ISSUE L 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 −B− 1 4 F −A− NOTE 2 L C J −T− N SEATING PLANE D H M K G 0.13 (0.005) M T A M B M http://onsemi.com 8 DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10 0.030 0.040 MC3423 SOIC−8 D SUFFIX CASE 751−07 ISSUE AE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 1 0.25 (0.010) M Y M 4 K −Y− G C N X 45 DIM A B C D G H J K M N S SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 MC3423 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 10 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC3423/D