Hot Swappable I2C-Bus and SMBus Bus Buffer

PCA9511A
Hot Swappable I2C-Bus and
SMBus Bus Buffer
The PCA9511A is a hot swappable I2C−bus and SMBus buffer that
allows I/O card insertion into a live backplane without corrupting the
data and clock buses. Control circuitry prevents the backplane from
being connected to the card until a stop command or bus idle occurs on
the backplane without bus contention on the card. When the
connection is made, the PCA9511A provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
The PCA9511A rise time accelerator circuitry allows the use of
weaker DC pull−up currents while still meeting rise time
requirements. The PCA9511A incorporates a digital ENABLE input
pin, which enables the device when asserted HIGH and forces the
device into a low current mode when asserted LOW, and an
open−drain READY output pin, which indicates that the backplane
and card sides are connected together (HIGH) or not (LOW).
During insertion, the PCA9511A SDA and SCL lines are
precharged to 1 V to minimize the current required to charge the
parasitic capacitance of the chip.
Features
• Bidirectional Buffer for SDA and SCL Lines Increases Fan−Out and
•
•
•
•
•
•
•
•
•
•
•
•
Prevents SDA and SCL Corruption During Live Board Insertion and
Removal from Multipoint Backplane Systems
DV/Dt Rise Time Accelerators on all SDA and SCL lines
Active HIGH ENABLE Input
Active HIGH READY Open−Drain Output
High−Impedance SDA and SCL for VCC = 0 V
1 V precharge on all SDA and SCL Lines
Supports Clock Stretching and Multiple Master
arbitration/Synchronization
VCC Operating Range: 2.7 V to 5.5 V
I2C and SMBus SCL Clock Frequency up to 1 MHz
Alternate Features for
PCA9510A/PCA9512A/PCA9513A/PCA9514A
Available in: Micro8, SOIC−8
ESD Performance: 8000 V HBM, 600 V MM, 2000V CDM
These are Pb−Free Devices
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MARKING
DIAGRAMS
Micro8]
DM SUFFIX
CASE 846A
8
9511
AYWG
G
1
8
SOIC−8
CASE 751
8
1
1
A
L
M
Y
W
G
9511
AYWW
G
= Assembly Location
= Wafer Lot
= Date Code
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
Applications
• cPCI, VME, AdvancedTCA cards and other multipoint backplane
cards that are required to be inserted or removed from an operating
system
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 0
1
Publication Order Number:
PCA9511A/D
PCA9511A
FEATURE SELECTION
FEATURE SELECTION CHART
Feature
PCA9510A
PCA9511A
PCA9512A
PCA9513A
PCA9514A
idle detect
Yes
Yes
Yes
Yes
Yes
high−impedance SDA, SCL pins for VCC = 0 V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
rise time accelerator circuitry on SDAn and SCLn
lines
rise time accelerator circuitry hardware disable pin
for lightly loaded systems
Yes
rise time accelerator threshold 0.8 V versus 0.6 V
improves noise margin
ready open−drain output
Yes
Yes
two VCC pins to support 5 V to 3.3 V level
translation with improved noise margins
Yes
1 V precharge on all SDA and SCL lines
In only
Yes
Yes
Yes
92 mA current source on SCLIN and SDAIN for
PICMG applications
BLOCK DIAGRAM
Figure 1. Block Diagram of PCA9511A
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PCA9511A
PIN ASSIGNMENT
PCA9511A
Figure 2. SOIC8 / Micro−8
PIN DESCRIPTIONS
Symbol
Pin
Description
ENABLE
1
Chip enable. Grounding this input puts the part in a low current (< 1 mA) mode. It also disables the
rise time accelerators, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT.
SCLOUT
2
Serial Clock Output to and from the SCL bus on the card
SCLIN
3
Serial Clock Input to and from the SCL bus on the backplane
GND
4
Ground. Connect this pin to a ground plane for best results.
READY
5
Open−drain output which pulls LOW when SDAIN and SCLIN are disconnected from SDAOUT
and SCLOUT, and goes HIGH when the two sides are connected Port.
SDAIN
6
Serial Data Input to and from the SDA bus on the backplane
SDAOUT
7
Serial Data Output to and from the SDA bus on the card
VCC
8
Supply Voltage
FUNCTIONAL DESCRIPTION
disturbances that result from inserting a card into the
backplane where the backplane and the card are at opposite
logic levels.
Please refer to Figure 1 “Block Diagram of PCA9511A”.
Start−up
An undervoltage / initialization circuit holds the parts in
a disconnected state which presents high−impedance to all
SDA and SCL pins during power−up. A LOW on the
ENABLE pin also forces the parts into the low current
disconnected state when the ICC is essentially zero. As the
power supply is brought up and the ENABLE is HIGH or the
part is powered and the ENABLE is taken from LOW to
HIGH, it enters an initialization state where the internal
references are stabilized and the precharge circuit is enabled.
At the end of the initialization state, the ‘Stop Bit And Bus
Idle’ detect circuit is enabled. With the ENABLE pin HIGH
long enough to complete the initialization state (ten) and
remaining HIGH when all the SDA and SCL pins have been
HIGH for the bus idle time or when all pins are HIGH and
a STOP condition is seen on the SDAIN and SCLIN pins,
SDAIN is connected to SDAOUT and SCLIN is connected
to SCLOUT. The 1 V precharge circuitry is activated during
the initialization and is deactivated when the connection is
made. The precharge circuitry pulls up the SDA and SCL
pins to 1 V through individual 100 kW nominal resistors.
This precharges the pins to 1 V to minimize the worst case
Connect Circuitry
Once the connection circuitry is activated, the behavior of
SDAIN and SDAOUT, as well as SCLIN and SCLOUT,
become identical with each acting as a bidirectional buffer
that isolates the input capacitance from the output bus
capacitance while communicating the logic levels. A LOW
forced on either SDAIN or SDAOUT will cause the other
pin to be driven to a LOW by the part. The same is also true
for the SCL pins. Noise between 0.7VCC and VCC is
generally ignored because a falling edge is only recognized
when it falls below 0.7 VCC with a slew rate of at least
1.25 V/ms. When a falling edge is seen on one pin, the other
pin in the pair turns on a pull−down driver that is referenced
to a small voltage above the falling pin. The driver will pull
the pin down at a slew rate determined by the driver and the
load initially, because it does not start until the first falling
pin is below 0.7 VCC. The first falling pin may have a fast or
slow slew rate, if it is faster than the pull down slew rate, then
the initial pull−down rate will continue. If the first falling pin
has a slow slew rate, then the second pin will be pulled down
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PCA9511A
LOW level at the signal origination end (master) is
dependent upon the load, and the only specification point is
that the I2C−bus specification of 3 mA will produce VOL <
0.4 V, although if lightly loaded, the VOL may be ~0.1 V.
Assuming VOL = 0.1 V and Voffset = 0.1 V, the level after four
buffers would be 0.5 V, which is only about 0.1 V below the
threshold of the rising edge accelerator (about 0.6 V). With
great care, a system with four buffers may work, but as the
VOL moves up from 0.1 V, noise or bounces on the line will
result in firing the rising edge accelerator, thus introducing
false clock edges. Generally, it is recommended to limit the
number of buffers in series to two, and to keep the load light
to minimize the offset.
The PCA9510A (rise time accelerator is permanently
disabled) and the PCA9512A (rise time accelerator can be
turned off) are a little different with the rise time accelerator
turned off because the rise time accelerator will not pull the
node up, but the same logic that turns on the accelerator turns
the pull−down off. If the VIL is above ~0.6 V and a rising
edge is detected, the pull−down will turn off and will not turn
back on until a falling edge is detected.
at its initial slew rate only until it is just above the first pin
voltage, then they will both continue down at the slew rate
of the first.
Once both sides are LOW, they will remain LOW until all
the external drivers have stopped driving LOWs. If both
sides are being driven LOW to the same value, for instance,
10 mV by external drivers, which is the case for clock
stretching and is typically the case for acknowledge, and one
side external driver stops driving that pin will rise until the
internal driver pulls it down to the offset voltage. When the
last external driver stops driving a LOW, that pin will rise up
and settle out just above the other pin, as both rise together
with a slew rate determined by the internal slew rate control
and the RC time constant. As long as the slew rate is at least
1.25 V/ms, when the pin voltage exceeds 0.6 V for the
PCA9511A, the rise time accelerator’s circuits are turned on
and the pull−down driver is turned off.
Maximum Number of Devices in Series
Each buffer adds about 0.1 V dynamic level offset at 25_C
with the offset larger at higher temperatures. Maximum
offset (Voffset) is 0.150 V with a 10 kW pull−up resistor. The
Figure 3. System with 3 Buffers Connected to Common Node
buffer B. The node on the input of buffer A will go HIGH as
will the input node of buffer C. After the common node
voltage is stable for a while, the rising edge accelerators will
turn off and the common node will return to ~0.5 V because
the buffer B is still on. The voltage at both the Master and
Slave C nodes would then fall to ~0.6 V until Slave B turned
off. This would not cause a failure on the data line as long as
the return to 0.5 V on the common node (~0.6 V at the Master
and Slave C) occurred before the data setup time. If this were
the SCL line, the parts on buffer A and buffer C would see
a false clock rather than a stretched clock, which would
cause a system error.
Consider a system with three buffers connected to a
common node and communication between the Master and
Slave B that are connected at either end of buffer A and
buffer B in series as shown in Figure 3. Consider if the VOL
at the input of buffer A is 0.3 V and the VOL of Slave B (when
acknowledging) is 0.4 V, with the direction changing from
Master to Slave B and then from Slave B to Master. Before
the direction change, you would observe VIL at the input of
buffer A of 0.3 V and its output, the common node, is ~0.4
V. The output of buffer B and buffer C would be ~0.5 V, but
Slave B is driving 0.4 V, so the voltage at Slave B is 0.4 V.
The output of buffer C is ~0.5 V. When the Master
pull−down turns off, the input of buffer A rises and so does
its output, the common node, because it is the only part
driving the node. The common node will rise to 0.5 V before
buffer B’s output turns on, if the pull−up is strong, the node
may bounce. If the bounce goes above the threshold for the
rising edge accelerator ~0.6 V, the accelerators on both
buffer A and buffer C will fire contending with the output of
Propagation Delays
The delay for a rising edge is determined by the combined
pull−up current from the bus resistors and the rise time
accelerator current source and the effective capacitance on
the lines. If the pull−up currents are the same, any difference
in rise time is directly proportional to the difference in
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PCA9511A
sinking 3 mA while holding 0.4 V on the pin. Connect a
resistor of 10 kW to VCC to provide the pull−up.
capacitance between the two sides. The tPLH may be
negative if the output capacitance is less than the input
capacitance and would be positive if the output capacitance
is larger than the input capacitance, when the currents are the
same.
The tPHL can never be negative because the output does
not start to fall until the input is below 0.7 VCC, and the
output turn on has a non−zero delay, and the output has a
limited maximum slew rate, and even if the input slew rate
is slow enough that the output catches up, it will still lag the
falling voltage of the input by the offset voltage. The
maximum tPHL occurs when the input is driven LOW with
zero delay and the output is still limited by its turn−on delay
and the falling edge slew rate. The output falling edge slew
rate is a function of the internal maximum slew rate which
is a function of temperature, VCC and process, as well as the
load current and the load capacitance.
ENABLE Low Current Disable
Grounding the ENABLE pin disconnects the backplane
side from the card side, disables the rise time accelerators,
drives READY LOW, disables the bus precharge circuitry,
and puts the part in a low current state. When the pin voltage
is driven all the way to VCC, the part waits for data
transactions on both the backplane and card sides to be
complete before reconnecting the two sides.
Resistor Pull−Up Value Selection
The system pull−up resistors must be strong enough to
provide a positive slew rate of 1.25 V/ms on the SDA and
SCL pins, in order to activate the boost pull−up currents
during rising edges. Choose maximum resistor value using
the formula given below:
Rise Time Accelerators
R PU v 800
During positive bus transitions, a 2 mA current source is
switched on to quickly slew the SDA and SCL lines HIGH
once the input level of 0.6 V for the PCA9511A is exceeded.
The rising edge rate should be at least 1.25 V/ms to guarantee
turn on of the accelerators. The built−in DV/Dt rise time
accelerators on all SDA and SCL lines require the bus
pull−up voltage and supply voltage (VCC) to be the same.
ǒ
10 3
Ǔ
V CC(min) * 0.6
C
where RPU is the pull−up resistor value in W, VCC(min) is the
minimum VCC voltage in volts, and C is the equivalent bus
capacitance in picofarads (pF).
In addition, regardless of the bus capacitance, always choose
RPU ≤ 65.7 kW for VCC = 5.5 V maximum, RPU ≤ 45 kW for
VCC = 3.6 V maximum. The start−up circuitry requires logic
HIGH voltages on SDAOUT and SCLOUT to connect the
backplane to the card, and these pull−up values are needed
to overcome the precharge voltage. See the curves in
Figures 4 and 5 for guidance in resistor pull−up selection.
READY Digital Output
This pin provides a digital flag which is LOW when either
ENABLE is LOW, or the start−up sequence described
earlier in this section has not been completed. READY goes
HIGH when ENABLE is HIGH and start−up is complete.
The pin is driven by an open−drain pull−down capable of
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PCA9511A
(1) Unshaded area indicates recommended pull−up, for rise time < 300 ns, with PCA9511A.
(2) Rise time without PCA9511A.
Figure 4. Bus Requirements for 3.3 V Systems
(1) Unshaded area indicates recommended pull−up, for rise time < 300 ns, with PCA9511A.
(2) Rise time without PCA9511A.
Figure 5. Bus Requirements for 5 V Systems
Hot Swapping and Capacitance Buffering Application
and fall time requirements difficult to meet. Placing a bus
buffer on the edge of each card, however, isolates the card
capacitance from the backplane. For a given I/O card, the
PCA9511A drives the capacitance of everything on the card
and the backplane must drive only the capacitance of the bus
buffer, which is less than 10 pF, the connector, trace, and all
additional cards on the backplane.
Figures 6 through 9 illustrate the usage of the PCA9511A
in applications that take advantage of both its hot swapping
and capacitance buffering features. In all of these
applications, note that if the I/O cards were plugged directly
into the backplane, all of the backplane and card
capacitances would add directly together, making rise time
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PCA9511A
Remark: The PCA9511A can be used in any combination depending on the number of rise time accelerators
that are needed by the system. Normally only one PCA9511A would be required per bus.
Figure 6. Hot Swapping multiple I/O Cards into a Backplane using the PCA9511A in a cPCI, VME and
AdvancedTCA System
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PCA9511A
Figure 7. Hot Swapping Multiple I/O Cards into a Backplane Using the PCA9511A in a PCI System
Figure 8. Repeater / Bus Extender Application using the PCA9511A
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PCA9511A
VCC > VCC_LOW
Rdrop is the line loss of VCC in the backplane.
Figure 9. System with Disparate VCC Voltages
Figure 10. Typical Application
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PCA9511A
MAXIMUM RATINGS
Symbol
VCC
Vn
Value
Unit
Supply Voltage
Parameter
−0.5 to +7.0
V
Input / Output Voltage
SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE
−0.5 to +7.0
V
II
Input Current
±20
mA
IO
Output Current
±50
mA
ICC
DC Supply Current
±100
mA
IGND
DC Ground Current
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
150
°C
qJA
Thermal Resistance
SOIC8 (Note 1)
Micro8
146
205
°C/W
PD
Power Dissipation in Still Air at 85°C
SOIC8
Micro8
856
609
mW
MSL
FR
VESD
ILATCHUP
Moisture Sensitivity
Level 1
Flammability Rating Oxygen Index: 28 to 34
ESD Withstand Voltage
UL 94 V−0 @ 0.125 in
Human Body Mode (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Latchup Performance Above VCC and Below GND at 125°C (Note 5)
> 8000
> 600
> 2000
V
±100
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm by 1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22−A114−A.
3. Tested to EIA / JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA / JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Positive DC Supply Voltage
Vn
Input / Output Voltage
TA
Operating Free−Air Temperature
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Min
Max
Unit
2.7
5.5
V
0
5.5
V
−40
+85
°C
PCA9511A
CHARACTERISTICS VCC = 2.7 V to 5.5 V, unless otherwise specified.
TA = −405C to +855C
Typ
Max
Unit
VCC = 5.5 V;
VSDAIN = VSCLIN = 0 V
3.5
6
mA
VENABLE = 0 V;
All other pins at VCC or GND
0.1
Parameter
Symbol
Conditions
Min
SUPPLIES
ICC (Note 6)
ICC(sd)
Supply Current
Shutdown Mode Supply Current
mA
START−UP CIRCUITRY
Vpch (Note 6)
Precharge Voltage
VIH(ENABLE)
High−Level Input Voltage
VIL(ENABLE)
Low−Level Input Voltage
II(ENABLE)
Input Current on pin ENABLE
SDA, SCL Floating
0.8
1.1
1.2
0.7 x
VCC
VENABLE = 0 V to VCC
V
V
±0.1
0.3 x
VCC
V
±1
mA
ten (Note 7)
Enable Time
110
tidle(READY)
(Note 6)
Bus Idle Time to READY Active
tdis(EN−RDY)
Disable Time (ENABLE to READY)
30
ns
tstp(READY)
(Note 8)
SDAIN to READY delay after STOP
1.2
ms
tREADY (Note 8)
SCLOUT/SDAOUT to READY delay
0.8
ms
mA
50
105
ms
200
ms
ILZ(READY)
Off−State Leakage Current on pin
READY
VENABLE = VCC
±0.3
CI(ENABLE)
(Note 9)
Input Capacitance on pin ENABLE
VI = VCC or GND
1.9
4
pF
CO(READY)
(Note 9)
Input Capacitance on pin ENABLE
VI = VCC or GND
2.5
4
pF
VOL(READY)
(Note 6)
Low−Level Output Voltage on pin
READY
0.4
V
VENABLE = VCC; Ipu = 3 mA
RISE TIME ACCELERATORS
Positive transition on SDA, SCL;
VCC = 2.7 V;
Slew rate = 1.25 V/ms
1
2
Offset Voltage
10 kW to VCC on SDA, SCL;
VCC = 3.3 V
0
110
tPLH
Low to High Propagation Delay
SCL to SCL and SDA to SDA;
10 kW to VCC; CL = 100 pF
each side
0
ns
tPHL
High to Low Propagation Delay
SCL to SCL and SDA to SDA;
10 kW to VCC; CL = 100 pF
each side
70
ns
Input Leakage Current
SDAn, SCLn pins; VCC = 5.5 V
Itrt(pu)
(Notes 10, 11)
Transient Boosted Pull−up Current
mA
INPUT−OUTPUT CONNECTION
Voffset
(Notes 6, 12, 13)
ILI
CI(SCL/SDA)
(Note 9)
VOL (Note 6)
SCL and SDA Input Capacitance
Low−Level Output Voltage
5
VI = 0 V; SDAn, SCLn pins;
Isink = 3 mA, VCC = 2.7 V
175
mV
±1
mA
7
pF
0.4
V
6. This specification applies over the full operating temperature range.
7. The enable time can slow considerably for some parts when temperature is < −20°C.
8. Delays that can occur after ENABLE and/or idle times have passed.
9. Guaranteed by design, not production tested.
10. Itrt(pu) varies with temperature and VCC voltage, as shown in the “Typical performance characteristics” section.
11. Input pull−up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage
to the positive supply rail.
12. The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function
of the pull−up resistor and VCC voltage is shown in the “Typical performance characteristics” section.
13. Force VSDAIN = VSCLIN = 0.1 V, tie SDAOUT and SCLOUT through 10 kW resistor to VCC and measure the SDAOUT and SCLOUT output.
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PCA9511A
SYSTEM CHARACTERISTICS VCC = 2.7 V to 5.5 V, unless otherwise specified.
TA = −405C to +855C
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
0
400
0
1000
kHz
fSCL
(Note 14)
SCL Clock Frequency
tBUF
(Note 14)
Bus Free Time Between a
STOP and START Condition
1.3
0.5
ms
tHD;STA
(Note 14)
Hold Time (Repeated)
START Condition
0.6
0.26
ms
tSU;STA
(Note 14)
Setup Time for a Repeated
START Condition
0.6
0.26
ms
tSU;STO
(Note 14)
Setup Time for STOP
Condition
0.6
0.26
ms
tHD;DAT
(Note 14)
Data Hold Time
300
120
ns
tSU;DAT
(Note 14)
Data Setup Time
100
50
ns
tLOW
(Note 14)
LOW Period of SCL
1.3
0.5
ms
tHIGH
(Note 14)
HIGH Period of SCL
0.6
0.26
ms
tf
(Note 14)
Fall Time of SDA and SCL
20 + 0.1 x Cb
(Note 15)
300
−
120
ns
tr
(Note 14)
Rise Time of SDA and SCL
20 + 0.1 x Cb
(Note 15)
300
−
120
ns
14. Guaranteed by design, not production tested.
15. Cb = total capacitance of one bus line in pF.
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PCA9511A
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11. ICC vs. Temperature
Figure 12. Itrt(pu) vs. Temperature
Figure 13. Input/Out tPHL vs. Temperature
Figure 14. Connection Circuitry VO − VI
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PCA9511A
TIMING DIAGRAMS
Figure 15. Timing for ten, tidle(READY) and tdis
Figure 16. tstp(READY) That Can Occur After ten
Figure 17. tstp(READY) Delay that Can Occur After ten and tidle(READY)
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PCA9511A
TEST SETUP
Figure 18. Test Circuitry for Switching Times
ORDERING INFORMATION
Device
Package
Shipping
PCA9511ADR2G
In Development
SOIC8
(Pb−Free)
3000 / Tape & Reel
PCA9511ADMR2G
Micro−8
(Pb−Free)
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PCA9511A
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE J
D
HE
PIN 1 ID
−T−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
E
e
b 8 PL
0.08 (0.003)
M
T B
S
A
DIM
A
A1
b
c
D
E
e
L
HE
S
SEATING
PLANE
A
0.038 (0.0015)
A1
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
L
c
RECOMMENDED
SOLDERING FOOTPRINT*
8X
8X
0.48
0.80
5.25
0.65
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
16
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
PCA9511A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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