Spice Simulation Circuit

RATIO_AUX = -0.1
RATIO_POW = -0.055
D1
1N5822
4
Vout
12
10
Rser
100m
R1
1
C6
1nF
∆
Vclamp
R6
100k
6
Icoil
1
Aux
L1
1.9m
17
C1
470uF
IC = 6.2
Rload
12
Aux
5
D2
MUR160
D3
1N4934
Lleak
10uH
R8
220
14
11
X7
MOC8101
IDrain
Aux
R3
22k
ZCD
X1
MC33364D2
15
FB
13
2
21
1
8
2
7
3
6
4
MC33364
Vdrain
D4
1N752
Vcc
8
X2
MTP2N60E
18
5
Vgs
3
CVcc
22uF
IC = 16
∆
Vin
300
Vref
FB
FB
R9
270
Igate
Vsense
7
C2
10nF
Rsense
2.2
* ON Semiconductor
* MC33364 model developed by Christophe BASSO, Toulouse (FRANCE)
* e-mail: [email protected]
* INTUSOFT’s IsSpice4 compatible
*
* These models account for the various propagation delays and
* timers, except the internal 100ms re-start delay which has
* purposely NOT been included.
*
* Last modified: 8/26/99