MC33364 Critical Conduction GreenLinet SMPS Controller The MC33364 series are variable frequency SMPS controllers that operate in the critical conduction mode. They are optimized for high density power supplies requiring minimum board area, reduced component count, and low power dissipation. Integration of the high voltage startup saves approximately 0.7 W of power compared to the value of the resistor bootstrapped circuits. Each MC33364 features an on--board reference, UVLO function, a watchdog timer to initiate output switching, a zero current detector to ensure critical conduction operation, a current sensing comparator, leading edge blanking, a CMOS driver and cycle--by--cycle current limiting. The MC33364D1 has an internal 126 kHz frequency clamp. The MC33364D2 is available without an internal frequency clamp. The MC33364D has an internal 126 kHz frequency clamp which is pinned out, so that the designer can adjust the clamp frequency by connecting appropriate values of resistance. Features http://onsemi.com MARKING DIAGRAMS 8 8 1 SO--8 D1, D2 SUFFIX CASE 751 1 16 SO--16 D SUFFIX CASE 751K 16 1 x A WL Y W, WW G or G Package MC33364D1G MC33364D1R2G MC33364D2G MC33364D2R2G MC33364DG MC33364DR2G Shipping† 2500 Units / Tape & Reel 96 Units / Rail Zero Current 1 Current Sense 2 8 Line 7 VCC Voltage FB 3 6 Gate Drive Vref 4 5 GND (Top View) 2500 Units / Tape & Reel SO--16 (Pb--Free) 1 or 2 Assembly Location Wafer Lot Year Work Week Pb--Free Package MC33364D1 MC33364D2 96 Units / Rail SO--8 (Pb--Free) = = = = = = PIN CONNECTIONS ORDERING INFORMATION Device MC33364D AWLYWWG 1 Lossless Off--Line Startup Leading Edge Blanking for Noise Immunity Watchdog Timer to Initiate Switching Operating Temperature Range --25C to +125C Shutdown Capability Over Temperature Protection Optional/Adjustable Frequency Clamp to Limit EMI This is a Pb--Free and Halide--Free Device M64Dx ALYW G 48 Units / Rail 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MC33364D 16 Line Zero Current 1 N/C 2 Current Sense 3 Voltage FB 4 13 N/C N/C Vref 5 12 Vcc 6 11 Gate Drive N/C 7 10 P GND Freq Clamp 8 9 A GND (Top View) Semiconductor Components Industries, LLC, 2010 November, 2010 -- Rev. 18 1 Publication Order Number: MC33364/D MC33364 Vcc Vref Line Startup Vref regulator UVLO turn on Vref turn on + -- UVLO + -- 15V/ 8.1V -+ ZCD Vref 10V 15V/ 7.6V UVLO 1.2V/ 1.0V + -- Thermal Shutdown 5k 45k Vcc 15k Reset 15V/ var Watchdog Timer FB Vcc R CS R -+ LEB Level Q SNA S Gate P Gnd 0.1V A Gnd Frequency Clamp FC Figure 1. Representative Block Diagram Input AC Voltage Output Voltage MC33364D ZCD Line CS FB FC Vcc Drive P Gnd A Gnd R1 R2 Vref Rsense Figure 2. Typical Application Circuit http://onsemi.com 2 MC33364 Startup circuit is charging the VCC capacitor Startup circuit turns off when VCC is 15V 15V Supply Voltage, VCC 8.1V VT (3.5 to 6V) 5V Startup circuit turns on when VCC reaches the threshold VT Reference Voltage, Vref 0V Vref regulator turns on when VCC reaches 15V Vref falls faster than VCC since Vref capacitor is much smaller than VCC capacitor Vref regulator turns off when VCC falls below 8.1 V Maximum drain current is limited to 1.15V / Rsense Drain Current 0A Switching stops when Vref falls below 3.7V Switching starts when Vref reaches 5V Figure 3. Timing Diagram in Fault Condition Criticial Mode Discontinous Conduction Mode Output Current No load Maximum drain current is limited to 1.15V/ Rsense Drain Current LEB toff(min) Secondary Side Diode Current Drain Voltage Vin 10V Voltage at ZCD 0.7V ZCD is ignored during minimum off--time limit Figure 4. Timing Diagram in Normal Condition http://onsemi.com 3 MC33364 PIN DESCRIPTION Pin Function Description 1 (1) Zero Current Detect The ZCD Pin ensures critical conduction mode. ZCD monitors the voltage on the auxiliary winding, during the demagnetization phase of the transformer, comparing it to an internal reference. The ZCD sets the latch for the output driver. 3 (2) Current Sense The Current Sense Pin monitors the current in the power switch by measuring the voltage across a resistor. Leading Edge Blanking is utilized to prevent false triggering. The voltage is compared to a resistor divider connected to the Voltage Feedback Pin. A 110 mV voltage off--set is applied to compensate the natural optocoupler saturation voltage. 4 (3) Voltage Feedback 6 (4) Vref 8 (NA) Frequency Clamp 9 (5) A GND This pin is the ground for the internal circuitry excluding the gate drive stage. 10 (5) P GND This pin is the ground for the gate drive stage. 11 (6) Gate Drive 12 (7) VCC Provides the voltage for all internal circuitry including the gate drive stage and Vref. This pin has Undervoltage Lockout with hysteresis. 16 (8) Line The Line Pin provides the initial power to the VCC pins. Internally the line pin is a high voltage current source, eliminating the need for an external startup network. NOTE: The Voltage Feedback Pin is typically connected to the collector of the optocoupler for feedback from the isolated secondary output. The Feedback is connected to the Vref Pin via a 5 k resistor providing bias for the external optocoupler. The Vref Pin is a buffered internal 5.0 V reference with Undervoltage Lockout. The Frequency Clamp Pin ensures a minimum off--time value, typically 6.9 ms. It prevents the MOSFET from restarting within a fixed (33364D1) or adjustable (33364D) delay. The minimum off--time is disabled in the 33364D2. Therefore the maximum switching frequency cannot exceed 1/(TON + TOFFmin). The gate drive is the output to drive the gate of the power MOSFET. For further information please refer to the following Application Notes; AN1594: Critical Conduction Mode, Flyback Switching Power Supply Using the MC33364. AN1681: How to keep a Flyback Switch--Mode Power Supply Stable with a Critical--Mode Controller. MAXIMUM RATINGS (TA = 25C, unless otherwise noted.) Symbol Value Unit Power Supply Voltage (Operating) VCC 16 V Line Voltage VLine 700 V Current Sense, Compensation, Voltage Feedback, Restart Delay and Zero Current Input Voltage Vin1 --1.0 to +10 V Zero Current Detect Input Iin 5.0 mA Restart Diode Current Iin 5.0 mA Rating Power Dissipation and Thermal Characteristics D1 and D2 Suffix, Plastic Package Case 751 Maximum Power Dissipation @ TA = 70C PD 450 mW RθJA 178 C/W PD 550 mW RθJA 145 C/W TJ 150 C Operating Ambient Temperature TA --25 to +125 C Storage Temperature Range Tstg --55 to +150 C Thermal Resistance, Junction--to--Air D Suffix, Plastic Package Case 751B--05 Maximum Power Dissipation @ TA = 70C Thermal Resistance, Junction--to--Air Operating Junction Temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: ESD data available upon request. http://onsemi.com 4 MC33364 ELECTRICAL CHARACTERISTICS (VCC = 15.5 V, for typical values TA = 25C, for min/max values TJ = --25 to 125C) Characteristic Symbol Min Typ Max Unit VOLTAGE REFERENCE Reference Output Voltage (IOut = 0 mA, TJ = 25C) Vref 4.90 5.05 5.20 V Line Regulation (VCC = 10 V to 20 V) Regline -- 2.0 50 mV Load Regulation (IOut = 0 mA to 5.0 mA) Regload -- 0.3 50 mV Maximum Vref Output Current IO -- 5 -- mA Reference Undervoltage Lockout Threshold Vth -- 4.5 -- V Input Threshold Voltage (Vin Decreasing) Vth 0.9 1.0 1.1 V Hysteresis (Vin Decreasing) VH -- 200 -- mV Input Clamp Voltage -- High State (IDET = 3.0 mA) Input Clamp Voltage -- Low State (IDET = --3.0 mA) VIH VIL 9.0 --1.1 10.33 --0.75 12 0.5 V Input Bias Current (VCS = 0 to 2.0 V) IIB --0.5 0.02 0.5 mA Built In Offset VIO 50 108 170 mV ZERO CURRENT DETECTOR CURRENT SENSE COMPARATOR Feedback Pin Input Range VFB 1.1 1.24 1.4 V Feedback Pin to Output Delay tDLY 100 232 400 ns Source Resistance (Drive = 0 V, VGate = VCC -- 1.0 V) Sink Resistance (Drive = VCC, VGate = 1.0 V) ROH ROL 10 5 36 11 70 25 Ω Ω Output Voltage Rise Time (25% -- 75%) (CL = 1.0 nF) tr -- 67 150 ns DRIVE OUTPUT Output Voltage Fall Time (75% -- 25%) (CL = 1.0 nF) Output Voltage in Undervoltage (VCC = 7.0 V, ISink = 1.0 mA) tf -- 28 50 ns VO(UV) -- 0.01 0.03 V tPHL(in/out) -- 250 -- ns Tsd TH --- 180 50 --- C tDLY 200 360 700 ms LEADING EDGE BLANKING Delay to Current Sense Comparator Input (VFB = 2.0 V, VCS = 0 V to 4.0 V step, CL = 1.0 nF) THERMAL SHUTDOWN Shutdown (Junction Temperature Increasing) Hysteresis (Junction Temperature Decreasing) TIMER Watchdog Timer UNDERVOLTAGE LOCKOUT Startup Threshold (VCC Increasing) Minimum Operating Voltage After Turn--On (VCC Decreasing) Vth(on) 14 15 16 V VShutdown 6.5 7.6 8.5 V fmax 104 126 145 kHz FREQUENCY CLAMP Internal FC Function (pin open) Internal FC Function (pin grounded) fmax 400 564 800 kHz Frequency Clamp Input Threshold Vth(FC) 1.89 1.95 2.01 V Frequency Clamp Control Current Range (Sink) IControl 30 70 110 mA Td 3.5 5.0 6.5 ms Line Startup Current (VLine = 50 V) (VCC = Vth(on) -- 1.0 V) Restart Delay Time ILine tDLY 5.0 8.5 100 12 mA ms Line Pin Leakage (VLine = 500 V) ILine 0.5 32 70 mA Line Startup Current (VCC = 0 V, VLine = 50 V) ILine 6.0 10 12 mA ICC 1.5 2.75 4.5 mA ICC Off 300 544 800 mA Dead Time (FC pin = 1.7 V) TOTAL DEVICE VCC Dynamic Operating Current (50 kHz, CL = 1.0 nF) VCC Off State Consumption (VCC = 11 V) http://onsemi.com 5 MC33364 30 20 t DLY, WATCHDOG TIME DELAY ( s) 25 OUTPUT VOLTAGE (V) 500 VCC = 14 V CL = 1000 pF TA = 25C 15 10 5.0 0 --5.0 350 --25 0 25 50 75 100 5.0 ms/DIV TA, AMBIENT TEMPERATURE (C) Figure 5. Drive Output Waveform Figure 6. Watchdog Timer Delay versus Temperature R JA(t), THERMAL RESISTANCE JUNCTION--TO--AIR ( C/W) 4.0 Circuit of Figure 12 TA = 25C 2.0 40 6.0 8.0 10 12 14 125 0.1 1.0 10 100 t, TIME (s) Figure 7. Supply Current versus Supply Voltage Figure 8. Transient Thermal Resistance 1.4 1.2 30 25 20 15 10 5 FC--to--Gnd 10 100 VCC, SUPPLY VOLTAGE (V) FC--to--Vref 35 D Suffix 16 Pin SOIC 10 0.01 16 CURRENT SENSE VOLTAGE I CC , SUPPLY CURRENT (mA) 400 1000 0 4.0 MINIMUM OFF--TIME (ms) VCC = 15 V 300 --55 6.0 0 450 D Suffix 16 Pin SOIC TA = 25C VCC = 15 V 1.0 0.8 0.6 0.4 0.2 0 --0.2 100 --0.4 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 RESISTOR (kΩ) FEEDBACK VOLTAGE Figure 9. Minimum Off--time versus Timing Resistor on the FC Pin Figure 10. Feedback Voltage versus Current Sense Voltage http://onsemi.com 6 5.5 6.0 MC33364 OPERATING DESCRIPTION Introduction this case. Figure 3 shows the timing diagram in a fault condition. There are three Under--Voltage Lock--Out (UVLO) thresholds with respect to VCC. The upper threshold is 15 V. When this limit is reached, the startup circuit block turns off and VCC declines due to power consumption of the circuitry. The startup circuit block turns on when VCC reaches 7.6 V and if Vref is higher than 3.7 V. It is the second threshold of VCC. If Vref is smaller than 3.7 V, the startup circuit will turn on when VCC reaches a temperature dependent value VT ranging between 3.5 V and 6 V. It is the last threshold of VCC. This temperature dependent threshold is lower when temperature is higher so that it takes a longer time to restore the VCC. It is a protection feature, which allows more dead time for cooling in high temperature condition. There is an UVLO in the Vref regulator block. When VCC falls below typical 8.1 V in abnormal situation, the Vref regulator block stops. Vref and VCC collapses due to power consumption of the circuitry. When Vref collapses to below 3.7 V, the device cannot provide the Drive output and makes a dead time. This dead time is designed for minimal power transfer in the abnormal conditions. The dead time ends when VCC reaches 15 V after reaching the UVLO limit VT (3.5 to 6 V). Reaching VT enables the startup circuit block, charging up the VCC capacitor again. When VCC reaches 15 V again, the Vref regulator block turns on and allows the output to work again. It is recommended to put a 0.1 uF capacitor on Vref pin for stability of the voltage buffer. The VCC capacitor is relatively larger than this 0.1 uF capacitor, making a longer VCC charging time from VT to 15 V and a longer dead time in the abnormal or fault conditions. The MC33364 series represents a variable--frequency current--mode critical--conduction solution with integrated high voltage startup and protection circuitry to implement an off--line flyback converter for modern consumer electronic power supplies. Different frequency clamp options offer different customized needs. This device series includes an integrated 700 V Very High--Voltage (VHV) start--up circuit. Thus, it is possible to design an application with universal input voltage from 85 Vac to 265 Vac without any additional startup circuits or components. The critical conduction feature offers some advantages. First, the MOSFET turns on at zero current and the diode turns off at zero current. The zero current reduces these turn--on and turn--off switching losses. It also reduces the Electro--Magnetic Interface (EMI) of the SMPS and a less expensive rectifier can be used. Second, by preventing the SMPS from entering the discontinuous conduction mode (DCM), the peak MOSFET drain current is limited to only twice the average input current. It needs a smaller and less expensive MOSFET. Third, by preventing the SMPS from entering the Continuous Conduction Mode (CCM), the flyback topology transfer function stays first--order and its feedback compensation network is considerably simplified. It also maximizes the power transfer by the flyback transformer to its 1/2 L I2 limits. A description of each of the functional blocks is given below. The representative block diagram and typical application circuit are in Figure 1 and Figure 2. Line, VCC, Startup Circuit and Reference Voltage The Line pin is capable of a maximum 700 V so that it is possible to connect this pin directly to the rectified high--voltage Alternating Current (AC) input for minimizing the number of external components. There is a startup circuit block that regulates voltage from the Line pin to the VCC pin in an abnormal situation. In normal conditions, the auxiliary winding powers up the VCC and this startup circuit is opened and saves approximate 0.7 W of power compared to the resistor bootstrapped circuits. In normal operation, the auxiliary winding powers up the VCC voltage. This voltage is a constant value between the UVLO limits (7.6 V and 15 V). It is further regulated to a constant 5 V reference voltage Vref for the internal circuitry usage. As long as the VCC voltage is between 7.6 V and 15 V, it means the auxiliary winding can provide voltage as in normal condition. The device recognizes that there is no fault in the circuit and the device remains in the normal operation status. However, when the auxiliary winding cannot power up VCC, the VCC voltage will reach its UVLO limit. The device recognizes that it is an abnormal situation (such as startup or output short--circuited). The VCC voltage is not constant in Zero Current Detect To achieve critical conduction mode, MOSFET conduction is always initiated by sensing a zero current signal from the Zero Current Detect (ZCD) pin. The ZCD pin indirectly monitors the inductor current by sensing the auxiliary winding voltage. When the voltage falls below a threshold of 1.0V, the comparator resets the RS latch to turn the MOSFET on. There is 200 mV of hysteresis built into the comparator for noise immunity and to prevent false tripping. There are 10 V and 0.7 V clamps in the ZCD pin for protection. An external resistor is recommended to limit the input current to 2 mA to protect the clamps. Watchdog Timer A watchdog timer block is added to the device to start or restart the Drive output when something goes wrong in the ZCD. When the inductor current reaches zero for longer than approximate 410 ms, the timer reset the RS latch and that turns the MOSFET on. http://onsemi.com 7 MC33364 Current Sense and Feedback Regulation Frequency Clamp Options Current--mode control is implemented with the Current Sense (CS) pin and Feedback (FB) pin. The FB pin is internally pulled up with a 5 kOhm resistor from the 5 V Vref. There is a resistor divider circuit and a 0.1 V offset in this functional block. The following equation describes the relation between the voltages of the FB and CS pins, VFB and VCS respectively. The drawback of critical conduction mode is variable switching frequency. The switching frequency can increase dramatically to hundreds of kHz when the output current is too low or vanishes. It is a big problem when EMI above 150 kHz is concerned. Frequency Clamp (FC) is an optional feature in the device to limit the upper switching frequency to nominal 126 kHz by inserting a minimum off--time (toff(min)). When a minimum off--time is inserted, the maximum frequency (fmax) limit is set. VCS(max) = VFB∕4 − 0.1 V When the output is short circuited, there is no feedback signal from the opto coupler and the FB pin is opened. It gives VFB = 5 V and the maximum voltage of the CS pin is 1.15 V. When the voltage exceeds 1.15 V, the current sense comparator turns on and terminates the MOSFET conduction. It stops current flowing through the sense resistor (RSense) and hence the sense resistor limits the maximum MOSFET drain current by the following equation. f max = 1 ton(min) + toff(min) The SMPS is forced to operate in DCM when the maximum frequency is reached. The minimum off--time is immediately counted after the driving signal goes low. If the ZCD signal comes within this minimum off--time, the ZCD information is ignored until the minimum off--time expires. The next ZCD signal starts the MOSFET conduction. There are three available FC options: MC33364D -adjustable minimum off--time by external resistor, MC33364D1 -- 6.9 us fixed minimum off--time, and MC33364D2 -- no minimum off--time (FC disable). The MC33364D has a FC pin, which can vary the minimum off--time (or the maximum frequency) externally in Figure 11. If the FC pin is opened, the minimum off--time is fixed at 6.9 us. If the FC pin is grounded, the clamp is disabled, and the SMPS will always operate in critical mode. It is generally not recommended to sink or source more than 80 uA from the FC pin because high currents may cause unstable operation. Maximum Drain Current = 1.15∕Rsense When the output voltage is too high, the FB pin voltage is pulled down by the opto coupler current and the duty ratio is reduced. The output voltage is then regulated. There is a Leading Edge Blanking (LEB) circuit with 250 ns propagation delay to prevent false triggering due to parasitics in the CS pin. It makes a minimum on--time of the MOSFET (ton(min)). Thermal Shutdown There is a thermal shutdown block to prevent overheating condition and protect the device from overheating. When temperature is over 180_C, the Drive output and startup circuit block are disable. The device resumes operation when temperature falls below 130_C. Gate Drive Output The IC contains a CMOS output driver specifically designed for direct drive of power MOSFET. The Drive Output typical rise and fall times are 50 ns with a 1.0 nF load. Unbalanced Source and Sink eliminates the need for an external resistor between the device Drive output and the Gate of the external MOSFET. Additional internal circuitry has been added to keep the Drive Output in a sinking mode whenever the UVLO is active. This characteristic eliminates the need for an external gate pull--down resistor. Vref FC FC GND Increase toff FC Decrease toff FC GND toff = 6.9us toff = 0us (FC disable) Figure 11. Frequency Clamp Setting http://onsemi.com 8 MC33364 APPLICATION INFORMATION Design Example startup switch is turned off by the undervoltage and the overvoltage control circuit. Because the power supply can be shorted on the output, causing the auxiliary voltage to be zero, the MC33364 will periodically start its startup block. This mode is named “hiccup mode”. During this mode the temperature of the chip rises but remains protected by the thermal shutdown block. During the power supply’s normal operation, the high voltage internal MOSFET is turned off, preventing wasted power, and thereby, allowing greater circuit efficiency. Since a bridge rectifier is used, the resulting minimum and maximum dc input voltages can be calculated: Design an off--line Flyback converter according to the following requirements: Output Power: 12 W Output: 6.0 V @ 2 Amperes Input voltage range: 90 Vac -- 270 Vac, 50/60 Hz The operation for the circuit shown in Figure 12 is as follows: the rectifier bridge D1--D4 and the capacitor C1 convert the ac line voltage to dc. This voltage supplies the primary winding of the transformer T1 and the startup circuit in U1 through the line pin. The primary current loop is closed by the transformer’s primary winding, the TMOS switch Q1 and the current sense resistor R7. The resistors R5, R6, diode D6 and capacitor C4 create a snubber clamping network that protects Q1 from spikes on the primary winding. The network consisting of capacitor C3, diode D5 and resistor R1 provides a VCC supply voltage for U1 from the auxiliary winding of the transformer. The resistor R1 makes VCC more stable and resistant to noise. The resistor R2 reduces the current flow through the internal clamping and protection zener diode of the Zero Crossing Detector (ZCD) within U1. C3 is the decoupling capacitor of the supply voltage. The resistor R3 can provide additional bias current for the optoisolator’s transistor. The diode D8 and the capacitor C5 rectify and filter the output voltage. The TL431, a programmable voltage reference, drives the primary side of the optoisolator to provide isolated feedback to the MC33364. The resistor divider consisting of R10 and R11 program the voltage of the TL431. The resistor R9 and the capacitors C7 and C8 provide frequency compensation of the feedback loop. Resistor R8 provides a current limit for the opto coupler and the TL431. Since the critical conduction mode converter is a variable frequency system, the MC33364 has a built--in special block to reduce switching frequency in the no load condition. This block is named the ”frequency clamp” block. MC33364 used in the design example has an internal frequency clamp set to 126 kHz. However, optional versions with a disabled or variable frequency clamp are available. The frequency clamp works as follows: the clamp controls the part of the switching cycle when the MOSFET switch is turned off. If this ”off--time” (determined by the reset time of the transformer’s core) is too short, then the frequency clamp does not allow the switch to turn--on again until the defined frequency clamp time is reached (i.e., the frequency clamp will insert a dead time). There are several advantages of the MC33364’s startup circuit. The startup circuit includes a special high voltage switch that controls the path between the rectified line voltage and the VCC supply capacitor to charge that capacitor by a limited current when the power is applied to the input. After a few switching cycles the IC is supplied from the transformer’s auxiliary winding. After VCC reaches the undervoltage lockout threshold value, the V V in(min) in(max) dc = 2 xV dc = 2 xV in(min) in(max) ac = 290 Vac = 127 V ac = 2270 Vac = 382 V The maximum average input current is: I in = P out nV in(min) = 12 W = 0.118 A 0.8127 V where n = estimated circuit efficiency. A TMOS switch with 600 V avalanche breakdown voltage is used. The voltage on the switch’s drain consists of the input voltage and the flyback voltage of the transformer’s primary winding. There is a ringing on the rising edge’s top of the flyback voltage due to the leakage inductance of the transformer. This ringing is clamped by the RCD network. Design this clamped wave for an amplitude of 50 V below the avalanche breakdown of the TMOS device. Add another 50 V to allow a safety margin for the MOSFET. Then a suitable value of the flyback voltage may be calculated: V flbk = V − V − 100 V in(max) TMOS = 600 V − 382 V − 100 V = 118 V Since this value is very close to the Vin(min), set: V flbk = V in(min) = 127 V The Vflbk value of the duty cycle is given by: ∂max = V V 127 V flbk = = 0.5 [127 V + 127 V] +V in(min) flbk The maximum input primary peak current: I ppk = 2I in = 2.00.118 A = 0.472 A ∂max 0.5 Choose the desired minimum frequency fmin of operation to be 70 kHz. After reviewing the core sizing information provided by a core manufacturer, a EE core of size about 20 mm was chosen. Siemens’ N67 magnetic material is used, which corresponds to a Philips 3C85 or TDK PC40 material. http://onsemi.com 9 MC33364 The primary inductance value is given by: Lp = ∂max V in(min) Ippkfmin = The approximate value of rectifier capacitance needed is: t (I ) (5 m sec)(0.118 A) C1 = off in = = 11.8 mF V 50 V ripple 0.5127 V = 1.92 mH 0.472 A70 kHz where the minimum ripple frequency is 2 times the 50 Hz line frequency and toff, the discharge time of C1 during the haversine cycle, is assumed to be half the cycle period. Because we have a variable frequency system, all the calculations for the value of the output filter capacitors will be done at the lowest frequency, since the ripple voltage will be greatest at this frequency. When selecting the output capacitor select a capacitor with low ESR to minimize ripple from the current ripple. The approximate equation for the output capacitance value is given by: The manufacturer recommends for that magnetic core a maximum operating flux density of: B max = 0.2 T The cross--sectional area Ac of the EF20 core is: A c = 33.5 mm 2 The operating flux density is given by: B max = L pI ppk N pA c From this equation the number of turns of the primary winding can be derived: np = C5 = ppk B maxA c A = = L n 2p L pB maxA c = 2 R7 = 2 L p I ppk 0.2 T33.5 E--6 m 2 .00192 H0.472 A np = AL 1∕2 0.00192 H = 100 nH 2 2 = 105 nH 1∕2 = 139 turns R The number of turns needed by the 6.0 V secondary is (assuming a Schottky rectifier is used): ns = Vs + Vfwd1–∂maxnp = = lower V (TL431) 2.5 V = R11 = ref = = 10 k I 0.25 mA div V out − V I ref (TL431) div 6.0 V − 2.5V = = 14 k 0.25 mA ∂maxVin(min) 6.0 V + 0.3 V1 − 0.5139 = 7 turns 0.5127 V (V aux + V 2A = 286 mF (70 kHz)(0.1 V) V cs 1.2 V = = 2.54 Ω ≈ 2.2 Ω I 0.472 A ppk R upper = R10 = The value of the resistor that would provide the bias current through the optoisolator and the TL431 is set by the minimum operating current requirements of the TL431. This current is minimum 1.0 mA. Assign the maximum current through the branch to be 5 mA. That makes the bias resistor value equal to: The auxiliary winding to power the control IC is 16 V and its number of turns is given by: naux = = The error amplifier function is provided by a TL431 on the secondary, connected to the primary side via an optoisolator, the MOC8102. The voltage of the optoisolator collector node sets the peak current flowing through the power switch during each cycle. This pin will be connected to the feedback pin of the MC33364, which will directly set the peak current. Starting on the secondary side of the power supply, assign the sense current through the voltage--sensing resistor divider to be approximately 0.25 mA. One can immediately calculate the value of the lower and upper resistor: From the manufacturer‘s catalogue recommendation the core with an AL of 100 nH is selected. The desired number of turns of the primary winding is: Lp )(V ) min rip Determining the value of the current sense resistor (R7), one uses the peak current in the predesign consideration. Since within the IC there is a limitation of the voltage for the current sensing, which is set to 1.2 V, the design of the current sense resistor is simply given by: L pI The AL factor is determined by: Lp (f I out )(1 − ∂max)n p fwd ∂max(Vin(min)) R bias (16 V + 0.9 V)(1 − 0.5)139 = 19 turns [0.5(127 V)] =R = S = http://onsemi.com 10 V out − [V (TL431) + V ] LED ref I LED 6.0 V − [2.5V + 1.4V] = 420 Ω ≈ 430 Ω 5.0 mA MC33364 The MOC8102 has a typical current transfer ratio (CTR) of 100% with 25% tolerance. When the TL431 is full--on, 5 mA will be drawn from the transistor within the MOC8102. The transistor should be in saturated state at that time, so its collector resistor must be R collector The gain exhibited by the open loop power supply at the high input voltage will be: 2 Vin max − Vout Ns 382 V − 6.0 V2(7) A= = (Vin max)(Verror)(Np) (382 V)(1.2 V)(139) V − V sat 5.0 V − 0.3 V = ref = = 940 Ω I 5.0 mA LED = 15.53 = 23.82 dB Since a resistor of 5.0 k is internally connected from the reference voltage to the feedback pin of the MC33364, the external resistor can have a higher value The maximum approximately: f c = fs min = 5 (R )(R ) int collector = (5.0 k)(940) R ext = R3 = (R ) − (R ) 5.0 k − 940 int collector = 1157 Ω ≈ 1200 Ω noload = (I Gc = 20 log heavy R 1 in ( 2π R noload C out ) fc ph 14177kHz − 23.82 dB − A = 20 log = R upper || R lower = 10 k || 14 k = 5833 Ω R9 = (Ac) (R ) = 29.75 k ≈ 30 k in 1 = 0.46 Hz (2π)(1143)(300 mF) C8 = 1 2π (Ac) (Rin) (fc) = 382 pF ≈ 390 pF The compensation zero must be placed at or below the light load filter pole: V 6.0 V = out = = 3.0 Ω I out 2.0 A C7 = The output filter pole at heavy load of this output is f ph = f Now the compensation circuit elements can be calculated. The output resistance of the voltage sense divider is given by the parallel combination of resistors in the divider: In heavy load condition the ILED and Idiv is negligible. The heavy load resistance is given by: R A c = 10 (Gc∕20) = 10 (14.14∕20) = 5.1 +I The output filter pole at no load is: = 70 kHz = 14 kHz 5 The gain in absolute terms is: ) div 6.0 V = = 1143 Ω (5.0 mA + 0.25 mA) f ph = is = 14.14 dB V out LED bandwidth The gain needed by the error amplifier to achieve this bandwidth is calculated at the rated load because that yields the bandwidth condition, which is: This completes the design of the voltage feedback circuit. In no load condition there is only a current flowing through the optoisolator diode and the voltage sense divider on the secondary side. The load at that condition is given by: R recommended 1 1 = = 177 Hz (2π R heavyC out) (2π)(3)(300 mF) http://onsemi.com 11 1 2π (R9) (fpn) = 11.63 mF ≈ 10 mF MC33364 1N4006 D1 EMI Filter 85 to 265 VAC D2 + D3 C1 10mF 400V D4 T1 D5 1N4934 D8 MBR340 R1 56 Vcc UVLO Vcc Reference C3 20mF 15 / 7.6 ZCD R2 22 k StartUp Vref Buffer ZCD 10V R3 5k FB R R S 45k GATE R4 470 (optional) Thermal shutdown 0.1V 4k FC Vcc Q Frequency clamp 2V C4 1mF D6 MUR160 Restart Delay Watchdog Timer Current Sense 1.25V 15k 4.7 MC33364D 1.2/1.0 VREF C10 0.1mF R5 47 K R6 47 K Ref UVLO 6.0 V 2.0 A C5 300mF Line PGND Q1 MTD1N60 R7 2.2 R8 430 R10 14 k CS LEB 10V AGND U3 MOC8102 5 1 4 2 R9 39 k U2 TL431 Figure 12. Circuit in the Design Example http://onsemi.com 12 3 1 2 C7 10 mF C8 330 pF R11 10 k MC33364 The described critical conduction mode flyback converter has the following performance and maximum ratings: Output power 12W Output 12V @ 1Amp max Input voltage range 90VAC -- 270VAC J1 D1 S380 10uF 400V 1 C4 10uF 220 2 1 R1 D2 1N4148 Gnd 1 MBRD360 +Vout C6 300uF R6 2k7 C5 1nF R7 820 R8 18k 1 2 D3 MURS160T3 4 Q1 MTD1N60 1 C9 3 6 100nF 2 FB R5 2.2 U3 MOC8102 U2 1 5 3 4 4 R3 47k ZCD 7 GATE MC33364 GND CS VREF 5 VCC 8 LINE U1 9 7 R4 47k R2 100k J3 D4 T1 3 2 0.1uF 4 1 TL431 R9 4k7 2 Line J2 3 1 2 J4 1 --Vout Figure 13. Critical Conduction Mode Flyback Converter CONVERTER TEST DATA Test Conditions Results Line Regulation Vin = 120VAC to 240VAC, Iout = 0.8A ΔV = 50mV Load Vin = 120VAC, Iout = 0.2A to 0.8A ΔV = 40mV Vin = 240VAC, Iout = 0.2A to 0.8A ΔV = 40mV Vin = 120VAC, Iout = 0.8A ΔV = 290mV Vin = 240VAC, Iout = 0.8A ΔV = 24mV Vin = 120VAC, Iout = 0.8A η = 78.0% Vin = 240VAC, Iout = 0.8A η = 79.4% Vin = 120VAC, Iout = 0.8A Pf = 0.491 Vin = 240VAC, Iout = 0.8A Pf = 0.505 Output Ripple Efficiency Power Factor Vout Vout Iout Iout Ch1: 2.0V/div Ch2: 200mA/div 2.0 msec/div Ch1: 2.0V/div Ch2: 200mV/div Figure 14. Load Regulation 120V 2.0 msec/div Figure 15. Load Regulation 240V http://onsemi.com 13 MC33364 J2 1 Output 12 V @ 0.8 Amp max Input Voltage Range 90 -- 270 Vac, 50/60 Hz 2 R13 22 k R12 82 k R11 10 k 5 VS GND 4 6 CSB CMP 3 U2 7 VCC MC33341 CTA 2 CSA 1 8 DO 5.1 V R8 4.7 k D8 B2X84C5V1LT1 R9 100 C5 100 mF C6 1.0 mF R7 100 D7 1N4148 R10 0.25 C7 33 nF D6 MURS320T3 9 7 2 1 5 4 T1 4 3 R6 47 k 2 C4 1.0 nF 5 D5 MURS 160T3 R5 47 k Q1 MTD1N60E R4 2.2 U3 MOC8102 D3 1N4148 R1 220 R3 22 k C2 20 mF 6 2 CS Gate 1 ZCD 7 VCC C1 D1 B250R 8 Line 10 mF 400 V F1 T 0.2 A U1 MC33364D1 GND 5 FB 3 C3 Vref 4 0.1 mF T1 = 139 Turns #28 Awg, primary winding 2 -- 3 7 Turns, Bifilar 2 x #26 Awg, output winding 9 -- 7 19 Turns #28 Awg, auxiliary winding 4 -- 5 on Philips EF20--3C85 core gap for a primary inductor of 1.92 mH. 1 2 J1 Line Figure 16. Universal Input Battery Charger http://onsemi.com 14 MC33364 PACKAGE DIMENSIONS SO--8 D1, D2 SUFFIX CASE 751--07 ISSUE AJ --X-- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751--01 THRU 751--06 ARE OBSOLETE. NEW STANDARD IS 751--07. A 8 5 S B 1 0.25 (0.010) M Y M 4 --Y-- K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE --Z-- 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC33364 PACKAGE DIMENSIONS SO--16 D SUFFIX CASE 751K--01 ISSUE O --A-16 --B-- P 1 0.25 (0.010) M B S 9 M_ F 8 G R X 45 _ C --T-K 14 X D 0.25 (0.010) M T A S B SEATING PLANE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.368 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 S GreenLine is a trademark of Motorola, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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