AN1598/D H124, 125, 350−352 Translator I/O SPICE Modelling Kit Prepared by: Debbie Beckwith Andrea Diermeier ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides the SPICE information necessary to accurately model system interconnect situations for designs which utilize the translator circuits of the MECL 10KH family. Also included is information on the H124, H125, H350, H351, and H352 translators. INTRODUCTION With the difficulty in designing high−speed controlled impedance PC boards and the expense of reworking those boards, the ability to model circuit behavior prior to committing to a board layout is essential for high speed logic designers. The purpose of this document is to provide the user with enough information to perform basic SPICE model analysis on the interconnect traces being driven or driving the H124, H125, H350, H351, and H352 translator chips. The packet includes schematics of the input and output structures as well as ESD protection structures and package models which may affect the waveshape of the input and output waveforms. Internal bias regulators and logic circuitry are not included as they have little impact on the I/O characteristics of the device and add a significant amount of time to the standard simulation analysis. In addition, a SPICE parameter set for the devices referenced in the schematics is provided. The remainder of this document will introduce the various input and output stages for the above translators as well as the other structures which affect the I/O characteristics of these devices. appropriate subcircuit schematic sheet. This hierarchical method of schematic representation is used to help simplify and clarify the buffer schematics. The H124 I/O buffer is represented by the H124 I/O Gate schematic of Figure 1. This device is a dual supply device which means it requires +5 V, −5.2 V, and ground supplies. The AIN and CSTROBE inputs are single−ended TTL level inputs and should be driven with the minimum HIGH level at 2.4 V and the maximum LOW level at 0.5 V. Package Models Due to different dimensions of the packages and the different lead lengths of center and corner pins, different package models are asserted. 750Ω October, 2003 − Rev. 1 TPKG EXT LPKG INT LPKG CPKG Schematic Overview There are five basic schematics which can represent the I/O for the MECL10KH family of translator chips. The rest of the schematics provided represent subcircuit schematics for the above mentioned I/O buffers and package models. The devices shown in shaded boxes on the I/O buffer schematics are modelled by the subcircuits illustrated on the Semiconductor Components Industries, LLC,2003 750Ω Figure 1. Package Model The H125 is also a dual supply device represented by one structure as shown in the H125 I/O schematic of Figure 2. The H125 requires a differential input, IN and INN, which should be driven from 0.9 to 1.75 V. 1 Publication Order Number: AN1598/D AN1598/D TVCC EVCCI R1 216Ω EVCCO R2 809Ω AIN D3 FLD003 CSTROBE R6 242Ω D7 FLD003 Q8 T8106 Q9 T8106 Q1 T08I3 D4 FLD003 R7 242Ω Q2 T08I3 Q12 T08I3 Q6 T08I2 OUT OUTB VBB′ Q13 T08I3 R3 426Ω Q2 T08I3 Q4 T06B4 Q3 T06B4 All resistors modelled according to 7. R4 225Ω Q7 T12B4 VCS R5 225Ω R8 111Ω VEE Figure 2. H124 I/O Gate TVCC R1 795Ω R2 7KΩ R5 987Ω Q8 FLNN01 QRXCX1 RXCX1 Q1 T12B1 VCS R6 Q2 1314Ω T16I3 R3 426Ω INN RB2 75Ω DS1 FSS002 Q6 T16I2 R7 400Ω R8 20KΩ QRXCX2 RXCX1 OUT Q10 T12B1 Q9 T025E Q11 T12B1 VEE Q3 Q4 T16I3 T16I3 VBB″ Q5 T18B1 Q7 T16I3 RB1 75Ω GND0 IN VCS All resistors modelled according to 7. R4 75Ω VEE Figure 3. H125 I/O Gate http://onsemi.com 2 STS002 DS2 AN1598/D The H350 I/O gate is represented by the schematic of Figure 4. The H350 I/O gate is designed to operate from a single supply of VCC = 5.0 V. The IN and INN inputs should be driven differentially with standard PECL input swings of VCC − .9 to VCC − 1.75 V. TVCCI QRXCX2 RXCX1 R6 30KΩ R7 6KΩ NE R9 5KΩ FLS107 DS2 FLS104 DS5 FLS107 DS3 RB2 75Ω Q9 FLN001 FLS107 DS4 R1 150Ω Q10 FLNN01 Q3 T04I3 R2 2.5KΩ R3 150Ω R10 26.26K Q4 T04I3 R4 2.5KΩ OUT FLS001 DS6 FLS107 DS1 Q7 T04I3 Q8 FLNS01 Q6 T04I3 Q5 T04I3 FLD003 D1 Q11 FLN113 Q12 FLN113 R11 1KΩ R5 500Ω FLS002 DS9 R12 1.5KΩ Q13 FLN103 Q15 QPN139 FLS101 DS8 RB1 75Ω Q2 T04I3 Q17 90PF INN Q1 T04I3 Q16 90PF IN R8 3KΩ FLS101 DS7 QRXCX1 RXCX1 EVCC Q14 FLNS01 F All resistors modelled according to 7. VEE EVCC R20 10KΩ R21 4.22KΩ R22 1.47KΩ R26 19KΩ Q20 FLNT02 FLS002 DS21 FLS001 DS20 Q21 FLNT01 F R23 5kΩ FLS001 DS20 OEN R27 6.16KΩ Q22 FLN111 Q25 FLN101 Q23 FPN108 R24 8.66KΩ Q26 FLN101 Q24 QPN139 R25 2.76KΩ VEE Figure 4. H350 I/O Gate http://onsemi.com 3 All resistors modelled according to 7. NE AN1598/D at 0.5 V. The single ended input, STROBE, enables the output when driven with a “high” TTL level input. For the H352, the IN input should be driven with single ended CMOS level voltage swings from 0 to 5 V. The single ended input, STROBE, enables the output when driven with a “high” CMOS level input. The H351 and H352 utilize similar I/O buffers. These buffers are represented by the “H351 I/O Gate Schematic” and the “H352 I/O Gate Schematic” of Figures 5 and 6, respectively. For the H351, the IN input should be driven with single ended TTL level voltage swings with the minimum HIGH level at 2.4 V and the maximum LOW level EVCCI R1 2kΩ R2 5kΩ EVCCO R3 R4 249Ω 249Ω Q10 C15PF Q9 C15PF TVCCI Q12 T5406 Q13 T5406 DS3 FLS006 DS1 FLS009 Q5 TPNP2 Q7 T08I3 Q2 T08I3 STROBE DS2 FLS009 Q4 T08I3 Q15 T12B1 Q11 T12B1 VCS Q3 Q1 T08I3 TPNP2 OUTB R6 1.5KΩ Q8 T08I3 R5 110Ω Q16 T12B1 Q17 T12B1 Q14 C60PF IN OUT Q6 T08I3 Q18 T12B1 Q19 T12B1 Q20 T12B1 All resistors modelled according to 7. TGNDI Figure 5. H351 I/O Gate EVCCI R2 5kΩ DS1 FLS006 IN DS2 FLS009 STROBE Q5 TPNP2 DS3 FLS009 Q3 T08I3 Q4 T08I3 Q12 T5406 Q21 T08I3 Q13 T5406 Q7 T08I3 Q2 T08I3 Q1 TPNP2 R3 R4 249Ω 249Ω Q11 T12B1 VCS R7 4kΩ R6 1.5KΩ Q8 T08I3 R5 110Ω Q6 T08I3 Q15 T12B1 Q14 C60PF R1 2kΩ EVCCO Q10 C15PF Q9 C15PF TVCCI Q20 T12B1 Q16 T12B1 Q17 T12B1 Q18 T12B1 Q19 T12B1 All resistors modelled according to 7. TGNDI Figure 6. H352 I/O Gate http://onsemi.com 4 OUT OUTB AN1598/D there are parasitic capacitances associated with each. The subcircuit schematic is shown for the resistors in the “Resistor Model” schematic of Figure 7. The value of each subcircuit resistor is one half the value given on the top level schematic and the parasitic capacitance is modelled by a diode back biased to VCC. Also note that the resistor temperature coefficient (TC) values for both the resistor subcircuit and the resistors in the device subcircuits are provided. For modelling at nominal temperatures only, these TCs can be omitted. If however, modelling will be performed at the temperature extremes, the TC information should be included. Table 1 is provided to summarize the various internal voltage swings and bias levels required to run the appropriate SPICE simulations. Table 1.Input and Bias Levels Schematic Input Levels H124 I/O AIN/BIN VBB′ VCS 0.5 to 3.5V −2.1V VEE + 1.3V H125 I/O IN/INN VBB″ VCS −0.9 to −1.75V VCC − 2.9V VEE + 1.3V H350 I/O IN OEN (VCC − 0.9 to VCC − 1.75) 0.5 to 3.5V H351 I/O IN Strobe VCS 0..5 to 3.5V 0.5 to 3.5V VEE + 1.3V H352 I/O IN Strobe VCS 0 to 5.0V 0 to 5.0V VEE + 1.3V VCC1 POS D1 RES−DIODE R1A SPICEPAR/2 TC = 431.6U, 8.97U R1B SPICEPAR/2 NEG Figure 7. Resistor Model For the dual supply devices with ECL inputs, the VCC and the VEE on the typical ECL input gates should be tied to ground and −5.2 V respectively. All input pins should have a package model connected to them. The “Package Model” of Figure 1 is self explanatory, the parasitic values provided in Table 2 are worst case numbers. The package capacitance combines with the parasitic transistor, capacitance of the input device and the ESD circuitry to comprise the load capacitance of the input. The typical ECL input schematic represents a single ended ECL input, the VBB reference should be tied to VCC − 1.3 V and the VCS bias should be tied to VEE + 1.3 V. Handling Power Supplies It is important to properly apply the power supply voltages to accurately model these circuits. This section will explain the power supply terminology used on the I/O buffer schematics and how to properly apply these supplies with the appropriate package model. Table 2 lists the voltage supplies referenced on the I/O schematics along with a description of each. The key to properly simulating these power supplies is in the application of the package model. Because the output buffers, to a varying degree, share VCC and ground pins, adjustments need to be made to get a more accurate model if all of the outputs are not simulated at the same time. If for example, a single output is to be simulated, the package model for the TVCC and GND supplies should be scaled based on the number of outputs which normally share the supplies. If the simulated output normally shares its supplies with two other outputs, the package inductance would be tripled to simulate the same inductive glitch seen on the power pin in an actual application. The capacitive value for the package model is not as critical and thus can be left alone. This method will allow users to more accurately model an output behavior without resorting to more complicated and lengthy simulations. The internal power and ground pins are all powered through a single pin and are basically static, as a result no adjustments are needed for the package models on these supplies. Table 2.Package Model Values Package Pin CPKG (pF) LPKG (nH) RPKG (Ω) PLCC 20 All Pins 1.5 3.5 0.2 DIP 16 End Pin 1.3 5.5 0.1 Center Pin 0.7 2.5 0.1 Center Pin 0.8 4.85 0.036 End Pin 2.76 7.17 0.036 Center Pin 0.68 2.99 0.03 End Pin 1.26 6.7 0.05 DIL 20 DIP 20 For all of the I/O buffer schematics, the resistors should NOT be simulated as simple SPICE resistors. Because these resistors are realized by a diffusion step in wafer processing, http://onsemi.com 5 AN1598/D Table 4.Power Pins vs Outputs Table 3 outlines the internal power distribution for the MECL10KH translators, this information can be used to determine the scaling factors for the package inductance for the output buffers. To use the table, simply identify the output in question and divide the number of outputs in the group by the number of power pins for that group, this will give the multiplication factor for the inductance. Part Type No. of Outputs No. of TVCC No. of TGND H124 8 1 1 H125 4 1 1 H350 4 2 1 H351 8 4 1 H352 8 4 1 Table 3.Power Pin Descriptions Power Supply EVCC Description EVCC is the most positive supply for the ECL inputs (+5 V for the H350, H351 and H352, and ground for H124−H125). VEE Summary The information included in this kit should provide the user with all of the information necessary to do SPICE level system interconnect modelling. The schematic information provided in this document is available in netlist form through EMAIL or an IBM or Macintosh disk (for HSPICE and Berkeley SPICE). If, however, the netlists are designed or questions arise about the contents of this document, the user can contact an ECL applications engineer for assistance. VEE is the most negative supply for an ECL gate. For the H350, it is equal to ground; for the H124−125, it is equal to −5.2 V. TVCC Internal VCC for TTL circuitry GNDI Internal Ground for TTL circuitry FSS002 TC = .445M, 2.78U STS002 N1 DS1 WSS002 DS1 GRTS002 RX 2 RX 2 TC = .445M, 2.78U REPI 3.32 REXT 21.5 D1 DSBSS002 N2 FLNN01 N1 REPI 2.83 REXT 17.4 N1 RT 40.4 DS1 FPN01 N2 Q1 PNN01A Q2 PNN01B D1 DSBTS002 TC = .445M, 2.78U N2 N1 FLD003 D2 DIOD003 RSEXT 43.3 D1 DSUBD003 N2 TC = .445M, 2.78U Figure 8. Subcircuits http://onsemi.com 6 N3 N4 D1 DSUBN01 AN1598/D N1 N1 N1 FLS107 FLS104 DS1 WS107 DS1 WS106 D1 DSUBS107 REXT 22.6 FLS101 D1 DSUBS106 REXT 19.25 N2 DS1 WS101 N2 TC = 4.45E−4, 2.78E−6 D1 DSUBS101 REXT 125.3 N2 TC = 4.45E−4, 2.78E−6 TC = 4.45E−4, 2.78E−6 N1 N1 FLN113 FLN103 R1 45.9 DS1 W113 Q1 PN113 N2 TC = 3.166E−4, 8.33E−6 R1 38.6 DS1 W103 D1 DSUB113 Q1 PN103 N2 TC = .445M, 2.78U N3 D1 DSUB103 N3 N1 FLNN01 RT 40.4 DS1 FPN01 N2 FLD003 N1 Q1 PNN01A D2 DIOD003 D1 DSUBN01 Q2 PNN01B D1 DSUBD003 RSEXT 43.3 N2 TC = .445M, 2.78U TC = .445M, 2.78U N3 N4 Figure 8. Subcircuits (Continued) http://onsemi.com 7 AN1598/D N1 N1 FLNT01 FLNT02 R1 56.18 Q1 PNT01 N2 TC = 3.166E−4, 8.33E−6 R1 30.7 D1 DSUBT01 Q1 PNT02 N2 TC = .445M, 2.78U N3 D1 DSUBT02 N3 N1 N1 FLN101 FPN108 R1 122.29 DS1 W101 Q1 PN101 N2 TC = 3.166E−4, 8.33E−6 R1 19.5 DS1 W108 D1 DSUB101 Q1 PN108 N2 TC = 4.45E−4, 2.78E−6 N3 N1 D1 DSUB108 N3 N1 FLN111 FLN001 R1 99.65 DS1 W111 Q1 PN111 N2 TC = 3.166E−4, 8.33E−6 R1 122.3 DS1 GR001 D1 DSUB111 Q1 PN001 N2 TC = .445M, 2.78U N3 Figure 8. Subcircuits (Continued) http://onsemi.com 8 N3 D1 DSUB001 AN1598/D N1 FLNS01 FLS001 N1 DS1 FPS01 DS1 GRS001 RX 2 R1 52.8 TC = .445M, 2.78U REPI 15.3 Q1 PNS01 N2 TC = .445M, 2.78U N2 D1 DSUBS001 REXT 13.7 N2 N3 N1 QPN139 R1 7.89 DS1 GR139 D1 DSUBS01 DS2 GR139 Q1 PN139 R2 7.89 FLS002 R3 7.89 DS3 GR139 RX 2 TC = .445M, 2.78U Q3 PN139 Q2 PN139 DS1 GRS002 R4 7.89 DS4 GR139 Q4 PN139 REPI 3.32 D1 DSUB139 D1 DSUBS002 REXT 21.5 TC = 4.45M, 2.78U N3 N2 FLS006 N1 FLS009 N1 DS1 GRS009 DS1 GRS006 RX 2 RX 2 TC = 4.45M, 2.78U TC = .445M, 2.78U REPI 13.1 REPI 3.32 D1 DSUBS006 REXT 67.6 N1 D1 DSUBS009 REXT 21.5 N2 N2 Figure 8. Subcircuits (Continued) http://onsemi.com 9 AN1598/D ***************************************************************** * PSPICE * ***************************************************************** * H124,125,350−352 Translator I/O Modelling Kit − Netlist * * Schematics * * * * The purpose of this document is to provide the netlists * * for the various schematics of the H124,125,350−352 Translator * * I/O Modelling Kit Application Note. To use these netlists, it * * will require a copy of the H124,125,350−352 I/o Spice * * Modelling Kit application note. This note is needed to * * identify appropriate input and output models for a specific * * device. In addition, a copy of this note will help visualize * * the netlists and ease the building of the simulation * * circuits. * * * * Netlist Organization * * * * All of the subcircuits are labeled as to what they * * represent, (i.e., H124 I/O gate) and are cross referenced * * to the figure numbers in the application note. In * * addition, all of the subcircuits list the node names for * * the specified inputs and outputs for the cell. * * The component labels used in the netlists are identical to * * those on the schematics in the application note. With the * * simplicity of the models, this should allow the user to trace * * the netlists back to the schematics. * * To ease the task of interconnecting the simulation netlist, * * multiple subcircuit models for the different types of * * packages are included. The user is expected to call the * * subcircuit by the name of the desired translator with an * * additional extension that defines the type of used package * * (i.e., H124_PLCC20 for a PLCC20 package). These subcircuits * * use the pinout as it is printed in the MECL DEVICE DATA Sheet.* * The list below provides a summary of the different types of * * packages available. * * H124,H125,H350 : _DIP16 (16 pin plastic or ceramic * * package), * * _PLCC20 (20 lead PLCC package). * * H351,H352 : _DIP20 (20 pin plastic package), * * _DIL20 (20 pin ceramic package), * * _PLCC20 (20 lead PLCC package). * * If all of the outputs are not simulated at the same time, the * * unused translator structures may be omitted in the netlist to * * shorten simulation time. In that case, the elements in some * * of the packages have to be modified according to the hints * * that are given in the application note. For that purpose, the * * multiplication factor, that is optionally passed to the * * package subcircuit as a parameter, might be useful. The * * inductance and resistance of the package are multiplied * * by the parameter value, whereas the capacitance is to be * * divided. This helps to avoid the usage of additional * * modified package subcircuits. * * * * The user may notice that there are four terminals on * * the transistor models. The fourth terminal represents * * the connection to the substrate and is always biased to the * * most negative voltage in the schematic. * * * ***************************************************************** http://onsemi.com 10 AN1598/D **************************************************************** * * * Subcircuit Netlists * * * **************************************************************** **** H124 16 Pin Plastic or Ceramic Package (DIP/DIL16) ***** * * **************************************************************** .SUBCKT H124_DIP16 VCC VEE GND AIN BIN CIN DIN CSTROBE + AOUT AOUTN BOUT BOUTN COUT COUTN DOUT DOUTN V_VCS VCS 0 −3.9 V_VBB’ VBB’ 0 −2.1 XP1 BOUT INT_BOUT DIP16EP_PKG XP2 AOUT INT_AOUT DIP16EP_PKG XP3 BOUTN INT_BOUTN DIP16CP_PKG XP4 AOUTN INT_AOUTN DIP16CP_PKG XP5 AIN INT_AIN DIP16CP_PKG XP6 CSTROBE INT_CSTROBE DIP16CP_PKG XP7 BIN INT_BIN DIP16EP_PKG XP8 VEE INT_VEE DIP16EP_PKG XP9 VCC INT_VCC DIP16EP_PKG XP10 CIN INT_CIN DIP16EP_PKG XP11 DIN INT_DIN DIP16CP_PKG XP12 COUTN INT_COUTN DIP16CP_PKG XP13 DOUTN INT_DOUTN DIP16CP_PKG XP14 DOUT INT_DOUT DIP16CP_PKG XP15 COUT INT_COUT DIP16EP_PKG XP16 GND INT_GND DIP16EP_PKG XH124A INT_VCC INT_GND INT_VEE VBB’ VCS INT_GND INT_AIN + INT_CSTROBE INT_AOUT INT_AOUTN H124IO XH124B INT_VCC INT_GND INT_VEE VBB’ VCS INT_GND INT_BIN + INT_CSTROBE INT_BOUT INT_BOUTN H124IO XH124C INT_VCC INT_GND INT_VEE VBB’ VCS INT_GND INT_CIN + INT_CSTROBE INT_COUT INT_COUTN H124IO XH124D INT_VCC INT_GND INT_VEE VBB’ VCS INT_GND INT_DIN + INT_CSTROBE INT_DOUT INT_DOUTN H124IO .ENDS H124_DIP16 ********* H124 20 lead PLCC Package ********** * * **************************************************************** .SUBCKT + V_VCS V_VBB’ XP2 XP3 XP4 XP5 XP7 XP8 XP9 XP10 XP12 XP13 XP14 XP15 H124_PLCC20 VCC VEE GND AIN BIN CIN DIN CSTROBE AOUT AOUTN BOUT BOUTN COUT COUTN DOUT DOUTN VCS 0 −3.9 VBB’ 0 −2.1 BOUT INT_BOUT PLCC20_PKG AOUT INT_AOUT PLCC20_PKG BOUTN INT_BOUTN PLCC20_PKG AOUTN INT_AOUTN PLCC20_PKG AIN INT_AIN PLCC20_PKG CSTROBE INT_CSTROBE PLCC20_PKG BIN INT_BIN PLCC20_PKG VEE INT_VEE PLCC20_PKG VCC INT_VCC PLCC20_PKG CIN INT_CIN PLCC20_PKG DIN INT_DIN PLCC20_PKG COUTN INT_COUTN PLCC20_PKG http://onsemi.com 11 AN1598/D XP17 DOUTN INT_DOUTN PLCC20_PKG XP18 DOUT INT_DOUT PLCC20_PKG XP19 COUT INT_COUT PLCC20_PKG XP20 GND INT_GND PLCC20_PKG XH124A INT_VCC INT_GND INT_VEE VBB’ VCS + INT_CSTROBE INT_AOUT INT_AOUTN XH124B INT_VCC INT_GND INT_VEE VBB’ VCS + INT_CSTROBE INT_BOUT INT_BOUTN XH124C INT_VCC INT_GND INT_VEE VBB’ VCS + INT_CSTROBE INT_COUT INT_COUTN XH124D INT_VCC INT_GND INT_VEE VBB’ VCS + INT_CSTROBE INT_DOUT INT_DOUTN .ENDS H124_PLCC20 INT_GND H124IO INT_GND H124IO INT_GND H124IO INT_GND H124IO INT_AIN INT_BIN INT_CIN INT_DIN *************************************************************** *************************************************************** **** H125 16 Pin Plastic or Ceramic Package (DIP/DIL16) **** * * *************************************************************** .SUBCKT H125_DIP16 VCC VEE GND AIN AINN BIN BINN CIN CINN + DIN DINN AOUT BOUT COUT DOUT V_VCS VCS 0 −3.9 V_VBB’’ VBB’’ 0 −2.9 XP2 AINN INT_AINN DIP16EP_PKG XP3 AIN INT_AIN DIP16CP_PKG XP4 AOUT INT_AOUT DIP16CP_PKG XP5 BOUT INT_BOUT DIP16CP_PKG XP6 BINN INT_BINN DIP16CP_PKG XP7 BIN INT_BIN DIP16EP_PKG XP8 VEE INT_VEE DIP16EP_PKG XP9 VCC INT_VCC DIP16EP_PKG XP10 CINN INT_CINN DIP16EP_PKG XP11 CIN INT_CIN DIP16CP_PKG XP12 COUT INT_COUT DIP16CP_PKG XP13 DOUT INT_DOUT DIP16CP_PKG XP14 DINN INT_DINN DIP16CP_PKG XP15 DIN INT_DIN DIP16EP_PKG XP16 GND INT_GND DIP16EP_PKG XH125A INT_VCC INT_GND INT_VEE VBB’’ VCS INT_AIN INT_AINN + INT_AOUT H125IO XH125B INT_VCC INT_GND INT_VEE VBB’’ VCS INT_BIN INT_BINN + INT_BOUT H125IO XH125C INT_VCC INT_GND INT_VEE VBB’’ VCS INT_CIN INT_CINN + INT_COUT H125IO XH125D INT_VCC INT_GND INT_VEE VBB’’ VCS INT_DIN INT_DINN + INT_DOUT H125IO .ENDS H125_DIP16 ********* H125 20 lead PLCC Package ********** * * ************************************************************** .SUBCKT H125_PLCC20 VCC VEE GND AIN AINN BIN BINN CIN CINN + DIN DINN AOUT BOUT COUT DOUT V_VCS VCS 0 −3.9 V_VBB’’ VBB’’ 0 −2.9 XP3 AINN INT_AINN PLCC20_PKG XP4 AIN INT_AIN PLCC20_PKG http://onsemi.com 12 AN1598/D XP5 AOUT INT_AOUT PLCC20_PKG XP7 BOUT INT_BOUT PLCC20_PKG XP8 BINN INT_BINN PLCC20_PKG XP9 BIN INT_BIN PLCC20_PKG XP10 VEE INT_VEE PLCC20_PKG XP12 VCC INT_VCC PLCC20_PKG XP13 CINN INT_CINN PLCC20_PKG XP14 CIN INT_CIN PLCC20_PKG XP15 COUT INT_COUT PLCC20_PKG XP17 DOUT INT_DOUT PLCC20_PKG XP18 DINN INT_DINN PLCC20_PKG XP19 DIN INT_DIN PLCC20_PKG XP20 GND INT_GND PLCC20_PKG XH125A INT_VCC INT_GND INT_VEE VBB’’ + INT_AOUT H125IO XH125B INT_VCC INT_GND INT_VEE VBB’’ + INT_BOUT H125IO XH125C INT_VCC INT_GND INT_VEE VBB’’ + INT_COUT H125IO XH125D INT_VCC INT_GND INT_VEE VBB’’ + INT_DOUT H125IO .ENDS H125_PLCC20 VCS INT_AIN INT_AINN VCS INT_BIN INT_BINN VCS INT_CIN INT_CINN VCS INT_DIN INT_DINN *************************************************************** *************************************************************** **** H350 16 Pin Plastic or Ceramic Package (DIP/DIL16) **** * * *************************************************************** .SUBCKT H350_DIP16 TVCC EVCC GND AIN AINN BIN BINN CIN CINN + DIN DINN OEN AOUT BOUT COUT DOUT XP1 EVCC INT_EVCC DIP16EP_PKG XP2 AOUT INT_AOUT DIP16EP_PKG XP3 AIN INT_AIN DIP16CP_PKG XP4 AINN INT_AINN DIP16CP_PKG XP5 BINN INT_BINN DIP16CP_PKG XP6 BIN INT_BIN DIP16CP_PKG XP7 BOUT INT_BOUT DIP16EP_PKG XP8 GND INT_GND DIP16EP_PKG XP9 OEN INT_OEN DIP16EP_PKG XP10 DOUT INT_DOUT DIP16EP_PKG XP11 DIN INT_DIN DIP16CP_PKG XP12 DINN INT_DINN DIP16CP_PKG XP13 CINN INT_CINN DIP16CP_PKG XP14 CIN INT_CIN DIP16CP_PKG XP15 COUT INT_COUT DIP16EP_PKG XP16 TVCC INT_TVCC DIP16EP_PKG XH350A INT_TVCC INT_EVCC INT_GND INT_AIN INT_AINN INT_OEN + INT_AOUT H350IO XH350B INT_TVCC INT_EVCC INT_GND INT_BIN INT_BINN INT_OEN + INT_BOUT H350IO XH350C INT_TVCC INT_EVCC INT_GND INT_CIN INT_CINN INT_OEN + INT_COUT H350IO XH350D INT_TVCC INT_EVCC INT_GND INT_DIN INT_DINN INT_OEN + INT_DOUT H350IO .ENDS H350_DIP16 http://onsemi.com 13 AN1598/D ********* H350 20 lead PLCC Package ********** * * ************************************************************** .SUBCKT H350_PLCC20 TVCC EVCC GND AIN AINN + DIN DINN OEN AOUT BOUT XP2 EVCC INT_EVCC PLCC20_PKG XP3 AOUT INT_AOUT PLCC20_PKG XP4 AIN INT_AIN PLCC20_PKG XP5 AINN INT_AINN PLCC20_PKG XP7 BINN INT_BINN PLCC20_PKG XP8 BIN INT_BIN PLCC20_PKG XP9 BOUT INT_BOUT PLCC20_PKG XP10 GND INT_GND PLCC20_PKG XP12 OEN INT_OEN PLCC20_PKG XP13 DOUT INT_DOUT PLCC20_PKG XP14 DIN INT_DIN PLCC20_PKG XP15 DINN INT_DINN PLCC20_PKG XP17 CINN INT_CINN PLCC20_PKG XP18 CIN INT_CIN PLCC20_PKG XP19 COUT INT_COUT PLCC20_PKG XP20 TVCC INT_TVCC PLCC20_PKG XH350A INT_TVCC INT_EVCC INT_GND INT_AIN + INT_AOUT H350IO XH350B INT_TVCC INT_EVCC INT_GND INT_BIN + INT_BOUT H350IO XH350C INT_TVCC INT_EVCC INT_GND INT_CIN + INT_COUT H350IO XH350D INT_TVCC INT_EVCC INT_GND INT_DIN + INT_DOUT H350IO .ENDS H350_PLCC20 BIN BINN CIN CINN COUT DOUT INT_AINN INT_OEN INT_BINN INT_OEN INT_CINN INT_OEN INT_DINN INT_OEN **************************************************************** **************************************************************** ********* H351 20 Pin Ceramic Package (DIL20) ********** * * * * **************************************************************** .SUBCKT H351_DIL20 TVCC EVCC VCC VCC2 GND AIN BIN CIN DIN + CSTROBE + AOUT AOUTN BOUT BOUTN COUT COUTN DOUT DOUTN V_VCS VCS 0 1.3 XP1 BOUTN INT_BOUTN DIL20EP_PKG XP2 BOUT INT_BOUT DIL20EP_PKG XP4 AOUT INT_AOUT DIL20CP_PKG XP5 AOUTN INT_AOUTN DIL20CP_PKG XP6 VCC INT_VCC DIL20CP_PKG XP7 BIN INT_BIN DIL20CP_PKG XP8 AIN INT_AIN DIL20CP_PKG XP9 CSTROBE INT_CSTROBE DIL20EP_PKG XP10 GND INT_GND DIL20EP_PKG XP11 TVCC INT_TVCC DIL20EP_PKG XP12 DIN INT_DIN DIL20EP_PKG XP14 CIN INT_CIN DIL20CP_PKG XP15 VCC2 INT_VCC2 DIL20CP_PKG XP16 DOUTN INT_DOUTN DIL20CP_PKG XP17 DOUT INT_DOUT DIL20CP_PKG XP18 COUT INT_COUT DIL20CP_PKG XP19 COUTN INT_COUTN DIL20EP_PKG http://onsemi.com 14 AN1598/D XP20 EVCC INT_EVCC DIL20EP_PKG XH351A INT_TVCC INT_EVCC VCS INT_VCC INT_GND INT_AIN + INT_CSTROBE INT_AOUT INT_AOUTN H351IO XH351B INT_TVCC INT_EVCC VCS INT_VCC INT_GND INT_BIN + INT_CSTROBE INT_BOUT INT_BOUTN H351IO XH351C INT_TVCC INT_EVCC VCS INT_VCC2 INT_GND INT_CIN + INT_CSTROBE INT_COUT INT_COUTN H351IO XH351D INT_TVCC INT_EVCC VCS INT_VCC2 INT_GND INT_DIN + INT_CSTROBE INT_DOUT INT_DOUTN H351IO .ENDS H351_DIL20 ********* H351 20 Pin Plastic Package (DIP20) ********** * * * * ***************************************************************** .SUBCKT H351_DIP20 TVCC EVCC VCC VCC2 GND AIN BIN CIN DIN + CSTROBE + AOUT AOUTN BOUT BOUTN COUT COUTN DOUT DOUTN V_VCS VCS 0 1.3 XP1 BOUTN INT_BOUTN DIP20EP_PKG XP2 BOUT INT_BOUT DIP20EP_PKG XP4 AOUT INT_AOUT DIP20CP_PKG XP5 AOUTN INT_AOUTN DIP20CP_PKG XP6 VCC INT_VCC DIP20CP_PKG XP7 BIN INT_BIN DIP20CP_PKG XP8 AIN INT_AIN DIP20CP_PKG XP9 CSTROBE INT_CSTROBE DIP20EP_PKG XP10 GND INT_GND DIP20EP_PKG XP11 TVCC INT_TVCC DIP20EP_PKG XP12 DIN INT_DIN DIP20EP_PKG XP14 CIN INT_CIN DIP20CP_PKG XP15 VCC2 INT_VCC2 DIP20CP_PKG XP16 DOUTN INT_DOUTN DIP20CP_PKG XP17 DOUT INT_DOUT DIP20CP_PKG XP18 COUT INT_COUT DIP20CP_PKG XP19 COUTN INT_COUTN DIP20EP_PKG XP20 EVCC INT_EVCC DIP20EP_PKG XH351A INT_TVCC INT_EVCC VCS INT_VCC INT_GND INT_AIN + INT_CSTROBE INT_AOUT INT_AOUTN H351IO XH351B INT_TVCC INT_EVCC VCS INT_VCC INT_GND INT_BIN + INT_CSTROBE INT_BOUT INT_BOUTN H351IO XH351C INT_TVCC INT_EVCC VCS INT_VCC2 INT_GND INT_CIN + INT_CSTROBE INT_COUT INT_COUTN H351IO XH351D INT_TVCC INT_EVCC VCS INT_VCC2 INT_GND INT_DIN + INT_CSTROBE INT_DOUT INT_DOUTN H351IO .ENDS H351_DIP20 ********* H351 20 lead PLCC Package ********** * * * * ************************************************************** .SUBCKT H351_PLCC20 TVCC EVCC VCC VCC2 GND AIN BIN CIN DIN + CSTROBE + AOUT AOUTN BOUT BOUTN COUT COUTN DOUT DOUTN V_VCS VCS XP1 BOUTN 0 INT_BOUTN 1.3 PLCC20_PKG http://onsemi.com 15 AN1598/D XP2 BOUT INT_BOUT PLCC20_PKG XP4 AOUT INT_AOUT PLCC20_PKG XP5 AOUTN INT_AOUTN PLCC20_PKG XP6 VCC INT_VCC PLCC20_PKG XP7 BIN INT_BIN PLCC20_PKG XP8 AIN INT_AIN PLCC20_PKG XP9 CSTROBE INT_CSTROBE PLCC20_PKG XP10 GND INT_GND PLCC20_PKG XP11 TVCC INT_TVCC PLCC20_PKG XP12 DIN INT_DIN PLCC20_PKG XP14 CIN INT_CIN PLCC20_PKG XP15 VCC2 INT_VCC2 PLCC20_PKG XP16 DOUTN INT_DOUTN PLCC20_PKG XP17 DOUT INT_DOUT PLCC20_PKG XP18 COUT INT_COUT PLCC20_PKG XP19 COUTN INT_COUTN PLCC20_PKG XP20 EVCC INT_EVCC PLCC20_PKG XH351A INT_TVCC INT_EVCC VCS INT_VCC INT_GND INT_AIN + INT_CSTROBE INT_AOUT INT_AOUTN H351IO XH351B INT_TVCC INT_EVCC VCS INT_VCC INT_GND INT_BIN + INT_CSTROBE INT_BOUT INT_BOUTN H351IO XH351C INT_TVCC INT_EVCC VCS INT_VCC2 INT_GND INT_CIN + INT_CSTROBE INT_COUT INT_COUTN H351IO XH351D INT_TVCC INT_EVCC VCS INT_VCC2 INT_GND INT_DIN + INT_CSTROBE INT_DOUT INT_DOUTN H351IO .ENDS H351_PLCC20 ***************************************************************** ***************************************************************** ********* H352 20 Pin Ceramic Package (DIL20) ********** * * * * ***************************************************************** .SUBCKT H352_DIL20 CVCC EVCC VCC VCC2 GND AIN BIN CIN DIN + CSTROBE + AOUT AOUTN BOUT BOUTN COUT COUTN DOUT DOUTN V_VCS VCS 0 1.3 XP1 BOUTN INT_BOUTN DIL20EP_PKG XP2 BOUT INT_BOUT DIL20EP_PKG XP4 AOUT INT_AOUT DIL20CP_PKG XP5 AOUTN INT_AOUTN DIL20CP_PKG XP6 VCC INT_VCC DIL20CP_PKG XP7 BIN INT_BIN DIL20CP_PKG XP8 AIN INT_AIN DIL20CP_PKG XP9 CSTROBE INT_CSTROBE DIL20EP_PKG XP10 GND INT_GND DIL20EP_PKG XP11 CVCC INT_CVCC DIL20EP_PKG XP12 DIN INT_DIN DIL20EP_PKG XP14 CIN INT_CIN DIL20CP_PKG XP15 VCC2 INT_VCC2 DIL20CP_PKG XP16 DOUTN INT_DOUTN DIL20CP_PKG XP17 DOUT INT_DOUT DIL20CP_PKG XP18 COUT INT_COUT DIL20CP_PKG XP19 COUTN INT_COUTN DIL20EP_PKG XP20 EVCC INT_EVCC DIL20EP_PKG XH352A INT_CVCC INT_EVCC VCS INT_VCC INT_GND INT_AIN + INT_CSTROBE INT_AOUT INT_AOUTN H352IO XH352B INT_CVCC INT_EVCC VCS INT_VCC INT_GND INT_BIN + INT_CSTROBE INT_BOUT INT_BOUTN H352IO http://onsemi.com 16 AN1598/D XH352C INT_CVCC INT_EVCC VCS INT_VCC2 INT_GND INT_CIN + INT_CSTROBE INT_COUT INT_COUTN H352IO XH352D INT_CVCC INT_EVCC VCS INT_VCC2 INT_GND INT_DIN + INT_CSTROBE INT_DOUT INT_DOUTN H352IO .ENDS H352_DIL20 ********* H352 20 Pin Plastic Package (DIP20) ********** * * * * ***************************************************************** .SUBCKT H352_DIP20 CVCC EVCC VCC VCC2 GND AIN BIN CIN DIN + CSTROBE + AOUT AOUTN BOUT BOUTN COUT COUTN DOUT DOUTN V_VCS VCS 0 1.3 XP1 BOUTN INT_BOUTN DIP20EP_PKG XP2 BOUT INT_BOUT DIP20EP_PKG XP4 AOUT INT_AOUT DIP20CP_PKG XP5 AOUTN INT_AOUTN DIP20CP_PKG XP6 VCC INT_VCC DIP20CP_PKG XP7 BIN INT_BIN DIP20CP_PKG XP8 AIN INT_AIN DIP20CP_PKG XP9 CSTROBE INT_CSTROBE DIP20EP_PKG XP10 GND INT_GND DIP20EP_PKG XP11 CVCC INT_CVCC DIP20EP_PKG XP12 DIN INT_DIN DIP20EP_PKG XP14 CIN INT_CIN DIP20CP_PKG XP15 VCC2 INT_VCC2 DIP20CP_PKG XP16 DOUTN INT_DOUTN DIP20CP_PKG XP17 DOUT INT_DOUT DIP20CP_PKG XP18 COUT INT_COUT DIP20CP_PKG XP19 COUTN INT_COUTN DIP20EP_PKG XP20 EVCC INT_EVCC DIP20EP_PKG XH352A INT_CVCC INT_EVCC VCS INT_VCC INT_GND INT_AIN + INT_CSTROBE INT_AOUT INT_AOUTN H352IO XH352B INT_CVCC INT_EVCC VCS INT_VCC INT_GND INT_BIN + INT_CSTROBE INT_BOUT INT_BOUTN H352IO XH352C INT_CVCC INT_EVCC VCS INT_VCC2 INT_GND INT_CIN + INT_CSTROBE INT_COUT INT_COUTN H352IO XH352D INT_CVCC INT_EVCC VCS INT_VCC2 INT_GND INT_DIN + INT_CSTROBE INT_DOUT INT_DOUTN H352IO .ENDS H352_DIP20 ********* H352 20 lead PLCC Package ********** * * * * **************************************************************** .SUBCKT H352_PLCC20 CVCC EVCC VCC VCC2 GND AIN BIN CIN DIN + CSTROBE + AOUT AOUTN BOUT BOUTN COUT COUTN DOUT DOUTN V_VCS XP1 XP2 XP4 XP5 XP6 VCS BOUTN BOUT AOUT AOUTN VCC 0 INT_BOUTN INT_BOUT INT_AOUT INT_AOUTN INT_VCC 1.3 PLCC20_PKG PLCC20_PKG PLCC20_PKG PLCC20_PKG PLCC20_PKG http://onsemi.com 17 AN1598/D XP7 BIN INT_BIN PLCC20_PKG XP8 AIN INT_AIN PLCC20_PKG XP9 CSTROBE INT_CSTROBE PLCC20_PKG XP10 GND INT_GND PLCC20_PKG XP11 CVCC INT_CVCC PLCC20_PKG XP12 DIN INT_DIN PLCC20_PKG XP14 CIN INT_CIN PLCC20_PKG XP15 VCC2 INT_VCC2 PLCC20_PKG XP16 DOUTN INT_DOUTN PLCC20_PKG XP17 DOUT INT_DOUT PLCC20_PKG XP18 COUT INT_COUT PLCC20_PKG XP19 COUTN INT_COUTN PLCC20_PKG XP20 EVCC INT_EVCC PLCC20_PKG XH351A INT_CVCC INT_EVCC VCS INT_VCC INT_GND INT_AIN + INT_CSTROBE INT_AOUT INT_AOUTN H352IO XH351B INT_CVCC INT_EVCC VCS INT_VCC INT_GND INT_BIN + INT_CSTROBE INT_BOUT INT_BOUTN H352IO XH351C INT_CVCC INT_EVCC VCS INT_VCC2 INT_GND INT_CIN + INT_CSTROBE INT_COUT INT_COUTN H352IO XH351D INT_CVCC INT_EVCC VCS INT_VCC2 INT_GND INT_DIN + INT_CSTROBE INT_DOUT INT_DOUTN H352IO .ENDS H352_PLCC20 ********* H124 I/O Gate (NO TAG) ********** * * ******************************************************** .SUBCKT H124IO TVCC EVCC VEE VBB’ VCS EVCCO IN CSTROBE OUT OUTB Q1 2 4 5 VEE T08I3 Q2 EVCC 9 12 VEE T08I3 Q3 9 VCS 10 VEE T06B4 Q4 12 VCS 13 VEE T06B4 Q5 16 12 17 VEE T08I3 Q6 21 VBB’ 17 VEE T08I2 Q7 17 VCS 18 VEE T12B4 Q8 EVCCO 21 OUT VEE T8106 Q9 EVCCO 16 OUTB VEE T8106 XD3 4 IN FLD003 XD4 4 CSTROBE FLD003 Q12 5 5 6 VEE T08I3 Q13 6 6 7 VEE T08I3 XD7 7 EVCC FLD003 XR1 TVCC 2 TVCC RES params: R=216 XR2 2 4 TVCC RES params: R=809 XR3 7 9 TVCC RES params: R=426 XR4 10 VEE TVCC RES params: R=225 XR5 13 VEE TVCC RES params: R=225 XR6 EVCC 16 EVCC RES params: R=222 XR7 EVCC 21 EVCC RES params: R=222 XR8 18 VEE EVCC RES params: R=111 .ENDS H124IO ********* H125 I/O Gate (NO TAG) ********** * * * * ******************************************************** .SUBCKT H125IO TVCC GNDI VEE VBB’’ VCS IN INN OUT Q1 11 VCS 12 VEE T12B1 http://onsemi.com 18 AN1598/D Q2 6 11 GNDI VEE Q3 6 4 7 VEE Q4 6 VBB’’ 7 VEE Q5 7 VCS 8 VEE Q6 TVCC 15 20 VEE Q7 22 23 7 VEE XQ8 TVCC 6 26 OUT Q9 OUT 22 GNDI VEE Q10 17 17 18 VEE Q11 18 18 GNDI VEE QRXCX2 TVCC IN TVCC VEE QRXCX1 TVCC INN TVCC VEE XDS1 26 6 XDS2 GNDI OUT XRB1 IN 23 TVCC XRB2 INN 4 TVCC XR1 TVCC 6 TVCC XR2 TVCC 11 TVCC XR3 12 VEE TVCC XR4 8 VEE TVCC XR5 TVCC 15 TVCC XR6 15 17 TVCC XR7 20 22 TVCC XR8 26 OUT TVCC .ENDS H125IO T16I3 T16I3 T16I3 T18B1 T16I2 T16I3 FLNN01 T025E T12B1 T12B1 RXCX1 RXCX1 FSS002 STS002 RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: R=75 R=75 R=795 R=7000 R=475 R=75 R=987 R=1314 R=400 R=20000 ********* H350 I/O Gate (NO TAG) ********** * * * * ******************************************************** .SUBCKT Q1 Q2 Q3 Q4 Q5 Q6 Q7 XQ8 XQ9 XQ10 XQ11 XQ12 XQ13 XQ14 XQ15 Q16 Q17 XQ20 XQ21 XQ22 XQ23 XQ24 XQ25 XQ26 QRXCX2 QRXCX1 XD1 XD20 XDS1 H350IO TVCC EVCC VEE IN INN OEN OUT EVCC 2 9 VEE T04I3 EVCC 4 15 VEE T04I3 9 9 12 VEE T04I3 15 15 19 VEE T04I3 14 14 VEE VEE T04I3 18 14 VEE VEE T04I3 TVCC 21 18 VEE T04I3 21 18 VEE FLNS01 33 31 25 FLN001 TVCC 25 57 OUT FLNN01 25 23 26 FLN113 26 27 VEE FLN113 37 35 VEE FLN103 39 38 VEE FLN103 OUT 26 VEE QPN139 9 10 9 VEE C90PF 15 16 15 VEE C90PF EVCC 47 50 FLNT02 EVCC 50 32 FLNT01 43 41 44 FLN111 47 44 48 FPN108 32 48 VEE QPN139 54 53 32 FLN101 29 54 VEE FLN101 EVCC 4 EVCC VEE RXCX1 EVCC 2 EVCC VEE RXCX1 38 57 FLD003 41 OEN FLS001 23 21 FLS107 http://onsemi.com 19 AN1598/D XDS2 31 32 XDS3 25 32 XDS4 23 32 XDS5 57 33 XDS6 OUT 33 XDS7 26 38 XDS8 26 39 XDS9 VEE OUT XDS20 44 OEN XDS21 VEE OEN XRB1 IN 2 EVCC XRB2 INN 4 EVCC XR1 10 14 EVCC XR2 12 14 EVCC XR3 16 18 EVCC XR4 19 18 EVCC XR5 27 29 TVCC XR6 TVCC 21 TVCC XR7 TVCC 23 TVCC XR8 TVCC 25 TVCC XR9 TVCC 31 TVCC XR10 57 VEE TVCC XR11 26 35 TVCC XR12 26 37 TVCC XR20 EVCC 41 EVCC XR21 EVCC 43 EVCC XR22 EVCC 47 EVCC XR23 50 32 EVCC XR24 44 VEE EVCC XR25 48 VEE EVCC XR26 EVCC 53 EVCC XR27 EVCC 29 EVCC .ENDS H350IO FLS107 FLS107 FLS107 FLS104 FLS001 FLS101 FLS101 FLS002 FLS001 FLS002 RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: RES params: R=75 R=75 R=150 R=2500 R=150 R=2500 R=500 R=30000 R=6000 R=3000 R=5000 R=26260 R=1000 R=1500 R=10000 R=4220 R=1470 R=5000 R=8660 R=2760 R=19000 R=6160 ********* H351 I/O Gate (NO TAG) ********** * * * * ******************************************************** .SUBCKT H351IO TVCC EVCC VCS EVCCO GNDI IN STROBE OUT OUTB Q1 GNDI STROBE 2 TPNP2 Q2 4 4 5 GNDI T08I3 Q3 5 5 6 GNDI T08I3 Q4 6 6 7 GNDI T08I3 Q5 GNDI IN 2 TPNP2 Q6 7 7 GNDI GNDI T08I3 Q7 9 2 10 GNDI T08I3 Q8 14 15 10 GNDI T08I3 Q9 EVCC 9 EVCC GNDI C15PF Q10 EVCC 14 EVCC GNDI C15PF Q11 10 VCS 11 GNDI T12B1 Q12 EVCCO 14 OUT GNDI T5406 Q13 EVCCO 9 OUTB GNDI T5406 Q14 15 GNDI 15 GNDI C60PF Q15 EVCC 17 15 GNDI T12B1 Q16 17 17 18 GNDI T12B1 Q17 18 18 19 GNDI T12B1 Q18 19 19 20 GNDI T12B1 Q19 20 20 GNDI GNDI T12B1 Q20 15 20 GNDI GNDI T12B1 XDS1 GNDI IN FLS009 http://onsemi.com 20 AN1598/D XDS2 XDS3 XR1 XR2 XR3 XR4 XR5 XR6 .ENDS GNDI STROBE 2 4 TVCC 2 TVCC TVCC 4 TVCC EVCC 9 EVCC EVCC 14 EVCC 11 GNDI EVCC EVCC 17 EVCC H351IO FLS009 FLS006 RES params: RES params: RES params: RES params: RES params: RES params: R=2000 R=5000 R=249 R= 249 R=110 R=1500 ********* H352 I/O Gate (NO TAG) ********** * * * * ******************************************************** .SUBCKT H352IO CVCC EVCC VCS EVCCO GNDI IN STROBE OUT OUTB Q1 GNDI STROBE 2 TPNP2 Q2 4 4 5 GNDI T08I3 Q3 5 5 6 GNDI T08I3 Q4 6 6 7 GNDI T08I3 Q5 GNDI IN 2 TPNP2 Q6 7 7 GNDI GNDI T08I3 Q7 9 2 10 GNDI T08I3 Q8 14 15 10 GNDI T08I3 Q9 EVCC 9 EVCC GNDI C15PF Q10 EVCC 14 EVCC GNDI C15PF Q11 10 VCS 11 GNDI T12B1 Q12 EVCCO 14 OUT GNDI T5406 Q13 EVCCO 9 OUTB GNDI T5406 Q14 15 GNDI 15 GNDI C60PF Q15 EVCC 17 15 GNDI T12B1 Q16 17 17 18 GNDI T12B1 Q17 18 18 19 GNDI T12B1 Q18 19 19 20 GNDI T12B1 Q19 20 20 GNDI GNDI T12B1 Q20 15 20 GNDI GNDI T12B1 Q21 CVCC 2 21 GNDI T08I3 XDS2 GNDI IN FLS009 XDS3 GNDI STROBE FLS009 XDS1 2 4 FLS006 XR1 XR2 XR3 XR4 XR5 XR6 XR7 .ENDS CVCC 2 CVCC 4 EVCC 9 EVCC 14 11 GNDI EVCC 17 21 GNDI H352IO CVCC CVCC EVCC EVCC EVCC EVCC EVCC RES RES RES RES RES RES RES params: params: params: params: params: params: params: R=2000 R=5000 R=249 R=249 R=110 R=1500 R=4000 http://onsemi.com 21 AN1598/D ********** SUBCIRCUITS (NO TAG) *********** **************************************************************** **************************************************************** ********** FLS001 *********** * * **************************************************************** .SUBCKT FLS001 N1 N2 RX 3 4 2.0 TC=.445M,2.78U REPI 4 5 15.3 TC=.445M,2.78U REXT 5 N2 13.7 TC=.445M,2.78U DS1 N1 3 GRS001 D1 0 5 DSUBS001 .ENDS FLS001 ********** FLS002 *********** * * **************************************************************** .SUBCKT FLS002 N1 N2 RX 3 4 2.0 TC=.445M,2.78U REPI 4 5 3.32 TC=.445M,2.78U REXT 5 N2 21.5 TC=.445M,2.78U DS1 N1 3 GRS002 D1 0 5 DSUBS002 .ENDS FLS002 ********** FLS006 *********** * * **************************************************************** .SUBCKT FLS006 N1 N2 RX 3 4 2.0 TC=.445M,2.78U REPI 4 5 13.1 TC=.445M,2.78U REXT 5 N2 67.6 TC=.445M,2.78U DS1 N1 3 GRS006 D1 0 5 DSUBS006 .ENDS FLS006 ********** FLS009 *********** * * **************************************************************** .SUBCKT FLS009 N1 N2 RX 3 4 2.0 TC=4.45M,2.78U REPI 4 5 3.32 TC=4.45M,2.78U REXT 5 N2 21.5 TC=4.45M,2.78U DS1 N1 3 GRS009 D1 0 5 DSUBS009 .ENDS FLS009 http://onsemi.com 22 AN1598/D ********** FSS002 *********** * * **************************************************************** .SUBCKT FSS002 N1 N2 RX 3 4 2.0 TC=.445M,2.78U REPI 4 5 3.32 TC=.445M,2.78U REXT 5 N2 21.5 TC=.445M,2.78U DS1 N1 3 WSS002 D1 0 5 DSBSS002 .ENDS FSS002 ********** STS002 *********** * * **************************************************************** .SUBCKT STS002 N1 N2 RX 3 4 2.0 TC=.445M,2.78U REPI 4 5 2.83 TC=.445M,2.78U REXT 5 N2 17.4 TC=.445M,2.78U DS1 N1 3 GRTS002 D1 0 5 DSBTS002 .ENDS STS002 ********** FLD003 *********** * * **************************************************************** .SUBCKT FLD003 N1 N2 RSEXT 3 N2 43.3 TC=.445M,2.78U D2 N1 3 DIOD003 D1 0 3 DSUBD003 .ENDS FLD003 ********** FLS101 *********** * * **************************************************************** .SUBCKT FLS101 N1 N2 REXT 3 N2 125.3 TC=4.45E−4,2.78E−6 DS1 N1 3 WS101 D1 0 3 DSUBS101 .ENDS FLS101 ********** FLS104 *********** * * **************************************************************** .SUBCKT FLS104 N1 N2 REXT 3 N2 19.25 TC=4.45E−4,2.78E−6 DS1 N1 3 WS106 D1 0 3 DSUBS106 .ENDS FLS104 http://onsemi.com 23 AN1598/D ********** FLS107 *********** * * **************************************************************** .SUBCKT FLS107 N1 N2 REXT 3 N2 22.6 TC=4.45E−4,2.78E−6 DS1 N1 3 WS107 D1 0 3 DSUBS107 .ENDS FLS107 ********** FLNN01 *********** * * **************************************************************** .SUBCKT FLNN01 N1 N2 N3 N4 Q1 5 N2 N3 0 PNN01A Q2 5 N3 N4 0 PNN01B RT N1 5 40.4 TC=.445M,2.78U D1 0 5 DSUBN01 DS1 N2 5 FPN01 .ENDS FLNN01 ********** QPN139 *********** * * **************************************************************** .SUBCKT QPN139 N1 N2 N3 Q1 4 N2 N3 0 PN139 Q2 5 N2 N3 0 PN139 Q3 6 N2 N3 0 PN139 Q4 7 N2 N3 0 PN139 R1 N1 4 7.89 TC=4.45M,2.78U R2 N1 5 7.89 TC=4.45M,2.78U R3 N1 6 7.89 TC=4.45M,2.78U R4 N1 7 7.89 TC=4.45M,2.78U DS1 N2 4 GR139 DS2 N2 5 GR139 DS3 N2 6 GR139 DS4 N2 7 GR139 D1 0 7 DSUB139 .ENDS QPN139 ********** FLN113 *********** * * **************************************************************** .SUBCKT FLN113 N1 N2 N3 Q1 4 N2 N3 0 PN113 R1 N1 4 45.9 TC=3.166E−4,8.33E−6 D1 0 4 DSUB113 DS1 N2 4 W113 .ENDS FLN113 http://onsemi.com 24 AN1598/D ********** FLN103 ********** * * **************************************************************** .SUBCKT FLN103 N1 Q1 4 N2 N3 0 R1 N1 4 D1 0 4 DS1 N2 4 .ENDS FLN103 N2 N3 PN103 38.6 TC=.445M,2.78U DSUB103 W103 ********** FLN101 *********** * * **************************************************************** .SUBCKT FLN101 N1 N2 N3 Q1 4 N2 N3 0 PN101 R1 N1 4 122.29 TC=3.166E−4,8.33E−6 D1 0 4 DSUB101 DS1 N2 4 W101 .ENDS FLN101 ********** FLNT01 *********** * * **************************************************************** .SUBCKT FLNT01 N1 N2 N3 Q1 4 N2 N3 0 PNT01 R1 N1 4 56.18 TC=3.166E−4,8.33E−6 D1 0 4 DSUBT01 .ENDS FLNT01 ********** FLNT02 *********** * * **************************************************************** .SUBCKT FLNT02 N1 N2 N3 Q1 4 N2 N3 0 PNT02 R1 N1 4 30.7 TC=.445M,2.78U D1 0 4 DSUBT02 .ENDS FLNT02 ********** FLN001 *********** * * **************************************************************** .SUBCKT FLN001 N1 Q1 4 N2 N3 0 R1 N1 4 D1 0 4 DS1 N2 4 .ENDS FLN001 N2 N3 PN001 122.3 TC=.445M,2.78U DSUB001 GR001 http://onsemi.com 25 AN1598/D ********** FLN111 *********** * * **************************************************************** .SUBCKT FLN111 N1 Q1 4 N2 N3 0 R1 N1 4 D1 0 4 DS1 N2 4 .ENDS FLN111 N2 N3 PN111 99.65 TC=3.166E−4,8.33E−6 DSUB111 W111 ********** FPN108 *********** * * **************************************************************** .SUBCKT FPN108 N1 Q1 4 N2 N3 0 R1 N1 4 D1 0 4 DS1 N2 4 .ENDS FPN108 N2 N3 PN108 19.5 DSUB108 W108 ********** FLNS01 *********** * * **************************************************************** .SUBCKT FLNS01 N1 N2 N3 Q1 5 N2 N3 0 PNS01 R1 4 5 52.8 TC=4.45E−4,2.78E−6 D1 0 5 DSUBS01 DS1 N1 4 FPS01 .ENDS FLNS01 http://onsemi.com 26 AN1598/D ********** Package Models (NO TAG) ********** * * * * * Package Model (20−lead PLCC) * ***************************************************************** .SUBCKT PLCC20_PKG EXT INT params: MULT=1.0 CPKG 1 0 {1.5PF/MULT} RPKG1 EXT 1 {MULT*750} RPKG2 1 2 {MULT*750} RPKG3 2 INT {MULT*0.2} LPKG1 EXT 1 {MULT*3.5NH} LPKG2 1 2 {MULT*3.5NH} .ENDS PLCC20_PKG ******* ******* * * * Package Model (16−Pin DIP/DIL Center Pin) * ***************************************************************** .SUBCKT DIP16CP_PKG EXT INT params: MULT=1.0 CPKG 1 0 {0.7PF/MULT} RPKG1 EXT 1 {MULT*750} RPKG2 1 2 {MULT*750} RPKG3 2 INT {MULT*0.1} LPKG1 EXT 1 {MULT*2.5NH} LPKG2 1 2 {MULT*2.5NH} .ENDS DIP16CP_PKG ******* ******* * * * Package Model (16−Pin DIP/DIL End Pin) * ***************************************************************** .SUBCKT DIP16EP_PKG EXT INT params: MULT=1.0 CPKG 1 0 {1.3PF/MULT} RPKG1 EXT 1 {MULT*750} RPKG2 1 2 {MULT*750} RPKG3 2 INT {MULT*0.1} LPKG1 EXT 1 {MULT*5.5NH} LPKG2 1 2 {MULT*5.5NH} .ENDS DIP16EP_PKG ******* ******* * * * Package Model (20−Pin DIL Center Pin) * ***************************************************************** .SUBCKT DIL20CP_PKG EXT INT params: MULT=1.0 CPKG 1 0 {0.81PF/MULT} RPKG1 EXT 1 {MULT*750} RPKG2 1 2 {MULT*750} RPKG3 2 INT {MULT*0.036} LPKG1 EXT 1 {MULT*4.85NH} LPKG2 1 2 {MULT*4.85NH} .ENDS DIL20CP_PKG http://onsemi.com 27 AN1598/D ******* ******* * * * Package Model (20−Pin DIL End Pin) * ***************************************************************** .SUBCKT DIL20EP_PKG EXT INT params: MULT=1.0 CPKG 1 0 {2.76PF/MULT} RPKG1 EXT 1 {MULT*750} RPKG2 1 2 {MULT*750} RPKG3 2 INT {MULT*0.063} LPKG1 EXT 1 {MULT*7.17NH} LPKG2 1 2 {MULT*7.17NH} .ENDS DIL20EP_PKG ******* ******* * * * Package Model (20−Pin DIP Center Pin) * ***************************************************************** .SUBCKT DIP20CP_PKG EXT INT params: MULT=1.0 CPKG 1 0 {0.68PF/MULT} RPKG1 EXT 1 {MULT*750} RPKG2 1 2 {MULT*750} RPKG3 2 INT {MULT*0.03} LPKG1 EXT 1 {MULT*2.99NH} LPKG2 1 2 {MULT*2.99NH} .ENDS DIP20CP_PKG ******* ******* * * * Package Model (20−Pin DIP End Pin) * ***************************************************************** .SUBCKT DIP20EP_PKG EXT INT params: MULT=1.0 CPKG 1 0 {1.26PF/MULT} RPKG1 EXT 1 {MULT*750} RPKG2 1 2 {MULT*750} RPKG3 2 INT {MULT*0.05} LPKG1 EXT 1 {MULT*6.7NH} LPKG2 1 2 {MULT*6.7NH} .ENDS DIP20EP_PKG http://onsemi.com 28 AN1598/D ********** Resitor Model (NO TAG) ********** * * * * * Resistor with parsitic capacitance * ***************************************************************** .SUBCKT RES POS NEG VCC1 params: R=50 R1A POS 1 {R/2} TC=431.6U,8.97U R1B NEG 1 {R/2} TC=431.6U,8.97U DR 1 VCC1 RES−DIODE .ENDS RES *********************** SPICE Parameter List ************************* * * * TTL Subcircuit Models * * * ************************************************************************** .MODEL .MODEL + + + + + + + .MODEL + + .MODEL .MODEL + + + + + + + .MODEL + + .MODEL .MODEL + + + + + + + .MODEL + + **** .MODEL .MODEL + + + DSUB101 D PN101 NPN W101 D DSUB103 D PN103 NPN W103 D DSUB111 D PN111 NPN W111 D DSUB113 D PN113 NPN (CJO=104FF VJ=.51 M=.24) (IS=7E−18 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=0.1 NR=1 XCJC=0.1 VAR=100 IKR=.3MA ISC=7.59E−17 NC=1 RB=1441 RBM=400 RE=0 RC=217.6 CJE=41.3FF VJE=.9 MJE=.4 CJC=32.2FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=1.64MA PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) (IS=2.15E−13 RS=123.4 N=1.044 TT=10PS CJO=28.8FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (CJO=309.7FF VJ=.51 M=.24) (IS=1.89E−16 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=.1 NR=1 XCJC=0.1 VAR=100 IKR=8.1MA ISC=2.24E−16 NC=1 RB=715.6 RBM=98.4 RE=0 RC=8.06 CJE=646.4FF VJE=.9 MJE=.4 CJC=171.9FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=10A PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=.5) (IS=5.39E−13 RS=49.2 N=1.044 TT=10PS CJO=72.2FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (CJO=122FF VJ=.51 M=.24) (IS=1.05E−17 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=0.1 NR=1 XCJC=0.1 VAR=100 IKR=.45MA ISC=1.14E−16 NC=1 RB=1010 RBM=315.7 RE=0 RC=145 CJE=57.8FF VJE=.9 MJE=.4 CJC=39FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=2.46MA PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) (IS=4.8E−13 RS=68.2 N=1.044 TT=10PS CJO=64.3FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) FLN113 **** (CJO=182FF VJ=.51 M=.24) (IS=2.45E−17 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=0.1 NR=1 XCJC=0.1 VAR=100 IKR=1MA ISC=2.66E−16 NC=1 RB=469 RBM=171 RE=0 RC=62.2 http://onsemi.com 29 AN1598/D + + + + .MODEL + + .MODEL .MODEL + + + + + + + .MODEL + + .MODEL .MODEL + + + + + + + .MODEL + + + + + + + .MODEL + + .MODEL + + .MODEL + + .MODEL + + .MODEL + + .MODEL + + .MODEL + + .MODEL + + .MODEL + W113 D DSUBS01 D PNS01 NPN FPS01 D DSUBN01 D PNN01A NPN PNN01B NPN FPN01 D WS107 D DSUBS107 D GRS001 D DSUBS001 D GRS002 D DSUBS002 D GRTS002 D DSBTS002 D CJE=123FF VJE=.9 MJE=.4 CJC=69FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=5.74MA PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) (IS=7.41E−13 RS=43 N=1.044 TT=10PS CJO=99FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (CJO=164.4FF VJ=.51 M=.24) (IS=2.1E−17 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=.1 NR=1 XCJC=0.1 VAR=100 IKR=.9MA ISC=2.48E−17 NC=1 RB=573 RBM=225.8 RE=0 RC=72.5 CJE=107FF VJE=.9 MJE=.4 CJC=67.5FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=10A PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=.5) (IS=1.8E−13 RS=0 N=1.044 TT=10PS CJO=151.1FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (CJO=1.785PF VJ=.51 M=.24) (IS=1.68E−17 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=.1 NR=1 XCJC=0.1 VAR=100 IKR=.72MA ISC=1.99E−17 NC=1 RB=982.1 RBM=357.1 RE=0 RC=90.7 CJE=83.6FF VJE=.9 MJE=.4 CJC=57FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=10A PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=.5) (IS=3.64E−16 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=.1 NR=1 XCJC=0.1 VAR=100 IKR=7.8MA ISC=2.15E−16 NC=1 RB=374.5 RBM=54.1 RE=0 RC=4.18 CJE=606.8FF VJE=.9 MJE=.4 CJC=160.4FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=10A PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=.5 (IS=8.63E−14 RS=39.4 N=1.044 TT=10PS CJO=72.3FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (IS=1.49E−12 RS=14 N=1.044 TT=10PS CJO=200FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (IS=1E−16 RS=0 N=1 TT=500PS CJO=221FF VJ=.51 M=.24 EG=1.115 XTI=3 FC=.5 BV=35) (IS=4.27E−14 RS=52.8 N=1.044 TT=10PS CJO=54FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (IS=1E−16 RS=0 N=1 TT=500PS CJO=87.7FF VJ=.51 M=.24 EG=1.115 XTI=3 FC=.5 BV=35) (IS=5.43E−13 RS=4.15 N=1.044 TT=10PS CJO=54FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (IS=1E−16 RS=0 N=1 TT=500PS CJO=593FF VJ=.51 M=.24 EG=1.115 XTI=3 FC=.5 BV=35) (IS=6.84E−13 RS=3.3 N=1.044 TT=10PS CJO=865FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (IS=1E−16 RS=0 N=1 TT=500PS CJO=673FF VJ=.51 M=.24 http://onsemi.com 30 AN1598/D + .MODEL + + .MODEL + + .MODEL + + .MODEL + + .MODEL .MODEL + + + + + + + .MODEL + + .MODEL .MODEL + + + + + + + .MODEL + + .MODEL .MODEL + + + + + + + .MODEL .MODEL + + + + + + + .MODEL .MODEL + + .MODEL .MODEL + WSS002 D DSBSS002 D DIOD003 D DSUBD003 D DSUB001 D PN001 NPN GR001 D DSUBS009 D PN009E NPN GRS009 D DSUBT01 D PNT01 NPN DSUBT02 D PNT02 NPN DSUBS106 D WS106 D DSUB139 D PN139 NPN EG=1.115 XTI=3 FC=.5 BV=35) (IS=7.52E−13 RS=28.3 N=1.044 TT=10PS CJO=100.8FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=35) (IS=1E−16 RS=0 N=1 TT=500PS CJO=97.8FF VJ=.51 M=.24 EG=1.115 XTI=3 FC=.5 BV=35) (IS=5.73E−17 RS=2.98 N=1 TT=500PS CJO=199.1FF VJ=.51 M=.24 EG=1.115 XTI=3 FC=.5 BV=35) (IS=1E−16 RS=0 N=1 TT=500PS CJO=276.8FF VJ=.51 M=.24 EG=1.115 XTI=3 FC=.5 BV=35) (CJO=105FF VJ=.51 M=.24) (IS=7E−18 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=0.1 NR=1 XCJC=0.1 VAR=100 IKR=.3MA ISC=7.59E−17 NC=1 RB=1341 RBM=300 RE=0 RC=217.6 CJE=41FF VJE=.9 MJE=.4 CJC=59FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=1.64MA PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) (IS=3.8E−14 RS=88 N=1.044 TT=10PS CJO=48FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (CJO=106FF VJ=.51 M=.24) (IS=3.92E−16 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=5 NR=1 XCJC=.1 VAR=100 IKR=.3MA ISC=4.25E−15 NC=1 RB=185 RBM=39 RE=0 RC=3.9 CJE=1.37PF VJE=.9 MJE=.4 CJC=609FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=1.64MA PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) (IS=5.4E−13 RS=9.57 N=1.044 TT=10PS CJO=683FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (CJO=155FF VJ=.51 M=.24) (IS=2.73E−17 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=0.1 NR=1 XCJC=0.1 VAR=100 IKR=1.17MA ISC=2.96E−16 NC=1 RB=566.4 RBM=181.8 RE=0 RC=55.79 CJE=129.5FF VJE=.9 MJE=.4 CJC=73.4FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=6.4MA PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) (CJO=97.8FF VJ=.51 M=.24) (IS=7.0E−18 BF=70 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=.1 NR=1 XCJC=0.1 VAR=100 IKR=.3MA ISC=8.28E−18 NC=1 RB=1475 RBM=433 RE=0 RC=217.6 CJE=41.3FF VJE=.9 MJE=.4 CJC=35.4FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=10A PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=.5) (CJO=149.4FF VJ=.51 M=.24) (IS=3.91E−13 RS=98.9 N=1.044 TT=10PS CJO=52.4FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) (CJO=2.12PF VJ=.51 M=.24) (IS=1.03E−16 BF=113 NF=1.008 VAF=30 IKF=10A ISE=0 NE=1 BR=5 NR=1 XCJC=.1 VAR=100 http://onsemi.com 31 AN1598/D + + + + + + .MODEL + + .MODEL .MODEL + + + + + + + .MODEL + + .MODEL + + .MODEL + + .MODEL + + .MODEL + + .MODEL * IKR=4.4MA ISC=1.22E−16 NC=1 RB=117 RBM=47 RE=0 RC=8.41 CJE=493FF VJE=.9 MJE=.4 CJC=244FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=96.7MA PTF=0 TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) GR139 D (IS=7E−14 RS=10 N=1.044 TT=10PS CJO=88FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) DSUB108 D (CJO=163FF VJ=.51 M=.24) PN108 NPN (IS=1.75E−17 BF=113 NF=1.008 VAF=30 IKF=10a ISE=0 NE=1 BR=5 NR=1 XCJC=.1 VAR=100 IKR=.75MA ISC=1.9E−16 NC=1 RB=638.8 RBM=222 RE=0 RC=87 CJE=90.6FF VJE=.9 MJE=.4 CJC=50.3FF VJC=.53 MJC=.37 TF=40P XTF=0 VTF=100 ITF=4.1MA PTF=0 TR=20Pp XTB=1.51 EG=1.115 XTI=5 FC=0.5) W108 D (IS=5.1E−13 RS=58.8 N=1.044 TT=10PS CJO=68.3FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) GRS006 D (IS=6.39E−14 RS=35 N=1.044 TT=10PS CJO=81FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) DSUBS006 D (IS=1E−16 RS=0 N=1 TT=500PS CJO=149FF VJ=.51 M=.24 EG=1.115 XTI=3 FC=.5 BV=35) WS101 D (IS=1.9E−13 RS=111 N=1.044 TT=10PS CJO=25.6FF VJ=.4 M=.33 EG=.69 XTI=3 FC=.5 BV=30) DSUBS101 D (IS=1E−16 RS=0 N=1 TT=500PS CJO=63.2FF VJ=.51 M=.24 EG=1.115 XTI=3 FC=.5 BV=35) FSS002 D IS=7.56E−13 *********************************************************************** * MECL10KH Transistor Models * * * *********************************************************************** .MODEL T04I3 NPN + IS=2.78E−17 BF=85 RB=707 RC=180 RE=12 BR=5 + CJE=.04E−12 CJC=.13E−12 CJS=.18E−12 .MODEL T06B4 NPN + IS=4.048E−17 BF=85 RB=1330 BR=5 RE=7.5 + RC=121.2 CJE=.06E−12 CJC=.1E−12 CJS=.161E−12 .MODEL T08I2 NPN + IS=2.6E−17 BF=85 RB=470 BR=5 + RC=163 RE=7.5 CJE=6.53E−14 CJC=1.235E−13 CJS=1.338E−13 .MODEL T025E NPN + IS=1.3E−15 BF=85 RB=64.5 BR=5 + RC=5.68 RE=.2 .MODEL T08I3 NPN + IS=4.189E−17 BF=85 RB=450 BR=5 + RC=118.9 RE=7.5 CJE=6.5E−14 CJC=1.72E−13 CJS=2.08E−13 .MODEL T12B1 NPN + IS=7.53E−17 BF=85 RB=707 BR=5 + RC=87.8 RE=3.75 CJE=.11E−12 CJC=.14E−12 CJS=.14E−12 .MODEL T12B4 NPN + IS=17E−17 BF=85 RB=750 BR=5 http://onsemi.com 32 AN1598/D + RC=25.27 CJE=1.14E−13 CJC=1.3E−13 CJS=1.477E−13 .MODEL T16I3 NPN + IS=7.96E−17 BF=85 RB=240 BR=5 + RC=63.1 RE=3.75 CJE=.12E−12 CJC=.27E−12 CJS=.25E−12 .MODEL T16I2 NPN + IS=7.96E−17 BF=85 RB=240 BR=5 + RC=88.6 RE=3.75 CJE=.12E−12 CJC=.25E−12 CJS=.18E−12 .MODEL T18B1 NPN + IS=1.10E−16 BF=85 RB=456 BR=5 + RC=61.3 RE=2.5 CJE=.17E−12 CJC=.19E−12 CJS=.19E−12 .MODEL T5406 NPN + IS=3.3E−16 BF=85 RB=86.6 BR=5 + RC=23.6 RE=.833 CJE=.495E−12 CJC=.722E−12 CJS=.576E−12 .MODEL T8106 NPN + IS=1.6E−16 BF=85 RB=61.1 BR=5 + RC=16 RE=.57 CJE=.726E−12 CJC=.556E−12 CJS=.724E−12 .MODEL TPNP2 PNP + IS=7.69E−17 BF=5 BR=1 RB=164 RC=56 CJE=.086E−12 + CJC=1.4E−12 .MODEL C15PF NPN + IS=8.9426E−16 BF=85 BR=5 RB=1016.2 RC=27 RE=.2 + CJE=1.2E−12 CJC=.64E−12 CJS=.4E−12 .MODEL RXCX1 NPN + IS=4.6077E−16 BF=85 BR=5 RB=7084 RC=24 RE=.5 + CJE=.647E−12 CJC=3.855E−12 CJS=.786E−12 .MODEL C60PF NPN + IS=8.8224E−16 BF=85 BR=5 RB=141 RC=16 RE=.3 + CJE=3.657E−12 CJC=2.927E−12 CJS=1.029E−12 .MODEL C90PF NPN + IS=1.419E−15 BF=85 BR=5 RB=16 RC=9 RE=.4 + CJE=5.325E−12 CJC=4.452E−12 CJS=1.448E−12 ********************************************************************** * Resistor Diode Model * * * ********************************************************************** .MODEL RES−DIODE D + IS=3.7E−16 CJO=4.14E−13 http://onsemi.com 33 AN1598/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 34 For additional information, please contact your local Sales Representative. AN1598/D