STK5F1U3xx Series Application Note

 STK5F1U3xx series
Application Note
http://onsemi.com
1. Product synopsis This application handbook is intended to provide practical guidelines for the STK5F1U3xx series use. The STK5F1U3xx series is hybrid ICs based upon ONs Insulated Metal Substrate Technology (IMST) for 3‐phase motor drives which contain the main power circuitry and the supporting control circuitry. The key functions are outlined below:  Highly integrated device containing all High Voltage (HV) control from HV‐DC to 3‐phase outputs in a single small DIP module.  Output stage uses IGBT/FRD technology and implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are provided for high side gate boost drive.  Option of a combined or individual shunt resistor per phase for OCP.  Externally accessible embedded thermistor for substrate temperature measurement.  All control inputs and status outputs are at low voltage levels directly compatible with microcon‐
trollers.  Single control power supply due to Internal bootstrap circuit for high side pre‐driver circuit.  Mounting points are available on DIP package A simplified block diagram of a motor control system is shown if Figure 1. Figure 1.
Motor Control System Block Diagram Semiconductor Components Industries, LLC, 2014
February, 2014
1/24
Rev.0
STK5F1U3xx series Application Note
2. Product description Table1. gives an overview of the available devices, for a detailed description of the packages refer to Chapter 6.
Device Feature Package Voltage (VCEmax.)
Current (Ic) Peak current (Ic) Isolation voltage Shunt resistance STK5F1U3C2D‐E
STK5F1U3E2D‐E
Single shunt
DIP4
600V
600V
30A
50A
49A
76A
2000V
2000V
13.5mΩ
9mΩ
Table 1. Device Overview NC(23,24)
U(34,35,36)
V(30,31,32)
W(26,27,28)
VB1(1)
VS1(2)
VB2(4)
VS2(5)
VB3(7)
VS1(8)
P
(42,43,44)
DB
DB DB
U.V.
U.V.
U.V.
RB
N
(38,39,40)
Shunt-Resistor
ISO(17)
Thermistor
TH(18)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1(10)
HIN2(11)
HIN3(12)
Logic
Logic
Logic
LIN1(13)
LIN2(14)
LIN3(15)
Shutdown
VDD(19)
Under voltage
Detect
S
+
Q
Timer
VSS(20)
Vref
Latch time about 18 to 80ms
ISD(21)
FAULT(16)
NC(22)
Figure 2.
STK5F1U3xx series equivalent circuits The high side drive is used with a bootstrap circuit to generate the higher voltage needed for gate drive. The Boost diodes are internal to the part and sourced from VDD (15V). There is an internal level shift cir‐
cuit for the high side drive signals allowing all control signals to be driven directly from Vss levels common with the control circuit such as the microcontroller without requiring external level shift such as opto iso‐
lators. 2/24
STK5F1U3xx series Application Note
3. Performance test guidelines The following Chapter gives performance test method shown in Figures 3 to 7. 3.1. Switching time definition and performance test method trr
10%
90%
VCE
90%
10%
Io
td(ON)
10%
td(OFF)
tr
tf
tOFF
tON
IN
Figure 3.
Switching time definition Ex) Lower side U phase measurement
VD1=15V
1
2
VD2=15V
4
5
VD3=15V
7
VD4=15V
Input signal
42,43,44
34,35,36
VCC
CS
8
19
Io
13 38,39,40
20,21
Figure 4.
Evaluation circuit (Inductive load) H-IC
Ho
HIN1,2,3
CS
Driver
Io
LIN1,2,3
Input signal
VCC
U,V,W
Lo
Io
Input signal
Io
Figure 5.
Switching loss circuit 3/24
STK5F1U3xx series Application Note
H-IC
Ho
HIN1,2,3
CS
Driver
Io
LIN1,2,3
Input signal
VCC
U,V,W
Lo
Io
Input signal
Io
Figure 6.
R.B.SOA circuit H-IC
Ho
HIN1,2,3
CS
Driver
Io
LIN1,2,3
Input signal
VCC
U,V,W
Lo
Io
Input signal
Io
Figure 7.
S.C.SOA circuit 4/24
STK5F1U3xx series Application Note
3.2. Thermistor Characteristics An integrated thermistor is used to sense the internal module temperature its electrical characteristic is outlined below. Parameter
Resistance
Resistance
B-Constant(25-50°C)
Symbol
R25
Condition
Tc=25°C
R100
Tc=100°C
B
Temperature Range
Min
97
Typ.
100
Max
103
Unit
kΩ
4.93
5.38
5.88
kΩ
4165
4250
4335
K
°C
-40
+125
Table 2. NTC Thermistor value Rt is the value of the integrated NTC thermistor at Tc=25°C. The resistance value is 100kΩ±3% and the value of the B‐Constant (25‐50°C) is 4250K±2%. The temperature depended value is calculated as shown in the formula. 1
R(t)= R25 x e B( T
The resulting in the NTC values over temperatures 1
298
)
Figure 8.
typical NTC value over temperature
4. Protective functions and Operation Sequence This chapter describes the protection features.  over current protection  short circuit protection  under Voltage Lockout (UVLO) protection  cross conduction prevention 5/24
STK5F1U3xx series Application Note
4.1. Over current protection Over current protection is implemented by measuring the voltage across a shunt resistor to the negative supply terminal. In case of an OCP fault the gate drivers are shut down internally and the external Fault signal becomes active (low). The trip level of the over current protection current is programmable with an external resistance RSD between the ISD and VSS terminals as shown in over current protection Figure 9. Figure 9.
over current protection circuit Once activated by a fault condition the FAULT signal output returns to inactive (and is pulled high by the external resistor) when the fault condition is over and the fault clear time (FLTCLR) has passed. This im‐
plies that the system microcontroller needs to disable all input signals to the module by driving them low upon detection of a fault condition. The OCP trip level is programmed within the default or lower levels by an external resistor (RSD) between the ISD and VSD pins according to Figure 10. When the default level is used both terminals must be shorted e.g. by a 0Ω resistor. Note 1: One should be aware that the “N” and the “VSS” pins are internally connected. Therefore an external short between these pins can cause the OCP level to be lower than desired. Note 2: In order to prevent false OCP events due to switching noise and recovery current – a blank‐
ing time of some microseconds is implemented. This blanking time will also filter repetitive short high current pulses without tripping the OCP. Over Current Protection (ISD) [A] (RSD) [kΩ] min typ max 0
58.8
66.4
74.2
2
57.0
64.3
71.7
3.9
55.7
62.8
70.1
5.6
54.9
61.9
69.0
10
53.4
60.1
67.1
22
51.5
57.9
64.6
47
50.1
56.4
62.8
100
49.3
55.4
61.7
Open
48.4
54.4
60.6
Set up of Over current protection (ISD)
80
Over Current Protection Level (ISD) [Ａ]
External Resistance 76
72
68
min
typ
max
64
60
56
52
48
0
Figure 10.
10
20
30
40
50
External Resistor Value (ISD-Vss) (RSD) [kΩ]
STK5F1U3E2D‐E RSD values and resulting ISD curve 6/24
STK5F1U3xx series Application Note
Over Current Protection (ISD) [A] Set up of Over current protection (ISD)
(RSD) [kΩ] min typ max 0
38.6
43.6
48.6
2
37.5
42.3
47.3
3.9
36.8
41.5
46.3
5.6
36.3
40.9
45.7
10
35.4
39.9
44.5
22
34.2
38.6
43.0
47
33.4
37.6
41.9
100
32.8
37.0
41.2
Open
32.3
36.3
40.4
50
Over Current Protection Level (ISD) [Ａ]
External Resistance 48
46
44
42
min
typ
max
40
38
36
34
32
30
0
10
20
30
40
50
External Resistor Value (ISD-Vss) (RSD) [kΩ]
Figure 11.
STK5F1U3C2A‐E RSD values and resulting ISD curve HIN/LIN
Protection state
Set
Reset
HVG/LVG
Normal operation
Over current
Over current
detection
IGBT turn off
Output Current Ic (A)
Over current reference voltage
Voltage of
Shunt resistor
RC circuit time constant
Fault output
Fault output
Figure 12.
Over current protection Timing chart 4.2. Under Voltage Lockout Protection The UVLO protection is designed to prevent unexpected operating behavior as described in Table 3. Both High‐side and Low‐side have UV protecting function. However the fault signal output only corresponds to the Low‐side UVLO Protection. During the UVLO state the fault output is continuously driven (low). 7/24
STK5F1U3xx series Application Note
VDD Voltage (typ. Value)
Operation behavior
< 12.5V
As the voltage is lower than the UVLO threshold the control
circuit is not fully turned on.
A perfect functionality cannot be guaranteed.
12.5 V – 13.5 V
IGBTs can work, however conduction and switching losses
increase due to low voltage gate signal.
13.5 V – 16.5 V
Recommended conditions
16.5 V – 20.0 V
IGBTs can work. Switching speed is faster and saturation
current higher, increasing short-circuit broken risk.
> 20.0 V
Control circuit is destroyed. Absolute max. rating is 20 V.
Table 3. Module operation according to control supply voltage The sequence of events in case of a low side UVLO event (IGBTs turned off and active fault output) is shown in Figure 13. Figure 14 shows the same for a high side UVLO (IGBTs turned off and no fault output). LIN
Reset
Protection state
Control supply voltage VD
Set
Under voltage trip
Reset
Under voltage reset
Normal operation
Output Current Ic (A)
After the voltage level reaches UV reset, the circuits start to
operate when next input is applied .
IGBT turn off
Fault output
Fault output
Figure 13.
Low side UVLO timing chart 8/24
STK5F1U3xx series Application Note
HIN
Reset
Protection state
Control supply voltage VD
Set
Reset
Under voltage reset
Under voltage trip
Normal operation
Output Current Ic (A)
IGBT turn off
After the voltage level reaches UV reset, the circuits start to
operate when next input is applied .
Fault output
Keeping high level output ( No Fault output )
Figure 14.
High side UVLO timing chart 4.3. Cross conduction prevention The STK5F1U3xx series module implement a cross conduction prevention logic at the pre‐driver to avoid simultaneous drive of the low‐ and high‐side IGBTs as shown in Figure 15. V+
High side driver
HIN
INPUT
NOISE
FILTER
HVG
DEADTIME&
SHOOT-THROUGH
PREVENTION
LIN
U,V,W
LVG
INPUT
NOISE
FILTER
Low side driver
Figure 15.
VRU
VRV
VRW
Cross Input Conduction Prevention In case of both high and low side drive inputs are active (high) the logic prevents both gates from being driven – a corresponding timing diagram can be found in Figure 16 below. 9/24
STK5F1U3xx series Application Note
HIN
LIN
Shoot-Through
Prevention
HVG
Normal operation
Normal operation
LVG
VDD
Fault output
Keeping high level output ( No Fault output )
Figure 16.
cross conduction prevention timing diagram Even so cross conduction on the IGBTs due to incorrect external driving signals is prevented by the cir‐
cuitry the driving signals (HIN and LIN) need to include a “dead time”. This period where both inputs are inactive between either one becoming active is required due to the internal delays within the IGBTs. Fig‐
ure 17 shows the delay from the HIN‐input via the internal HVG to high side IGBT, the similar path for the low side and the resulting minimum dead time which is equal to the potential shoot through period: HIN
LIN
tON
High Side IGBT
Low Side IGBT
tOFF
Shoot-Trough Period
Dead time = tOFF-tON
Figure 17.
Shoot Trough Period 10/24
STK5F1U3xx series Application Note
5. PCB design and mounting guidelines This chapter provides guidelines for an optimized design and PCB layout as well as module mounting recommendations to appropriately handle and assemble the HIC module. 5.1. Application (schematic) design The following two figures18 gives an overview of the external circuitry’s functionality when designing with the STK5F1U3xx series module. Noise absorb
Restraint of surge voltage
and vibration voltage
Stability of VB
1
Prevention of voltage
up by the surge voltage
Vz<
22V
Vz<
22V
Prevention of miss
operation by the noise
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
Vz<
22V
47uF
/25V
2
100nF
/25V
4
47uF 100nF
/25V /25V
47uF 100nF
/25V /25V
5
7
8
13
14
15
0.1uF
/630V
DC IN
N
snubber
38,39,40
DC OUT
VB1
VS1
U
HIN2
100
34,35,36
V
30,31,32
W
26,27,28
HIN3
LIN1
LIN2
U
V
To
compressor
W
LIN3
100
3.3k x 6
Control power
Signal GND
Fault
Temp.
16
17
18
+15V
To
Controller
From small
voltage to
large voltage
VS1
11
12
42,43,44
P
VB1
HIN1
100
100
VS1
10
100
100
VB1
100nF
/25V
19
20
Vz<
22V
FAULT
ISO
TH
VDD
VSS
220uF
/25V
Amp.
21
22
Prevention of voltage
up by the surge voltage
RSD
NC
NC
NC
24
23
Stability of VDD
Noise absorb
Figure 18.
STK5F1U3xx series application circuit 11/24
STK5F1U3xx series Application Note
5.2. Notes on PCB design (1) Snubber capacitor between the positive terminal and the negative terminal of the power,
please place as close as possible to the hybrid IC. (2) Power side GND and control side GND must not be a solid common wiring. Signal side GND is recommended to design the patterns in one point of connection to Vss terminal so that it does not flow to the power side the GND signal current.
The terminal Vss (control side GND) is connected to N terminal (power side GND) in the interior of the hybrid IC. (3) Capacitor and zener diode should be placed close to the terminal. (4) C‐R filter should be placed close to the terminal. (5) Capacitor and zener diode should be placed close to the terminal. STK5F1U3xx series
P N
Figure 19.
STK5F1U3xx series PCB design 5.3. Pin by pin design and usage notes This section provides pin by pin PCB layout recommendations and usage notes. For a complete list of module pins refer to the datasheet or Chapter 6. P & N These pins are connected with the main DC power supply. The applied voltage is up to the Vcc level. Overvoltage on these pins could be generated by voltage spikes during switching at the floating inductance of the wiring. To avoid this behavior the wire trac‐
es need to be as short as possible to reduce the floating inductance. In addition a snubber capacitor needs to be placed as close as possible to these pins to stabilize the voltage and absorb voltage surges. 12/24
STK5F1U3xx series Application Note
U, V, W These terminals are the output pins for connecting the 3‐phase motor. They share the same GND potential with each of the high side control power supplies. Therefore they are also used to connect the GND of the of the bootstrap capacitors. These bootstrap capacitors should be placed as close to the module as possible. These pins connect with the circuitry of the internal protection and pre‐drivers for the low ‐side power elements and also with the control power supply of the logic circuitry. Voltage to input these terminals is monitored by the under voltage protection circuit. The VSS terminal is the reference voltage for the control inputs signals as well as Fault and ISO. VSS is connected with the “ N“ terminal internally. The main circuit does typi‐
cally not draw current from VSS. When the “N“ and “VSS” pins are connected externally care must be taken to select a single connection point as close as possible to the IC. In case of multiple connections to these pins and longer traces being used, the overcurrent protection level may become low. Therefor this should be avoided. VDD, VSS The VBx pins are internally connected to the positive supply of the high‐side drivers. The supply needs to be floating and electrically isolated. The boot‐strap circuit shown in Figure 20 forms this power supply individually for every phase. Due to integrated boot resistor and diode (RB & DB) only an external boot capacitor (CB) is required. VB1, VB2, VB3 There are two current path to charge CB – depicted as ① and ②. ① when the low side power IGBT is ON ② when motor current is flows in CB The capacitor is discharged while the high‐side driver is activated. Thus CB needs to be selected taking the maximum on time of the high side and the switching frequency into account. DB
CB
Driver RB ② ①
VDD
Driver
Figure 20.
Boot Strap Circuit To set an initial charge on CB a high ohmic resistor can be used between the motor and the “N“ pins – considering the max voltage rating of the device. The voltages on the high side drivers are individually monitored by the under voltage protection circuit. In case an UVP event is detected on a phase its operation is stopped.
13/24
STK5F1U3xx series Application Note
HIN1, LIN1, HIN2, LIN2, HIN3, LIN3 Typically a CB value of less or equal 47uF (±20%) is used. In case the CB value needs to be higher an external resistor (of apx. 20Ω or less) should be used in series with the capacitor to avoid high currents which can cause malfunction of the hybrid IC. These pins are the control inputs for the power stages. The inputs on HIN1/HIN2/HIN3 control the high‐side transistors of U/V/W, and the inputs on LIN1/LIN2/LIN3 control the low‐side transistors of U/V/W respectively. The input are active high and the input thresholds VIH and VIL are 5V compatible to allow direct control with a microcontroller system Simultaneous activation of both low and high side is prevented internally to avoid shoot through at the power stage. However, due to IGBT switching delays the control signals must include a dead‐time. The equivalent input stage circuit is shown in Figure 21. IN VSS
33kΩ Figure 21.
Fault Internal Input Circuit For fail safe operation the control inputs are internally tied to VSS via a 33kΩ (typ) re‐
sistor. To avoid switching captured by external wiring to influence the module behavior an additional external low‐ohmic pull‐down resistor with a value of 2.2kΩ‐3.3kΩ should be used. The output might not respond when the width of the input pulse is less than 1µs (both ON and OFF). The Fault pin is an active low input and open‐drain output. It is used to indicate an in‐
ternal fault condition of the module and also can be used to disable the module opera‐
tion. The I/O structure is shown in Figure 22. The internal sink current IoSD during an active fault is nominal 2mA @ 0.1V. Depending on the interface supply voltage the external pull‐up resistor (RP) needs to be selected to set the low voltage below the VIL trip level. For the commonly used supplies VP: VP = 15V ‐> RP >= 20kΩ VP = 5V ‐> RP>= 6.8kΩ 14/24
STK5F1U3xx series Application Note
VP
VDD
RP FAULT
VSS Figure 22.
Fault Connection For a detailed description of the fault operation refer to Chapter 4. Note: The Fault signal does not latch permanently. The modules operation is automat‐
ically re‐started after the causing protection event end and after the minimum of the fault timeout(18ms). Therefore the input needs to be driven low externally activated as soon as a fault is detected. The ISO pin allows monitoring the output voltage of the integrated current sense am‐
plifier. This pin is usually left unconnected. Any external circuitry needs to have an impedeance higher than 5.6kΩ. Note: In case this pin is shorted to VSS – current sensing will not function. 0.60
0.50
0.40
0.30
0.20
STK5F1U3C2D-E
STK5F1U3E2D-E
0.10
0.00
30
0
10
20
40
50
60
Output curent
(A)
ISO Output Voltage (V)
ISO Figure 23.
The output current (Io) vs ISO characteristics TH RCIN An internal thermistor to sense the substrate temperature is connected between VSS and the TH pins. In conjunction with an external pull‐up resistor Rth a module temper‐
ature monitor can be build. Note: with this mimic only the substrate temperature can be monitored. This pin is used to the set the fault clear time. It is recommended to leave this pin open to select the default fault clear time of 18 ms. 15/24
STK5F1U3xx series Application Note
Figure 24.
RCIN Circuit To shorten the fault clear time connect an external resistor RF between VDD and RCIN. To extend the fault clear time) connect an external capacitor CF between RCIN and VSS.
5.4. Heat sink mounting and torque If a heat sink is used, insufficiently secure or inappropriate mounting can lead to a failure of the heat sink to dissipate heat adequately. This can lead to an inability of the device to provide its inherent perfor‐
mance, a serious reduction in reliability, or even destruction, burst and burn of the device due to over‐
heating. The following general points should be observed when mounting H‐IC on a heat sink: 1. Verify the following points related to the heat sink: ‐ There must be no burrs on aluminum or copper heat sinks. ‐ Screw holes must be countersunk. ‐ There must be no unevenness in the heat sink surface that contacts H‐IC. ‐ There must be no contamination on the heat sink surface that contacts H‐IC. 2. Highly thermal conductive silicone grease needs to be applied to the whole back (aluminum substrate side) uniformly, and mount H‐IC on a heat sink. Upon re‐mounting apply silicone grease(100um to 200um) again uniformly. 3. For an intimate contact between the H‐IC and the heat sink, the mounting screws should be tightened gradually and sequentially while a left/right balance in pressure is maintained. Either a bind head screw or a truss head screw is recommended. Please do not use tapping screw. We recommend using a flat washer in order to prevent slack. The standard heat sink mounting condition of an STK5F1U3xx series is as follows. 16/24
STK5F1U3xx series Application Note
Item
Recommended Condition
68.0 0.1mm (Please refer to Package Outline Diagram)
Pitch
Screw
Washer
diameter : M4
Bind machine screw, Truss machine screw, Pan machine screw
Plane washer
The size is D:9mm, d:4.8mm and t:0.8mm (Fig.2) JIS B 1256
Heat
sink
Material : copper or Aluminum
Warpage (the surface that contacts H‐IC) : ‐50 to 100 μm
Screw holes must be countersunk.
No contamination on the heat sink surface that contacts H‐IC.
Torque
Final tightening : 0.79 to 1.17Nm
Temporary tightening : 20 to 30 % of final tightening Grease
Silicon grease
Thickness : 100 to 200 μm
Uniformly apply silicon grease to whole back. (Fig.3)
Table 4. heat sink mounting HIC
Figure 25.
Mount on Heat Sink steps to mount an HIC on a heat sink 1st: Temporarily tighten maintaining a left/right balance. 2nd : Finally tighten maintaining a left/right balance. 17/24
STK5F1U3xx series Application Note
5.5. Mounting and PCB considerations (general information) In designs in which the printed circuit board and the heat sink are mounted to the chassis independently, use a mechanical design which avoids a gap between H‐IC and the heat sink, or which avoids stress to the lead frame of H‐IC by an assembly that a moving H‐IC is forcibly fixed to the heat sink with a screw. Figure 26.
Fix to Heat Sink Do not mount H‐IC with a tilted orientation. This can result in stress being applied to the lead frame and H‐IC substrate could short out tracks on the printed circuit board. Always mount the H‐IC vertically. If stress is given by compulsory correction of a lead frame after the mounting, a lead frame may drop out. Be careful of this point. When designing the PCB layout take care that the bent part portion of the lead frame pins does not short‐circuit to VIA holes or tracks on the PCB. Since the use of sockets to mount H‐IC can result in poor contact with H‐IC leads, we strongly recommend making direct connections to PCB. H‐IC modules are flame retardant. However, under certain conditions, it may burn, and poisonous gas may be generated or it may explode. Therefore, the mounting structure of the H‐IC module should also be flame retardant. Mounting on a Printed Circuit Board 1. Align the lead frame with the holes in the printed circuit board and do not use excessive force when inserting the pins into the printed circuit board. To avoid bending the lead frames, do not try to force pins into the printed circuit board unreasonably. 2. Do not insert H‐IC into printed circuit board with an incorrect orientation, i.e. be sure to prevent reverse insertion. H‐IC may be destroyed, exploded, burned or suffer a reduction in their operating lifetime by this mistake. 3. Do not bend the lead frame. 5.6. Cleaning H‐IC has a structure that is unable to withstand cleaning. As a basic policy, do not clean independent H‐IC or printed circuit boards on which an H‐IC is mounted. 18/24
STK5F1U3xx series Application Note
6. Package Outline STK5F1U3xx series is DIP4 package. (Dual‐line‐package) 6.1. Package outline and dimension Note2 Note1
Figure 27.
STK5F1U3xx series Package Outline 6.2. Laser Marking Note 1: Note2: The labeling designates the model number – centered within a field of 4.5 mm width and 35 mm length The labeling designates the order number – right justified within a field of 3.5 mm width and 14 mm length *We examine the design except for the above. 19/24
STK5F1U3xx series Application Note
6.3. Pin Out Description Pin No.
Name
Description
Pin No.
Name
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VB1
VS1
VB2
VS2
VB3
VS3
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
FAULT
ISO
TH
VDD
VSS
ISD
High side floating supply voltage 1
High side floating supply offset voltage
Without pin
High side floating supply voltage 2
High side floating supply offset voltage
Without pin
High side floating supply voltage 3
High side floating supply offset voltage
Without pin
Logic input high side driver-Phase1
Logic input high side driver-Phase2
Logic input high side driver-Phase3
Logic input low side driver-Phase1
Logic input low side driver-Phase2
Logic input low side driver-Phase3
Fault out (open drain)
Current monitor pin
Thermistor out
+15V main supply
Negative main supply
Over-current protection level setting pin
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
P
P
P
N
N
N
U
U
U
V
V
V
W
W
W
NC
Positive bus input voltage
Positive bus input voltage
Positive bus input voltage
Without pin
Negative bus input voltage
Negative bus input voltage
Negative bus input voltage
Without pin
U-phase output
U-phase output
U-phase output
Without pin
V-phase output
V-phase output
V-phase output
Without pin
W-phase output
W-phase output
W-phase output
Without pin
-
22
NC
-
23
NC
-
20/24
STK5F1U3xx series Application Note
7. Demo Board The demo board consists of the minimum required components such as snubber capacitor and bootstrap circuit elements of STK5F1U3xx series. P P P N N N Figure 28.
evaluation board schematic Top view Bottom view PCB dimension : 200 x 150 x 1.5 t (mm) Material : FR‐4, Dabble layer Cu thickness : 70um
Figure 29.
evaluation board picture STK5F1U3xxx‐E 21/24
STK5F1U3xx series Application Note
Top view
Bottm view
Figure 30.
evaluation board PCB layout 22/24
STK5F1U3xx series Application Note
33
34
HIC
P
Bottom layer
N Please use these
terminals as the
U connection with a
V motor, and an object
f or power supply
W voltage connection.
1
TP1.
TP2.
TP3.
TP4.
TP5.
TP6.
TP7.
TP8.
VB1
VB2
VB3
VDD
Fault
ISO
NC
TH
TP9. ISD
TP10.HIN1
TP11.HIN2
TP12.HIN3
TP14.LIN1
TP15.LIN2
TP16.LIN3
2
1. VDD2 (+5V)
3. VDD2 (+5V)
5. Vth OUT
7. ISO
9. NC
11.Fault
13.LIN3
15.LIN2
17.LIN1
19.HIN3
21.HIN2
23.HIN1
Please use these
25.NC
pins as an object
27.NC
f or the
29.NC
connection to the
31.NC
control part.
33.NC
2 to34. Control Signal GND
These pins can
be used as test
pin of each
control signal.
Figure 31.
DC
Power
supply
+
-
evaluation board connectors ②,⑤
U
V
Logic
HIC
Bottom layer
W
DC15V
④
①
③
①: HIC, each power supply, the logic parts, and the motor are connected to an evaluation board.
Please confirm that each power supply is OFF at this time.
②: Please stand by for operation of the logic parts.
③: The power supply of DC 15V is switched on.
④: Please perform a voltage setup according to specifications, and switch on the power supply
between the P and the N terminal.
⑤: Control of HIC is started from the logic parts.
(Boot strap circuit has included in STK 5FxU3xx-E. So before running please set electric
charge to upper side of boot strap capacitor to turn on Lower side of IGBT.)
※ When you turn off a power supply,
please turn OFF the switch of a power supply part and a logic part in a reverse order from ④.
Figure 32.
evaluation board instructions 23/24
STK5F1U3xx series Application Note
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