STV1601A SERIAL INTERFACE TRANSMISSION ENCODER THIS IC CONTAINS ALL THE CIRCUITS NEEDED FOR CONVERSION FROM PARALLEL DATA, AND PARALLEL CLOCK, INTO SERIAL DATA. APPLICATIONS ARE STRAIGHTFORWARD AS ONLY A FEW EXTERNAL COMPONENTS ARE NEEDED. OTHER RELATED IC’s INCLUDE : STV1602A, A SERIAL TRANSMISSION DECODER (WITH A BUILT-IN CABLE EQUALIZER AND PARALLEL-TO-SERIAL CONVERSION) STV1389AQ COAXIAL CABLE DRIVER . . . CODE LIMITATION The word composing the Sync word listed above shall not appear during data words. This limitation includes 00 and FF in 8-bit use and 000 through 003 and 3FC through 3FF in 10-bit use. DESCRIPTION The STV1601Ais a Hybrid IC encoder that converts parallel data into serial data for a serial transmission line. STRUCTURE Hybrid IC APPLICATIONS ORDER CODE : STV1601A D0X D1Y D1X D2Y D2X D3Y 27 26 25 24 23 22 21 20 19 RSE 28 18 D3X V CC 29 17 D4Y PCX 30 16 D4X PCY 31 15 D5Y GND 32 14 D5X D7Y 10 D7X TN1 35 1st word FFH 3FFH PCK 36 37 NC 2nd word 00H 000H 3rd word 00H 000H November 1992 2 GND LST Sync word conversion (8-bit timing reference signal is internally converted to 10-bit). 1 3 4 5 6 7 8 9 1601A-01.EPS 11 10 bit D8Y D6X 8 bit D8X D6Y 12 D9Y 13 34 D9X 33 GND FV TRP SY Parallel-to-serial conversion Scrambler : Modulo - 2 division by G(x) = (x9 + x4 + 1) (x + 1) PLL for serial clock generation PLL lock detection Sync word required with the parallel data stream D0Y FUNCTIONS V EE PIN CONNECTIONS V EE APPLICATIONS EXAMPLES Serial data transmission of digital television signal 525-625 lines 4:2:2 component 270Mb/s (10-BIT) 4*FSC PAL composite 177Mb/s (10-BIT) 4*FSC NTSC composite 143Mb/s (10-BIT) SX . . .. . .. .. . PGA37 (Ceramic Package) SERIAL DATA TRANSMISSION ENCODER 100 to 270 Mb/s 1/17 STV1601A PIN DESCRIPTION Pin Symbol N Equivalent circuit GND Description I/O PLL lock detection. Is High while PLL locked. If unlocked, becomes irregular. At free running (TN1 H) turns Low H L O Clock output frequency divided to 1/10 VCO output. Used to check VCO free running frequency H L O Standard Min. Typ. Max. Unit V CC 4kΩ 1 LST 1 -4.0 V V 2kΩ 1601A-02.EPS 2kΩ -1.0 VEE GND 600Ω PCK 36 -0.8 -1.6 V V -1.6 -2.4 V V 1601A-03.EPS 36 600Ω 240Ω V EE GND 10 0Ω SX VCC 100Ω 30Ω Differential Serial Output Input parallel data is converted to serial, then from scrambled NRZ to NRZI data H L 30Ω 4 3 4 SY 2kΩ VEE 2/17 115Ω 2kΩ 1601A-04.EPS VR3 O 1601A-01.TBL VCC 3 STV1601A PIN DESCRIPTION (continued) Pin Symbol N 29 VCC Equivalent circuit 29 1kΩ D9X D9Y D8X D8Y D7X D7Y D6X D6Y D5X D5Y D4X D4Y D3X D3Y D2X D2Y D1X D1Y D0X D0Y 6 7 V R3 2kΩ V EE 1601A-05.EPS 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description I/O Parallel data and clock input buffers power supply. When this pin is connected to +5V, parallel data clock turns to TTL mode. When this pin is connected to GND, parallel data clock turns to ECL mode. - Parallel input ports: LSB : D0X or Y MSB : D9X or Y Signal : DnX Return : DnY For ECL mode, VCC shalll be 0V H L ForTTL mode, VCC shall be +5V H L Standard Min. Typ. Max. Unit -1.0 -1.6 V V 0.8 V V -4.0 V V 2.0 GND 2kΩ VCO range selection H : high range 140 to 270MHz L : low range 100 to 145MHz H L 28 RSE 70kΩ 10kΩ V EE 1601A-02.TBL 10kΩ -0.4 1601A-06.EPS 28 I 3/17 STV1601A PIN DESCRIPTION (continued) Pin Symbol N Equivalent circuit Description I/O Standard Min. Typ. Max. Unit VCC 2kΩ 30 2kΩ PCX Parallel clock (PCX) and its return (PCY) For ECL mode, VCC = 0 H L For TTL mode, VCC = +5V H L 30 31 V R3 -1.0 -1.6 V V 0.8 V V 2.0 PCY 2kΩ VEE 1601A-07.EPS 31 I 2, 5, 32 GND GND 26 VEE -5V power supply I/O buffer PLL -5.2 -5.0 -4.8 V 27 VEE -5V power supply Logic part -5.2 -5.0 -4.8 V GND 33 VCC 0.022µF FV 220Ω 1kΩ 1kΩ 34 0.1µF 1kΩ 1kΩ 10kΩ V9 1601A-08.EPS 2µF TRP I VCO input and phase comparator output should be connected to a parallel clock frequency trap filter to minimize jitter O Test mode : High : VCO free running condition (input disabled) Low : Normal mode (input enabled) I -3.9 V -3.2 V 33 1kΩ 34 VCO free running frequency adjustment : VEE level gives the lowest frequency. To adjust, set TN1 high. VE E VCC GND 12kΩ 20kΩ 35 TN1 1 -1.0 V -4.5 V VR3 4/17 1601A-03.TBL VEE 1601A-09.EPS 4kΩ STV1601A BLOCK DIAGRAM PCY PCX 31 30 TN1 FV TRP RSE PCK 35 33 34 28 36 37 N.C. LST PHAS E DETECT OR PLL LOCK DE TECTOR 1 TIMING GENERATOR VCO 2 GND 5 GND 3 NRZ ⊗ NRZI SY Serial Clock SX 9 Parallel Load Parallel Clock 4 X + X + 1 SCR AMBLER 4 32 GND PAR ALELL TO SERIAL CONVER TER 26 V EE 000hex DETECTO R 10-BIT X 3 WORD SHIFT REGISTER 1601A-10.EPS 25 D0Y 23 24 D0X 22 D1Y 20 21 D1X 19 D2Y 17 18 D2X D7X 16 D3Y D8Y 14 15 D3X D8X 13 D4Y D9Y 12 D4X 10 11 D5Y 9 D5X 8 D6Y 7 D6X 6 D7Y 29 V CC D9X 27 V EE Parameter Supply Voltage Supply Voltage Input Voltage Output Current Operating Temperature Storage Temperature Allowable Power Dissipation Value -6 +6 VEE to VCC -30 0 to 65 -50 to 125 2.0 Unit V V V mA o C o C W 1601A-04.TBL Symbol VEE VCC VIN IOUT Toper Tstg PD Value -4.8 to -5.2 4.8 to 5.2 0 to 65 Unit V V o C 1601A-05.TBL ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Symbol VEE VCC Toper Parameter Supply Voltage Supply Voltage * Operating Temperature * For TTL input. Voltages are given with respect to GND ELECTRICAL CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA = 25oC unless otherwise speciied) Parameter Test Conditions Test Circuit Min. Typ. Max. Unit IEE ICC Supply Current 1 Supply Current 2 Figure 2 140 7 mA mA 5/17 1601A-06.TBL Symbol DC CHARACTERISTICS STV1601A ELECTRICAL CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA = 25oC unless otherwise speciied) Symbol Parameter Test Conditions Test Circuit Min. VCC = GND PCX, PCY, DnX, DnY -1.0 VCC = +5V PCX, PCY, DnX, DnY 2.0 Typ. Max. Unit DC CHARACTERISTICS VIH VIL VIH VIL IIH IIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL Input Voltage Input Current -1.6 PCX, PCY, DnX, DnY Figure 3 RSE Figure 7 Input Voltage TN1 Figure 6 -1 -0.4 -4.0 -1 -4.5 -0.8 -1.6 PCK R P = 1kΩ Output Voltage 0.8 5 +1 LST IOH = -10µA, IOL = +10µA Figure 5 -1.0 -4.0 -1.6 -2.4 SX, SY R P = 220Ω V V V V µA µA V V V V V V V V V V fMAX1 fMIN1 fMAX2 fMIN2 fHP1 fLP1 fHP2 fLP2 fHP3 fLP3 fOP1 fOP2 VCO VCO VCO VCO tjit Jitter Max. Oscillation Frequency 1 Min. Oscillation Frequency 1 Max. Oscillation Frequency 2 Min. Oscillation Frequency 2 RSE = ”H” PLL Generator Frequency 30.0 14.0 15.0 RSE = ”L” f signal = 270MHz RSE = ”H” PLL Pull in Range Figure 4 10.0 Figure 1 27.7 25.5 f signal = 177MHz RSE = ”H” 18.8 f signal = 143MHz RSE = ”H” 15.0 RSE = ”H” RSE = ”L” f signal = 270MHz RSE = ”H” 14.0 10.0 16.5 13.0 27.0 14.5 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ±0.25 nsec Figure 8 1601A-07.TBL AC CHARACTERISTICS Tested through PCK : 1/10 of serial clock. Parameter Rise Time Fall Time Rise Time Fall Time Test Conditions PCK R P = 1kΩ Test Circuit Min. Figure 10 SX, SY R P = 220Ω Unit nsec nsec nsec nsec 1601A-08.TBL Symbol tr tf tr tf Max. Unit +5 + tc/2 nsec +5 nsec 1601A-09.TBL SWITCHING CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA = 25oC unless otherwise speciied) Typ. 0.8 1.4 0.7 0.7 Max. TIMING RELATION OF INPUT CLOCK AND DATA Symbol tw td 6/17 Parameter Pulse Width Delay Time Test Conditions PCX, PCY PCX - Dn Test Circuit Figure11 Min. -5 + tc/2 -5 Typ. tc/2 1601A-11.EPS SIGNAL GENERATOR HP8180A 0.1 VR +1.4V -1.3V D9Y D8X D8Y 7 8 9 5 32 29 VCC 0.1 -5V -5V B 28 33 SW1 RSE FV 4 3 1 A 22kΩ 10µF/10V 150pF -5V 0.22µ H 0.1 220 Ω PLL LOCK DETECTOR 1kΩ -5V A B LOW RANGE HIGH RANGE -5V 220 Ω 220Ω 0.1 220Ω SW2 ON : AF FREQUENCY ADJUST FREQUENCY MONITOR VCO RANGE SELECT TN1 35 -5V 220Ω TRP 34 SY SX LST PCK 36 N.C. 37 26 VEE 27 0.1 10/16V VEE -5V 10/16V VCC D.U.T. STV1601A GND V R1 10kΩ 25 D0Y 24 D0X 23 D1Y 22 D1X 21 D2Y 20 D2X 19 D3Y 18 D3X 17 D4Y 16 D4X 15 D5Y 14 D5X 13 D6Y 12 D6X 11 D7Y 10 D7X D9X 6 31 PCY 30 PCX 2 +5V GND VCO FREQUENCY ADJUST TTL ECL INPUT LEVEL 0.1 0.1 220Ω -5V 150Ω 0.1 150Ω STV1389AQ 0.1 0.1 75 Ω 75Ω 2 1 SERIAL OUT B A -5V 220 Ω 73Ω SERIAL IN 10kΩ CABLE INPUT DIGITAL INPUT -5V A B INPUT SELECT 0.1 220 Ω 220Ω 41pF 41pF 100Ω 10µF SW2 SX SY 10kΩ VCO FREQUENCY V R2 ADJUST -5V 0.1 35 -5V 0.1 QSW TN1 D9 5 6 9 D8 10 D7 11 D6 12 D5 13 D4 14 D3 15 D2 16 D1 17 D0 18 PCK 19 EVR 21 SYN 20 7 DPR 100kΩ 36 37 1 22 FV 8 V EE STV1602A GND 24 27 30 23 RSE ESO ESI 34 DIY 33 DIX 25 AIY 26 AIX 28 QFS 31 MON 29 CX 32 ADS 4 3 2 0.1 10/16V -5V 10µF 0.1 -5V 0.1 SIGNAL ANALYZER HP8182A 330Ω LED SW3 ON : AF FREQUENCY ADJUST 1kΩ x 8 22kΩ -5V TRS DETECTOR SIGNAL FREQENCY MONITOR 1kΩ x 4 STV1601A Figure 1 : Test Circuit Diagram Example 7/17 STV1601A Figure 2 V CC +5V V EE -5V I CC I EE A A 10/16V 10/16V 0.1 0.1 2 5 32 GND 29 27 V CC 26 V EE 1kΩ PCX 30 220Ω STV1601A SX 3 SY 4 220Ω FV RSE TN1 33 28 35 -5V 0.1µF SW1 10µF POSITION ON 10kΩ 1601A-12.EPS SW1 22kΩ V R1 -5V -5V Figure 4 -5V V1 V2 A1 A2 -0.8V -1.6V -1.6V -0.8V I IH I IL I IL I IH 10/16V 0.1 2 5 32 GND 29 27 26 V EE V CC 1kΩ PCX 30 30 PCX 220Ω STV1601A 31 PCY SX 3 SY 4 220Ω V1 12 FV RSE TN1 33 28 35 -5V 0.1µF V2 10µF SW1 SW2 B 22kΩ V R1 8/17 POSITION ANY ON A 10kΩ -5V SW1 SW2 -5V -5V 1601A-13.EPS 11 STV1601A Figure 4 -5V 10/16V 0.1 2 5 32 29 GND 27 26 FREQUENCY MONITOR V EE V CC 1kΩ PCX 30 220Ω STV1601A SX 3 SY 4 220Ω FV RSE TN1 33 28 35 -5V 0.1µF POSITION SW1 A B SW2 ON ON VCO RANGE HIGH LOW 10µF SW1 SW2 B A 10kΩ 1601A-14.EPS 22kΩ V R1 -5V -5V -5V Figure 5 -5V V1 V2 V -0.8V -1.6V -1.6V -0.8V VOH VOL 10/16V 0.1 2 5 32 29 GND 27 26 V CC V EE 30 PCX 31 PCY STV1601A LST 1 V V2 FV RSE TN1 33 28 35 10µF SW1 SW2 B SW1 SW2 POSITION ANY OFF A 10kΩ 22kΩ 1601A-15.EPS V1 V R1 -5V -5V -5V 9/17 STV1601A Figure 6 Figure 7 -5V 2 5 32 29 GND 31 TN1 -5V 10/16V 10/16V 0.1 0.1 27 26 V CC 2 VEE 5 32 29 GND 27 26 1kΩ V1 PCX 30 30 PCX 28 RSE STV1601A LST 220Ω STV1601A V1 1 SX 3 SY 4 220Ω V 31 PCY -0.8V FREQUENCY MONITOR V EE V CC FV RSE FV TN1 33 28 33 35 -5V 0.1µF -1.6V 10µF 10kΩ 1601A-16.EPS 10kΩ V R1 -5V 22kΩ VR1 -5V -5V 1601A-17.EPS SW2 Figure 8 -5V 10/16V 0.1 2 5 32 GND 29 27 26 V CC VEE TRIGGER FREQUENCY MONITOR -5V 1kΩ STV1389AQ PCX 30 Parallel clock data STV1601A SX 0.1 SIGNAL 75Ω 3 1 220Ω 0.1 SY FV RSE TN1 33 28 35 0.1 4 220Ω 220Ω 150Ω 150Ω 75Ω -5V -5V 0.1µF 0.1µF 2 10µF SW2 SERIAL OUT SIGNAL 270Mb/s 22kΩ VR1 -5V -5V 10/17 jitter = 1/2 1601A-18.EPS t 10kΩ STV1601A Figure 9 : tr, tf Definition serial data. To ease clock extraction at the receiving end, serial data is scrambled. To minimize polarity effect, serial data is then converted to NRZI and output in differential mode. 80% A PLL lock detection circuit only enables the serial output when locked. tr 1601A-19.EPS 20% tf Figure 10 : td, tW Definition tc t c /2 Parallel clock and data are such that the rising edge of PCX should be at the middle of the data. A clock having the same phase as PCX is internally generated in order to latch the data. t c /2 1601A-20.EPS 50% td 1. Phase relation between input parallel clock and data The phase relation between the parallel clock and the data is shown in Figure 11. Both clock and data are differential inputs tw DESCRIPTION STV1601A internally generates a 10 times clock frequency locked to the parallel input clock thanks to a built-in PLLand converts input parallel data into 2. TTL input operation Parallel clock and data can be either TTL or ECL inputs. To use as TTL inputs VCC (Pin 29) shall be connected to +5V. A fixed bias of +1.4V shall be applied to PCY and DnY (n = 0 to 9). TTL signals and their parallel clock will be provided through 1kW resistors to each ”X” input. These 1kW resistors are effective to minimize the influence of the TTL input signals to the jitter characteristics of the serial output signal. For 8-bit data, unused LSB(s) must be fixed Low. Fixed bias value can be higher, for example, 2.5V in case of CMOS inputs. Figure 11 : Phase Relation between Clock and Data PCX (Input) 1601A-21.EPS DATA (Input) PCX (Output) Figure 12 : TTL Input Operation STV1601A PCX PCY D9X D9Y D0X D0Y 29 30 31 5 7 26 25 1kΩ Parallel Clock 1kΩ 1kΩ + 1.4V for TTL + 2.5V for CMOS Parallel Data 1601A-22.EPS + 5V V CC TTL Parallel Signal 11/17 STV1601A 3. PLL block PARALLEL CLOCK INPUT CONTROL PLL, PLL lock detection and the various blocks of the serial output control are shown in Figure 13. When TN1 is connected to GND (set High), the parallel clock input is disabled. The VCO turns to free running conditions and its frequency can be adjusted through FV. This frequency decreases when the resistor value between FV and VEE is reduced. Oscillation frequency monotoring is performed through PCK which delivers a frequency divided by ten. When PLL is locked, PLL and PCX input signal phases are nearly matched. The RC network connected to TN1, temporarily, disables the parallel clock in order to avoid mislocking problems. VCO oscillation frequency range selection is available through RSE ; High : from 140 to 270MHz ; Low : from 100 to 145MHz. TRP (Pin 34) is the phase comparator output. To minimize jitter, a trap circuit, consisting in a serial tuned circuit at parallel clock frequency can be used. PLL LOCK DETECTION The LST signal is generated by latching the incoming parallel clock by the internal one (which is 1/10 of the VCO frequency). LST is used as a PLL lock detection signal and also controls the serial output. If the parallel clock input is disabled (by means of TN1), LST turns Low and the serial output is disabled as described in the previous section (SX (Pin 3) = High, SY (Pin 4) = Low). If the serial output has to be disabled while no parallel clock input is provided, PCX must be set Low and PCY must be set High. 4. Sync word To convert serial data back to parallel, insertion of some timing reference data indicating the parallel data word boundary in the serial data is needed. This, called TRS (Timing Reference Signal) in the digital interface format, consists of the three consecutive words 3FFH, 000H, 000H. Conversion to 10-bit TRS from 8-bit (TRS) 8-bit parallel data 8-bit parallel data can be converted into 10-bit data by using the 8th bit as the MSB and by setting the 2 LSBs at logical states as shown in Figure 14. Figure 13 : PLL and Serial Output Control Block PCY PCX TN1 TRP PHASE COMPARATOR FV RSE VCO PCK 1/10 DIVIDER ”0” LST Q D Q D SX Serial Clock 12/17 NRZ To NRZI CONVERSION SCRAMBLER 1601A-23.EPS SY STV1601A Figure 16 : (x9 + x 4 +1) Basic Scrambling Circuit Figure 14 : 8-bit Parallel Input Data (ECL level) D1 6 21 D1X D1Y D0X D0Y 22 23 24 25 D2 D3 D4 D5 D6 D7 D8 D9 1601A-26.EPS STV1601A Figure 17 : (x9 + x4 +1) Basic Scrambling Circuit 1601A-24.EPS D1 V EE D2 D3 D4 D6 D7 D8 D9 1601A-27.EPS 10k Ω 8-bit Parallel Data D5 The conversion algorithm detects 2 successive 000H words and sets the two LSBs of the previous word, which is supposed to be FF, according to the standard. To eliminate signal polarity of scrambled data, conversion from NRZ to NRZI is performed (Figures18 and 19). Figure 10 : Conversion from 8-bit TRS to 10-bit TRS Therefore, the polarity for output distribution or receiving is not needed. This allows easy system design. The NRZ to NRZI polynominal is x + 1. Input Data Fixed Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 Input Parallel Data MSB LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Parallel Data after Conversion Conversion in the case of more than three successive ”000H” words. If more than 3 consecutive words of 000 in D1 standard, or 4 consecutive words of 000 in D2 standard occur at the parallel input (illegal according to the standard), thus no proper operation is possible. 5. Scrambling and NRZ to NRZI conversion Figures 16 and 17 show the scrambling circuit, the scrambling polynomial is as follows : x9 + x4 + 1. 1601A-25.EPS Input Order VCO temperature compensation and oscillation frequency adjustment VCO oscillation frequency depends on the temperature as shown in Figures 22 and 23 ”Representative characteristics examples”. Within the normal range of operation, frequency increases with temperature. FV voltage remains almost constant regardless of temperature. Figure 20 shows an example of a temperature compensation circuit using a diode (transistor with C-B diode short-circuited) and a resistor connected between FV and VEE. Examplesof representativecharacteristics for various temperatures are shown in Figures 22 and 23 concerning oscillation frequency and PLL pull-in range (signal frequency 270, 177 and 143MHz). VCO free running frequency adjustment VCO free running frequency adjustment is performed at room temperature. If TN1 is set High, VCO free runs. Wait for 5 to 10 minutes after turning power supply ON (warm up time). While monitoring PCK output (Pin 36) adjust the signal frequency (within ± 1%) with the variable resistor connected between FV and VEE. 13/17 STV1601A Figure 19 : Relation between NRZ and NRZI Signals Time scale NRZ signal NRZI signal NRZ to NRZI conversion NRZI signal 1601A-29.EPS NRZI inverted signal NRZ to NRZI conversion Figure 20 : VCO Temperature Compensation and Free Running Adjustment STV1601A TN1 TRP FV PCK 35 34 33 36 C1 10µF Small signal transistor 22kΩ Frequency monitor 1kΩ 1601A-30.EPS L1 10kΩ V EE Jitter trap Since the internally generated serial clock is locked to the incoming parallel clock, there exists periodic jitter components which are generated from the phase comparison process of the PLL. A serial resonant circuit (trap) connected between TRP (Pin 34) and VEE tuned at the parallel clock frequency reduces effectively the fundamental component of the jitter well below the specification (±0.25ns). Recommended values of C1 and L1 are given in the following table. 14/17 RECOMMENDED VALUES OF THE TRAP CIRCUIT COMPONENT C1 (pF) L1 (µH) D1 150 0.2 STANDARD D2 PAL NTSC 240 300 0.3 0.4 An important remark in a practical implementation is that TRP node is an input of a very sensitive voltage-frequency converter (VCO) which can be easily disturbed by any pick-up noise. Hence, the trap circuit should be carefully located and be kept as short as possible from the Pin 34 in order to avoid noise problems. 1601A-31.EPS Parallel Data IN (ECL Balanced Pair) 18 D3X 17 D4Y 16 D4X 15 D5Y 14 D5X 13 D6Y 12 D6X 11 D7Y 10 D7X D2X 20 19 D8X D8Y D3Y 8 9 STV1601A GND 5 SY 4 D1X 22 21 23 D1Y 24 D0X (ENCODERMODULE) D9X 6 D2Y D9Y 7 25 D0Y SX 3 36 VCC 29 PCX 30 PCY 31 GND 32 FV 33 TRP 34 TN1 35 PCK N.C. 37 VEE 27 26 RSE 28 (Rate select) LST 1 V EE GND 2 -5V LOW HIGH 4.7kΩ 10kΩ C1 51 Ω 0.1 Q1 -5V -5V -5V 150Ω D2 D1 Unit PAL NTSC C1 151 210 300 nF L1 0.2 0.3 0.4 µH Recommended values Parallel Clock In 51Ω 0.1 150Ω -5V 0.1µF STV1389AQ 0.1µF 0.1µ F 220Ω (Return) 220Ω -5V ((115mA typical) D2 NTSC D1, D2 PAL 2.2kΩ L1 22kΩ -5V Test Jumper 10kΩ 10µF/16V 1kΩ Parallel Clock Test Ponit 220Ω 0.1µF 1kΩ 0.1µF 220Ω 220Ω For coaxial cable processing 68Ω 68Ω For signal Processig STV1601A Figure 21 : Application Circuit Example 15/17 STV1601A EXAMPLE OF REPRESENTATIVE CHARACTERISTICS Figure 23 : VCO Oscillation Frequency versus FV Pin Voltage 260 220 180 140 0.80 0.90 1.00 1.10 1.20 1.30 FV pin Voltage (V) Figure 24 : Pull in Range and Free Run Frequency (270Mb/s) VCO oscillationfrequency (MHz) 300 5°C 140 85°C -15°C 130 120 110 100 0.90 1.00 1.10 1.20 1.30 21 27 Free run 26 25 Low pull in 5 25 45 65 85 Ambient temperature (°C) Figure 26 : Pull in Range and Free Run Frequency (143Mb/s) 18 High pull in 17 16 15 Free run 14 13 12 5 25 45 65 Ambient temperature (°C) 85 1601A-36.EPS Low pull in 11 -15 19 18 Free run 17 16 Low pull in 15 23 -15 High pull in 20 14 -15 5 25 45 Ambient temperature (°C) 65 85 1601A-35.EPS Frequency (MHz) 28 1601A-34.EPS Frequency (MHz) 65°C Figure 25 : Pull in Range and Free Run Frequency (177Mb/s) High pull in 29 24 Frequency (MHz) 150 RSE : ”L” FV pin Voltage (V) 30 16/17 25°C 45°C 1601A-33.EPS RSE: ”H” 25°C 5°C 45°C 65°C -15°C 85°C 1601A-32.EPS VCO oscillationfrequency (MHz) Figure 22 : VCO Oscillation Frequency versus FV Pin Voltage STV1601A PACKAGE MECHANICAL DATA 37 PINS - CERAMIC PGA Dimensions in mm 3.8 25.4 0.5 0.2 Seating plane 1.15 0.15 1.2 0.46 0.1 0.05 4.2 2.54 x 9 = 22.86 0.25 Pin 28 Pin 36 Pin 37 2.032 max. 2.54 2.54 PM-PGA37.EPS Pin 10 Bottom View 25.4 2.54 x 9 = 22.86 0.5 0.25 Pin 19 Pin 1 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 17/17