Topology Aspects of a High-Speed CAN Bus

AND8376/D
AMIS-30660/42000 Topology Aspects of a
High-Speed CAN Bus
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APPLICATION NOTE
Introduction
Although these points are analyzed separately, all of them
should be considered and the resulting conditions should be
fulfilled simultaneously in order to achieve a correct bus
topology.
AMIS−30660, together with AMIS−42000, is a family of
high speed CAN transceiver products intended for
automotive and industrial applications. Although individual
members of the product family differ in some aspects –
operation modes, additional features, single−channel bus
versus bus−repeater etc. – they all incorporate high−speed
CAN transceiver(s) compliant with ISO11898 norm. The
transceiver functional blocks throughout the product family
share the same set of limitations which have to be considered
when designing the topology of the CAN bus which they
interface.
A CAN bus topology is determined by the number of
nodes, maximum allowed bus length and the maximum
allowed length of unterminated stubs connected to the main
bus line. These topology parameters are mainly defined by:
1. The delay of the line and the loop delay of the
nodes (loop delay is the sum of the receiver delay,
the transmitter delay and the delays of the
interface lines between the transceiver and the
CAN controller)
2. The signal amplitude drop due to the non−zero bus
wire resistance and the finite input resistance of
the nodes
3. Differences of oscillator frequency between nodes
This application note deals with points 1 and 2, whereas
point 3 – the oscillator frequency tolerance – is not
considered.
After a definition of CAN bit timing related terms and
parameters in the “Definition of CAN Bit Timing” section,
the application note addresses the following questions in
individual chapters:
1. What is the maximum bus length if the bit timing
parameters are known?
2. What is the maximum length of unterminated
stubs if the bit timing parameters are known?
3. What is the maximum bus length for a given
number of nodes which still guarantees sufficient
signal amplitude?
4. What is the maximum number of nodes which can
be driven by the given CAN transceiver?
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 2
DEFINITION OF CAN BIT TIMING
Parameter Definition
This paragraph gives an abbreviated definition of
parameters related to the CAN bit timing which will be used
later in relation with the bus topology aspects.
A CAN bus system uses a nominal bit rate fnbr (in bits per
second) which is uniform throughout the network. To each
bit corresponds an interval of time:
T bit +
1
f nbr
As defined in detail in [1], each node in a CAN network
has to perform frequent “hard synchronization” and
“re−synchronization” in order to ensure correct data
processing according the CAN protocol. For the purpose of
the synchronization, the CAN controller regards each bit
period as being split to several segments as shown in
Figure 1.
The time in a CAN node is referred to a CAN system
clock, the period of which is called “time quantum” TQ. ISO
CAN norm [1] requires that each bit period is split to 8−25
time quanta, i.e. that the CAN system clock is 8−25 times
faster than the nominal bit rate. The CAN system clock
controls the bit timing and sampling of the bus state. The
CAN system clock is derived from the node local oscillator
by means of a prescaler. The choice of the local oscillator
frequency and of the time quantum value derived from the
local oscillator is a task of the CAN system design.
1
Publication Order Number:
AND8376/D
AND8376/D
Tbit
TSEG1
node B
SYNC_
SEG
TSEG2
PROP_SEG
PHASE_SEG1
PHASE_SEG2
Tprop(A,B)
sample
point
Tprop(B,A)
node A
SYNC_
SEG
PROP_SEG
CAN system clock of node A
PHASE_SEG1
PHASE_SEG2
PD20061016.1
TQ
Figure 1. CAN Bit Timing
Each bit period begins with a SYNC_SEG, the duration of
which is fixed to one period of the CAN system clock.
Transmitting node begins to drive the bus at the beginning
of the SYNC_SEG, whereas a correctly synchronized
receiving node expects every edge on the bus arriving during
SYNC_SEG.
The bit period continues with a PROP_SEG, a period
fixed by the CAN system design to 1−8 time quanta. It’s the
minimum time a receiver will wait before accepting a valid
bus value sample. Following segments PHASE_SEG1 and
PHASE_SEG2 are periods of time which are adapted during
the “re−synchronization” in order to move the “sample
point”. The maximum allowed one−time modification of the
PHASE_SEG1 or PHASE_SEG2 is referred to as SJW, or
“synchronization jump width”.
Some definitions or software packages might use an
alternative set of terms, splitting the bit period to
SYNC_SEG, SEG1 and SEG2 (see Figure 1), where:
bit period. Under the worst case conditions, by modifying
the duration of PHASE_SEG1 and PHASE_SEG2, the
sample point might arrive as early as immediately after the
PROP_SEG part of the bit period.
Maximum Bus Length in Function of Maximum Bus
Line Delay
To identify the permissible maximum line delay, the node
relation in Figure 1 has to be considered. During an
“acknowledge” field, the transmitting node (node A)
transmits a recessive bit but expects a dominant bit being
transmitted by other nodes (node B in the figure). For the
“acknowledge” field to be correctly received, node A has to
sample “dominant” at his sample point.
As explained in “Definition of CAN Bit Timing” section,
the sample point might arrive as early as immediately after
the PROP_SEG period, which must thus accommodate for
all propagation delays between node A and node B:
T PROP_SEG w T PROP(A,B) ) T PROP(B,A)
T SEG1 + T PROP_SEG ) T PHASE_SEG1
T SEG2 + T PHASE_SEG2
The propagation delays are the total delays between the
CAN controller interface of node A (pins TxDA and RxDA)
and the CAN controller interface of node B (pins TxDB and
RxDB) and their components are shown in Figure 2.
However, the CAN timing remains identical, as these
definitions are purely formal.
The bus state detected at the “sample point” is accepted by
the receiving node as the logical value valid for the current
node A
node B
T TRANS(A)
T TRANS(B)
CANH
CANH
TxDA
TxDB
CANL
CANL
T
RxDA
BUS(A,B)
RxDB
T BUS(B,A)
T
T
REC(A)
REC(B)
T PROP(A,B)
T PROP(B,A)
PD20061016.2
Figure 2. Components of the CAN Bus Delay
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AND8376/D
The bus line is then limited by the following formula:
The delays can be expressed as follows:
ǒ
T PROP(A,B) + T TRANS(A) ) T BUS(A,B) ) T REC(B)
T PROP(B,A) + T TRANS(B) ) T BUS(B,A) ) T REC(A)
T
PROP_SEG
L BUS_MAX_DEL +
Where:
TBUS(X,Y) is the proper bus line delay from node X to node
Y.
TTRANS(X) and TREC(X) are delays of node X transmitter and
receiver parts, respectively.
The sum of TTRANS(X) and TREC(X) can be found in
specifications of CAN transceivers as “propagation delay
TxD to RxD”.
2
* T PROP(RxD,TxD)
Ǔ
T PROP(BUS)
Where:
LBUS_MAX_DEL is the biggest allowed distance between any
two nodes.
TPROP_SEG is the length of PROP_SEG part of one bit
period.
TPROP(RxD,TxD) is the propagation delay TxD to RxD of the
used CAN transceiver.
TPROP(BUS) is the bus line delay per unit length.
Example
Given:
AMIS−42665 transceivers will be used with the following relevant parameters (extract from the datasheet):
Symbol
Parameter
Conditions
Min
Max
Unit
tpd(rec−dom)
Propagation Delay TxD to RxD
70
230
ns
tpd(dom−rec)
Propagation Delay TxD to RxD
100
245
ns
Maximum Unterminated Stub Length
The transceiver delay is slightly different for opposite edges
(recessive to dominant vs. dominant to recessive). To
analyze the worst case, we will take 245 ns.
The bus line has a delay of 5 ns per 1 m length
The bit rate of 500 kbps is required, resulting in 1 bit period
of 2 ms
The CAN controller is setup to have PROP_SEG equal to
1100 ns
Then:
The maximum permissible bus line delay is (1100 ns / 2 –
245 ns) = 305 ns.
The maximum allowed distance between any two nodes
LBUS_MAX_DEL is 61 m (= 305 ns / 5 ns).
A CAN bus is intended to be as close as possible to a single
line structure. However, deviations from this basic topology
must be taken into account – e.g. for temporary connection
of diagnostic equipment or for connection of nodes by short
unterminated cables. In all these case, signal reflections will
occur in the bus due to the existence of unterminated stubs.
An example of a CAN bus with unterminated stubs can be
seen in Figure 3.
node 3
Ri(dif)
node 2
Ri(dif)
RT
RT
node 4
CANH
Ri(dif)
node 1
L
L
STUB1
STUB2
Ri(dif)
CANL
L
PD20061016.3
BUS_LINE
Figure 3. CAN Bus with Unterminated Stubs
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AND8376/D
Although the reflected signals will disappear once they
arrive at a bus termination, and although the CAN protocol
is robust, an upper limit must be set to the allowed
unterminated stub length as well as to the cumulative stubs
length.
Some rules of thumb can be used:
L STUB_MAX t
Where:
LSTUB_MAX is the maximum length of one unterminated
stub.
LSTUB_TOT_MAX is the cumulative length of all
unterminated stubs in the bus.
TPROP_SEG is the duration of the PROP_SEG part of the bit
time (see the “Definition of CAN Bit Timing” section and
Figure 1).
TPROP(BUS) is the propagation delay of the bus line per unit
length.
Furthermore, the sum of all stub length must be subtracted
from the maximum bus length LBUS_MAX_DEL calculated
from the maximum permissible propagation delay (as per
the “Definition of CAN Bit Timing” section). In the example
depicted in Figure 3, the sum (LSTUB1 + LSTUB2 +
LBUS_LINE) must be less than LBUS_MAX_DEL.
T PROP_SEG
50 @ T PROP(BUS)
AND
L STUB_TOT_MAX t
TPROP_SEG
10 @ TPROP(BUS)
Example
Given:
AMIS−42665 transceivers will be used with the following relevant parameters (extract from the datasheet):
Symbol
Parameter
Conditions
Min
Max
Unit
tpd(rec−dom)
Propagation delay TxD to RxD
70
230
ns
tpd(dom−rec)
Propagation delay TxD to RxD
100
245
ns
Maximum Bus Line Length in Function of the Required
Signal Amplitude
The transceiver delay is slightly different for opposite edges
(recessive to dominant vs. dominant to recessive). To
analyze the worst case, we will take 245 ns.
Other parameters are:
The bus line has a delay of 5 ns per 1 m length
The bit rate of 500 kbps is required, resulting in 1 bit period
of 2 ms
The CAN controller is setup to have PROP_SEG equal to
1100 ns
Then:
Maximum permissible stub length LSTUB_MAX is 4.4 m
(1100 ns / 5 ns / 50)
Maximum
permissible
cumulative
stub
length
LSTUB_TOT_MAX is 22 m (1100 ns / 5 ns / 10)
If the full total length of stubs is used, the main bus line
may be max. 39 m long (61 m – 22 m, see example in the
“Maximum Unterminated Stub Length” section for
LBUS_TOT_MAX calculation)
Another limitation on the CAN bus topology is defined by
the amplitude of the bus voltage required for correct
reception of the bus state. Dominant bit signaled by any
single node of the bus must be correctly detected as
dominant at all other nodes. The signal amplitude is
decreased by voltage drops along the bus line, as the bus is
loaded by the bus terminations and the finite input
resistances of the nodes. Signal integrity of a recessive state
is not influenced by these drops, as it’s defined by the
termination resistors as typically zero differential voltage.
To analyze the effect of voltage drops, bus topology with
n nodes shown in Figure 4 will be considered. A
representation of the worst case is shown in Figure 5. The
transmitting node, together with its termination resistor RT,
is placed on one side of the bus, whereas all other nodes and
the second termination resistor are situated on the opposite
side of the bus line. Each node loads the bus with its
differential mode input resistance Ri(diff), the non−zero
resistance of the wires is represented by resistors RW. The
differential voltage driven by the transmitting node is
denoted Vo(diff), the receiving node can see differential
voltage Vi(diff) on its input.
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AND8376/D
node 1
node 2
Ri(dif)
Ri(dif)
........
node n
Ri(dif)
CANH
R
R
T
T
CANL
PD20060927.1
Figure 4. Basic CAN Bus Topology
R
W
i(dif)
V
R
T
R i(dif)
/(n−2)
o(dif)
i(dif)
R
V
R
T
R W
PD20060927.2
Figure 5. Electric Representation of the CAN bus from Figure 4
For proper detection of the dominant state, a minimum
differential voltage Vi(diff)_MIN_REQ is required at the input
of the receiving node. This minimum is given by the receiver
threshold and a user−defined safety margin:
Minimum differential voltage Vo(diff)_MIN is driven by the
transmitting node.
Maximum receiver threshold Vi(diff)_MAX.
Maximum value of the bus resistance RW_MAX is
encountered.
Minimum termination resistors RT_MIN are placed on the bus.
The nodes are loading the bus with their minimum
differential input resistance Ri(diff)_MIN.
Number of nodes connected to the bus is nNODES.
Under the above conditions, the differential input voltage
will reach its minimum:
V i(diff)_MIN_REQ + V i(diff)_TH ) k @ ǒV o(diff) * V i(diff)_THǓ
Where:
Vi(diff)_MIN_REQ is the minimum required dominant
differential voltage at any receiving node
Vi(diff)_TH is the receiver threshold level
Vo(diff) is the dominant differential voltage driven by the
transmitting node
k is an optional “safety margin” coefficient, its value ranging
from 0 to 1.
The maximum wire length with respect to the voltage drop
can be then found out with the help of Figure 5 and
considering following worst−case situation:
LBUS_MAX_DROP +
1
2.ò W_MAX
ȡ
ȧV
Ȣ
V o(diff)_MIN
V i(diff)_MIN +
1 ) 2.R W_MAX @
ǒ
1
R
T_MIN
)
n
Ǔ
NODES*1
R
i(diff)_MIN
This worst case differential voltage must be higher than the
required minimum Vi(diff)_MIN_REQ defined above.
Knowing that the cable resistance RW is proportional to its
length L with ratio òW representing the specific resistance,
both equations can be combined to yield:
V o(diff)_MIN
ǒ
i(diff)_MAX ) k @ V o(diff)_MIN * V i(diff)_TH_MAX
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Ǔ
ȣ
ȧ
Ȥ
*1
R T_MIN @ Ri(diff)_MIN
R i(diff)_MIN ) ǒn NODES * 1Ǔ @ R T_MIN
AND8376/D
Example
Given:
AMIS−42665 transceivers will be used with the following relevant parameters (extract from the datasheet):
Parameter
Min
Typ
Max
Unit
Differential bus output voltage (VCANH −
VCANL)
VTxD = 0V; dominant;
42.5W < RLT < 60W
Conditions
1.5
2.25
3.0
V
Vihcm(dif) (th)
Differential receiver threshold voltage for
high common−mode (see Figure 5)
−35V <VCANL < +35V;
−35V <VCANH < +35V;
0.40
0.7
1.00
V
Ri(dif)
Differential input resistance
25
50
75
W
From the above table, the following inputs for the
calculations will be extracted:
Minimum differential output voltage Vo(diff)_MIN: 1.5 V
Maximum dominant threshold of the receiver Vi(diff)_MAX:
1.00 V
Minimum differential input resistance of a receiver
Ri(diff)_MIN: 25000 W
Remaining inputs for the calculations are:
Maximum specific bus line resistance QW_MAX: 0.0346 W
/m
Minimum termination resistor value RT_MIN: 95 W
Number of nodes nNODES: 60
Safety margin coefficient k: 0
Then:
Maximum bus line length with respect to the voltage drop is
LBUS_MAX_DROP: 560 m.
Maximum Number of Nodes in Function of the
Transmitter Driving Capability
The maximum number of nodes is limited by the driving
capability of a CAN transmitter. It’s usually specified by the
minimum allowed load resistance RL_MIN. The load of a
transmitter in the CAN bus is composed of the termination
resistors and the parallel combination of differential input
resistances of all nodes – see Figure 6.
T
nodes
R
o(dif)
MAX
R i(dif)
V
R i(dif)
R
T
n
R i(dif)
Symbol
Vo(dif) (bus_dom)
PD20061017.1
Figure 6. Electric Representation of a CAN Bus for Calculation of the Maximum Number of Nodes
The transmitter is then loaded with resistance RL, calculated
as:
RL +
R T_MIN
ǒnMAX * 1Ǔ
one node.
nMAX is the number of nodes connected to the bus.
The resulting resistance RL must stay above the specified
minimum value RL_MIN, leading to the following limit for
the number of nodes:
R i(diff)_MIN
R T_MIN ) 2 @ R i(diff)_MIN
Where:
RT_MIN is the minimum termination resistance.
Ri(diff)_MIN is the minimum differential input resistance of
n MAX + 1 ) R i(diff)_MIN
ǒ
Ǔ
1
2
*
R L_MIN R T_MIN
Example
Given:
AMIS42665 transceivers will be used with the following relevant parameters (extract from the datasheet):
Symbol
Parameter
Vo(dif) (bus_dom)
Differential bus output voltage
(VCANH − VCANL)
Ri(dif)
Differential input resistance
Conditions
VTxD = 0V; dominant;
42.5 W < RLT < 60 W
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Min
Typ
Max
Unit
1.5
2.25
3.0
V
25
50
75
W
AND8376/D
Then:
The maximum allowed number of nodes nMAX connected to
the CAN bus is 62.
From the above table, the following inputs for the
calculations will be extracted:
Minimum differential input resistance of a receiver
Ri(diff)_MIN: 25000 W.
Minimum allowed load to be driven by the transmitter
RL_MIN: 42.5 W (see the “Conditions” column of the above
table).
Remaining input for the calculations is:
Minimum termination resistor RT_MIN: 95 W
References
[1] ISO11898/1 − Road vehicles – Controller area network
(CAN) – Part 1: Data link layer and physical signaling
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