NCV7342 High Speed Low Power CAN Transceiver Description The NCV7342 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and may be used in both 12 V and 24 V systems. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The NCV7342 is an addition to the CAN high−speed transceiver family complementing NCV734x CAN stand−alone transceivers and previous generations such as AMIS42665, AMIS3066x, etc. Due to the wide common−mode voltage range of the receiver inputs and other design features, the NCV7342 is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. http://onsemi.com MARKING DIAGRAM 8 8 SOIC−8 CASE 751AZ • Compatible with the ISO 11898−2, ISO 11898−5 Standards • High Speed (up to 1 Mbps) • VIO Pin on NCV7342−3 Version Allowing Direct Interfacing with • • • • NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable Typical Applications • Automotive • Industrial Networks December, 2013 − Rev. 1 8 1 TxD GND VCC STB 2 3 7 CANH 6 5 4 RxD CANL VSPLIT NCV7342D10R2G (Top View) 1 8 2 7 TxD GND VCC Quality © Semiconductor Components Industries, LLC, 2013 PIN ASSIGNMENT STB 3 NV7342−3 ALYWG G • • (Note: Microdot may be in either location) NV7342−0 ALYWG G • • • • • • • 1 NV7342−x= Specific Device Code x = 0 or 3 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package Features 3 V to 5 V Microcontrollers VSPLIT Pin on NCV7342−0 Version for Bus Common Mode Stabilization Very Low Current Consumption in Standby Mode with Wake−up via the Bus Excellent Electromagnetic Susceptibility (EMS) Level Over Full Frequency Range. Very Low Electromagnetic Emissions (EME) Low EME Also Without Common Mode (CM) Choke Bus Pins Protected Against >15 kV System ESD Pulses Transmit Data (TxD) Dominant Time−out Function Bus Dominant Time−out function in Standby Mode Under All Supply Condition the Chip Behaves Predictably No Disturbance of the Bus Lines with an Unpowered Node Thermal Protection Bus Pins Protected Against Transients in an Automotive Environment Bus Pins Short Circuit Proof to Supply Voltage and Ground These are Pb−Free Devices NV7342−x ALYW G G 1 6 5 4 RxD CANH CANL VIO NCV7342D13R2G (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. 1 Publication Order Number: NCV7342/D NCV7342 Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES Symbol VCC VUVDVCC Min Max Unit Power supply voltage Parameter Conditions 4.5 5.5 V Undervoltage detection voltage on pin VCC (NCV7342−3 only) 3.5 4.5 V ICC Supply current Dominant; VTxD = 0 V Recessive; VTxD = VIO 75 10 mA ICCS Supply current in standby mode including VIO current TJ v 100°C, (Note 1) 15 mA VCANH DC voltage at pin CANH 0 < VCC < 5.5 V; no time limit −50 +50 V VCANL DC voltage at pin CANL 0 < VCC < 5.5 V; no time limit −50 +50 V DC voltage between CANH and CANL pin 0 < VCC < 5.5 V −50 +50 V Electrostatic discharge voltage IEC 61000−4−2 at pins CANH and CANL −15 15 kV VO(dif)(bus_dom) Differential bus output voltage in dominant state 45 W < RLT < 65 W 1.5 3 V CM−range Input common−mode range for comparator Guaranteed differential receiver threshold and leakage current −35 +35 V Cload Load capacitance on IC outputs 15 pF tpd0 Propagation delay TxD to RxD (NCV7342−0 version) See Figure 8 50 230 ns tpd3 Propagation delay TxD to RxD (NCV7342−3 version) See Figure 8 50 230 ns −40 150 °C VCANH,L VESD TJ Junction temperature 1. Not tested in production. Guaranteed by design and prototype evaluation. http://onsemi.com 2 NCV7342 BLOCK DIAGRAMS VCC 3 VCC NCV7342−0 7 Thermal Shutdown 1 TxD VCC Timer 5 VCC 8 STB VSPLIT VSPLIT Mode & Driver Wake−up Control 6 CANL Control 4 RxD Wake−up Filter GND CANH COMP 2 COMP RB 20121109 Figure 1. NCV7342−0 Block Diagram http://onsemi.com 3 NCV7342 VIO VCC 3 5 VIO NCV7342−3 7 Thermal Shutdown 1 TxD CANH Timer VIO 8 STB Mode & Driver Wake−up Control 6 Control 4 RxD Wake−up Filter GND COMP 2 COMP RB 20121109 Figure 2. NCV7342−3 Block Diagram http://onsemi.com 4 CANL NCV7342 TYPICAL APPLICATION VBAT 5V−reg 3V−reg VIO VIO VCC 3 5 7 STB CANH 8 Micro CLT = 4.7 nF CAN BUS NCV7342−3 RxD Controller RLT = 60 W 4 TxD 6 1 CANL RLT = 60 W 2 GND GND RB20120816 Figure 3. Application Diagram NCV7342−3 VBAT IN 5V−reg OUT VCC VCC STB RxD 8 7 NCV7342−0 Micro Controller 3 4 TxD 1 RB20120816 5 6 RLT = 60 W CANH CANL RLT = 60 W 2 GND CLT = 4.7 nF VSPLIT GND Figure 4. Application Diagram NCV7342−0 Table 2. PIN FUNCTION DESCRIPTION Pin Name 1 TxD Description Transmit data input; Low input Ù dominant driver; internal pull−up current 2 GND Ground 3 VCC Supply voltage 4 RxD Receive data output; dominant transmitter Ù Low output 5 5 VIO VSPLIT Input/Output pins supply voltage. On NCV7342−3 only Common−mode stabilization output. On NCV7342−0 only 6 CANL Low−level CAN bus line (Low in dominant mode) 7 CANH High−level CAN bus line (High in dominant mode) 8 STB Standby mode control input http://onsemi.com 5 CAN BUS NCV7342 FUNCTIONAL DESCRIPTION NCV7342 has two versions which differ from each other only by function of pin 5. NCV7342−0: Pin 5 is common mode stabilization output VSPLIT. (see Figure 4) This version is full replacement of NCV7340. monitors the bus lines for CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 mA. When a wake−up request is detected by the low−power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of tdwakerd. The RxD pin is driven Low by the transceiver to inform the controller of the wake−up request. NCV7342−3: Pin 5 is VIO pin, which is supply pin for transceiver digital inputs/output (supplying pins TxD, RxD, STB) The VIO pin should be connected to microcontroller supply pin. By using VIO supply pin shared with microcontroller, the I/O levels between microcontroller and transceiver are properly adjusted. This adjustment allows communication between 3 V microcontroller and the transceiver. (See Figure 3) VIO Supply Pin The VIO pin (available only on NCV7342−3 version) should be connected to microcontroller supply pin. By using VIO supply pin shared with microcontroller the I/O levels between microcontroller and transceiver are properly adjusted. See Figure 3. Pin VIO also provides the internal supply voltage for low−power differential receiver of the transceiver. This allows detection of wake−up request even when there is no supply voltage on Pin VCC. Operating Modes NCV7342 provides two modes of operation as illustrated in Table 3. These modes are selectable through pin STB. Split Circuit The VSPLIT pin (available on NCV7342−0 version) is operational only in normal mode. In standby mode this pin is floating. The VSPLIT can be connected as shown in Figure 4 or, if it’s not used, can be left floating. Its purpose is to provide a stabilized DC voltage of 0.5 · VCC to the bus reducing possible steps in the common−mode signal, therefore reducing EME. These unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 · VCC voltage. Table 3. OPERATING MODES Pin RxD Pin STB Mode Low Normal Bus dominant Bus recessive High Standby Wake−up request detected No wake−up request detected Low High Normal Mode In normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give extremely low EME. Wake−up When a valid wake−up (dominant state longer than tWake) is received during the standby mode, the RxD pin is driven Low after tdwakerd. The wake−up detection is not latched: RxD returns to High state after tdwakedr when the bus signal is released back to recessive – see Figure 5. Standby Mode In standby mode both the transmitter and receiver are disabled and a very low−power differential receiver >tWake <tWake CANH CANL STB RxD tdwakerd normal standby tdwakedr RB20130219 Figure 5. NCV7342 Wake−up behavior http://onsemi.com 6 time NCV7342 Over−temperature Detection state. If the dominant state on the bus is kept for longer time than tdom(bus), the RxD pin is released to High level. The timer is reset when CAN bus changes from dominant to recessive state. This feature prevents generating permanent wake−up request by the bus clamped to the dominant level. A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 180°C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off−state resets when the temperature decreases below the shutdown threshold and pin TxD goes High. The thermal protection circuit is particularly needed in case of a bus line failure. Fail Safe Features A current−limiting circuit protects the transmitter output stage from damage caused by an accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. VCC supply dropping below VUVDVCC undervoltage level will force transceiver to switch into the standby mode. The logic level on pin STB will be ignored as long as undervoltage condition is not recovered. (NCV7342−3 version only) VIO supply dropping below VUVDVIO undervoltage detection level will cause the transceiver to disengage from the bus (no bus loading) until the VIO voltage recovers. (NCV7342−3 version only) The pins CANH and CANL are protected against automotive electrical transients (according to ISO 7637; see Figure 6). Pins TxD and STB are pulled High internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse supply should the VCC supply be removed. TxD Dominant Time−out Function A TxD dominant time−out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication), if pin TxD is forced permanently Low by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TxD. If the duration of the low−level on pin TxD exceeds the internal timer value tdom(TxD), the transmitter is disabled, driving the bus into a recessive state. The timer is reset by a positive edge on pin TxD. This TxD dominant time−out time (tdom(TxD)) limits the minimum possible bit rate to 8 kbps. Bus Dominant Time−out Function Bus dominant time−out timer is started in the standby mode when CAN bus changes from recessive to dominant http://onsemi.com 7 NCV7342 ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. Table 4. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Min Max Unit VSUP Supply voltage VCC, VIO −0.3 6 V VCANH DC voltage at pin CANH 0 < VCC < 5.5 V; no time limit −50 50 V VCANL DC voltage at pin CANL 0 < VCC < 5.5 V; no time limit −50 50 V DC voltage at pin CANH and CANL during load dump condition 0 < VCC < 5.5 V; less than one second − 58 V DC voltage at VSPLIT pin (On NCV7342−0 version only) 0 < VCC < 5.5 V; no time limit −50 50 V −0.3 6 V −4 4 kV −750 750 V VCANH,Lmax VSPLIT VIO DC voltage at pin TxD, RxD, STB Vesd Electrostatic discharge voltage at all pins according to EIA−JESD22 Note 2 Standardized charged device model ESD pulses according to ESD−STM5.3.1−1999 Vschaff Latch−up Electrostatic discharge voltage at CANH,CANL, VSPLIT pins according to EIA−JESD22 Note 2 −8 8 kV Electrostatic discharge voltage at CANH, CANL pins According to IEC 61000−4−2 Note 3 −15 15 kV Transient voltage at CANH, CANL pins, See Figure 6 Note 4 −150 100 V Static latch−up at all pins Note 5 150 mA Tstg Storage temperature −55 +150 °C Tamb Ambient temperature −40 +125 °C Maximum junction temperature −40 +170 °C TJ Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor. 3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor referenced to GND. Verified by external test house 4. Pulses 1, 2a,3a and 3b according to ISO 7637 part 3. Verification by external test house. 5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78. Table 5. THERMAL CHARACTERISTICS Symbol Parameter Conditions Value Unit RqJA_1 Thermal Resistance Junction−to−Air, 1S0P PCB (Note 6) Free air 125 K/W RqJA_2 Thermal Resistance Junction−to−Air, 2S2P PCB (Note 7) Free air 75 K/W 6. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage. 7. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage. http://onsemi.com 8 NCV7342 Table 6. CHARACTERISTICS VCC = 4.5 V to 5.5 V; VIO = 2.8V to 5.5 V (Note 8); TJ = −40 to +150°C; RLT = 60 W unless specified otherwise. On chip versions without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO. Symbol Parameter Conditions Min Typ Max Unit 50 6.8 75 10 mA 8 15 mA 17 mA 3.5 4.5 V 6 V SUPPLY (Pin VCC) Supply current Dominant; VTxD = 0 V Recessive; VTxD = VIO ICCS0 Supply current in standby mode for NCV7342−0 TJ v 100°C (Note 9) ICCS3 Supply current in standby mode for NCV7342−3 including current into VIO TJ v 100°C (Note 9) ICC VCC Undervoltage detection voltage on VCC pin (NCV7342−3 only) TRANSMITTER DATA INPUT (Pin TxD) VIH High−level input voltage Output recessive 2.0 VIL Low−level input voltage Output dominant −0.3 0.8 V IIH High−level input current VTxD = VIO −5 0 5 mA IIL Low−level input current VTxD = 0V −385 −200 −45 mA Ci Input capacitance Not tested 5 10 pF TRANSMITTER MODE SELECT (Pin STB) VIH High−level input voltage Standby mode 2.0 VIO+0.3 (Note 10) V VIL Low−level input voltage Normal mode −0.3 0.8 V IIH High−level input current VSTB = VIO −5 0 5 mA IIL Low−level input current VSTB = 0 V −10 −4 −1 mA Ci Input capacitance Not tested 5 10 pF RECEIVER DATA OUTPUT (Pin RxD) IOH High−level output current Normal mode VRxD = VIO – 0.4 V −1.2 −0.4 −0.1 mA IOL Low−level output current VRxD = 0.4 V 1.5 6 12 mA VOH High−level output voltage Standby mode IRxD = −100 mA VIO – 1.1 VIO –0.7 VIO – 0.4 V BUS LINES (Pins CANH and CANL) Vo(reces) (norm) Recessive bus voltage on pins CANH and CANL VTxD = VIO; no load; normal mode 2.0 2.5 3.0 V Vo(reces) (stby) Recessive bus voltage on pins CANH and CANL VTxD = VIO; no load; standby mode −100 0 100 mV Io(reces) (CANH) Recessive output current at pin CANH −30 V < VCANH< 35 V; 0 V < VCC < 5.5 V −2.5 2.5 mA Io(reces) (CANL) Recessive output current at pin CANL −30 V < VCANL < 35 V; 0 V <VCC < 5.5 V −2.5 2.5 mA ILI(CANH) Input leakage current to pin CANH −10 0 10 mA ILI(CANL) Input leakage current to pin CANL 0W < R(VCC to GND) < 1 MW 0W < R(VIO to GND) < 1 MW VCANL = VCANH = 5 V (Note 8) −10 0 10 mA VTxD = 0 V 3.0 3.6 4.25 V Vo(dom) (CANH) Dominant output voltage at pin CANH 8. Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin. 9. Not tested in production. Guaranteed by design and prototype evaluation. 10. In case VIO > VCC, the limit is VIO + 0.3 V http://onsemi.com 9 NCV7342 Table 6. CHARACTERISTICS VCC = 4.5 V to 5.5 V; VIO = 2.8V to 5.5 V (Note 8); TJ = −40 to +150°C; RLT = 60 W unless specified otherwise. On chip versions without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO. Symbol Parameter Conditions Min Typ Max Unit BUS LINES (Pins CANH and CANL) Vo(dom) (CANL) Dominant output voltage at pin CANL VTxD = 0 V 0.5 1.4 1.75 V Vo(dif) (bus_dom) Differential bus output voltage (VCANH − VCANL) VTxD = 0 V; dominant; 45 W < RLT < 65 W 1.5 2.25 3.0 V Vo(dif) (bus_rec) Differential bus output voltage (VCANH − VCANL) VTxD = VIO; recessive; no load −120 0 50 mV Vo(sym) (bus_dom) Bus output voltage symmetry VCANH + VCANL VTxD = 0 V 0.9 1.1 VCC Io(sc) (CANH) Short circuit output current at pin CANH VCANH = 0 V; VTxD = 0 V −90 −70 −40 mA Io(sc) (CANL) Short circuit output current at pin CANL VCANL = 36 V; VTxD = 0 V 40 70 100 mA Differential receiver threshold voltage −12 V < VCANL < 12 V; −12 V < VCANH < 12 V; VCC = 4.75 V to 5.25 V 0.5 0.7 0.9 V Differential receiver threshold voltage for high common−mode −30 V < VCANL < 35 V; −30 V < VCANH < 35 V; VCC = 4.75 V to 5.25 V 0.40 0.7 1.0 V Differential receiver threshold voltage in standby mode −12 V < VCANL < 12 V; −12 V < VCANH < 12 V; VCC = 4.5 V to 5.5 V 0.4 0.8 1.15 V Vi(dif) (th) Vihcm(dif) (th) Vi(dif) (th)_STDBY Ri(cm) (CANH) Common−mode input resistance at pin CANH 15 26 37 kW Ri(cm) (CANL) Common−mode input resistance at pin CANL 15 26 37 kW Ri(cm) (m) Matching between pin CANH and pin CANL common mode input resistance −0.8 0 0.8 % 25 50 75 kW Ri(dif) VCANH = VCANL Differential input resistance Ci(CANH) Input capacitance at pin CANH VTxD = VIO; not tested 7.5 20 pF Ci(CANL) Input capacitance at pin CANL VTxD = VIO; not tested 7.5 20 pF Differential input capacitance VTxD = VIO ; not tested 3.75 10 pF Ci(dif) COMMON−MODE STABILIZATION (Pin VSPLIT) Only for NCV7342−0 version VSPLIT Reference output voltage at pin VSPLIT Normal mode; −500 mA < ISPLIT < 500 mA 0.3 0.7 VCC VSPLITo Reference output voltage at pin VSPLIT RloadVsplit > 1 MW 0.45 0.55 VCC ISPLIT(i) VSPLIT leakage current Standby mode −5 5 mA ISPLIT(lim) VSPLIT limitation current Normal mode 1.3 5 mA 2.8 5.5 V 14 mA VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7342−3 version VIO Supply voltage on pin VIO IIOS Supply current on pin VIO Standby mode IIONM Supply current on pin VIO Normal mode Dominant; VTxD = 0 V Recessive; VTxD = VIO 0.30 0.29 8. Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin. 9. Not tested in production. Guaranteed by design and prototype evaluation. 10. In case VIO > VCC, the limit is VIO + 0.3 V http://onsemi.com 10 0.70 0.44 1.10 0.68 mA NCV7342 Table 6. CHARACTERISTICS VCC = 4.5 V to 5.5 V; VIO = 2.8V to 5.5 V (Note 8); TJ = −40 to +150°C; RLT = 60 W unless specified otherwise. On chip versions without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO. Symbol Parameter Conditions Min Typ Max Unit 2.7 V 200 °C VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7342−3 version VUVDVIO Undervoltage detection voltage on VIO pin 1.3 THERMAL SHUTDOWN TJ(SD) Shutdown junction temperature junction temperature rising 160 180 TIMING CHARACTERISTICS (See Figure 7 and 8) td(TxD−BUSon) Delay TxD to bus active Ci = 100 pF between CANH to CANL 60 ns td(TxD−BUSoff) Delay TxD to bus inactive Ci = 100 pF between CANH to CANL 30 ns td(BUSon−RxD) Delay bus active to RxD CRxD = 15 pF 60 ns td(BUSoff−RxD) Delay bus inactive to RxD CRxD = 15 pF 70 ns tpd_dr Propagation delay TxD to RxD dominant to recessive transition Ci = 100 pF between CANH to CANL, CRxD = 15 pF 50 100 230 ns tpd_rd Propagation delay TxD to RxD recessive to dominant transition Ci = 100 pF between CANH to CANL, CRxD = 15 pF 50 120 230 ns td(stb−nm) Delay standby mode to normal mode 47 ms tWake Dominant time for wake−up via bus 0.5 5 ms tdwakerd Delay to flag wake event (recessive to dominant transitions) See Figure 5 Valid bus wake−up event, CRxD = 15 pF 1 10 ms tdwakedr Delay to flag end of wake event (dominant to recessive transition) See Figure 5 Valid bus wake−up event, CRxD = 15 pF 0.5 5 ms tdom(TxD) TxD dominant time for time out VTxD = 0 V 1.3 3 ms tdom(bus) Bus dominant time out Standby mode 1.3 3 ms 8. Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin. 9. Not tested in production. Guaranteed by design and prototype evaluation. 10. In case VIO > VCC, the limit is VIO + 0.3 V http://onsemi.com 11 NCV7342 MEASUREMENT SET−UPS AND DEFINITIONS +5 V 100 nF VIO VCC 3 5 CANH 7 TxD 1 nF NCV7342 1 RxD Transient Generator 1 nF 4 6 15 pF CANL 2 8 RB20121608 GND STB Figure 6. Test Circuit for Automotive Transients +5 V 100 nF VIO 47 uF VCC 5 3 CANH 7 1 RxD RL 4 6 CANL 2 8 15 pF 100 pF NCV7342 TxD STB RB20120816 GND Figure 7. Test Circuit for Timing Characteristics http://onsemi.com 12 NCV7342 recessive TxD recessive dominant 50% 50% CANH CANL 0.9 V Vi(dif) = VCANH − VCANL 0.5 V 0.3 x VCC* RxD td(TxD−BUSon) 0.7 x VCC* td(TxD−BUSoff) td(BUSon−RxD) tpd_rd tpd_dr *On NCV7342−3 VCC is replaced by VIO td(BUSoff−RxD) RB20130429 Figure 8. Transceiver Timing Diagram DEVICE ORDERING INFORMATION Part Number Description NCV7342D10R2G High Speed CAN Transceiver with Standby and VSPLIT pin NCV7342D13R2G High Speed CAN Transceiver with Standby and VIO pin (available in 2014) Package Shipping† SOIC 150 8 GREEN (Matte Sn, JEDEC MS−012) (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 13 NCV7342 PACKAGE DIMENSIONS SOIC 8 CASE 751AZ ISSUE O http://onsemi.com 14 NCV7342 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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