Generating a 1.2 V Voltage Supply using the NCP102 Voltage Regulator

AND8303/D
Generating a 1.2 V Voltage
Supply using the NCP102
Voltage Regulator
Prepared by: Juan Carlos Pastrana
ON Semiconductor
http://onsemi.com
INTRODUCTION
The minimum output voltage is limited by the voltage
reference. The pass transistor is selected to achieve the
desired input voltage and output current.
Stability of linear regulators is very critical as with any
feedback system. The main contributors to the stability of a
linear regulator are the error amplifier, the external pass
transistor, the output capacitor(s) and load. Figure 2 shows
a model of a linear regulator used to evaluate the frequency
response of the regulator.
The NCP102 low dropout linear regulator controller
contains all the control and protection features needed to
implement a low voltage regulator. The required external
N-Channel MOSFET allows the device to be used in
applications across a broad range of voltage and power levels.
The NCP102 is the ideal choice for new generation low
voltage supplies in computing motherboard and consumer
applications thanks to the following features:
• A dedicated enable input: allows the controller to be
remotely enabled or sequenced.
• An extremely accurate 0.8 V (+2.0%) reference:
allows the implementation of sub 1 V voltage supplies.
• Adjustable soft-start: allows the system to turn on in
a controlled manner eliminating output voltage
overshoot.
• Minimum drive capability of +5 mA: provides fast
transient response. The drive current is internally
limited to protect the controller in case of an external
MOSFET failure.
• Wide voltage supply operation: allows the controller
to be biased directly from existing voltage supplies
without the need of external voltage limiting circuits.
VDRV
Rg
Cgs
Error Amplifier
+
EA(s)
Cout2
Rout
VREF
R2
RESR1
Gdiv(s)
RESR2
T(s)
H(s) + EA(s) @ G div(s) @ T(s)
(eq. 1)
The error amplifier (EA(s)) usually has a dominant pole
at a low frequency with additional poles or zeros at higher
frequencies. Assuming its additional frequency components
are above the frequency range of interest, the frequency
response can be approximated to a single pole response as
given by Equation 2.
Error Amplifier
Cout
EA(s) +
R2
VREF
K1
(s ) p1)
(eq. 2)
where K1 is the dc gain and p1 is the dominant pole. The
resistor divider attenuates the system gain, Gdiv(s), and its
magnitude is given by Equation 3.
Figure 1. Simplified Linear Regulator Model
ǒR1 R2
Ǔ
) R2
A fraction of the output voltage is compared to the internal
reference voltage by means of resistor divider R1 and R2.
January, 2008 - Rev. 0
Cout1
The overall system response, H(s), is given by Equation1.
R1
© Semiconductor Components Industries, LLC, 2008
gmVgs
Figure 2. Frequency Model of a Linear Regulator
Vout
+
Vgs
_
Vout
R1
Linear regulators are a common topology for generating
a lower voltage supply from a higher voltage. A linear
regulator consists of a voltage reference (VREF), an error
amplifier and a pass transistor as shown in Figure 1.
Pass Transistor
Cgd
+
Linear Regulators
Vin
Vin
System
G div(s) + 20 @ log
1
(eq. 3)
Publication Order Number:
AND8303/D
AND8303/D
The frequency response of the external components from
VDRV to Vout is a little more complicated. The response is
determined by the output capacitors and the external pass
transistor. If only one capacitor is considered the transfer
response can be simplified as described in
ONSemiconductor's application note AND8037.
T(s) +
Each output capacitor contributes a zero due to its
equivalent series resistance (ESR). In the case of two types
of output capacitors (such as electrolytic and ceramic), zeros
at different frequencies are generated. The external pass
transistor contributes a zero and affects the poles of the
system. The frequency response from VDRV to Vout is given
by Equation 4.
R out(sC gs ) 1) @ (sR ESR1C OUT1 ) 1) @ (sR ESR2C OUT2 ) 1)
D 4s 4 ) D 3s 3 ) D 2s 2 ) D 1s ) (1 ) g mR out)
(eq. 4)
where:
D4 = CgsRoutCgdRgRX
D3 = CgsRoutCgdRgRX + RgRXCX + CXRoutRgRESR2Cout2Cout1 + RoutRgRESR1Cout1Cout2CX + RoutRX(RggmCgd + Cgs)
D2 = CgsRoutCgdRg + RgRESR1Cout1CX + RX + RESR2Cout2RgCX + Cout1RoutRESR2Cout2 + Cout1RoutRgCX +
D2 = Cout2RoutRESR1Cout1 + Cout2RoutRgCX + gmRoutRX + gmRoutRgCgdRS + CgsRoutRS
D1 = RgCX + RS + Rout (Cout1 + Cout2 + Cgs) + gmRout(RS + CgdRg)
RX = RESR1Cout1RESR2Cout2
CX = Cgs + Cgd
RS = RESR1Cout1 + RESR2Cout2
and gm is the transconductance of the external transistor.
It is obvious that the overall transfer response is too
dissipation, PD, of the external MOSFET. The power
dissipation is calculated using Equation 6 and the maximum
complex for hand calculations. Even with several
junction temperature, TJ, using Equation 7.
simplifications the roots of the transfer function to
determine the poles of T(s) are too complex. A design tool
(eq. 6)
P D + (V in * V out) @ Iout
is available for the NCP102 allowing the user to evaluate the
(eq. 7)
T J + P D @ R qJA ) T A
system response. The design tool can be downloaded at
www.onsemi.com.
where, R
is the junction to ambient thermal resistance (in
qJA
°C/W) of the external MOSFET. The NCP102 design tool
automatically calculates the power dissipation and junction
temperature.
Using RqJA doesn't always result in accurate junction
temperature calculations as RqJA depends on the board
layout. Alternatively, TJ can be calculated using the junction
to case thermal resistance, RqJC, and measuring the case
temperature (TC). Equation 8 relates the TJ to RqJC.
DESIGN EXAMPLE
The flexibility of the NCP102 is demonstrated by
designing a 1.2 V/3.0 A voltage regulator using the NCP102
design tool. The input and supply voltages selected are
typically found in computing mother board applications.
The regulator specifications are listed in Table 1.
Table 1. Design Specifications
Parameter
Symbol
Min
Max
Input Voltage
Vin (V)
1.8 (±2%)
Output Voltage
Vout (V)
1.2 (±2%)
Output Current
Iout (A)
0.3
3.0
Ambient Temperature
TA (°C)
-
50
Supply Voltage
VCC (V)
5 V (±5%)
Derating Factor
-
90 %
T J + P D @ R qJC ) T C
ON Semiconductor's NTD40N03 is used in this design. It
has a Vth of 2.0 V, an RqJA of 71.4°C/W and an RqJC of
3°C/W. Using RqJA and the maximum ambient temperature
a TJ of 178°C is calculated. That is slightly higher than the
maximum junction temperature of the device and exceeds
the derating factor. As RqJA provided in the NTD40N03
datasheet is for a specific layout, we will evaluate the board
at full load and use RqJC to calculate TJ. It will be shown that
the junction temperature meets the derating factor. This
board provides a place holder for a parallel MOSFET (Q2)
allowing the user to spread the power dissipation if needed.
Transconductance is the ratio of output current to the input
voltage. In a MOSFET, it is the ratio of drain current (ID) to
gate-to-source voltage (VGS) as given by Equation 9.
DESIGN PROCEDURE
External MOSFET:
The 1st step in the regulator design is to select the external
pass transistor. The output and supply voltages as well as
MOSFET gate-to-source threshold voltage, Vth, need to be
considered. The MOSFET threshold voltage, Vth, should be
less than VCC minus Vout as given by Equation 5.
V th v V CC * V out
(eq. 8)
gm +
(eq. 5)
Solving 5 using the design specifications, Vth should be
less than 3.8 V. The next step is to calculate the power
DID
DV GS
(eq. 9)
Referring to the NTD40N03R datasheet, the
transconductance is calculated using the On-Region
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AND8303/D
40
180
30
135
Simulated Phase
20
90
10
45
0
0
PHASE (°)
MAGNITUDE (dB)
Characteristics Curve (Figure 1). Let's calculate the
transconductance for a VDS of 0.5 V with a VGS variation
from 2.8 V to 3 V. The drain current at 2.8V is ~1.8 A and
at 3 V it is approximately 3.8 A. Using these values a
transconductance of 10 is calculated.
The gate-to-source, CGS, and drain-to-source, CDS,
capacitances are needed for the frequency response analysis.
The capacitances are calculated from the Capacitance
Variation curve on the NTD40N03R datasheet. Crss is the
gate-to-drain capacitance. Ciss is the sum of CGS and CGD.
Coss is the sum of CDS and CGD. Referring to the
Capacitance Variation curve, Crss is approximately 150pF,
Ciss is approximately 700 pF and Coss is approximately
600pF at a VDS of 0.5 V, resulting in a CDS of 450 pF and
a CGS of 550 pF.
-45
-10
-90
-20
Simulated Gain
-135
-30
-40
1
10
100
FREQUENCY (kHz)
-180
1000
Figure 3. Simulated Frequency Response
Output Capacitor:
The approximate crossover frequency is 50 kHz with a
phase margin of 85°.
The next step is to select the output capacitor. It is very
common to use an electrolytic capacitor for bulk storage and
a ceramic capacitor for high frequency bypass. However, the
capacitors need to be carefully selected as they affect the
stability of the system.
An electrolytic capacitor has high capacitance and high
ESR resulting in a zero at a low frequency (typically below
1kHz) and a dominant pole at a higher frequency. The
ceramic capacitor has very low ESR placing a zero at a high
frequency. If the ceramic capacitor capacitance is large
(above 4.7 mF) the resulting zero may be in the crossover
frequency range and thus affect the stability of the system.
This design uses a 1000 mF electrolytic capacitor with an
ESR of 212 mW and a 4.7 mF ceramic in parallel.
Soft-Start:
Soft-start slowly increases the regulator output voltage
reducing stress during power up. The NCP102 implements
soft-start by slowly charging the soft-start capacitor
(CSOFT-S) with a fixed current source (ISOFT-S). The
soft-start voltage is then used to control the dv-dt of the
DRV pin. The soft-start period ends once the soft-start
voltage reaches 0.8 V. Equation 10 is used to calculate the
soft-start period.
t SOFT*S +
C SOFT*S @ 0.8V
I SOFT*S
(eq. 10)
The design tool calculates the soft-start capacitor based
on the user provided soft-start period. The user can override
the suggested soft-start capacitor value and the tool
calculates the soft-start period based on the provided
capacitor value. This design uses a 0.1 mF soft-start
capacitor for a 16 ms period.
Resistor Divider:
The output voltage is sampled by resistor divider R1 and
R2. The node between the resistors must equal the reference
voltage (0.8 V) at the desired output voltage. Using the
design tool, the user arbitrarily selects a value for R2 and the
tool suggests a value for R1. The user can override the
suggested R1 value. In this design, R2 is set at 20 kW and R1
at 10 kW.
BOARD LAYOUT
The regulator is built to validate the design using a 2 layer
FR4 board having 1 oz copper plating. The board size is
3.5in. x 3.2 in. Test points are provided for the Enable, DRV,
Soft-Start, FB, Vin, Vout signals.
During the layout process care was taken to:
1. Minimize trace length, especially for high current
loops.
2. Use wide traces for high current connections.
3. Use a single ground connection.
4. Place decoupling capacitors close to the NCP102
and board terminals.
5. Sense output voltage at the output connector to
improve load regulation.
The top layer is shown in Figure 4 and the bottom layer is
shown in Figure 5. The top layer shows the component
location.
Frequency Response:
The NCP102 design tool simplifies the frequency response
analysis of the regulator. It is a good tool to evaluate the
interaction between the components and approximate the
cross over frequency. However, it does not take into account
2nd order effects such as transconductance variations with
load current. The simulated frequency response of the
regulator at minimum load is shown in Figure 3.
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AND8303/D
Figure 4. Layer 1 (Top)
Figure 5. Layer 2 (Bottom)
DESIGN VALIDATION
The circuit schematic is shown in Figure 6 and the bill of
materials is shown in Table 2.
The layout files may be available. Please contact your
sales representative for availability.
Vin
VCC
TP2a
J2
J1
TP2
TP1
R8
ENABLE 1 k
J5
C11
100 p
MMBT3904
Q3
U1
1
R7
365 k
R6
10 k
2
3
Open
EN
VCC
GND
DRV
FB
TP12
TP5
6
0.01
C3
SOFT-S
4
C5
C6
470
4.7
0.1
NTD40N03
Q2
R1
5
C10
200
Q1
C4
100 p
R2
TP6a
100
Vout
C7
C8
C9
J3
1000
4.7
0.1
TP6
TP7
NCP102 TP4
R5
0
C1
0.01
R3
10 k
TP8
TP9
TP10
TP11
TP3
R4
20 k
Figure 6. Circuit Schematic
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GND
J4
J6
AND8303/D
Table 2. Bill of Materials
Reference
Value
Part
Vendor
Comments
C1, C3
0.01 mF, 50 V
(0.01 mF, 25 V)
C1608X7R1H103K
(VJ0603Y103KXXA)
TDK
(Vishay)
Capacitor, Ceramic
C2
N/A
N/A
N/A
Not Used
C4, C11
100 pF, 50 V
(100 pF, 25 V)
C1608CH1H1015
(VJ0603Y101KXXA)
TDK
(Vishay)
Capacitor, Ceramic
C5, C8
4.7 mF, 16 V
C3216X5R1C475K
TDK
Capacitor, Ceramic
C6, C9
0.1 mF, 25 V
C3216CH1E104J
(VJ1206Y104KXXA)
TDK
(Vishay)
Capacitor, Ceramic
C7
1000 mF, 25 V
ESMG250ELL102MJ20S
United-Chemicon
Capacitor, Aluminum Electrolytic
C10
470 mF, 25 V
ESMG250ELL471MJC5S
United-Chemicon
Capacitor, Aluminum Electrolytic
Q1
45 A, 25 V
NTD40N03RG
ON Semiconductor
Power MOSFET, N-Channel
Q2
N/A
N/A
N/A
Not Used
Q3
200 mA, 40 V
MMBT3904LT1G
ON Semiconductor
Transistor, Sm Signal, NPN
R1
200 W, 0.25 W
CRCW1206200RF
Vishay
Resistor, Thick Film
R2
100 W, 0.25 W
CRCW1206100RF
Vishay
Resistor, Thick Film
R3
10 kW, 0.25 W
CRCW12061002F
Vishay
Resistor, Thick Film
R4
20 kW, 0.25 W
CRCW12062002F
Vishay
Resistor, Thick Film
R5
0 W, 0.1 W
CRCW06030R00F
(*CRCW06030000Z0)
Vishay
Resistor, Thick Film
R6
10 k, 0.1 W
CRCW06031002F
Vishay
Resistor, Thick Film
R7
365 kW, 0.1 W
CRCW06033653F
Vishay
Resistor, Thick Film
R8
1 kW, 0.1 W
CRCW06031001F
Vishay
Resistor, Thick Film
NCP102SNT1G
ON Semiconductor
Low Dropout Linear Regulator Controller
U1
J2
10ADC
571-0500
Deltron Emcon
Banana Jack, 4 mm Socket, Red,
Horizontal Mt.
J3
10ADC
571-0700
Deltron Emcon
Banana Jack, 4 mm Socket, Yellow,
Horizontal Mt.
J4, J6
10ADC
571-0100
Deltron Emcon
Banana Jack, 4 mm Socket, Black,
Horizontal Mt.
J5
300 V, 16 A
DigiKey ED1930-ND or
equivalent
Terminal Block, 2 Pole, Side Entry
TP1
TP-015-01-01
Components Corporation
Test Point, Brown
TP2
TP-015-01-02
Components Corporation
Test Point, Red
TP3
TP-015-01-03
Components Corporation
Test Point, Orange
TP4
TP-015-01-04
Components Corporation
Test Point, Yellow
TP5
TP-015-01-05
Components Corporation
Test Point, Green
TP6
TP-015-01-06
Components Corporation
Test Point, Blue
TP7
TP-015-01-07
Components Corporation
Test Point, Violet
TP8 - TP11
TP-015-01-00
Components Corporation
Test Point, Black
TP12
TP-015-01-08
Components Corporation
Test Point, Gray
TP6a, TP2a
131-5031-00 (pkg of 25)
Tektronix
3.5 mm dia. Probe Adapter
* Alternate
1. TDK components can be ordered at (847) 803-6100.
2. Vishay Components can be ordered at (402) 563-6866.
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AND8303/D
Startup:
The final step is to verify the board performance. The
evaluation criteria include step load and power up responses,
load regulation, stability and power dissipation.
The startup behavior of the regulator is evaluated at
minimum and maximum load enabling the controller using
the enable pin while Vin and VCC are already high. The
startup waveforms at minimum and maximum load are
shown in Figure 8 and 9, respectively.
Dynamic Response:
The dynamic response of the regulator is evaluated
stepping the load current from 10% to 100% and from 100%
to 10% of the rated output current. The step load responses
are shown in Figure 7.
Vout
Enable
Vin
Soft-start
Figure 9. Output Voltage During Power Up at
Maximum Load
Figure 7. Output Voltage Response to a Step Load
from 0.3 A to 3.0 A to 0.3 A
Line and Load Regulation:
Line and load regulation are calculated using Equations 11
and 12, respectively. Line regulation is measured at 0.1%
and load regulation is measured at 0.067%. The output
voltage vs. input voltage and output load is shown in
Figure10.
The output voltage stays within the 2% tolerance limit.
The initial drop on the output voltage as a higher load is
applied is mostly dependent on the output capacitor and not
on the loop response of the system. No ringing is observed,
indicating an adequate phase margin.
Reg (line) +
Vout
Reg (load) +
DV out
DV in
(eq.
11)
V out(noload) * V out(fullload)
V out(noload)
(eq. 12)
Enable
1.224
Vout, OUTPUT VOLTAGE (V)
Vin
1.216
1.208
Soft-start
Iout = 3.0 A
1.200
Iout = 0.3 A
1.192
1.184
Figure 8. Output Voltage During Power Up at
Minimum Load
1.176
1.55
1.65
1.75
1.85
Vin, INPUT VOLTAGE (V)
1.95
Figure 10. Output Voltage Response to Input
Voltage and Output Load Variations
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2.05
AND8303/D
Frequency Response:
As expected, the hottest component on the board is the
external pass transistor. The case temperature is measured at
78.4°C at room temperature. Using Equation 8, the junction
temperature is calculated at 84°C. The maximum junction
temperature is calculated at 109°C assuming a 25°C
temperature delta between room and maximum ambient
temperatures. A junction temperature of 109°C meets our
derating guidelines.
The thermal performance of the board can be optimized
by using a heatsink, increasing the number of external pass
transistors (Q1 & Q2) pad area, increasing the copper weight
of the board or using an additional pass transistor.
The open loop response is measured by injecting an AC
signal across R2 using a network analyzer and an isolation
transformer. The measured and calculated open loop
responses at minimum load are shown in Figure 11. The
measured crossover frequency is 58 kHz with a phase
margin of 70°. A good correlation is observed between
simulated and calculated responses up to around 200 kHz.
40
180
135
Simulated Phase
20
90
10
45
0
0
Measured Phase
-10
PHASE (°)
MAGNITUDE (dB)
30
SUMMARY
A 1.2 V regulator is designed and built using the NCP102.
The regulator has excellent line and load regulation with
better than ±2% output voltage regulation.
The regulator provides excellent transient response.
Phase margin and crossover frequency are measured at 70°
and 58 kHz, respectively.
-45
-90
-20
Simulated Gain
-135
-30
Measured Gain
-40
1
10
100
FREQUENCY (kHz)
-180
1000
REFERENCES
1. Tod Schiff, “Stability in High Speed Linear LDO
Regulator,” AND8037/D, www.onsemi.com.
2. Low Dropout Linear Regulator Controller Datasheet
NCP102, www.onsemi.com.
3. Power MOSFET 45 A, 25 V Datasheet NTD40N03R,
www.onsemi.com
Figure 11. Measured and Calculated Open
Loop Frequency Responses
Power Dissipation:
This demo board is designed to operate with no airflow.
However, in most desktop computing applications airflow
will be present. The thermal performance of the board is
evaluated using an infrared camera. Figure 12 shows the
thermal image of the board at maximum output load.
Figure 12. Thermal Image of the Board at
Maximum Load
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AND8303/D
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