INTEGRATED CIRCUITS SA1638 Low voltage IF I/Q transceiver Product specification IC17 Data Handbook 1997 Sept 03 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 • High performance on-board integrated receive filters with DESCRIPTION The SA1638 is a combined Rx and Tx IF I/Q circuit. The receive path contains an IF amplifier, a pair of quadrature down-mixers, and a pair of baseband filters and amplifiers. A second pair of mixers in the transmit path transposes a quadrature baseband input up to the IF frequency. An external VCO signal is divided down internally and buffered to provide quadrature local oscillator signals for the mixers. A further divider chain, reference divider and phase detector are provided to avoid the need for an external IF synthesizer. Rx or Tx path or the entire circuit may be powered down by logic inputs. On-board voltage regulators are provided to allow direct connection to a battery supply. bandwidth tunable between 50-850 kHz • Switchable alternative bandwidth setting available to allow channel bandwidth flexibility in operation • Designed for a widely used I and Q baseband GSM interface • Control registers power up in a default state • Optional DC offset trim capability to <200mV • Only a standard reference input frequency required, choice of 13, 26, 39 or 52MHz • Fully compatible with SA1620 GSM RF front-end (see Figure 9) FEATURES • Direct supply: 3.3V to 7.5V • Two DC regulators giving 3.0V output • Low current consumption: 18mA for Rx or 22mA for Tx • Input/output IF frequency from 70-400 MHz • Internal IF PLL for synthesizing the local oscillator signal APPLICATIONS • IF circuitry for GSM 900MHz hand-held units • IF circuitry for PCN (DCS1800) hand-held units • Quadrature up and down mixer stage PIN CONFIGURATION 48 47 46 45 44 43 42 VREG1 VREGF2 VREG2 GNDREG2 PON CP VccCP PONPLL 3 4 5 AOUT 7 48–pin LQFP 8 9 RESD 10 RESA 11 RESB GND3 2 6 DCRES 41 40 39 38 37 1 VBATT BOUT TxIFOUTX TxIFOUT GND2 RxIF INX RxIF IN GND1 VccTxRx GNDREG1 LQFP Package 12 36 VEECP 35 IREF 34 LO INX 33 LO IN 32 ADJ IN 31 CLK IN 30 CLK INX 29 LOCK 28 STROBE 27 CLOCK 26 DATA 25 VEEDIG VccDIG PDTx ITx INX ITx IN QTx INX QTx IN IRxOUTX IRxOUT QRxOUTX QRxOUT VREF PONRx 13 14 15 16 17 18 19 20 21 22 23 24 SR00524 Figure 1. SA1638 Pin Configuration ORDERING INFORMATION DESCRIPTION 48-Pin Thin Quad Flat Pack (LQFP) 1997 Sept 03 2 TEMPERATURE RANGE ORDER CODE DWG # -40 to +85°C SA1638BE SOT313-2 853-1818 18351 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 VREG2 GNDREG2 VREGF2 PON V BATT GNDREG1 VREG1 RESD RESB RESA BLOCK DIAGRAM PONRx BIAS RX V.REG.1 V.REG.2 V REF PDTx ITx IN BIAS TX ITx INX TxIFOUT TxIFOUTX QTx IN VCCTxRx QTx INX GND3 IRxOUT GND1 IRxOUTX RxIF IN IF AMP RxIF INX QRxOUT GND2 QRxOUTX LO IN ÷2 LO INX DCRES DC BUFFERS ADJUST AOUT STATUS ADJ IN BOUT REGISTER ÷N LOCK DC REGISTER CP PHASE TEST PUMP DETECTOR REGISTER DIG V EE CLK IN DIG V CC 13, 26 SYNTH SERIAL 39, 52 REGISTER INPUT CLK INX ÷ VEECP STROBE VCCCP CLOCK PONPLL CHARGE DATA IREF SR00525 Figure 2. SA1638 Block Diagram 1997 Sept 03 3 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 PIN DESCRIPTIONS Pin No. Pin Name Description 1 VREG1 Output voltage of regulator 1 2 VREGF2 Feedback of regulator 2 3 VREG2 Output voltage of regulator 2 4 GNDREG2 Ground of regulator 2 5 PON Power-on input for voltage regulators 1 and 2 (active high) 6 VBATT Input voltage for regulators 1 and 2 7 AOUT Programmable logic output (see Figure 9) 8 BOUT Programmable logic output (see Figure 9) 9 DCRES Reference current setting resistor for DC offset circuit 10 RESD Additional external current defining resistor for filters 11 RESA Principal external current defining resistor for filters 12 RESB Principal external current defining resistor for filters 13 PONRx Power-on input for Rx (active high) 14 VREF Reference voltage 15 QRxOUT Differential receive baseband output 16 QRxOUTX Differential receive baseband output 17 IRxOUT Differential receive baseband output 18 IRxOUTX Differential receive baseband output 19 QTx IN Differential transmit baseband input 20 QTx INX Differential transmit baseband input 21 ITx IN Differential transmit baseband input 22 ITx INX Differential transmit baseband input 23 PDTx Power-on for transmitter (active low) 24 VCCDIG Digital circuit supply 25 VEEDIG Digital ground 26 DATA Serial bus data input 27 CLOCK Serial bus clock input 28 STROBE Serial bus strobe input 29 LOCK Test control/synthesizer lock indicator 30 CLK INX Differential reference divider input 31 CLK IN Differential reference divider input 32 ADJ IN Used for test only. Do not connect 33 LO IN Differential LO input 34 LO INX Differential LO input 35 IREF Reference current setting for charge pump 36 VEECP Charge pump ground 37 CP Charge pump output 38 VCCCP Charge pump circuit supply 39 POnPLL Power-on input for synthesizer circuits (active high) 40 GND3 Ground (internal connection to GND1 and GND2) 41 TxIFOUTX Differential transmit IFoutput (open collector) 42 TxIFOUT Differential transmit IFoutput (open collector) 43 GND2 Ground (internal connection to GND1 and GND3) 44 RxIF INX Differential receive IF input 45 RxIF IN Differential receive IF input 46 GND1 Ground (internal connection to GND2 and GND3) 47 VCCTxRx Transmit and receive circuits supply voltage (also feedback of Regulator 1) 48 GNDREG1 Ground of regulator 1 NOTE: There are no ESD protection diodes at Pins 41 and 42. Thus, open collector outputs may have increased DC voltage or higher AC peak voltage. 1997 Sept 03 4 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNITS VCCXXX Supply voltages: VCCTxRx, VCCDIG, VCCCP -0.3 to +6.0 V Battery voltage -0.3 to +8.0 V -0.3 to (VCCXXX+0.3) V VBATT VIN Voltage applied to any other pin ∆VG Any GND pin to any other GND pin PD Power dissipation, TA = 25°C (still air) 0 V 300 mW TJMAX Maximum operating junction temperature 150 °C PMAX Maximum power input/output +20 dBm TSTG Storage temperature range –65 to +150 °C NOTE: 1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, θJA. 48-pin LQFP: θJA = 67°C/W. RECOMMENDED OPERATING CONDITIONS SYMBOL RATING UNITS Supply voltages: VCCTxRx, VCCDIG 2.7 to 5.5 V VCCCP Charge pump supply voltage 2.9 to 5.5 V VBATT Battery voltage 3.3 to 7.5 V Operating ambient temperature range -40 to +85 °C VCCXXX TA PARAMETER Voltage Regulators TA = 25°C, PON = 3V, PONRX = 0V, PDTX = 3V, PONPLL = 0V, VBATT = 3.3V, IOUT1 = IOUT2 = 15mA, VREG1 connected to VCCTxRx, VREG2 connected to VREGF2; VCCDIG = VCCCP = 3V; unless otherwise stated. SYMBOL VREG1, VREG2 PARAMETER TEST CONDITIONS Nominal VOUT VBATT IOUT1, IOUT2 IBATT Supply current for both regulators +3σ Max 2.85 2.93 3.00 3.07 3.15 V 7.5 V 30 mA ILOAD = 0mA 4.3 5 5.7 7 mA 7.7 9 10.3 15 µA 0.1 1000 µF 0.1 500 µF % Power-down supply current CREG12 VREG1 cap load CREG22 VREG2 cap load LINEREG Line regulation DC, VBATT = 3.3V to 7.5V LOADREG Load regulation ILOAD = 15mA to 30mA Bandwidth Feedthrough attenuation from PON to each regulator FREG Feedthrough attenuation from VBATT to each regulator tON Typ PON = 0V, ILOAD = 0mA IBATT PD FPON UNITS –3σ 3.3 Maximum output current for each regulator1 BW LIMITS Min –0.4 –0.2 0.001 0.2 0.4 –5 –0.37 -0.17 0.03 5 100 f ≤ 100kHz f = 10MHz f = 100MHz f = 400MHz Turn ON time ≤ -40 dB ≤ -61 ≤ -32 ≤ -37 ≤ -48 dB 10 µs NOTES: 1. At Tj ≥ 150°C a thermal switch reduces the output current to avoid damage. 2. Recommended load capacitors: In every case CREG1 = CREG2 = 100nF to ground with series resistance ≤0.1Ω. Additional capacitor optional ≤1000µF with series resistance ≤5Ω. The low series resistance is very important to ensure regulator stability. 3. Standard deviations are based on the characterization results of 90 ICs. 1997 Sept 03 5 % kHz Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 DC ELECTRICAL CHARACTERISTICS VCCTxRx=VCCDIG=VCCCP=PONRx=PONPLL= +3V; VEEDIG = VEECP=GND1=GND2=GND3=PDTx = 0V; TA = 25°C, unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN –3σ TYP +3σ MAX UNITS Supply current ICC Rx and IF synthesizer active PONRx = PONPLL = PDTx = Hi 14.4 16 17.6 20 Tx and IF synthesizer active PONRx = PDTx = Low; PONPLL = Hi 17.4 19.5 21.6 24 Power-down mode VREF IVREF IOUT Reference voltage VREF PONRx = PONPLL = Low; PDTx = Hi 0.068 Generated internally 1.39 1.57 ISINK ISOURCE DC output current 1.75 V 5 5 At pins TxIFOUT and TxIFOUTX mA 1.5 1.86 µA 2.0 2.14 2.7 mA Digital inputs (PON) VIH High level input voltage range 2.0 VBATT V VIL Low level input voltage range 0 0.8 V Digital inputs (PDTx, PONRx, PONPLL, PON) VIH High level input voltage range 2.0 VCCTxRx V VIL Low level input voltage range 0 0.8 V Digital inputs (Clock, Data, Strobe) VIH High level input voltage range 2.0 VCCDig V VIL Low level input voltage range 0 0.8 V Digital outputs (LOCK, AOUT, BOUT) VOH Output voltage HIGH IO = -2mA VOL Output voltage LOW IO = 2mA V VCCDIG–0.4 0.4 V AC ELECTRICAL CHARACTERISTICS VCCTxRx=VCCDIG=VCCCP=PONRx=PONPLL= +3V; VEEDIG = VEECP=GND1=GND2=GND3=PDTx = 0V; LOIN = 100mVPEAK, 800MHz; CLKIN = 100mVPEAK, 52MHz; serial registers programmed with default values; TA = 25°C unless otherwise stated. Test Circuit Figure 8. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN –3σ TYP +3σ 0.82 0.94 1.06 MAX UNITS IF Transmit Modulator BW VCOM VIN Input modulation bandwidth 200Ω source impedance Common mode range for baseband inputs DC at pins ITxIN, ITxINx, QTxIN, QTxINx Peak input signal amplitude 1 1.5 Centered on VCOM Third harmonic distortion1 | ITxIn | = | ITxInX | = | QTxIn | = | QTxInX | = 0.75VPEAK; fin = 20kHz RINTx Input resistance Between pins: ITxIn and ITxInX or QTxIn and QTxInX CINTx Input capacitance MHz 2 0.75 -61 -57 V V -53 -40 112 dB kΩ At ITxIn, ITxInX, QTxIn, QTxInX Output saturation limit 10 pF VCCTxRx-0.3 V 1.08 mA IOUT RMS output current | ITxIn | = | ITxInX | = | QTxIn | = | QTxInX | = 0.75VPEAK SLO LO suppression1 | ITxIn | = | ITxInX | = | QTxIn | = | QTxInX | = 0.75VPEAK; fin = 20k +30 +43 dB SSB Sideband suppression1 | ITxIn | = | ITxInX | = | QTxIn | = | QTxInX | = 0.75VPEAK; fin = 20k +35 +50 dB 1997 Sept 03 6 0.6 0.73 0.82 0.91 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN –3σ TYP +3σ -130 -129 -128 -133 -131 -129 MAX UNITS IF Transmit Modulator (continued) Noise density at 600kHz Noise density at 10MHz |ITxIn| = |ITxInX| = |QTxIn| = |QTxInX| = 0.75VPEAK dBc/Hz tON Turn ON time PdTx = LO, transmit signal to 90% 5 µs tOFF Turn OFF time PdTx = HI, transmit signal to 10% 5 µs 5 || 0.6 kΩ || pF 1 kΩ IF Receiver (R = 36kΩ between pins RESA and RESB) RInRx ROutRx Differential input impedance fIN = 400MHz Output impedance Output common mode voltage f3dB VREF Low pass filter -3dB bandwidth 70 Low pass filter attenuation: 200kHz 400kHz 600kHz 6.5MHz 13.0MHz VG Voltage gain Differential output PD into GSM baseband relative to 1200Ω source EMF NF Noise figure8 1200Ω source and external matching resistor and inductor 8.9 38.1 10.7 45 70 >80 >80 12.5 51.9 43 49.4 51 52.7 5.7 7.0 8.3 fIN = 400.005MHz -1.5 Output DC offset2 Differential, DCRES=562kΩ -60 Output drive current at each pin VOUT Minimum differential output swing P-1dB Input 1dB compression point: In band 200kHz 400kHz 600kHz Source (Sink) 1200Ω source EMF 90 6.5 30 Channel matching: Gain Phase IOUT V 83 -59 -54 -55.3 -49.3 kHz dB 58 dB dB -0.26 0.0 1.5 dB degrees -25 60 mV 10 (700) µA 2.0 V -53 -47 -47 -47 -50.7 -44.8 -47 -40 dBV tON Turn ON time3 POnRx = HI, to baseband signal out 2 µs tOFF Turn OFF time POnRx = LO, to no baseband signal out 2 µs IF Synthesizer fLO Local oscillator input frequency range9 140 ZLOIN Differential input impedance Between pins LOIN and LOINX, fIN = 800MHz VLOIN LO peak input voltage range Single-ended Referred to 50Ω Programmable divider: Division range Step size Reference clock input frequency Differential input impedance Between pins ClkIn and ClkInX VCLKIN CLKIN peak input voltage range Single-ended, referred to 50Ω | ICP | Charge pump output current: c0...c2 = 000 c0...c2 = 111 Step size 1997 Sept 03 50 100 mV 511 1 fCLKIN IREF MHz Ω || pF 276 || 0.6 64 ZCLKIN Charge pump input reference current 800 VCLKIN = 100mVPEAK 52 10 || 1.0 50 400 7 0.425 0.85 0.045 0.487 0.979 0.062 0.5 1.0 0.071 mV µA 31.2 IREF =31.2µA, VCP = VCCCP/2 MHz kΩ || pF 0.513 1.021 0.08 0.575 1.15 0.105 mA Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER LIMITS TEST CONDITIONS MIN UNITS –3σ TYP +3σ MAX 0.1 1.3 2.5 ±10 % ±12 % ±15 nA IF Synthesizer (cont.) DI CP I CP Relative output current variation4 IREF =31.2µA IREF =31.2µA, VCP = VCCCP/2 ∆ICP_M Output current matching5 |ICP_L| Output leakage current VCP = 0.3V to VCCCP-0.3V tON Turn ON time POnPLL = HI, to full charge pump current 15 µs tOFF Turn OFF time6 POnPLL = LO, to ICCCP, ICCDIG <5% of operational supply current 15 µs -0.02 0.1 0.22 Serial Interface7 fCLOCK Clock frequency 10 MHz tSU Set-up time: DATA to CLOCK, CLOCK to STROBE 30 ns tH Hold time: CLOCK to DATA 30 ns Pulse width: CLOCK 30 Pulse width: STROBE 30 tW ns NOTES: 1. Parameter measured relative to modulation sideband amplitude. 2. After programming the DC offset register for minimum offset. DCRES = 562kΩ. 3. The turn on time relates only to the power up time of the circuit. The settling time of the integrated baseband filters has to be added (for GSM–mode = 8µs with filter bandwidth setting resistor = 36kΩ). DI OUT (I * I 1) 4. The relative output current variation is defined thus: +2@ 2 ; with V1 = 0.3V, V2 = VCCCP – 0.3V (see Figure 3). |(I 2 ) I 1)| I OUT 5. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on. 6. As soon as PONPLL is set to LO, the phase detector is reset and no charge pumps pulses are generated. 7. Guaranteed by design. 8. NF = ƪ 20 log ǒ E no Ǹ4kTR Ǔƫ * VG where, Eno is the output noise voltage measured in a 1Hz bandwidth, R = 1200Ω, VG = gain in dB. 9. Minimium frequency is guaranteed by design. address bits and 1 subaddress bit. Figure 2 shows the timing diagram of the serial input. When the STROBE = L, the clock driver is enabled and on the positive edges of the CLOCK the signal on DATA input is clocked into a shift register. When the STROBE = H, the clock is disabled and the data in the shift register remains stable. Depending on the value of the subaddress bit the data is latched into different working registers. Table 3 shows the contents of each word. CURRENT I2 I1 VOLTAGE V1 V2 Default States Upon power up (VCCDIG is applied) a reset signal is generated, which sets all registers to a default state. The logic level at the STROBE pin should be low during power up to guarantee a proper reset. These default states are shown in Table 3. I2 I1 Reference Divider SR00526 The reference divider can be programmed to four different division ratios (:13, :26, :39, :52), see registers r0, r1; default setting: divide by 13. Figure 3. Relative Output Current Variation FUNCTIONAL DESCRIPTION Serial Programming Input Main Divider The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program the counter ratios, charge pump current, status- and DC-offset register, mode select and test register. The programming data is structured into two 21-bit words; each word includes 4 chip 1997 Sept 03 The external VCO signal, applied to the LOIN and LOINX inputs, is divided by two and then fed to the main divider (:N). The main divider is a programmable 9 bit divider, the minimum division ratio is 8 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 divide by 64. The division ratio is binary coded and set in the registers n0 to n8. The default setting is a divide by 400. Status Register At the completion of a main divider cycle, a main divider output is generated which will drive the phase detector. The s0 and s1 status bits determine the values of the logic output pins AOUT and BOUT. These outputs can be connected to the AGC control inputs A and B of the SA1620. (See Figure 9) Phase Detector DC Offset Register Registers i0 to i3 and q0 to q3 control a correction to the output DC offset of the I and Q channels of the receiver. The polarity of the DC offset correction in the I and Q channels are determined by i0 and q0, respectively. The other bits set the magnitude of the offset correction. The step size of the two offset correction DACs is fixed by an external resistor between the DCRES pin and ground. A value of 120kΩ will give a step size of 200mV. The phase detector is a D-type flip-flop phase and frequency detector shown in Figure 5. The flip-flops are set by the negative edges of the output signals of the dividers. The rising edge of the signal L will reset the flip-flops after both flip-flops have been set. Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flip-flops drive on-chip charge pumps. A source current from the charge pump acts to increase the VCO frequency; a sink current acts to decrease the VCO frequency. Mode Select Register t0: Current Setting The charge pump current is defined by the current set between the pin IREF and VEECP. The current value to be set there is 31.2µA. This current can be set by an external resistor to be connected between the pin IREF and VEECP. The typical value REXT (current setting resistor) can be calculated with the formula R EXT The attenuation switch is included between the IF amplifier and the I and Q mixers, thereby influencing the noise figure negligibly. The purpose of this switch is to provide another AGC step which does not influence the receiver noise figure. Please note that this gain change will influence the DC offset of the I and Q mixers. t1 = 0 test mode only, always to be set to 0. t2, t3 sets the mode of the level locked loop (LLL) V CCCP 1.4V 31.2mA The current can be set to zero by connecting the pin IREF to VCCCP. The LLL is a circuit which processes the LO input signal in order to provide an LO signal with a perfect 50% duty cycle, which determines the precision of the 90° shift of the I and Q mixing signals generated by the ÷2 divider. For an external tuning of the 90° phase shift of the I and Q mixing signals, a trimming resistor may be connected (but is not required) between the ADJIN pin and ground, and the LLL has to be put in one of the following modes: Charge Pumps The charge pumps at pin CP are driven by the phase dectector and the current value is determined by the binary value of the charge pumps register CN = c2, c1, c0, default 1mA. The active charge pump current is typically: |I CP| (c0 2c1 4c2) 71mA switches the RX IF gain. t0 = 0 no attenuation t0 = 1 10dB attenuation 500mA Table 2. Mode Select Register Lock Detect t2 t3 LLL Status The output LOCK is H when the phase detector indicates a lock condition. This condition is defined as a phase difference of less than ±1 cycle on the reference input CLKIN, CLKINX. 0 0 LLL on (no external tune, monitor performance, default) 0 1 LLL on (with medium external tune) 1 0 LLL off (tune externally) Test Modes (Synthesizer, Transmit Mixer) 1 1 LLL on (with fine external tune) The LOCK output is selectable as a test output. Bits x0, x1 control the selection, the default setting is normal lock output as described in the Lock detect section. The selection of a Bit x0, x1 combination has a twofold effect: First it routes a divider output signal to the LOCK pin, second it disables mixer stages in the transmit path. Setting x0,1 = 11 disables both transmit path mixers. This mode can be used to prevent the transmitter from producing an IF output signal even if the transmit part is powered on (PDTx = 0V). This can be used to simplify the control timing while commanding the transmit and receive simultaneously without the transmit part causing interference. Table 1. t4 t5 With t5, two external resistor values are selectable. t5 = 0 the resistance between the pins RESA and RESB determines the cutoff frequency. For GSM a nominal bandwidth of 80kHz is chosen when the external resistor is 36kΩ. t5 = 1 a second resistor between the pins RESB and RESD is connected in parallel to the first external resistor, thus increasing the filter bandwidth. The relative amplification is decreased in this mode. Test Modes Transmit Mixer x0 x1 Synthesizer y Signal g at LOCK Pin Q-mixer I-mixer 0 0 normal lock detect on on 1 0 CLKIN divided by reference divider ratio off on 0 1 LOIN ÷ 2 * (main divider ratio) on off 1 1 main divider output, that goes to the phase detector off off 1997 Sept 03 selects the bandwidth of the RC low pass filters at the I, Q Rx mixer outputs t4 = 0 cutt-off frequency (-3dB) 110kHz t4 = 1 cutt-off frequency (-3dB) 792kHz selects the bandwidth of the integrated 5th-order gyrator filters. The filters are tuneable over a range of 50kHz to 1MHz with external resistors. The -3dB bandwidth is inversely proportional to the value of the external resistor. 9 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 PONRx = H powers up the receiver part. The overall filter response in the receive section is the sum of the filter responses of the passive RC low-pass filter and the active gyrator filter. PDTx = L powers up the transmitter part. PONPLL = H powers up the synthesizer part. As it also powers up the first divide by 2 stage for generating the 0/90 degree phase shifted signals for the transmit and receive mixers, it also has to be set H if either the transmit part or the receive part is used. PONPLL = L powers down the dividers, resets the phase detector and disconnects the current setting pin IREF. In PONPLL = L mode, the values in the serial input registers are still kept and the part still can be reprogrammed as long as VCCDIG is present. Power Down Modes There are 4 power-on pins in the SA1638: PON, PONRx, PDTx, PONPLL. PON = H powers up both voltage regulators VREG1 and VREG2. PON should be set to L, if these internal voltage regulators are not to be used. Table 3. Definition of SA1638 Serial Registers First data word: (shown with default values) Sub Adr Address SA1638 Ref ÷ Reg N-Divider Charge-Pump Reg Test MSB LSB a0 a1 a2 a3 sa n0 n1 n2 n3 n4 n5 n6 n7 n8 r0 r1 c0 c1 c2 x0 x1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 Address: Sub:Address: N-Divider: Reference Divider Register: Charge-Pump Register: Test Register: 4 bits, a0...a3, fixed to 1110 1 bit, sa, fixed to 0 for first data word 9 bits, n0...n8, values 64 (00100 0000) to 511 (111111111) allowed for IF-choice, default 400 2 bits, r0...r1, 00 = ÷13, 01 = ÷26, 10 = ÷39, 11 = ÷52. Default: 00 3 bits, c0...c2, Binary current setting factor for charge pumps, values 000 = minimum current to 111 = maximum current, default maximum charge pump current 2 bits, x0...x1, default 00, see Functional Description Second data word: (shown with default values) Sub Adr Address SA1638 DC Offset Register Status Reg Q-Channel Mode Select Register I-Channel MSB LSB a0 a1 a2 a3 sa s0 s1 q0 q1 q2 q3 i0 i1 i2 i3 t0 t1 t2 t3 t4 t5 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address: Sub:Address: Status Register: DC Offset Register: Mode Select Register: 1997 Sept 03 4 bits, a0...a3, fixed to 1110 1 bit, sa, fixed to 1 for second data word 2 bits, s0 sets pin AOUT; s1 sets pin BOUT, see Functional Description 4 bits per channel, i0...i3 and q0...q3, no correction as default i0 and q0 switches offset polarity, 0 to lower voltage, 1 to higher voltage il...i3 and q1...q3, 000 no correction to 111 max. correction enabled 6 bits, t0...t5, 000000 = normal GSM-Operation as default, see Functional Description 10 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 LSB DATA MSB X1 or t5 a1 X0 or t4 a0 tH tSU tSU 50% CLOCK FIRST CLOCK LAST CLOCK FIRST CLOCK tSU STROBE CLOCK ENABLED SHIFT IN DATA CLOCK DISABLED STORE DATA tW 50% CLOCK SR00527 STROBE Figure 4. Serial Input Timing Sequence L “1” CLKIN REFERENCE DIVIDER D Q C VCCCP R R P P-TYPE CHARGE PUMP “1” LOIN ÷2 MAIN DIVIDER D CP R C X N-TYPE CHARGE PUMP Q N VSS CLKIN L R X P N ICP SR00528 Figure 5. Phase Detector Structure with Timing 1997 Sept 03 11 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 PIN FUNCTIONS PIN PIN DC V No. MNEMONIC PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT EQUIVALENT CIRCUIT 5 47 VCCTxRx BG 3.0 2.5 6 10 1.2 RESD 10 0.05 — + 1 t5 35k 48 GNDREG1 0.0 47 11 25k RESA 0.00 RESB 0.05 11 40 43 46 48 1 VREG1 3.0 2 VREGF2 3.0 VREG2 3.0 3 40 43 46 5 BG 2.5 6 1.2 — + 4 GNDREG2 0.0 3 35k 12 2 5 PON 3.3 6 VBATT 3.3 7 AOUT 3.0 25k 4 12 40 43 46 7 13 PONRx 3.0 13 14 VREF 1.5 8 8 BOUT 3.0 14 9 9 DCRES 1.6 15 QRXOUT 1.5 16 QRXOUTX 1.5 17 IRXOUT 1.5 18 IRXOUTX 1.5 15, 17 16, 18 SR00529 Figure 6. Pin Functions 1997 Sept 03 12 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 PIN FUNCTIONS (continued) PIN PIN DC V No. MNEMONIC 19 QTXIN 1.5 20 QTXINX 1.5 21 ITXIN 1.5 22 ITXINX 1.5 0.0 24 VCCDIG 3.0 25 VEEDIG 3.0 26 DATA 27 CLOCK 28 STROBE 29 30 23 32 33 CLKINX ADJIN LOIN LOINX 36 VEECP 0.0 37 CP 38 VCCCP 3.0 39 PONPLL 3.0 40 GND3 0.0 35 37 39 41 41 TXIFOUTX 42 TXIFOUTX 43 GND2 0.0 44 RxIFINX 1.5 RxIFIN 1.5 42 2.0 31 2.0 2.0 45 32 44 45 VREF 46 GND1 0.0 47 VCCTxRx 3.0 48 GNDREG1 0.0 2.0 33 34 1.6 29 30 31 IREF 26, 27, 28 LOCK CLKIN 35 EQUIVALENT CIRCUIT OPEN COLLECTOR PdTx 19, 20, 21, 22 OPEN COLLECTOR 23 PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT 2.0 34 SR00530 Figure 7. Pin Functions (cont.) 1997 Sept 03 13 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 output power can be reduced to an appropriate level by choice of an external resistor. Overview of Dual GSM/PCN Architecture The SA1620 RF front-end and SA1638 IF transceivers form a dual conversion architecture which uses a common IF and standard I/Q baseband interface for both transmit and receive paths. The time division multiplex nature of the GSM system permits integration of the transmit and receive functions together on the one RF and one IF chips. This simplifies the distribution of local oscillator signals, maximizes circuitry commonality, and reduces power consumption. • DC offsets generated in the receive channel are independent of the LNA AGC setting, and correctable by software to prevent erosion of signal handling dynamic range by DC offsets. • Minimal high-quality filter requirements. As a result of the integration in the SA1638 of high quality channel selectivity filters, only sufficient filtering is needed in the receive path to provide blocking protection for the second mixers. This reduces receiver cost and size. The SA1620 and SA1638 allow considerable flexibility to optimize the transceiver design for particular price/size/performance requirements, through choice of appropriate RF and IF filters. The IF may be chosen freely in the range 70–400 MHz. The same IF can be used in the transmit and receive directions. Alternately, different IFs can be used if the SA1638 synthesizer frequency is switched between transmit and receive timeslots. The comparison frequency of the SA1638 PLL is high in order to provide fast switching time. • Operation at a high IF allows RF image reject filter requirements to be relaxed. For example, at a 400MHz IF, the natural gain roll-off in the SA1620 LNAs and mixer suppresses the image signal in the 1800MHz band by typically 28dB below the desired 900MHz band signal. DC Offset Correction With suitable choice of the IF, an identical SA1638 IF receiver design can be used for both 900MHz GSM and 1800MHz PCN (DCS1800) equipment. DC offset correction is provided by two DACs each feeding into one of the two Rx channels. The step size of both DACs is set by the value of the external resistor between DCRES and ground. Thus any original offset less than 1.5V magnitude in either channel can be reduced to the specified level by selecting the appropriate DAC setting via the serial interface. General Benefits/Advantages • 2.7V operation. Compatible with 3V digital technology and portable applications. (Higher voltage operation also possible, if desired.) Integrated Receive Filters • Excellent dynamic range. The low-pass characteristics of the Rx channel are determined by two low-pass responses. The first of these is a passive filter at the output of the quadrature mixers and the second is the low-pass filters which follow the post-mixer amplifiers. These specifications refer only to the response of the default state, but this may be switched by the control register to an alternative setting with a nominal 3dB point of 792kHz. The availability of two LNAs in the SA1620 allows flexibility in receiver dynamic design for portable and mobile GSM spec. applications with appropriate filters. If for a particular application a GaAs or discrete front-end is desired, one of the LNAs can be left unpowered. Placing the AGC gain switches at the front results in some attenuation most of the time, further increasing typical dynamic performance beyond that specified by GSM. The corner frequency of the low pass filters can be adjusted over a wide range by varying the value of the external resistor between RESA and RESB. The range of feasible corner frequencies extends at least between 50kHz and 500kHz. • High power transmit output driver, delivering +7.5dBm output. This is sufficient to drive a filter and power amplifier input, without a driver amplifier. To avoid unnecessary current consumption, the 1997 Sept 03 14 Philips Semiconductors Product specification Low voltage IF I/Q transceiver 1 SA1638 VREG1 GNDREG1 48 100nF 2 0–30mA 3 VREGF2 VCCTxRx GND1 VREG2 47 3V 46 4 0–30mA RxIFIN GNDREG2 5 RxIFINX PON 44 1800Ω 51.4Ω 2:1 6 GND2 VBATT 43 TxOUT 100nF 17.4Ω TC4–14 AOUT 7 BOUT 51.4Ω 1.8pF 1nF VBATT 2.5kΩ TC4–14 45 33nH PON RxIN 1.8pF 100nF 8 AOUT TxIFOUT BOUT TxIFOUTX 42 294Ω 41 294Ω 2:1 9 112kΩ 1MΩ 10 GND3 DCRES 40 1nF PONPLL 39 RESD PONPLL 100nF 1nF 22kΩ 11 VCCP 38 RESA VCCP RESB CP 2–3V 56kΩ 12 37 VCP 10nF PONRx 13 36 VEECP PONRx VREF 14 15 VREF IREF QRxOUT LOINX VCO 800MHz 35 34 10nF 4740Ω 17.4Ω 4.7nF 470pF LOIN 294Ω 16 10kΩ Rx OUT 17 + QRxOUTX LOIN 18 10nF 294Ω ADJIN 32 IRxOUT ADJIN 10kΩ – 33 IRxOUTX CLKIN 31 10nF 1nF 17.4Ω 10kΩ 49.9Ω 19 10kΩ QTxIN CLKINX 30 294Ω 294Ω 10nF I/Q 20 QTxINX LOCK CLKIN LOCK 29 GEN 2.7pF 21 DC - 1MHz ITxIN STROBE STROBE 28 10pF 22 ITxINX CLOCK CLOCK 27 SERIAL 10pF PD Tx 23 PDTx DATA 3-WIRE DATA 26 BUS 10pF 1nF VCC DIG 24 1nF VCC DIG VEE DIG 25 10nF SR00531 Figure 8. SA1638 Test Circuit 1997 Sept 03 15 1997 Sept 03 Rx: 890–915MHz Tx: 935–960MHz PA B A PCA5075 SERIAL POWER AMP INPUT CONTROLLER SSB MIXER LNA1 PD 16 PD LNA2 ATTENUATION CONTROL LOGIC POWER SUPPLY Tx/Rx SA1620 INTERFACE TO MICROCONTROLLER BUFFER LINEAR IF LEVEL CONTROL (SA8025, UMA1019) FREQUENCY SYNTHESIZER SAW 400MHz LO1 (1290–1360MHz) 400MHz LO2 800MHz Figure 9. SA1620 / SA1638 System Block Diagram CLKIN 13MHz ÷ ÷ INTERFACE TO MICROCONTROLLER ÷ VAR LPF SA1638 BOUT (to SA1620 ATTENUATION CONTROL LOGIC INPUTS) AOUT Q Q I I Q Q I I Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 SR00532 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 TYPICAL PERFORMANCE CHARACTERISTICS Regulator Dropout Voltage vs. Temperature and VBATT 5 Regulator Supply Current vs. Temperature and VBATT 7 7.5V 4.5 6.5 6 CURRENT (mA) VOLTAGE (V) 4 ILOAD=30mA 3.5 3 5.5V 2.5 2 1.5 No Load 5.5 5 4.5 3.3V 4 5.5V 7.5V 3.5 1 3 3.3V 0.5 -50 -40 -30 -20 -10 0 0 10 20 30 40 50 60 70 80 90 80 90 80 90 Temperature (°C) -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 90 Regulator Load Regulation vs. Temperature and VBATT Regulator Powerdown Supply Current vs. Temperature and VBATT 1 40 0.8 35 ILoad = 15mA to 30mA 7.5V 0.6 30 REGULATION (%) CURRENT ( µ A) 0.4 25 5.5V 20 15 3.3V 10 0.2 7.5V 0 5.5V -0.2 3.3V -0.4 -0.6 5 -0.8 -1 0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 -50 -40 -30 -20 -10 90 40 50 60 70 Regulator Output Voltage vs. Temperature and VBATT Regulator Line Regulation vs. Temperature and VBATT 3.15 0.4 3.3V 0.3 3.1 0.2 7.5V 0.1 5.5V 0 3.3V -0.1 VOLTAGE (V) ILOAD =15mA REGULATION (%) 0 10 20 30 Temperature (°C) 3.05 ILOAD =15ma 5.5V 7.5V 3 2.95 -0.2 2.9 -0.3 2.85 -0.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 -50 -40 -30 -20 -10 90 Temperature (°C) Figure 10. Typical Performance Characteristics 1997 Sept 03 17 0 10 20 30 Temperature (°C) 40 50 60 70 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Transmitter Output Second Harmonic Distortion Transmitter Input Modulation Bandwidth vs. Temperature and VCCTxRx -50 1050.0 Tx In = 1.5VP-P ITXIN=ITXINX=QTXIN=QTXINX=1.5Vpp 1000.0 950.0 900.0 850.0 SECOND HARMONIC LEVEL (dBc) FREQUENCY (kHz) 1100.0 2.7V 5.5V 4.0V 3.0V 800.0 -50 -30 -10 10 30 Temperature (°C) 50 70 90 Transmitter Output Third Harmonic vs. Temperature and VCCTxRx -55 4V 2.7V -60 3V 5.5V -65 -70 -50 0 TXIN=1.5VP-P -55 100 2.7V 3V 4V -60 50 Temperature (°C) Transmitter Output Fourth Harmonic Distortion 5.5V -60 -65 Tx In = 1.5VP-P -70 -50 -30 -10 10 30 Temperature (°C) 50 70 FOURTH HARMONIC LEVEL (dBc) DISTORTION LEVEL (dBc) -50 90 Transmitter Output Fifth Harmonic Distortion -60 -65 2.7V 3V 4V 5.5V -70 -75 FIFTH HARMONIC LEVEL (dBc) Tx In = 1.5VP-P 3V -65 -80 4V -50 0 50 Temperature (°C) 5.5V -70 -75 -80 -50 0 50 100 Temperature (°C) Figure 11. Typical Performance Characteristics (continued) 1997 Sept 03 18 100 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Transmitter RMS Output Current vs. Temperature and VCCTxRx -50 1.1 -52 1.05 -54 TXIFOUT=TXIFOUTX=VccTxRx–0.3V 1 2.7V -56 RMS CURRENT (mA) 5th HARMONIC DISTORTION LEVEL (dBc) Transmitter Output Saturation vs. Temperature and VccTxRx 3.0V -58 4.0V -60 -62 5.5V -64 -66 -68 IF=400MHz 0.95 0.9 5.5V 4.0V 3.0V 2.7V 0.85 0.8 0.75 0.7 0.65 -70 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0.6 90 -50 -40 -30 -20 -10 Temperature (°C) -38.0 SUPPRESSION (dBc) 2.3 CURRENT (mA) 30 40 50 60 70 80 90 -36.0 2.4 2.2 5.5V 4.0V 3.0V 1.9 20 Transmitter LO Suppression vs. Temperature and VccTxRx 2.5 2 10 Temperature (°C) Transmitter DC Output Current vs. Temperature and VCCTxRx 2.1 0 2.7V 1.8 -40.0 -42.0 5.5V 4.0V 3.0V 2.7V -44.0 -46.0 1.7 -48.0 1.6 -50.0 1.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 -50 -40 -30 -20 -10 Temperature (°C) 40 50 60 70 80 90 Transmit Noise Floor vs Temperature and Supply Voltage Transmitter Side Band Suppresion vs. VCCTxRx and Temperature -126 Baseband Input = 1.5VP-P differential, 30kHz -35 -127 -40 -128 OUTPUT NOISE (dBc/Hz) SUPPRESSION (dBc) 0 10 20 30 Temperature (°C) 5.5V -45 4.0V 3.0V -50 2.7V -55 -60 -65 -129 -130 -131 -132 -133 600kHz from Carrier 5.5V 4V 3V 2.7V 5.5V 4V 3V -134 2.7V 10MHz from Carrier -135 -70 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 90 -136 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) Figure 12. Typical Performance Characteristics (continued) 1997 Sept 03 19 40 50 60 70 80 90 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Transmitter Input Common Mode Range Vs. Supply Voltage Receiver 3dB Bandwidth vs. Temperature and VCCTxRx 0 100.0 90.0 2.7V 3.0V FREQUENCY (kHz) 5th HARMONIC dBc 2.7V T = +25°C -20 5.5V 4.0V -40 80.0 3.0V 4.0V 70.0 5.5V 60.0 -60 50.0 -80 40.0 0 1 2 3 4 5 6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) COMMON MODE VOLTAGE Receiver NF vs Temperature and Supply Voltage Receiver Gain vs. Temperature and VCCTxRx 16 60.0 5.5V 58.0 54.0 12 2.7V 2.7V 52.0 10 NF (dB) GAIN (dB) 56.0 Relative to 1200Ω source resistance 14 IF=400.005MHz, LO=400MHz 4.0V 3.0V 50.0 48.0 46.0 8 3V 5.5V 4V 6 44.0 4 42.0 40.0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 2 90 0 -50 -40 -30 -20 -10 Receiver Gain match vs VCCTxRx and Temperature 5 0.6 4 0.4 3 Φ ERROR (o) MATCH (dB) 0.8 0.2 0 -0.2 40 50 60 70 80 90 80 90 Receiver Channel Matching Phase Error vs. Temperature and VCCTxRx 1 5.5V 3.0V 4.0V 0 10 20 30 Temperature (°C) -0.4 2 1 0 -1 5.5V 2.7V 3.0V 4.0V -2 2.7V -0.6 -3 -0.8 -4 -1 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 -5 90 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) Figure 13. Typical Performance Characteristics (continued) 1997 Sept 03 20 40 50 60 70 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Receiver Corrected Output Offset Voltage vs. Temperature and VCCTxRx Receiver In–band 1dB Compression Point vs. Temperature and VCCTxRx 200 -47.0 DCRes Resistor=100k 150 -49.0 5.5V 50 LEVEL (dBm) OFFSET (mV) 100 4.0V 2.7V 3.0V 0 -50 -51.0 5.5V -53.0 -55.0 -100 3.0V 4.0V 2.7V -57.0 -150 -200 -59.0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 90 -50 -40 -30 -20 -10 SA1638 Receiver QRXOUT Voltage 0 10 20 30 Temperature (°C) 40 50 60 70 Reference Voltage 1.8 1.8 5.5V 5.5V 1.75 1.7 4V VREF (V) PIN 15 DC VOLTAGE (V) 1.7 1.6 1.65 4V 1.6 3V 3V 1.55 1.5 2.7V 2.7V 1.5 1.4 1.45 -50 0 50 TEMPERATURE (°C) -50 100 0 50 TEMPERATURE (°C) 100 LOIN Maximum Frequency Div800 Receiver IP2 vs Temperature and Supply Voltage 1100 5.00 4.00 VLOIN = 100mVPEAK 3.00 1050 3V 3V FREQUENCY (MHz) IP2 (dBm) 2.00 1.00 0 -1.00 5.5V 4V 2.7V -2.00 2.7V 1000 4V 950 5.5V -3.00 -4.00 900 -5.00 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 -50 90 0 50 TEMPERATURE (°C) Figure 14. Typical Performance Characteristics (continued) 1997 Sept 03 21 100 80 90 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 TYPICAL PERFORMANCE CHARACTERISTICS (continued) CLKIN Maximum Frequency Div52 N Charge Pump Output Current 000 250 -495 2.7V 2.7V 3V -500 3V -505 4V CURRENT ( µ A) FREQUENCY (MHz) 225 200 175 VCLKIN = 100mVPEAK 4V -510 -515 5.5V -520 5.5V 150 -50 0 50 TEMPERATURE (°C) -525 100 -50 0 50 TEMPERATURE (°C) P Charge Pump Output Current 111 100 N Charge Pump Relative Output Variation -1000 1.25 2.7V 5.5V -1010 3V -1020 VARIATION (%) CURRENT ( µ A) 1 4V -1030 -1040 0.75 0.5 4V 5.5V 3V 0.25 -1050 2.7V -1060 0 -50 0 50 TEMPERATURE (°C) 100 -50 Charge Pump Match Current 111 0 50 TEMPERATURE (°C) 100 Charge Pump Output Leakage Current 0.25 -20 2.7V 2.7V 3V 0 CURRENT (nA) CURRENT ( µ A) -30 4V -40 3V 4V -0.25 5.5V -0.5 -50 5.5V -0.75 -60 -50 0 50 TEMPERATURE (°C) -50 100 0 50 TEMPERATURE (°C) Figure 15. Typical Performance Characteristics (continued) 1997 Sept 03 22 100 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Transmitter Supply Current vs. Temperature and VCCTxRx Receiver Supply Current vs. Temperature and VCCTxRx 26 20 24 19 18 5.5V 20 4.0V 18 3.0V 2.7V 16 5.5V 17 CURRENT (mA) CURRENT (mA) 22 14 16 4.0V 15 3.0V 14 2.7V 13 12 12 11 10 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 90 10 -50 -40 -30 -20 -10 Power Down Supply Current vs. Temperature and VCCTxRx 40 50 60 70 80 90 Receiver Uncorrected Output Offset Voltage vs Temperature and VCCTxRx 270 160 DCRES = 100kΩ 140 265 5.5V 120 100 VOLTAGE (mV) CURRENT ( µ A) 0 10 20 30 Temperature (°C) 4.0V 80 3.0V 60 2.7V 260 255 250 40 245 20 0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (°C) 40 50 60 70 80 5.5V 4.0V 3.0V 2.7V 240 -50 90 -30 Receiver Output Offset Control Step Size vs Temperature and VCCTxRx 10 30 TEMPERATURE (°C) 50 70 90 Receiver Output Offset Control Step Size vs Temperature and VCCTxRx 37 330 320 5.5V 4.0V 3.0V 310 2.7V DCRES = 100kΩ 36 VOLTAGE (mV) VOLTAGE (mV) -10 300 34 5.5V 4.0V 3.0V 2.7V 33 290 280 -50 35 DCRES = 1MΩ -30 -10 10 30 TEMPERATURE (°C) 50 70 32 -50 90 -30 -10 10 30 TEMPERATURE (°C) Figure 16. Typical Performance Characteristics (continued) 1997 Sept 03 23 50 70 90 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm 1997 Sept 03 24 SOT313-2 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 NOTES 1997 Sept 03 25 Philips Semiconductors Product specification Low voltage IF I/Q transceiver SA1638 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 08-98 Document order number: 1997 Sept 03 26 9397 750 06847