5-Bit, Programmable, Single-Phase, Synchronous Buck Controller

ADP3209D
5-Bit, Programmable,
Single-Phase, Synchronous
Buck Controller
The ADP3209D is a highly efficient, single−phase, synchronous
buck switching regulator controller. With its integrated drivers, the
ADP3209D is optimized for converting the notebook battery voltage
to render the supply voltage required by high performance Intel
chipsets. An internal 5−bit DAC is used to read a VID code directly
from the chipset and to set the GMCH core voltage to a value within
the range of 0.4 V to 1.25 V.
The ADP3209D uses a multi−mode architecture. It provides
programmable switching frequency that can be optimized for
efficiency depending on the output current requirement. In addition,
the ADP3209D includes a programmable load line slope function to
adjust the output voltage as a function of the load current so that the
core voltage is always optimally positioned for a load transient. The
ADP3209D also provides accurate and reliable current overload
protection and a delayed power−good output. The IC supports
On−The−Fly (OTF) output voltage changes requested by the chipset.
The ADP3209D is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 32−lead
LFCSP.
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LFCSP32
CASE 932AE
MARKING DIAGRAM
ADP3209D
AWLYYWWG
A
WL
YYWW
G
Features
• Single−Chip Solution
• Fully Compatible with the Intel® GMCH Chipset Voltage Regulator
Applications
VID3
VID4
VID2
VID1
VID0
EN
VARFREQ
PWRGD
25
24
COMP
DRVH
ADP3209D
CREF
SW
(top view)
NC
PVCC
DRVL
IMON
PGND
IREF
9
GND
RT
17
16
ILIMP
8
ILMIN
RPM
VCC
BST
FB
RAMP
•
•
•
•
•
32
CSFB
•
1
CSREF
•
•
FBRTN
LLINE
•
PIN ASSIGNMENT
CSCOMP
•
•
•
Specifications
Integrated MOSFET Drivers
Input Voltage Range of 3.3 V to 22 V
±8 mV Worst−Case Differentially Sensed Core Voltage Error
Overtemperature
Automatic Power−Saving Modes Maximize Efficiency During Light
Load Operation
Soft Transient Control Reduces Inrush Current and Audio Noise
Independent Current Limit and Load Line Setting Inputs for
Additional Design Flexibility
Built−In Power−Good Masking Supports Voltage Identification
(VID) OTF Transients
5−Bit, Digitally Programmable DAC with 0.4 V to 1.25 V Output
Short−Circuit Protection with Latchoff Delay
Output Current Monitor
32−Lead LFCSP
This is a Pb−Free Device
= Assembly Location
= Wafer Lot
= Date Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 26 of this data sheet.
• Notebook Power Supplies for Next−Generation Intel Chipsets
© Semiconductor Components Industries, LLC, 2010
March, 2010 − Rev. 0
1
Publication Order Number:
ADP3209D/D
ADP3209D
GND
VCC EN
RPM RT RAMP
BST
UVLO
Shutdown
and Bias
COMP
+
REF
LLINE
+
Σ
_
1.7 V
DRVH
Driver
Logic
VEA
−
+
CSREF
+
Σ
Oscillator
SW
PVCC
DRVL
−
+
FB
VARFREQ
PGND
OVP
DAC + 200mV
OCP
Shutdown
Delay
−
+
CSREF
−
+
DAC − 300mV
FBRTN
PWRGD
Startup
Delay
PWRGD
Open
Drain
Soft
Transient
Delay
Precision
Reference
DAC
VID0
VID2
VID1
VID3
IMON
+
−
CSREF
CSFB
CSCOMP
Delay
Disable
VID
DAC
VID4
Current
Monitor
ILIM
REF
Soft−Start
IREF
PWRGD
Current
Limit
Circuit
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
VCC
−0.3 to +6.0
V
FBRTN, PGND
−0.3 to +0.3
V
BST
DC
t < 200 ns
−0.3 to +28
−0.3 to +33
BST to SW
−0.3 to +6.0
SW
DC
t < 200 ns
−5 to +22
−10 to +28
DRVH to SW
DC
−0.3 to +6.0
DRVL to PGND
DC
t < 200 ns
−0.3 to +6.0
−0.3 to +6.0
−5.0 to +6.0
V
RAMP (in Shutdown)
−0.3 to +22
V
All Other Inputs and Outputs
−0.3 to +6.0
V
Storage Temperature
−65 to +150
°C
0 to 100
°C
Operating Junction Temperature
125
°C
Thermal Impedance (θJA) 2−Layer Board
32.6
°C/W
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
300
260
Operating Ambient Temperature Range
V
V
V
V
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
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2
ADP3209D
PIN FUNCTION DESCRIPTIONS
Pin No
Mnemonic
1
FBRTN
Description
2
FB
3
COMP
Voltage Error Amplifier Output and Frequency Compensation Point.
4
CREF
This pins sets the internal bias currents. Connect an 80kW resistor from either this pin or IREF pin to
ground. If an 80 kW resistor is connected from this pin to ground, IREF pin must remain floating.
5
NC
6
IMON
Current Monitor Output. Open−drain output. This pin sources a current proportional to the output load
current. A resistor from IMON to FBRTN sets the current monitor gain.
7
IREF
This pins sets the internal bias currents. Connect an 80 kW resistor from either this pin or CREF pin to
ground. If an 80 kW resistor is connected from this pin to ground, CREF pin must remain floating.
8
RPM
RPM Mode Timing Control Input. An external resistor between this pin to ground sets the RPM mode
turn−on threshold voltage.
9
LLINE
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP can be tied to this pin to set the load line slope.
10
CSCOMP
11
CSREF
Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor.
12
CSFB
Non−inverting Input of the Current Sense Amplifier. The combination of a resistor from the switch node
to this pin and the feedback network from this pin to the CSCOMP pin sets the gain of the current
sense amplifier.
13
RAMP
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin
sets the slope of the internal PWM stabilizing ramp.
14
ILIMN
Current Limit Set Point. An external resistor between ILIMN and ILIMP sets the current limit set point.
15
ILIMP
Current Limit Set Point. An external resistor between ILIMN and ILIMP sets the current limit set point.
16
RT
17
GND
18
PGND
Low−Side Driver Power Ground. This pin should be connected close to the source of the lower
MOSFET(s).
19
DRVL
Low−Side Gate Drive Output.
20
PVCC
Power Supply Input/Output of Low−Side Gate Driver.
21
SW
22
DRVH
23
BST
High−Side Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while the
high−side MOSFET is on.
24
VCC
Power Supply Input/Output of the Controller.
25 to 29
VID4 to VID0
30
EN
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low.
31
PWRGD
Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of
the VID DAC defined range.
32
VARFREQ
Variable Frequency Enable Input. Pulling this pin to ground sets the normal RPM mode of operation.
Pulling this pin to 5.0 V sets the fixed−frequency PWM mode of operation.
Feedback Return Input/Output. This pin remotely senses the GMCH voltage. It is also used as the
ground return for the VID DAC and the voltage error amplifier blocks.
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Not Connected.
Current Sense Amplifier Output and Frequency Compensation Point.
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM
oscillator frequency.
Analog and Digital Signal Ground.
Current Return For High−Side Gate Drive.
High−Side Gate Drive Output.
Voltage Identification DAC Inputs. A 5−bit word (the VID code) programs the DAC output voltage, the
reference voltage of the voltage error amplifier without a load (see the VID code table, Table 1). In
normal operation mode, the VID DAC output programs the output voltage to a value within the 0 V to
1.25 V range. The input is actively pulled down.
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3
ADP3209D
ELECTRICAL CHARACTERISTICS VCC = 5.0V, FBRTN = GND, VARFREQ = Low, VVID = 1.25 V, TA = −10°C to 100°C, unless
otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP)
FB, LLINE Voltage
Range (Note 2)
VFB, VLLINE
Relative to CSREF = VDAC
−200
+200
mV
FB, LLINE Offset
Voltage (Note 2)
VOSVEA
Relative to CSREF = VDAC
−0.5
+0.5
mV
FB Bias Current
(Note 2)
IFB
−1.0
+1.0
mA
LLINE Bias Current
ILL
−50
+50
nA
−82
mV
4.0
V
LLINE Positioning
Accuracy
VFB − VVID
Measured on FB relative to VVID, LLINE forced 80
mV below CSREF
−78
−80
COMP Voltage Range
(Note 2)
VCOMP
COMP Current
ICOMP
COMP = 2.0 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
SRCOMP
CCOMP = 10 pF, CSREF = VDAC,
Open loop configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
15
−20
Non−inverting unit gain configuration, RFB = 1 kW
20
COMP Slew Rate
Gain Bandwidth
(Note 2)
GBW
0.85
mA
−0.75
3.0
V/ms
MHz
VID DAC VOLTAGE REFERENCE
VDAC Voltage Range
(Note 3)
VDAC Accuracy
See VID Code Table
VFB − VVID
Measured on FB (includes offset), relative to VVID,
for VID table see Table 1, TA = −10°C to 85°C
VDAC Differential Non−linearity (Note 2)
VDAC Line Regulation
Soft−Start Delay
(Note 2)
DVFB
tSS
VDAC Slew Rate
FBRTN Current
0
1.5
−6.0
+6.0
−1.0
+1.0
V
mV
LSB
VCC = 4.75 V to 5.25 V
0.05
%
Measured from EN pos edge to FB = 1.25 V
within 5%
1.8
ms
0.0312
5.0
0.5
LSB/ms
Soft−Start
Non−LSB VID step
IFBRTN
70
200
mA
VOLTAGE MONITORING AND PROTECTION − Power Good
CSREF Undervoltage
Threshold
VUVCSREF
Relative to nominal DAC Voltage
−360
−300
−240
mV
CSREF Overvoltage
Threshold
VOVCSREF
Relative to nominal DAC Voltage
80
200
250
mV
CSREF Crowbar
Voltage Threshold
(Note 2)
VCBCSREF
Relative to FBRTN
1.57
1.7
1.78
V
CSREF Reverse
Voltage Threshold
VRVCSREF
Relative to FBRTN, Latchoff mode:
CSREF Falling
CSREF Rising
−350
−300
−75
−5.0
50
150
mV
0.1
mA
PWRGD Low Voltage
VPWRGD
IPWRGD(SINK) = 4 mA
PWRGD High, Leakage
Current
IPWRGD
VPWRDG = 5.0 V
PWRGD Startup Delay
TSSPWRGD
Measured from EN pos edge to PWRGD pos edge
2.0
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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4
mV
ms
ADP3209D
ELECTRICAL CHARACTERISTICS VCC = 5.0V, FBRTN = GND, VARFREQ = Low, VVID = 1.25 V, TA = −10°C to 100°C, unless
otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOLTAGE MONITORING AND PROTECTION − Power Good
PWRGD Latchoff Delay
TLOFFPWRGD
Measured from Out−off−Good−Window event to
Latchoff (switching stops)
8.0
ms
TPDPWRGD
Measured from Out−off−Good−Window event to
PWRGD neg edge
200
ns
Measured from Crowbar event to Latchoff
(switching stops)
200
ns
PWRGD Masking Time
Triggered by any VID change or OCP event
100
ms
CSREF Soft−Stop
Resistance
EN = L or Latchoff condition
70
W
PWRGD Propagation
Delay (Note 3)
Crowbar Latchoff Delay
(Note 2)
TLOFFCB
CURRENT CONTROL − Current Sense Amplifier (CSAMP)
CSSUM, CSREF
Common−Mode Range
(Note 2)
Voltage range of interest
CSREF − CSSUM, TA = 25°C
TA = −10°C to 85°C
0
2.0
V
−0.5
−1.6
+0.5
+1.6
mV
CSSUM, CSREF Offset
Voltage
VOSCSA
CSSUM Bias Current
IBCSSUM
−50
+50
nA
CSREF Bias Current
IBCSREF
−2.0
+2.0
mA
0.05
2.0
V
CSCOMP Voltage Range (Note 2)
Voltage range of interest
CSCOMP Current
CSCOMP = 2.0 V
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
−470
1.0
CCSCOMP = 10 pF
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
10
−10
Non−inverting unit gain configuration, RFB = 1 kW
20
ICSCOMPsource
ICSCOMPsink
CSCOMP Slew Rate
Gain Bandwidth
(Note 2)
GBWCSA
mA
mA
V/ms
MHz
CURRENT MONITORING AND PROTECTION
Current Reference
IREF Voltage
Current Limiter (OCP)
Current Limit Threshold
VREF
VLIMTH
Current Limit Latchoff
Delay
Current Monitor
Current Gain Accuracy
IMON Clamp Voltage
RREF = 80 kW to set IREF = 20 mA
1.55
1.6
1.65
Measured from CSCOMP to CSREF, RLIM = 4.5 kW
−70
−90
−110
Measured from OCP event to PWRGD
de−assertion
2.0
IMON/ILIM
Measured from ILIMP to IMON
ILIM = −20 mA
ILIM = −10 mA
ILIM = −5 mA
9.4
9.2
9.0
VMAXMON
Relative to FBRTN
1.0
10
10
10
V
mV
ms
10.7
11.0
11.3
1.15
V
1.17
5.0
V
PULSE WIDTH MODULATOR − Clock Oscillator
RT Voltage
VRT
VARFREQ = Low, RT = 120 kW,
VVID = 1.2500 V
VARFREQ = High
See also VRT(VVID) formula
1.07
5.0
0.95
PWM Clock Frequency
Range (Note 2)
fCLK
Operation of interest
0.3
PWM Clock Frequency
fCLK
TA = +25°C, VVID = 1.2000 V
RT = 73 kW (Note 2)
RT = 125 kW
RT = 180 kW (Note 2)
970
705
500
1.125
1.0
1.05
3.0
1270
830
600
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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5
157
0
955
750
MHz
kHz
ADP3209D
ELECTRICAL CHARACTERISTICS VCC = 5.0V, FBRTN = GND, VARFREQ = Low, VVID = 1.25 V, TA = −10°C to 100°C, unless
otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.0
VIN
1.1
V
RAMP GENERATOR
RAMP Voltage
VRAMP
EN = high, IRAMP = 30 mA
EN = low
0.9
RAMP Current Range
(Note 2)
IRAMP
EN = high
EN = low, RAMP = 19 V
1.0
−0.1
100
+0.1
mA
VRAMP − VCOMP
−3.0
+3.0
mV
PWM COMPARATOR
PWM Comparator
Offset (Note 2)
VOSRPM
RPM COMPARATOR
RPM Current
RPM Comparator Offset
(Note 2)
IRPM
VOSRPM
−6.0
VVID = 1.2 V, RT = 180 kW, VARFREQ = Low,
See also IRPM(RT) formula
mA
VCOMP − (1 +VRPM)
−3.0
3.0
mV
Operating Range for current sensing
−600
+200
mV
SWITCH AMPLIFIER
SW Common Mode
Range (Note 2)
SW Resistance
VSW(X)CM
RSW(X)
Measured from SW to PGND
1.5
kW
−6.0
mV
600
ns
ZERO CURRENT SWITCHING COMPARATOR
SW ZCS Threshold
VDCM(SW1)
Masked Off Time
tOFFMSKD
Measured from DRVH neg edge to DRVH pos
edge at max frequency of operation
SYSTEM I/O BUFFERS VID[4:0] INPUTS
Input Voltage
Refers to driving signal level:
Logic low, Isink w 1 mA
Logic high, Isource v −5 mA
Input Current
V = 0.2 V, VID[4:0] (active pulldown to GND)
VID Delay Time (Note 2)
Any VID edge to FB change 10%
0.3
1.7
−1.0
V
mA
200
ns
VARFREQ
Input Voltage
Refers to driving signal level:
Logic low, Isink w 1 mA
Logic high, Isource v −5 mA
0.3
4.0
Input Current
−1.0
V
mA
EN INPUT
Input Voltage
Refers to driving signal level:
Logic low, Isink w 1 mA
Logic high, Isource v −5 mA
Input Current
0.3
1.6
EN = L or EN = H (Static)
0.8 V < EN < 1.6 V (During Transition)
10
70
V
nA
mA
SUPPLY
Supply Voltage Range
VCC
Supply Current
VCC OK Threshold
VCC UVLO Threshold
4.5
EN = H
EN = 0 V
VCCOK
VCC is Rising
VCCUVLO
VCC is Falling
4.0
VCC Hysteresis (Note 2)
5.5
V
5.0
60
8.0
150
mA
mA
4.4
4.5
V
4.15
V
250
mV
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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ADP3209D
ELECTRICAL CHARACTERISTICS VCC = 5.0V, FBRTN = GND, VARFREQ = Low, VVID = 1.25 V, TA = −10°C to 100°C, unless
otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
HIGH−SIDE MOSFET DRIVER
Pullup Resistance,
Sourcing Current
BST = PVCC
1.8
3.3
W
Pulldown Resistance,
Sinking Current
BST = PVCC
1.0
3.0
W
BST = PVCC, CL = 3 nF, Figure 2
BST = PVCC, CL = 3 nF, Figure 2
15
13
35
31
ns
BST = PVCC, Figure 2
30
42
ns
EN = L (Shutdown)
EN = H, no switching
2.0
200
12
mA
Pullup Resistance,
Sourcing Current
BST = PVCC
1.7
3.3
W
Pulldown Resistance,
Sinking Current
BST = PVCC
0.8
2.0
W
trDRVL
tfDRVL
CL = 3 nF, Figure 2
CL = 3 nF, Figure 2
15
14
35
35
ns
tpdhDRVL
CL = 3 nF, Figure 2
10
30
ns
250
350
ns
Transition Times
trDRVH
tfDRVH
Dead Delay Times
tpdhDRVH
BST Quiescent Current
LOW−SIDE MOSFET DRIVER
Transition Times
Progation Delay Times
SW Transition Timeout
tTOSW
SW Off Threshold
DRVH = L, SW = 2.5 V
150
VOFFSW
PVCC Quiescent
Current
1.6
EN = L (Shutdown)
EN = H, no switching
V
5.0
240
15
mA
6.0
1.0
W
BOOTSTRAP RECTIFIER SWITCH
On Resistance
EN = L or EN = H and DRVL = H
3.0
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Timing is referenced to the 90% and 10% points, unless otherwise noted.
IN
tpdlDRVL
tfDRVL
tpdlDRVH
trDRVL
DRVL
tfDRVH
tpdhDRVH
DRVH
(WITH RESPECT TO SW)
trDRVH
VTH
VTH
tpdhDRVL
1.0 V
SW
Figure 2. Timing Diagram (Note 3)
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ADP3209D
TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.
40
OUTPUT
RIPPLE
350
70
SWITCHING
FREQUENCY
300
250
60
50
OUTPUT
RIPPLE
200
40
150
SWITCHING FREQUENCY (kHz)
80
OUTPUT RIPPLE (mV)
SWITCHING FREQUENCY (kHz)
400
425
30
400
20
SWITCHING
FREQUENCY
375
10
30
INPUT = 12 V
LOAD = 10 A
100
0.25
450
90
0.5
0.75
1
1.25
OUTPUT RIPPLE (mV)
450
OUTPUT = 1.2 V
LOAD = 10 A
350
20
0
5
1.5
10
OUTPUT VOLTAGE (V)
15
20
INPUT VOLTAGE (kHz)
Figure 3. Switching Frequency vs. Load Current
in RPM Mode
Figure 4. Switching Frequency vs. Input Voltage
in RPM Mode
1.3
OUTPUT VOLTAGE (V)
1.28
MEASURED LOAD LINE
1.26
+2%
1.24
1.22
1.2
−2%
1.18
1.16
1.14
0
5
10
15
LOAD CURRENT (A)
Figure 5. Switching Frequency vs. Input Voltage
in RPM Mode
Figure 6. Load Line Accuracy
OUTPUT VOLTAGE
OUTPUT VOLTAGE
INDUCTOR
CURRENT
INDUCTOR
CURRENT
LOW SIDE
GATE
LOW SIDE GATE
SWITCH
NODE
SWITCH NODE
Figure 7. DCM Waveforms, 0.5 A Load Current
Figure 8. CCM Waveforms, 3 A Load Current
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8
ADP3209D
TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.
OUTPUT VOLTAGE
OUTPUT VOLTAGE
SWITCH
NODE
Figure 9. Load Transient, 3 A to 10 A, VIN = 12 V
Figure 10. Load Transient, 3 A to 10 A, VIN = 12 V
OUTPUT VOLTAGE
OUTPUT VOLTAGE
SWITCH
NODE
VID0
Figure 11. Load Transient, 3 A to 10 A, VIN = 12 V
Figure 12. VID OTF, 1.25 V to 0.85 V
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9
ADP3209D
Theory of Operation
Operation Modes
The ADP3209D is a ramp−pulse−modulated (RPM)
controller for synchronous buck Intel GMCH core power
supply. The internal 5−bit VID DAC conforms to the Intel
IMVP−6+ specifications. The ADP3209D is a stable, high
performance architecture that includes
• High speed response at the lowest possible switching
frequency and minimal count of output decoupling
capacitors
• Minimized thermal switching losses due to lower
frequency operation
• High accuracy load line regulation
• High power conversion efficiency with a light load by
automatically switching to DCM operation
The ADP3209D runs in RPM mode for the purpose of fast
transient response and high light load efficiency. During the
following transients, the ADP3209D runs in PWM mode:
• Soft−Start
• Soft transient: the period of 100 ms following any VID
change
• Current overload
5.0 V
VRMP
FLIP−FLOP
IR = AR y IRAMP
S
Q
BST1
GATE DRIVER
BST
DRVH
RD
CR
FLIP−FLOP
400 ns
1.0 V
IN
SW
DCM
DRVL
Q
S
Q
VCC
RI
DRVH1
LOAD
DRVL1
Q
RD
R2
R1
R2
30 mV
R1
1.0 V
VDC
CSREF
+–
+
–
VCS
+
COMP
+
FBRTN
FB
LLINE
CSCOMP
CSSUM
RCS
CA
RA
CFB
CB
CCS
RB
Figure 13. RPM Mode Operation
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10
L
SW1
RPH
ADP3209D
5.0 V
BST1
GATE DRIVER
IR = A R y I RAMP
BST
DRVH
FLIP−FLOP
CLOCK
OSCILLATOR
S
Q
SW
IN
DRVL
RD
CR
VCC
DRVH1
RI
L
SW1
DRVL1
LOAD
AD
0.2 V
VCC
VDC
+ć
CSREF
–
+ V
CS
RAMP
+
COMP
+
FBRTN
FB
CSCOMP
LLINE
CSSUM
R CS
CA
RA
CFB
CB
RPH
C CS
RB
Figure 14. PWM Mode Operation
Setting Switch Frequency
Differential Sensing of Output Voltage
The ADP3209D combines differential sensing with a high
accuracy VID DAC, referenced by a precision band gap
source and a low offset error amplifier, to meet the rigorous
accuracy requirement of the Intel IMVP−6+ specification.
In steady−state mode, the combination of the VID DAC and
error amplifier maintain the output voltage for a worst−case
scenario within ±8 mV of the full operating output voltage
and temperature range.
The VCCGFX output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to
the positive regulation point; the VCC remote sensing pin of
the GMCH. FBRTN should be connected directly to the
negative remote sensing point; the VSS sensing point of the
GMCH. The internal VID DAC and precision voltage
reference are referenced to FBRTN and have a typical current
of 200 mA for guaranteed accurate remote sensing.
Master Clock Frequency in PWM Mode
When the ADP3209D runs in PWM, the clock frequency
is set by an external resistor connected from the RT pin to
GND. The frequency varies with the VID voltage: the lower
the VID voltage, the lower the clock frequency. The
variation of clock frequency with VID voltage maintains
constant VCGFX ripple and improves power conversion
efficiency at lower VID voltages.
Switching Frequency in RPM Mode
When the ADP3209D operates in RPM mode, its switching
frequency is controlled by the ripple voltage on the COMP
pin. Each time the COMP pin voltage exceeds the RPM pin
voltage threshold level determined by the VID voltage and
the external resistor connected between RPM and GND, an
internal ramp signal is started and DRVH is driven high. The
slew rate of the internal ramp is programmed by the current
entering the RAMP pin. One−third of the RAMP current
charges an internal ramp capacitor (5 pF typical) and creates
a ramp. When the internal ramp signal intercepts the COMP
voltage, the DRVH pin is reset low.
In continuous current mode, the switching frequency of
RPM operation is almost constant. While in discontinuous
current conduction mode, the switching frequency is
reduced as a function of the load current.
Output Current Sensing
The ADP3209D includes a dedicated current sense
amplifier (CSA) to monitor the total output current of the
converter for proper voltage positioning vs. load current and
for overcurrent detection. Sensing the current delivered to
the load is an inherently more accurate method than
detecting peak current or sampling the current across a sense
element, such as the low−side MOSFET. The current sense
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11
ADP3209D
amplifier can be configured several ways, depending on
system optimization objectives, and the current information
can be obtained by:
• Output inductor ESR sensing without the use of a
thermistor for the lowest cost
• Output inductor ESR sensing with the use of a
thermistor that tracks inductor temperature to improve
accuracy
• Discrete resistor sensing for the highest accuracy
At the positive input of the CSA, the CSREF pin is
connected to the output voltage. At the negative input (that
is, the CSFB pin of the CSA), signals from the sensing
element (in the case of inductor DCR sensing, signals from
the switch node side of the output inductors) are connected
with a resistor. The feedback resistor between the CSCOMP
and CSFB pins sets the gain of the current sense amplifier,
and a filter capacitor is placed in parallel with this resistor.
The current information is then given as the voltage
difference between the CSCOMP and CSREF pins. This
signal is used internally as a differential input for the current
limit comparator.
An additional resistor divider connected between the
CSCOMP and CSREF pins with the midpoint connected to
the LLINE pin can be used to set the load line required by
the GMCH specification. The current information to set the
load line is then given as the voltage difference between the
LLINE and CSREF pins. This configuration allows the load
line slope to be set independent from the current limit
threshold. If the current limit threshold and load line do not
have to be set independently, the resistor divider between the
CSCOMP and CSREF pins can be omitted and the
CSCOMP pin can be connected directly to LLINE. To
disable voltage positioning entirely (that is, to set no load
line), LLINE should be tied to CSREF.
To provide the best accuracy for current sensing, the CSA
has a low offset input voltage and the sensing gain is set by
an external resistor ratio.
droop voltage as a function of current, commonly known as
active voltage positioning. The output of the error amplifier
is the COMP pin, which sets the termination voltage of the
internal PWM ramps.
At the negative input, the FB pin is tied to the output sense
location using RB, a resistor for sensing and controlling the
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
Power−Good Monitoring
The power−good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open−drain
output that can be pulled up through an external resistor to
a voltage rail; not necessarily the same VCC voltage rail that
is running the controller. A logic high level indicates that the
output voltage is within the voltage limits defined by a range
around the VID voltage setting. PWRGD goes low when the
output voltage is outside of this range.
Following the GMCH specification, the PWRGD range is
defined to be 300 mV less than and 200 mV greater than the
actual VID DAC output voltage. To prevent a false alarm,
the power−good circuit is masked during any VID change
and during soft−start. The duration of the PWRGD mask is
set to approximately 100 ms by an internal timer.
Power−Up Sequence and Soft Start
The power−on ramp−up time of the output voltage is set
internally. The ADP3209D steps sequentially through each
VID code until it reaches the set VID code voltage. The
power−up sequence, including the soft−start is illustrated in
Figure 15.
V5_S
GFXCORE_EN
Active Impedance Control Mode
VCCGFX
To control the dynamic output voltage droop as a function
of the output current, the signal that is proportional to the
total output current, converted from the voltage difference
between LLINE and CSREF, can be scaled to be equal to the
required droop voltage. This droop voltage is calculated by
multiplying the droop impedance of the regulator by the
output current. This value is used as the control voltage of
the PWM regulator. The droop voltage is subtracted from the
DAC reference output voltage, and the resulting voltage is
used as the voltage positioning set−point. The arrangement
results in an enhanced feed−forward response.
100 mV/μ s
PWRGD
PGDELAY
Figure 15. Powerup Sequence of ADP3209D
VID Change and Soft Transient
When a VID input changes, the ADP3209D detects the
change but ignores new code for a minimum of 400 ns. This
delay is required to prevent the device from reacting to digital
signal skew while the 5−bit VID input code is in transition.
Additionally, the VID change triggers a PWRGD masking
timer to prevent a PWRGD failure. Each VID change resets
and retriggers the internal PWRGD masking timer.
Voltage Control Mode
A high−gain bandwidth error amplifier is used for the
voltage mode control loop. The non−inverting input voltage
is set via the 5−bit VID DAC. The VID codes are listed in
Table 1. The non−inverting input voltage is offset by the
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ADP3209D
The ADP3209D provides a soft transient function to
reduce inrush current during VID transitions. Reducing the
inrush current helps decrease the acoustic noise generated
by the MLCC input capacitors and inductors.
The soft transient feature is implemented internally. When
a new VID code is detected, the ADP3209D steps sequentially
through each VID voltage to the final VID voltage. The
ADP3209D steps through VID codes every 0.5 ms. This gives
a soft transient slew rate of 25 mV per 0.5 ms or 12.5 mV/ms.
There is a PWRGD masking time of 100ms after the last VID
code is changed internally.
With lighter loads, the ADP3209D enters discontinuous
conduction mode (DCM). Figure NO TAG shows a typical
single−phase buck with one upper FET, one lower FET, an
output inductor, an output capacitor, and a load resistor.
Figure 18 shows the path of the inductor current with the
upper FET on and the lower FET off. In Figure 19 the
high−side FET is off and the low−side FET is on. In CCM,
if one FET is on, its complementary FET must be off;
however, in DCM, both high− and low−side FETs are off and
no current flows into the inductor (see Figure 20). Figure 21
shows the inductor current and switch node voltage in DCM.
In DCM with a light load, the ADP3209D monitors the
switch node voltage to determine when to turn off the
low−side FET. Figure 22 shows a typical waveform in DCM
with a 1 A load current. Between t1 and t2, the inductor
current ramps down. The current flows through the source
drain of the low−side FET and creates a voltage drop across
the FET with a slightly negative switch node. As the inductor
current ramps down to 0 A, the switch voltage approaches
0 V, as seen just before t2. When the switch voltage is
approximately −6 mV, the low−side FET is turned off.
Figure 21 shows a small, dampened ringing at t2. This is
caused by the LC created from capacitance on the switch
node, including the CDS of the FETs and the output inductor.
This ringing is normal.
The ADP3209D automatically goes into DCM with a light
load. Figure 22 shows the typical DCM waveform of the
ADP3209D with a 1 A load current. As the load increases,
the ADP3209D enters into CCM. In DCM, frequency
decreases with load current, and switching frequency is a
function of the inductor, load current, input voltage, and
output voltage.
Current Limit, Short−Circuit, and Latchoff Protection
The ADP3209D has an adjustable current limit set by the
RCLIM resistor. This resistor is connected from the ILIMN
to ILIMP.
Normally, the ADP3209D operates in RPM mode. During
a current overload, the ADP3209D switches to PWM mode.
With low impedance loads, the ADP3209D operates in a
constant current mode to ensure that the external MOSFETs
and inductor function properly and to protect the GPU. With
a low constant impedance load, the output voltage decreases
to supply only the set current limit. If the output voltage drops
below the power−good limit, the PWRGD signal transitions.
After the PWRGD single transitions, the ADP3209D will
latchoff after 9 ms.
The latchoff function can be reset either by removing and
reapplying VCC or by briefly pulling the EN pin low.
During startup, when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot extend below ground.
This secondary current limit clamp controls the minimum
internal COMP voltage to the PWM comparators to 1.5 V.
This limits the voltage drop across the low−side MOSFETs
through the current balance circuitry.
Q1
INPUT
VOLTAGE
Light Load RPM DCM Operation
The ADP3209D operates in RPM mode. With higher
loads, the ADP3209D operates in continuous conduction
mode (CCM), and the upper and lower MOSFETs run
synchronously and in complementary phase. See Figure 16
for the typical waveforms of the ADP3209D running in
CCM with a 7 A load current.
DRVH
OUTPUT
VOLTAGE
SWITCH
L
NODE
Q2
C
DRVL
LOAD
Figure 17. Buck Topology
OUTPUT VOLTAGE 20 mV/DIV
4
ON
L
INDUCTOR CURRENT 5 A/DIV
OFF
2
C
LOAD
SWITCH NODE 5.0 V/DIV
Figure 18. Buck Topology Inductor Current During
t0 and t1
LOW−SIDE GATE 5.0 V/DIV
3
1
400 ns/DIV
Figure 16. Single−Phase Waveforms in CCM
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ADP3209D
Output Crowbar
To protect the load and output components of the supply,
the DRVL output is driven high (turning the low−side
MOSFETs on) and DRVH is driven low (turning the
high−side MOSFETs off) when the output voltage exceeds
the GMCH OVP threshold.
Turning on the low−side MOSFETs forces the output
capacitor to discharge and the current to reverse due to
current build up in the inductors. If the output overvoltage
is due to a drain−source short of the high−side MOSFET,
turning on the low−side MOSFET results in a crowbar
across the input voltage rail. The crowbar action blows the
fuse of the input rail, breaking the circuit and thus protecting
the GMCH chipset from destruction.
When the OVP feature is triggered, the ADP3209D is
latched off. The latchoff function can be reset by removing
and reapplying VCC to the ADP3209D or by briefly pulling
the EN pin low.
OFF
L
C
ON
LOAD
Figure 19. Buck Topology Inductor Current During
t1 and t2
OFF
L
OFF
C
LOAD
Figure 20. Buck Topology Inductor Current During
t2 and t3
Reverse Voltage Protection
Very large reverse current in inductors can cause negative
VCCGFX voltage, which is harmful to the chipset and other
output components. The ADP3209D provides a reverse
voltage protection (RVP) function without additional
system cost. The VCCGFX voltage is monitored through the
CSREF pin. When the CSREF pin voltage drops to less than
−300 mV, the ADP3209D triggers the RVP function by
setting both DRVH and DRVL low, thus turning off all
MOSFETs. The reverse inductor currents can be quickly
reset to 0 by discharging the built−up energy in the inductor
into the input dc voltage source via the forward−biased body
diode of the high−side MOSFETs. The RVP function is
terminated when the CSREF pin voltage returns to greater
than −100 mV.
Sometimes the crowbar feature inadvertently results in
negative VCCGFX voltage because turning on the low−side
MOSFETs results in a very large reverse inductor current.
To prevent damage to the chipset caused from negative
voltage, the ADP3209D maintains its RVP monitoring
function even after OVP latchoff. During OVP latchoff, if
the CSREF pin voltage drops to less than −300 mV, the
low−side MOSFETs is turned off by setting DRVL low.
DRVL will be set high again when the CSREF voltage
recovers to greater than −100 mV.
Figure 23 shows the reverse voltage protection function of
the ADP3209D. The CSREF pin is disconnected from the
output voltage and pulled negative. As the CSREF pin drops
to less than −300 mV, the low−side and high−side FETs turn
off.
INDUCTOR
CURRENT
SWITCH
NODE
VOLTAGE
t0
t1
t2
t3
t4
Figure 21. Inductor Current and Switch Node in DCM
4
OUTPUT VOLTAGE
20 mV/DIV
SWITCH NODE 5.0 V/DIV
2
3
INDUCTOR CURRENT
5 A/DIV
1
LOW−SIDE GATE DRIVE 5.0 V/DIV
2 ms/DIV
Figure 22. Single−Phase Waveforms in DCM with 1 A
Load Current
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ADP3209D
3
voltage is less than the VCCUVLO threshold or the EN pin is
logic low, the ADP3209D shuts off. In shutdown mode, the
controller holds DRVH and DRVL low, shorts the capacitors
of the SS and PGDELAY pins to ground, and drives PWRGD
to low.
The user must adhere to proper power−supply sequencing
during startup and shutdown of the ADP3209D. All input
pins must be at ground prior to removing or applying VCC,
and all output pins should be left in high impedance state
while VCC is off.
CSREF
PWRGD
2
DRVH
4
DRVL
1
CH1 5.00V
CH3 1.00V
CH2 5.00V
CH4 20.0V
M2.00ms
Current Monitor Function
A CH3
The ADP3209D has an output current monitor. The
IMON pin sources a current proportional to the inductor
current. A resistor from IMON pin to FBRTN sets the gain.
A 0.1 mF is added in parallel with RMON to filter the inductor
ripple. The IMON pin is clamped to prevent it from going
above 1.15 V.
580mV
Figure 23. ADP3209D RVP Function
Output Enable and UVLO
For the ADP3209D to begin switching, the VCC supply
voltage to the controller must be greater than the VCCOK
threshold and the EN pin must be driven high. If the VCC
Table 1. VID Code Table
Enable
VID4
VID3
VID2
VID1
VID0
Nominal VCCGFX (V)
1
0
0
0
0
0
1.250
1
0
0
0
0
1
1.225
1
0
0
0
1
0
1.200
1
0
0
0
1
1
1.175
1
0
0
1
0
0
1.150
1
0
0
1
0
1
1.125
1
0
0
1
1
0
1.100
1
0
0
1
1
1
1.075
1
0
1
0
0
0
1.050
1
0
1
0
0
1
1.025
1
0
1
0
1
0
1.000
1
0
1
0
1
1
0.975
1
0
1
1
0
0
0.950
1
0
1
1
0
1
0.925
1
0
1
1
1
0
0.900
1
0
1
1
1
1
0.875
1
1
0
0
0
0
0.850
1
1
0
0
0
1
0.825
1
1
0
0
1
0
0.800
1
1
0
0
1
1
0.775
1
1
0
1
0
0
0.750
1
1
0
1
0
1
0.725
1
1
0
1
1
0
0.700
1
1
0
1
1
1
0.675
1
1
1
0
0
0
0.650
1
1
1
0
0
1
0.625
1
1
1
0
1
0
0.600
1
1
1
0
1
1
0.575
1
1
1
1
0
0
0.550
1
1
1
1
0
1
0.525
1
1
1
1
1
0
0.500
1
1
1
1
1
1
0.400
0
X
X
X
X
X
0.000
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16
C28
1nF
RA1
20.0kW
1%
VSSSENSE
R53, 100W
CFB1
22pF
C??
0.1mF
VCCSENSE
TP6
FBRTN
TP5
FB
RIMON
???W
?%
R13, 100W
TP10
IMON
TP3
COMP
RB1
1.00kW
1%
CB1, DNP CA1, 470pF
R3
33.2kW
1%
R14
???W
?%
R18
???W
?%
R19
0W
R16
DNP
1
32
R1
10kW
TP7
CON2
R10
0W
R9
DNP
RPM
FBRTN
FB
COMP
NC
NC
IMON
IREF
PWRGD
V3.3S
ADP3209
D
2
1
C25
1nF
R11
340kW
1%
CCS1
DNP
R7
200kW
C6
1mF
C21
1mF
R2
10W
C27
100pF
TP12
DRVL
VGFX_CORE_RTN
VGFX_CORE
RPH2
DNP
RPH1
59.0kW
1%
Q2
NTMFS4846N
Q1
NTMFS4821N
CONNECT POWER GROUND TO
CONTROLLER GROUND UNDER
THE CONTROLLER.
SHORTPIN
JP1
RCS2
140kW, 1%
C24
DNP
R4
DNP
TP8 TP11
SW DRVH
C8
4.7mF
C1
10mF
25V
C3
10mF
25V
L1
560nH/1.3mW
C2
10mF
25V
RTH1
220kW
8% NTC
Q3
NTMFS4846N
Figure 24. Typical Application Circuit
R12 VDC
1.00kW
1%
RCS1
76.8kW, 1%
R17
0W
V5S
CCS2
2.2nF
R8
357kW
GND
SW
PVCC
DRVL
PGND
VCC
BST
DRVH
VR_ON
VID0
VID1
VID2
VID3
VID4
VARFREQ
PWRGD
EN
VID0
VID1
VID2
VID3
VID4
LLINE
CSCOMP
CSREF
CSFB
RAMP
ILIMN
ILIMP
RT
V5S
R54
(OPTIONAL)
R55
0W
RS1
(OPTIONAL)
C4
10mF
25V
C22
220mF
2.5V
C9
22mF
6.3V
GND
VDC
C23
220mF
2.5V
C10
22mF
6.3V
C30
DNP
C11
0.22mF
GND
VDC
C31
DNP
C12
0.1mF
C14
1nF
C15
DNP
VGFX_CORE_RTN
C13
0.1mF
VGFX_CORE
VGFX_CORE
ADP3209D
ADP3209D
Application Information
and transient response. Use this equation to determine a
starting value:
The design parameters for a typical IMVP−6+ compliant
GPU core VR application are as follows:
• Maximum input voltage (VINMAX) = 19 V
• Minimum input voltage (VINMIN) = 8.0 V
• Output voltage by VID setting (VVID) = 1.25 V
• Maximum output current (IO) = 15 A
• Droop resistance (RO) = 5.1 mW
• Nominal output voltage at 15 A load (VOFL) = 1.174 V
• Static output voltage drop from no load to full load
(DV) = VONL − VOFL = 1.25 V − 1.174 V = 76 mV
• Maximum output current step (DIO) = 8 A
• Number of phases (n) = 1
• Switching frequency (fSW) = 390 kHz
• Duty cycle at maximum input voltage (DMAX) = 0.15 V
• Duty cycle at minimum input voltage (DMIN) = 0.062
V
RR +
RR +
VR +
In PWM operation, the ADP3209D uses a
fixed−frequency control architecture. The frequency is set
by an external timing resistor (RT). The clock frequency
determines the switching frequency, which relates directly
to the switching losses and the sizes of the inductors and
input and output capacitors. For example, a clock frequency
of 300 kHz sets the switching frequency to 300 kHz. This
selection represents the trade−off between the switching
losses and the minimum sizes of the output filter
components. To achieve a 300 kHz oscillator frequency at
a VID voltage of 1.2 V, RT must be 237 kW. Alternatively,
the value for RT can be calculated by using the following
equation:
RT +
2
f SW
9 pF
* 16 kW
VR +
1.0 V
f SW
9 pF
* 16 kW
RDS
0.5
3
5
CR
(eq. 3)
360 nH
5.2 mW
5 pF
+ 462 kW
AR
(1 * D)
RR
0.5
V VID
CR
f SW
(1 * 0.061)
462 kW
5 pF
(eq. 4)
1.150 V
280 kHz
+ 0.83 V
The size of the internal ramp can be made larger or
smaller. If it is made larger, then stability and transient
response improves, but thermal balance degrades. Likewise,
if the ramp is made smaller, then thermal balance improves
at the sacrifice of transient response and stability. The factor
of three in the denominator of Equation 4 sets a minimum
ramp size that gives an optimal balance for good stability,
transient response, and thermal balance.
Setting the Switching Frequency for RPM Operation
During the RPM operation, the ADP3209D runs in
pseudo−constant frequency if the load current is high
enough for continuous current mode. While in DCM, the
switching frequency is reduced with the load current in a
linear manner. To save power with light loads, lower
switching frequency is usually preferred during RPM
operation. However, the VCCGFX ripple specification of
IMVP−6+ sets a limitation for the lowest switching
frequency. Therefore, depending on the inductor and output
capacitors, the switching frequency in RPM can be equal to,
greater than, or less than its counterpart in PWM.
A resistor from RPM to GND sets the pseudo constant
frequency as following:
(eq. 1)
where:
9 pF and 16 kW are internal IC component values.
VVID is the VID voltage in volts.
fSW is the switching frequency in hertz.
For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.
With VARFREQ pulled above 4.0 V, the ADP3209D
operates with a constant switching frequency. The switching
frequency does not change with VID voltage, input voltage,
or load current. In addition, the DCM operation at light load
is disabled, so the ADP3209D operates in CCM. The value
of RT can be calculated by using the following equation:
RT +
AD
where:
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
RDS is the total low−side MOSFET ON−resistance,
CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of
the internal ramp voltage (see Equation 3). For stability and
noise immunity, keep this ramp size larger than 0.5 V. Taking
this into consideration, the value of RR is selected as 280 kW.
The internal ramp voltage magnitude can be calculated
using:
Setting the Clock Frequency for PWM
V VID ) 1.0 V
L
AR
3
R RPM +
2
V VID
RT
1.0 V
AR
RR
(1 * D)
CR
V VID
f SW
* 0.5 kW
(eq. 5)
where:
AR is the internal ramp amplifier gain.
CR is the internal ramp capacitor value.
RR is an external resistor on the RAMPADJ pin to set the
internal ramp magnitude.
(eq. 2)
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the
internal PWM ramp. The value of this resistor is chosen to
provide the best combination of thermal balance, stability,
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17
ADP3209D
Selecting a Standard Inductor
Because RR = 280 kW, the following resistance sets up
300 kHz switching frequency in RPM operation.
R RPM +
2
280 kW
0.5
1.150 V ) 1.0 V
(1 * 0.061)
462 kW
5 pF
After the inductance and DCR are known, select a
standard inductor that best meets the overall design goals. It
is also important to specify the inductance and DCR
tolerance to maintain the accuracy of the system. Using 20%
tolerance for the inductance and 15% for the DCR at room
temperature are reasonable values that most manufacturers
can meet.
1.150
300 kHz
* 500 kW + 202 kW
(eq. 6)
Inductor Selection
The choice of inductance determines the ripple current of
the inductor. Less inductance results in more ripple current,
which increases the output ripple voltage and the conduction
losses in the MOSFETs. However, this allows the use of
smaller−size inductors, and for a specified peak−to−peak
transient deviation, it allows less total output capacitance.
Conversely, a higher inductance results in lower ripple
current and reduced conduction losses, but it requires
larger−size inductors and more output capacitance for the
same peak−to−peak transient deviation. For a buck
converter, the practical value for peak−to−peak inductor
ripple current is less than 50% of the maximum dc current
of that inductor. Equation 7 shows the relationship between
the inductance, oscillator frequency, and peak−to−peak
ripple current. Equation 8 can be used to determine the
minimum inductance based on a given output ripple voltage.
IR +
Lw
Power Inductor Manufacturers
The following companies provide surface−mount power
inductors optimized for high power applications upon
request.
• Vishay Dale Electronics, Inc.
• Panasonic
• Sumida Electric Company
• NEC Tokin Corporation
Output Droop Resistance
The design requires that the regulator output voltage
measured at the chipset pins decreases when the output
current increases. The specified voltage drop corresponds to
the droop resistance (RO).
The output current is measured by low−pass filtering the
voltage across the inductor or current sense resistor. The
filter is implemented by the CS amplifier that is configured
with RPH, RCS, and CCS. The output resistance of the
regulator is set by the following equations:
ǒ1 * D MINǓ
V VID
f SW
V VID
L
(eq. 7)
RO
(1 * (n
f SW
V RIPPLE
D MIN))
(eq. 8)
RO +
In this example, RO is assumed to be the ESR of the output
capacitance, which results in an optimal transient response.
Solving Equation 9 for a 16 mV peak−to−peak output ripple
voltage yields:
Lw
1.174 V
5.1 mW
390 kHz
(1 * 0.062)
16 mV
+ 901 nH
C CS +
RCS
R SENSE
RPH(x)
(eq. 10)
L
R SENSE
R CS
(eq. 11)
where RSENSE is the DCR of the output inductors.
Either RCS or RPH can be chosen for added flexibility. Due
to the current drive ability of the CSCOMP pin, the RCS
resistance should be greater than 100 kW. For example,
initially select RCS to be equal to 200 kW, and then use
Equation 11 to solve for CCS:
(eq. 9)
If the resultant ripple voltage is less than the initially
selected value, the inductor can be changed to a smaller
value until the ripple value is met. This iteration allows
optimal transient response and minimum output decoupling.
In this example, the iteration showed that a 560 nH inductor
was sufficient to achieve a good ripple.
The smallest possible inductor should be used to minimize
the number of output capacitors. Choosing a 560 nH
inductor is a good choice for a starting point, and it provides
a calculated ripple current of 6.6 A. The inductor should not
saturate at the peak current of 18.3 A, and it should be able
to handle the sum of the power dissipation caused by the
winding’s average current (15 A) plus the ac core loss.
Another important factor in the inductor design is the
DCR, which is used for measuring the inductor current. Too
large of a DCR causes excessive power losses, whereas too
small of a value leads to increased measurement error. For
this example, an inductor with a DCR of 1.3 mW is used.
C CS +
560 nH
1.3 mW
200 kW
+ 2.2 nF
(eq. 12)
If CCS is not a standard capacitance, RCS can be tuned. In
this case, the required CCS is a standard value and no tuning
is required. For best accuracy, CCS should be a 5% NPO
capacitor.
Next, solve for RPH by rearranging Equation 10 as
follows:
R PH w
1.3 mW
5.1 mW
200 kW + 51.0 kW
The standard 1% resistor for RPH is 51.1 kW.
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18
(eq. 13)
ADP3209D
Inductor DCR Temperature Correction
r CS1 +
If the DCR of the inductor is used as a sense element and
copper wire is the source of the DCR, the temperature
changes associated with the inductor’s winding must be
compensated for. Fortunately, copper has a well−known
temperature coefficient (TC) of 0.39%/°C.
If RCS is designed to have an opposite but equal
percentage of change in resistance, it cancels the
temperature variation of the inductor’s DCR. Due to the
nonlinear nature of NTC thermistors, series resistors RCS1
and RCS2 (see Figure 25) are needed to linearize the NTC and
produce the desired temperature coefficient tracking.
PLACE AS CLOSE AS POSSIBLE
TO INDUCTOR OR LOW-SIDE MOSFET
RTH
RCS1
CSCOMP
10
CCS1
CS2
r TH +
VCCGFX
SENSE
RCS2
KEEP THIS PATH AS SHORT
AS POSSIBLE AND AWAY FROM
SWITCH NODE LINES
The following procedure and expressions yield values for
RCS1, RCS2, and RTH (the thermistor value at 25°C) for a
given RCS value.
1. Select an NTC to be used based on its type and
value. Because the value needed is not yet
determined, start with a thermistor with a value
close to RCS and an NTC with an initial tolerance
of better than 5%.
2. Find the relative resistance value of the NTC at
two temperatures. The appropriate temperatures
will depend on the type of NTC, but 50°C and
90°C have been shown to work well for most
types of NTCs. The resistance values are called A
(A is RTH(50°C)/RTH(25°C)) and B (B is
RTH(90°C)/RTH(25°C)). Note that the relative
value of the NTC is always 1 at 25°C.
3. Find the relative value of RCS required for each of
the two temperatures. The relative value of RCS is
based on the percentage of change needed, which
is initially assumed to be 0.39%/°C in this
example. The relative values are called r1 (r1 is
1/(1+ TC × (T1 − 25))) and r2 (r2 is 1/(1 + TC ×
(T2 − 25))), where TC is 0.0039, T1 is 50°C, and
T2 is 90°C.
4. Compute the relative values for rCS1, rCS2, and rTH
by using the following equations:
A
(1 * B)
(1 * B)
r1 * B
r2 ) B
(1 * A)
(1 * A)
R TH(ACTUAL)
R TH(CALCULATED)
R CS1 + R CS
k
R CS2 + R CS
((1 * k) ) (k
COUT Selection
(eq. 15)
rCS1
r CS2))
(eq. 16)
The required output decoupling for processors and
platforms is typically recommended by Intel. For systems
containing both bulk and ceramic capacitors, however, the
following guidelines can be a helpful supplement.
Select the number of ceramics and determine the total
ceramic capacitance (CZ). This is based on the number and
type of capacitors used. Keep in mind that the best location
to place ceramic capacitors is inside the socket; however, the
physical limit is twenty 0805−size pieces inside the socket.
Additional ceramic capacitors can be placed along the outer
edge of the socket. A combined ceramic capacitor value of
40 mF to 50 mF is recommended and is usually composed of
multiple 10 mF or 22 mF capacitors.
Ensure that the total amount of bulk capacitance (CX) is
within its limits. The upper limit is dependent on the VID
OTF output voltage stepping (voltage step, VV, in time, tV,
with error of VERR); the lower limit is based on meeting the
critical capacitance for load release at a given maximum load
step, DIO. The current version of the IMVP−6+ specification
allows a maximum VCCGFX overshoot (VOSMAX) of 10 mV
more than the VID voltage for a step−off load current.
r CS2 +
r2 * A
(eq. 14)
For example, if a thermistor value of 100 kW is selected
in Step 1, an available 0603−size thermistor with a value
close to RCS is the Vishay NTHS0603N04 NTC thermistor,
which has resistance values of A = 0.3359 and B = 0.0771.
Using the equations in Step 4, rCS1 is 0.359, rCS2 is 0.729,
and rTH is 1.094. Solving for rTH yields 219 kW, so a
thermistor of 220 kW would be a reasonable selection,
making k equal to 1.005. Finally, RCS1 and RCS2 are found
to be 72.2 kW and 146 kW. Choosing the closest 1% resistor
values yields a choice of 71.5 kW and 147 kW.
Figure 25. Temperature−Compensation Circuit Values
r1
1
6. Calculate values for RCS1 and RCS2 by using the
following equations:
12
(A * B)
CS2
CS1
k+
CSFB
11
*r
TO
SWITCH
NODE
RPH
1
*r
1
5. Calculate RTH = rTH × RCS, and then select a
thermistor of the closest value available. In
addition, compute a scaling factor k based on the
ratio of the actual thermistor value used relative to
the computed one:
CCS2
CSREF
*r
1
1
1*r
CS2
TO
ADP3209
(1 * A)
1
1*r
r1
r2 * (A * B)
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19
ADP3209D
C x(MIN)
ȡ
wȧ
ȢǒR
C X(MAX) v
L
V
OSMAX
O)
DI
O
RO
2
Ǹ
ȡ
ȧ
Ȣ
where:
Ǔ
For this multi−mode control technique, an all ceramic
capacitor design can be used if the conditions of Equations
17, 18, and 19 are satisfied.
z
V VID
(eq. 17)
Power MOSFETs
For typical 15 A per phase applications, the N−channel
power MOSFETs are selected for one high−side switch and
one low−side switch. The main selection parameters for the
power MOSFETs are VGS(TH), QG, CISS, CRSS, and
RDS(ON). Because the voltage of the gate driver is 5.0 V,
logic−level threshold MOSFETs must be used.
The maximum output current, IO, determines the RDS(ON)
requirement for the low−side (synchronous) MOSFETs.
With conduction losses being dominant, the following
expression shows the total power that is dissipated in each
synchronous MOSFET in terms of the ripple current per
phase (IR) and the average total output current (IO):
Vv
L
k2
ȣ
*C ȧ
Ȥ
DI O
V VID
ǒ
1 ) tv
k + −1n
V VID
k
Vv
Ǔ ȣȧ
2
RO
* 1 * Cz
Ȥ
L
ǒ Ǔ
V ERR
VV
(eq. 18)
To meet the conditions of these expressions and the
transient response, the ESR of the bulk capacitor bank (RX)
should be less than two times the droop resistance, RO. If the
CX(MIN) is greater than CX(MAX), the system does not meet
the VID OTF specifications and may require less inductance.
In addition, the switching frequency may have to be increased
to maintain the output ripple.
For example, if two pieces of 22 mF, 0805−size MLC
capacitors (CZ = 44 mF) are used during a VID voltage
change, the VCCGFX change is 220 mV in 22 ms with a
setting error of 10 mV. If k = 3.1, solving for the bulk
capacitance yields:
C X(MIN)
P SF + (1 * D)
IR +
ȡǸ1 ) ǒ22 ms
ȧ
Ȣ
220 mV
(5.1 mW) 2
1.174 V
220 mV
1.174 V
3.1
Ǔ ȣȧ
5.1 mW
560 nH
2
* 1 + 992 mF
Ȥ
Using two 220 mF Panasonic SP capacitors with a typical
ESR of 7 mW each yields CX = 440 mF and RX = 3.5 mW.
Ensure that the ESL of the bulk capacitors (LX) is low
enough to limit the high frequency ringing during a load
change. This is tested using:
LX v CZ
LX v 44 mF
RO 2
Q2
(5.1 mW) 2
2 + 2.3 nH
2
ǒ Ǔƫ
IR
) 1
12
nSF
2
R DS(SF)
(1 * D)
L
V OUT
f SW
(eq. 21)
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the required
RDS(ON) for the MOSFET. For an 8−lead SOIC or 8−lead
SOIC−compatible MOSFET, the junction−to−ambient (PCB)
thermal impedance is 50°C/W. In the worst case, the PCB
temperature is 70°C to 80°C during heavy load operation of
the notebook, and a safe limit for PSF is about 0.8 W to 1.0 W
at 120°C junction temperature. Therefore, for this example
(15 A maximum), the RDS(SF) per MOSFET is less than
18.8 mW for the low−side MOSFET. This RDS(SF) is also at
a junction temperature of about 120°C; therefore, the RDS(SF)
per MOSFET should be less than 13.3 mW at room
temperature, or 18.8 mW at high temperature.
Another important factor for the synchronous MOSFET
is the input capacitance and feedback capacitance. The ratio
of the feedback to input must be small (less than 10% is
recommended) to prevent accidentally turning on the
synchronous MOSFETs when the switch node goes high.
The high−side (main) MOSFET must be able to handle
two main power dissipation components: conduction losses
and switching losses. Switching loss is related to the time for
the main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed
on the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression
8A
560 nH
n SF
Ǔ
where:
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
IR is the inductor peak−to−peak ripple current and is
approximately:
10 mV
3.12
IO
(eq. 20)
ȡ 560 nH 8 A
ȣ
wȧ
* 44 mFȧ+ 256 mF
Ȣǒ5.1 mW ) Ǔ 1.174 V
Ȥ
C X(MAX) v
ƪǒ
(eq. 19)
where:
Q is limited to the square root of 2 to ensure a critically
damped system.
LX is about 450 pH for the two SP capacitors, which is low
enough to avoid ringing during a load change. If the LX of
the chosen bulk capacitor bank is too large, the number of
ceramic capacitors may need to be increased to prevent
excessive ringing.
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ADP3209D
provides an approximate value for the switching loss per
main MOSFET:
P S(MF) + 2
f SW
V DC
IO
n MF
RG
nMF
C ISS
RR +
(eq. 22)
RR +
where:
nMF is the total number of main MOSFETs.
RG is the total gate resistance.
CISS is the input capacitance of the main MOSFET.
The most effective way to reduce switching loss is to use
lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
ƪǒ
P C(MF) + D
IO
Ǔ
n MF
2
) 1
12
ǒ Ǔƫ
IR
n MF
2
R DS(MF)
where RDS(MF) is the on resistance of the MOSFET.
Typically, a user wants the highest speed (low CISS)
device for a main MOSFET, but such a device usually has
higher on resistance. Therefore, the user must select a device
that meets the total power dissipation (about 0.8 W to 1.0 W
for an 8−lead SOIC) when combining the switching and
conduction losses.
For example, an IRF7821 device can be selected as the
main MOSFET (one in total; that is, nMF = 1), with
approximately CISS = 1010 pF (maximum) and RDS(MF) =
18 mW (maximum at TJ = 120°C), and an IR7832 device can
be selected as the synchronous MOSFET (two in total; that
is, nSF = 2), with RDS(SF) = 6.7 mW (maximum at TJ =
120°C). Solving for the power dissipation per MOSFET at
IO = 15 A and IR = 5.0 A yields 178 mW for each
synchronous MOSFET and 446 mW for each main
MOSFET. A third synchronous MOSFET is an option to
further increase the conversion efficiency and reduce
thermal stress.
Finally, consider the power dissipation in the driver. This
is best described in terms of the QG for the MOSFETs and
is given by the following equation:
ƪ
f SW
2
n
ǒnMF
Q GMF ) n SF
ƫ
Q GSFǓ ) I CC
3
AD
L
RDS
0.2
3
5
CR
(eq. 25)
560 nH
3.4 mW
5 pF
+ 439 kW
where:
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
RDS is the total low−side MOSFET on resistance.
CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of
the internal ramp voltage (see Equation 26). For stability and
noise immunity, keep the ramp size larger than 0.5 V. Taking
this into consideration, the value of RR in this example is
selected as 340 kW.
The internal ramp voltage magnitude can be calculated as
follows:
(eq. 23)
P DRV +
AR
VR +
VR +
AR
(1 * D)
RR
0.2
CR
V VID
f SW
(eq. 26)
(1 * 0.062)
340 kW
5 pF
1.174 V
390 kHz
+ 0.33 V
The size of the internal ramp can be increased or
decreased. If it is increased, stability and transient response
improves but thermal balance degrades. Conversely, if the
ramp size is decreased, thermal balance improves but
stability and transient response degrade. In the denominator
of Equation 25, the factor of 3 sets the minimum ramp size
that produces an optimal balance of good stability and
transient response.
COMP Pin Ramp
In addition to the internal ramp, there is a ramp signal on
the COMP pin due to the droop voltage and output voltage
ramps. This ramp amplitude adds to the internal ramp to
produce the following overall ramp signal at the PWM
input:
V RT +
ǒ
1*
V CC
VR
2
f
SW
(1*D)
C
X
R
Ǔ
(eq. 27)
O
where CX is the total bulk capacitance, and RO is the droop
resistance of the regulator. For this example, the overall
ramp signal is 0.23 V.
(eq. 24)
where QGMF is the total gate charge for each main
MOSFET, and QGSF is the total gate charge for each
synchronous MOSFET.
The previous equation also shows the standby dissipation
(ICC times the VCC) of the driver.
Current Limit Setpoint
To select the current limit setpoint, we need to find the
resistor value for RLIM. The current limit threshold for the
ADP3209D is set when the current in RLIM is equal to the
internal reference current of 20 mA. The current in RLIM is
equal to the inductor current times RO. RLIM can be found
using the following equation:
Ramp Resistor Selection
The ramp resistor (RR) is used to set the size of the internal
PWM ramp. The value of this resistor is chosen to provide
the best combination of stability and transient response. Use
the following expression to determine a starting value:
R LIM +
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21
I LIM
RO
20 mA
(eq. 28)
ADP3209D
where:
RLIM is the current limit resistor. RLIM is connected from the
ILIM pin to ground.
RO is the output load line resistance.
ILIM is the current limit set point. This is the peak inductor
current that will trip current limit.
VOLTAGE ERROR
AMPLIFIER
ADP3209
3
Current Monitor
1.15 V
10
RO
COMP
2
RA
The ADP3209D has output current monitor. The IMON
pin sources a current proportional to the total inductor
current. A resistor, RMON, from IMON to FBRTN sets the
gain of the output current monitor. A 0.1 mF is placed in
parallel with RMON to filter the inductor current ripple and
high frequency load transients. Since the IMON pin is
connected directly to the CPU, it is clamped to prevent it
from going above 1.15V.
The IMON pin current is equal to the RLIM times a fixed
gain of 10. RMON can be found using the following equation:
R MON +
REFERENCE
VOLTAGE
FB
CB
CFB
Figure 26. Voltage Error Amplifier
GAIN
–20dB/DEC
R LIM
I FS
OUTPUT
VOLTAGE
RFB
CA
–20dB/DEC
(eq. 29)
where:
RMON is the current monitor resistor. RMON is connected
from IMON pin to FBRTN.
RLIM is the current limit resistor.
RO is the output load line resistance.
IFS is the output current when the voltage on IMON is at full
scale.
0dB
f P1
f Z2
f Z1
FREQUENCY
f P2
Figure 27. Poles and Zeros of Voltage Error Amplifier
The following equations give the locations of the poles
and zeros shown in Figure 27:
Feedback Loop Compensation Design
Optimized compensation of the ADP3209D allows the
best possible response of the regulator’s output to a load
change. The basis for determining the optimum
compensation is to make the regulator and output
decoupling appear as an output impedance that is entirely
resistive over the widest possible frequency range, including
dc, and that is equal to the droop resistance (RO). With the
resistive output impedance, the output voltage droops in
proportion with the load current at any load current slew
rate, ensuring the optimal position and allowing the
minimization of the output decoupling.
With the multi−mode feedback structure of the
ADP3209D, it is necessary to set the feedback compensation
so that the converter’s output impedance works in parallel
with the output decoupling. In addition, it is necessary to
compensate for the several poles and zeros created by the
output inductor and decoupling capacitors (output filter).
A Type III compensator on the voltage feedback is
adequate for proper compensation of the output filter.
Figure 26 shows the Type III amplifier used in the
ADP3209D. Figure 27 shows the locations of the two poles
and two zeros created by this amplifier.
f Z1 +
2p
1
CA
f Z2 +
2p
1
C FB
f P1 +
f P2 +
RA
(eq. 30)
R FB
(eq. 31)
1
2pǒC A ) C BǓ
R FB
(eq. 32)
C B ) CA
(eq. 33)
CA ) CB
2p
RA
The expressions that follow compute the time constants
for the poles and zeros in the system and are intended to yield
an optimal starting point for the design; some adjustments
may be necessary to account for PCB and component
parasitic effects (see the Tuning Procedure for ADP3209D
section):
RE + RO ) AD
RDS )
2
L
RL
V ID
(1 * (n
CX
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22
V RT
RO
)
D))
V VID
V RT
(eq. 34)
ADP3209D
TA + CX
(R O * RȀ) )
T B + (RX ) RȀ * R O)
V RT
TC +
TD +
ǒ
L*
V VID
CX
CX
A
R O * RȀ
RO
RX
Soft Transient Setting
R
f
DS
SW
(eq. 36)
Ǔ
RE
CZ
As described in the Theory of Operation section, during
the soft transient, the slew rate of the VCCGFX reference
voltage change is controlled by the ST pin capacitance. The
ST pin capacitance is set to satisfy the slew rate for a fast exit
as follows:
(eq. 35)
CX
D
2
LX
C ST +
(eq. 37)
RO
(eq. 38)
where:
R’ is the PCB resistance from the bulk capacitors to the
ceramics and is approximately 0.4 mW (assuming an 8−layer
motherboard).
RDS is the total low−side MOSFET for on resistance.
AD is 5.
VRT is 1.25 V.
LX is the ESL of the bulk capacitors (450 pH for the two
Panasonic SP capacitors).
The compensation values can be calculated as follows:
CA +
RA +
CB +
RO
TA
RE
RB
Set−Up and Test the Circuit
1. Build a circuit based on the compensation values
computed from the design spreadsheet.
2. Connect a dc load to the circuit.
3. Turn on the ADP3209D and verify that it operates
properly.
4. Check for jitter with no load and full load
conditions.
(eq. 39)
Set the DC Load Line
CA
1. Measure the output voltage with no load (VNL)
and verify that this voltage is within the specified
tolerance range.
2. Measure the output voltage with a full load when
the device is cold (VFLCOLD). Allow the board to
run for ~10 minutes with a full load and then
measure the output when the device is hot
(VFLHOT). If the difference between the two
measured voltages is more than a few millivolts,
adjust RCS2 using Equation 45.
(eq. 40)
TB
RB
(eq. 41)
TD
RA
(eq. 42)
The standard values for these components are subject to
the tuning procedure described in the Tuning Procedure for
ADP3209D section.
CIN Selection and Input Current di/dt Reduction
R CS2(NEW) + R CS2(OLD)
In continuous inductor−current mode, the source current
of the high−side MOSFET is approximately a square wave
with a duty ratio equal to VOUT/VIN. To prevent large
voltage transients, use a low ESR input capacitor sized for
the maximum rms current. The maximum rms capacitor
current occurs at the lowest input voltage and is given by:
I CRMS + D
I CRMS + 0.15
IO
Ǹ1 * 1
D
15 A
(eq. 44)
Tuning Procedure for ADP3209D
TC
C FB +
SLEWRATE
where:
7.5 mA is the source/sink current of the ST pin. Slew Rate is
the voltage slew rate after a change in VID voltage and is
defined as 10 mV/mA in the IMVP−6+ specification. CST is
750 pF, and the closest standard capacitance is 680 pF.
RO 2
(RO * RȀ) ) C Z
7mA
V NL * V FLCOLD
V NL * V FLHOT
(eq. 45)
3. Repeat Step 2 until no adjustment of RCS2 is
needed.
4. Compare the output voltage with no load to that
with a full load using 5 A steps. Compute the load
line slope for each change and then find the
average to determine the overall load line slope
(ROMEAS).
5. If the difference between ROMEAS and RO is more
than 0.05 mW, use the following equation to adjust
the RPH values:
(eq. 43)
Ǹ
1
* 1 + 5.36 A
0.15
where IO is the output current.
In a typical notebook system, the battery rail decoupling
is achieved by using MLC capacitors or a mixture of MLC
capacitors and bulk capacitors. In this example, the input
capacitor bank is formed by four pieces of 10 mF, 25 V MLC
capacitors, with a ripple current rating of about 1.5 A each.
R PH(NEW) + R PH(OLD)
R OMEAS
RO
(eq. 46)
6. Repeat Steps 4 and 5 until no adjustment of RPH is
needed. Once this is achieved, do not change RPH,
RCS1, RCS2, or RTH for the rest of the procedure.
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23
ADP3209D
7. Measure the output ripple with no load and with a
full load with scope, making sure both are within
the specifications.
9. Ensure that the load step slew rate and the
power−up slew rate are set to ~150 A/ms to 250
A/ms (for example, a load step of 50 A should take
200 ns to 300 ns) with no overshoot. Some
dynamic loads have an excessive overshoot at
power−up if a minimum current is incorrectly set
(this is an issue if a VTT tool is in use).
Set the AC Load Line
1. Remove the dc load from the circuit and connect a
dynamic load.
2. Connect the scope to the output voltage and set it to
dc coupling mode with a time scale of 100 ms/div.
3. Set the dynamic load for a transient step of about
40 A at 1 kHz with 50% duty cycle.
4. Measure the output waveform (note that use of a
dc offset on the scope may be necessary to see the
waveform). Try to use a vertical scale of
100 mV/div or finer.
5. The resulting waveform will be similar to that
shown in Figure 28. Use the horizontal cursors to
measure VACDRP and VDCDRP, as shown in
Figure 28. Do not measure the undershoot or
overshoot that occurs immediately after the step.
Set the Initial Transient
1. With the dynamic load set at its maximum step
size, expand the scope time scale to 2 ms/div to
5 ms/div. This results in a waveform that may have
two overshoots and one minor undershoot before
achieving the final desired value after VDROOP
(see Figure 29).
VDROOP
VACDRP
VTRAN1
VTRAN2
VDCDRP
Figure 29. Transient Setting Waveform, Load Step
2. If both overshoots are larger than desired, try the
following adjustments in the order shown.
a. Increase the resistance of the ramp resistor
(RRAMP) by 25%.
b. For VTRAN1, increase CB or increase the
switching frequency.
c. For VTRAN2, increase RA by 25% and decrease
CA by 25%.
If these adjustments do not change the response, it
is because the system is limited by the output
decoupling. Check the output response and the
switching nodes each time a change is made to
ensure that the output decoupling is stable.
3. For load release (see Figure 30), if VTRANREL is
larger than the value specified by IMVP−6+, a
greater percentage of output capacitance is needed.
Either increase the capacitance directly or decrease
the inductor values. (If inductors are changed,
however, it will be necessary to redesign the
circuit using the information from the spreadsheet
and to repeat all tuning guide procedures).
Figure 28. AC Load Line Waveform
6. If the difference between VACDRP and VDCDRP is
more than a couple of millivolts, use Equation 47
to adjust CCS. It may be necessary to try several
parallel values to obtain an adequate one because
there are limited standard capacitor values
available (it is a good idea to have locations for
two capacitors in the layout for this reason).
C CS(NEW) + C CS(OLD)
V ACDRP
V DCDRP
(eq. 47)
7. Repeat Steps 5 and 6 until no adjustment of CCS is
needed. Once this is achieved, do not change CCS
for the rest of the procedure.
8. Set the dynamic load step to its maximum step size
(but do not use a step size that is larger than
needed) and verify that the output waveform is
square, meaning VACDRP and VDCDRP are equal.
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ADP3209D
VTRANREL
6. The output capacitors should be connected as close
as possible to the load (or connector) that receives
the power (for example, a microprocessor core). If
the load is distributed, the capacitors should also
be distributed and generally placed in greater
proportion where the load is more dynamic.
7. Avoid crossing signal lines over the switching
power path loop, as described in the Power
Circuitry section.
VDROOP
Power Circuitry
1. The switching power path on the PCB should be
routed to encompass the shortest possible length to
minimize radiated switching noise energy (that is,
EMI) and conduction losses in the board. Failure
to take proper precautions often results in EMI
problems for the entire PC system as well as
noise−related operational problems in the
power−converter control circuitry. The switching
power path is the loop formed by the current path
through the input capacitors and the power
MOSFETs, including all interconnecting PCB
traces and planes. The use of short, wide
interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance
in the switching loop, which can cause high energy
ringing, and it accommodates the high current
demand with minimal voltage loss.
2. When a power−dissipating component (for
example, a power MOSFET) is soldered to a PCB,
the liberal use of vias, both directly on the
mounting pad and immediately surrounding it, is
recommended. Two important reasons for this are
improved current rating through the vias and
improved thermal performance from vias extended
to the opposite side of the PCB, where a plane can
more readily transfer heat to the surrounding air.
To achieve optimal thermal dissipation, mirror the
pad configurations used to heat sink the MOSFETs
on the opposite side of the PCB. In addition,
improvements in thermal performance can be
obtained using the largest possible pad area.
3. The output power path should also be routed to
encompass a short distance. The output power path
is formed by the current path through the inductor,
the output capacitors, and the load.
4. For best EMI containment, a solid power ground
plane should be used as one of the inner layers and
extended under all power components.
Figure 30. Transient Setting Waveform, Load Release
Layout and Component Placement
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
1. For best results, use a PCB of four or more layers.
This should provide the needed versatility for
control circuitry interconnections with optimal
placement; power planes for ground, input, and
output; and wide interconnection traces in the rest
of the power delivery current paths. Keep in mind
that each square unit of 1 oz copper trace has a
resistance of ~0.53 mW at room temperature.
2. When high currents must be routed between PCB
layers, vias should be used liberally to create
several parallel current paths so that the resistance
and inductance introduced by these current paths is
minimized and the via current rating is not
exceeded.
3. If critical signal lines (including the output voltage
sense lines of the ADP3209D) must cross through
power circuitry, it is best if a signal ground plane
can be interposed between those signal lines and
the traces of the power circuitry. This serves as a
shield to minimize noise injection into the signals
at the expense of increasing signal ground noise.
4. An analog ground plane should be used around
and under the ADP3209D for referencing the
components associated with the controller. This
plane should be tied to the nearest ground of the
output decoupling capacitor, but should not be tied
to any other power circuitry to prevent power
currents from flowing into the plane.
5. The components around the ADP3209D should be
located close to the controller with short traces.
The most important traces to keep short and away
from other traces are those to the FB and CSFB
pins. Refer to Figure 25 for more details on the
layout for the CSFB node.
Signal Circuitry
1. The output voltage is sensed and regulated
between the FB and FBRTN pins, and the traces of
these pins should be connected to the signal
ground of the load. To avoid differential mode
noise pickup in the sensed signal, the loop area
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25
ADP3209D
should be as small as possible. Therefore, the FB
and FBRTN traces should be routed adjacent to
each other, atop the power ground plane, and back
to the controller.
2. The feedback traces from the switch nodes should
be connected as close as possible to the inductor.
The CSREF signal should be Kelvin connected to
the center point of the copper bar, which is the
VCCGFX common node for the inductor.
3. On the back of the ADP3209D package, there is a
metal pad that can be used to heat sink the device.
Therefore, running vias under the ADP3209D is
not recommended because the metal pad may
cause shorting between vias.
ORDERING INFORMATION
Device
ADP3209DJCPZ−RL
Temperature Range
Package
Package Option
Shipping†
0°C to 100°C
32−Lead Frame Chip Scale
Package [LFCSP_VQ]
CP−32−2
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*The “Z” suffix indicates Pb−Free part.
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ADP3209D
PACKAGE DIMENSIONS
LFCSP32 5x5, 0.5P
CASE 932AE−01
ISSUE A
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
D1
PIN ONE
REFERENCE
E1
E
DIM
A
A1
A3
b
D
D1
D2
E
E1
E2
e
H
K
L
M
0.20 C
0.20 C
TOP VIEW
H
(A3)
0.10 C
A
NOTE 4
0.08 C
SIDE VIEW
4X
A1
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
5.00 BSC
4.75 BSC
2.95
3.25
5.00 BSC
4.75 BSC
2.95
3.25
0.50 BSC
−−−
12 °
0.20
−−−
0.30
0.50
−−−
0.60
M
9
K
D2
4X
M
SOLDERING FOOTPRINT*
5.30
17
PIN 1
INDICATOR
32X
L
32
25
32X
b
0.10 C A B
0.05 C
BOTTOM VIEW
0.63
1
1
e
32X
3.14
E2
5.30
3.14
NOTE 3
PACKAGE
OUTLINE
32X
0.50
PITCH
0.28
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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27
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For additional information, please contact your local
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ADP3209D/D