AT89LP52 Drop-In Replacement of AT89S52 Features • • • • • ISP Flash Programming 12 Clock Instruction Compatibility Mode Compatibility Mode Configuration Fuses Polarity-selectable Reset using the former External Access (EA) pin Modified and New SFR registers 8-bit Flash Microcontrollers 1. Introduction The purpose of this application note is to help users convert existing designs from AT89S52/AT89LS52 (“AT89S52”) directly to AT89LP52 for drop-in replacement. For users looking for more performance, Fast mode and other new features are available. More detailed information can be found in the AT89LP52 datasheet and AT89S52 to AT89LP52 Migration Note. Application Note 2. Flash Programming Unlike AT89S52, the AT89LP52 microcontroller does not support high-voltage parallel programming. Users with third-party parallel programmers will need to update their programmer with the appropriate AT89LP52 serial driver. However, the In-System Programming (ISP) protocol is mostly compatible with the existing AT89S52. It is possible that some existing ISP programmers may be able to program the AT89LP52 with an AT89S52 driver in byte-mode, although it is recommended that drivers be updated to make use of the newer features on the AT89LP52. The flash programming differences are summarized in Table 2-1. Table 2-1. Summary of Flash Programming Differences on AT89LP52 Feature AT89S52 AT89LP52 High-Voltage Parallel Interface YES NO 3-wire Serial Interface YES YES Low-Voltage Parallel Interface NO YES Active-High Selectable Byte Command Length 4 bytes 4 bytes Page Command Length 258 bytes 67 bytes 1 2 Page Size 256 128 Page Buffer Size 256 64 0000H, 0100H, 0200H 0000H, 0001H, 0002H NO YES User Signature Array 0 256 bytes Flash Data Memory 0 256 bytes User Configuration Fuses 0 10 Reset Polarity Page Command Address Bytes Device Signature Locations Auto-Erase Commands 3718A–MICRO–9/10 Users migrating from AT89S52 to AT89LP52 devices will notice the following changes to the ISP protocol: 1. All Byte mode commands are identical to AT89S52 with the exception that device signature bytes 1 and 2 are located at addresses 0001H and 0002H instead of 0100H and 0200H for the “Read Signature Bytes” command. Existing AT89S52 ISP drivers should be able to program the AT89LP52 in Byte mode provided they do not strictly check the signature. 2. The AT89LP52 has a half-page buffer of 64 bytes. Therefore Page mode commands accept only 64 bytes of data and require an additional address byte. 3. The AT89LP52 has a selectable polarity RST pin. Existing AT89S52 ISP drivers expect the reset to have active-high polarity. In most existing applications the EA pin is tied high, so dropping in an AT89LP52 will result in an active-high reset. See Section 5. “Reset” on page 3. 2.1 Configuration Fuses The AT89LP52 has ten User Configuration Fuses for configuring the default behavior of the device. The fuses can only be changed by a device programmer that supports this feature. The factory default fuse settings are listed in Table 2-2. The factory default fuse settings are chosen to provide the greatest compatibility with the previous AT89S52 device and should only be changed in order to access Fast Mode or new features. See the AT89LP52 datasheet for more detailed information. For existing applications that use an external clock source instead of a crystal or resonator, it is recommended that the CS1 fuse (address 01H) be cleared to 00H to select the external clock configuration. This configuration provides better performance at higher frequencies than driving the on-chip crystal oscillator in open loop mode. Changes to this fuse will only take affect when the power is cycled off and on. Compatibility mode is selected by setting the Compatibility Mode Fuse at address 04H. Other features can be enabled/disabled by changing the respective fuse. Table 2-2. Address Default Factory Fuse Settings Fuse Name 00H Default FFH Clock Source 01H High Speed Crystal Oscillator (XTAL) FFH 02H FFH Start-up Time 03H 2 Description 16 ms Delay FFH 04h Compatibility Mode FFH CPU functions in 12-clock Compatibility mode 05h ISP Enable FFH In-System Programming Enabled 06H User Signature Programming FFH User Signature Programming Disabled 07H Tristate Ports 00H Ports default to Quasi-bidirectional mode 08H In-Application Programming FFH In-Application Programming Disabled 09H R1 Enable FFH Internal 5 MΩ resistor connected to XTAL1 89LP52 Drop-In Replacement of 89S52 3718A–MICRO–9/10 89LP52 Drop-In Replacement of 89S52 3. Compatibility Mode The AT89LP52 has a high performance, single-cycle CPU compatible with the 80C51 instruction set. For ease of migration, the AT89LP52 can operate in a Compatibility execution mode. In Compatibility mode the AT89LP52 CPU uses the six-state machine cycle of the standard 8051 where instruction bytes are fetched every three system clock cycles. Execution times in this mode are identical to AT89S52 with instructions taking 1, 2 or 4 machine cycles. Sub-instruction level operations may not occur at exactly the same point within the instruction as in AT89S52; however, this should be transparent to most users. 3.1 Migrating to Compatibility Mode Users migrating legacy software from AT89S52 to AT89LP52 in Compatibility mode should not need to make any changes to their software provided that the application code does not activate any of the new register bits in existing registers listed in Section 8.1 “Modified Registers” on page 4 in such a manner as to change the behavior of the application. In most cases this should not be an issue. 4. Memory Access The AT89LP52 supports the same memory spaces found on the AT89S52. The program memory has support for 64K bytes of directly addressable application code, with 8K bytes of on-chip Flash program memory and support for up to 56K bytes of external program memory using the standard 80C51 interface. The data memory has 256 bytes of internal RAM and 128 bytes of Special Function Register I/O space, with support for up to 64K bytes of external data memory also using the standard 80C51 interface. Applications that use these memory spaces should not need to be updated in Compatibility mode. 4.1 Program Memory The AT89LP52 supports both internal and external program memory. AT89S52 applications that only use external program memory, by tying the EA pin low, are not supported on the AT89LP52. Program addresses 0000H-1FFFH only resides in internal program memory. External program memory is only available at addresses 2000H–FFFFH. . In Compatibility mode there is no difference when executing from internal versus external program memory. 5. Reset The AT89LP52 has a user-selectable external reset pin. To support this feature, the former External Access pin (EA) of the AT89S52 is replaced by the Polarity pin (POL). When this pin is at VCC, the RST pin is active-HIGH with a pull-down resistor, compatible with AT89S52; and when this pin is at GND, the RST pin is active-LOW with a pull-up resistor. As a consequence the external access feature is NOT supported on the AT89LP52; however, external execution is still allowed for addresses 2000H–FFFFH. The majority of legacy AT89S52 applications have EA tied high for internal execution. Dropping an AT89LP52 into these applications will result in POL tied high for an AT89S52- compatible active-HIGH reset. If an AT89S52 application has EA tied low, the user must either modify the board to connect POL to high or disconnect the RST pin from any board-level signals. The POL pin must be driven high or low at all times. It does not have an internal pull-up or pulldown. The level of the POL pin is sampled during power-up. It is not possible to change the polarity once the device is operational. An active-low reset is recommended for all new applications. 3 3718A–MICRO–9/10 If In-System Programming is disabled, the only way to program the AT89LP52 is if RST is active during power-up. ISP is always enabled at power-up and will remain active until the first deactivation of RST. Users wishing to further program the device in such a state must have a means of connecting RST to VCC or GND at power-up, depending on the polarity. 6. System Clock The system clock source of the AT89LP52 is selectable between the crystal oscillator, an externally driven clock and an internal 1.8432 MHz auxiliary oscillator. In addition the crystal oscillator can operate in either high-power or low-power mode and optionally have an on-chip 5 MΩ resistor connected between XTAL1 and GND for improved startup. The clock source and options are controlled by the User Fuses. Section 2.1 “Configuration Fuses” on page 2. The A89LP52 is factory-configured to use the crystal oscillator in high-power mode. 6.1 Clock Divider The System Clock Divider scales the internal system clock versus the oscillator clock source. In Compatibility mode the system clock frequency is divided by 2 from the externally supplied XTAL1 frequency by default for compatibility with standard 8051s (12 clocks per machine cycle). 6.2 Timer Prescaler A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the Watchdog. The TPS3-0 bits in the CLKREG SFR control the prescaler. In Compatibility mode TPS3-0 defaults to 0101B, which causes the timers to count once every machine cycle. f SYS f TIMER = -------------------TPS + 1 7. I/O Ports The default port settings depend on the Tristate-Port User Fuse. For Compatibility mode, this fuse setting should be disabled, so that ports P1, P2 and P3 start in quasi-bidirectional mode and P0 starts in open-drain mode. 8. Special Function Registers This section lists the Special Function Registers (SFRs) that are new or modified in AT89LP52 from those in AT89S52. 8.1 Modified Registers The following registers are modified in their bit definitions from AT89S52. The highlighted bits are new in AT89LP52. For compatiblity with 89S52, the user should not activate these bits. For more detailed information see the AT89LP52 datasheet. Table 8-1. AUXR Register Bits AUXR (8EH) 7 6 5 4 3 2 1 0 AT89S52 – – – WDIDLE DISRTO – – DISALE AT89LP52 (Compatibility mode) – – – WDIDLE DISRTO WS0 EXRAM DISALE 4 89LP52 Drop-In Replacement of 89S52 3718A–MICRO–9/10 89LP52 Drop-In Replacement of 89S52 Note: 1. In Compatibility mode WS1 = 0. Table 8-2. AUXR1 Register Bits AUXR1 (A2H) 7 6 5 4 3 2 1 0 AT89S52 – – – – – – – DPS AT89LP52 DPU1 DPU0 DPD1 DPD0 SIGEN 0 – DPS 7 6 5 4 3 2 1 0 AT89S52 SMOD – – – GF1 GF0 PD IDL AT89LP52 SMOD1 SMOD0 PWDEX POF GF1 GF0 PD IDL Table 8-3. PCON Register Bits PCON (87H) 8.2 New Registers The following registers are additional registers not found in AT89S52. For compatibility with 89S52, the user should not access these registers. For more detailed information see the AT89LP52 datasheet Table 8-4. CLKREG Register Bits CLKREG (8FH) Reset = Note: (1) 7 6 5 4 3 2 1 0 TPS3 TPS2 TPS1 TPS0 CDV2 CDV1 CDV0 – 1. The reset value of CLKREG is 0000000B in Fast mode and 01010010B in Compatibility mode. Table 8-5. IPH Register Bits IPH (B7H) 7 6 5 4 3 2 1 0 Reset = XX00 0000 – – PT2H PSH PT1H PX1H PT0H PX0H 7 6 5 4 3 2 1 0 IAP AERS LDPG MWEN DMEN ERR BUSY WRTINH Table 8-6. MEMCON Register Bits MEMCON (96H) Reset = 0000 0XXX Table 8-7. P4 Register Bits P4 (C0H) 7 6 5 4 3 2 1 0 P4.7 P4.6 P4.5 P4.4 – – – – 7 6 5 4 3 2 1 0 P3M1 P3M0 P2M1 P2M0 P1M1 P1M0 P0M1 P0M0 Reset = 1111 XXXX Table 8-8. PMOD Register Bits PMOD (C1H) Reset = (2) 2. The reset value of PMOD is 0101 0101B when Tristate-Port Fuse is enabled and 0000 0011B when disabled 5 3718A–MICRO–9/10 Table 8-9. SADDR Register Bits SADDR (A9H) Reset = 0000 0000 Table 8-10. Reset = 0000 0000 5 4 3 2 1 0 SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0 7 6 5 4 3 2 1 0 SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0 7 6 5 4 3 2 1 0 T1OE T0OE SPEN – – – – – 6 5 4 3 2 1 0 SWRST WDTOVF WDTEN TCONB Register Bits TCONB (91H) Reset = 000X XXXX Table 8-12. 6 SADEN Register Bits SADEN (B9H) Table 8-11. 7 WDTCON Register Bits WDTCON (A6H) Reset = 0000 0XX0 7 PS2 PS1 PS0 WDIDLE DISRTO (3) 3. WDTCON.4 and WDTCON.3 function as WDIDLE and DISRTO only in Fast mode. In Compatibility mode these bits are in AUXR. 9. Revision History 6 Revision No. History Revision A – Sept. 2010 • Initial Release 89LP52 Drop-In Replacement of 89S52 3718A–MICRO–9/10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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