SAM G53G / SAM G53N Atmel | SMART ARM-based Flash MCU DATASHEET Description The Atmel® | SMART SAM G53 is a series of Flash microcontrollers based on the high-performance 32-bit ARM ® Cortex ® -M4 RISC processor. It operates at a maximum speed of 48 MHz and features up to 512 Kbytes of Flash and 96 Kbytes of SRAM. The peripheral set includes one USART, two UARTs, three I2C-bus interfaces (TWI), up to two SPIs, two three-channel general-purpose 16-bit timers, two I2S controllers with two-way, one-channel pulse density modulation, one realtime timer (RTT) and one 8-channel 12-bit ADC. The Atmel | SMART SAM G53 devices have two software-selectable low-power modes: Sleep and Wait. In Sleep mode, the processor is stopped while all other functions can be kept running. In Wait mode, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on events, including partial asynchronous wake-up (SleepWalking™). The Event System allows peripherals to receive, react to and send events in Active and Sleep modes without processor intervention. A general-purpose microcontroller with the best ratio in terms of reduced power consumption, processing power and peripheral set, the SAM G53 series sustains a wide range of applications including consumer, industrial control, and PC peripherals. The device operates from 1.62V to 3.6V and is available in a 49-ball WLCSP package and a 100-pin LQFP package. Features Core ̶ ARM Cortex-M4 up to 48 MHz ̶ Memory Protection Unit (MPU) ̶ DSP Instructions ̶ Floating Point Unit (FPU) ̶ Thumb®-2 instruction set Memories ̶ 512 Kbytes embedded Flash ̶ 96 Kbytes embedded SRAM System ̶ Embedded voltage regulator for single-supply operation Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 ̶ Power-on reset (POR) and Watchdog for safe operation ̶ Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for RTT or device clock ̶ High-precision 8/16/24 MHz factory-trimmed internal RC oscillator. In-application trimming access for frequency adjustment ̶ Slow clock internal RC oscillator as permanent Low-power mode device clock ̶ PLL range from 24 MHz to 48 MHz for device clock ̶ 28 peripheral DMA (PDC) channels ̶ 256-bit General-Purpose Registers (GPBR) ̶ 16 external interrupt lines Power consumption in Active mode ̶ 102 µA/MHz running Fibonacci in SRAM Low power modes (typical value) ̶ Wait mode down to 8 µA ̶ Wake-up time less than 5 µs ̶ Asynchronous partial wake-up (SleepWalking™) on UART and TWI Peripherals ̶ One USART with SPI mode ̶ Two Inter-IC Sound Controllers (I2S) Two UARTs ̶ Three Two-Wire Interface (TWI) modules featuring two TWI masters and one high-speed TWI slave ̶ One fast SPI at up to 24Mbit/s ̶ Two three-channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes ̶ One 32-bit Real-Time Timer (RTT) Analog One 8-channel ADC, resolution up to 12 bits, sampling rate up to 800 kSps Package ̶ 49-ball WLCSP ̶ 100-pin LQFP, 14 x 14 mm, pitch 0.5 mm Temperature operating range ̶ 2 ̶ Up to 38 controllable I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die series resistor termination. Individually programmable open-drain, pull-up and pull-down resistor and synchronous output ̶ Two-way one-channel Pulse Density Modulation (PDM) (interfaces up to two microphones in PDM mode) I/O ̶ ̶ Industrial (-40 °C to +85 °C) SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 1. Configuration Summary Table 1-1 summarizes the SAM G53 device configurations. Table 1-1. Configuration Summary Feature SAM G53G19 SAM G53N19 Flash 512 Kbytes 512 Kbytes SRAM 96 Kbytes 96 Kbytes Package WLCSP49 LQFP100 Number of PIOs 38 38 Event System Yes Yes 8 channels 8 channels Performance: Performance 800 KSps at 10-bit resolution 800 KSps at 10-bit resolution 200 KSps at 11-bit resolution 200 KSps at 11-bit resolution 50 KSps at 12-bit resolution 50 KSps at 12-bit resolution 6 channels 6 channels 16-bit Timer (3 external channels) (3 external channels) I2SC/PDM 2 / 1-channel 2-way 2 / 1-channel 2-way 12-bit ADC PDC Channels 28 28 USART/UART 1/2 1/2 SPI 1 1 2 masters at 400Kbits/s and 2 masters 400Kbits/s and 1 slave at 3.4Mbit/s 1 slave 3.4Mbit/s TWI SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 3 Block Diagram SAM G53 Block Diagram V TST U O D D D D IO T TD I TD O TM S TC /SW K D /S IO W JT C LK A G S E L Figure 2-1. V 2. Voltage Regulator PCK[2:0] PLL RC OSC 8/16/24 MHz Power Management Controller JTAG and Serial Wire In-Circuit Emulator WKUP[15:0] XIN XOUT Cortex-M4 Processor fMAX 48 MHz 3-20 MHz Crystal Osc. or External Osc. (bypass) Supply Controller DSP Tamper Detection 32K Crystal Osc. or External Osc. (bypass) XIN32 XOUT32 ERASE 24-bit SysTick Counter NVIC MPU FPU I/D Flash Unique Identifier S User Signature 32K RC Power-on Reset Real-time Clock 256-bit GPBR Real-time Timer VDDCORE 3-layer Bus Matrix fMAX 48 MHz Reset Controller NRST Watchdog Timer M M VDDIO S M Bridge PDC Supply Monitor Flash S 512 Kbytes S 96 Kbytes SRAM ROM(1) S 8 Kbytes PIOA/PIOB System Controller PDMDAT0 PDMCLK0 PDMIC0 PDMIC1 I2SCK[1:0] I2SWS[1:0] I2SDI[1:0] I2SDO[1:0] I2SMCK[1:0] PDC PDC SPI PDC PDC 2 x I2SC PDC 3 x TWI SCK TXD RXD RTS CTS PDC PDC Timer Counter A TC[0..2] 2 x UART Timer Counter B TC[3..5] AD[7:0] ADTRG PDC 12-bit ADC VDDIO Note: 4 TWCK[2:0] TWD[2:0] USART PDC URXD[1:0] UTXD[1:0] NPCS0 NPCS1 MISO MOSI SPCK 1. The ROM is reserved for future use. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Event System TCLK[2:0] TIOA[2:0] TIOB[2:0] 3. Signal Description Table 3-1 provides details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripheral I/O Lines, Voltage Regulator, ADC Power Supply Power – – VDDOUT Voltage Regulator Output Power – – – VDDCORE Core Chip Power Supply Power – – Connected externally to VDDOUT GND Ground Ground – – – Input – VDDIO Reset state: Output – – - PIO input Input – VDDIO - Internal pull-up disabled Output – – - Schmitt Trigger enabled 1.62V to 3.6V Clocks, Oscillators and PLLs XIN Main Oscillator Input (Bypass mode) XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input (Bypass mode) XOUT32 Slow Clock Oscillator Output Reset state: - PIO input PCK0 - PCK2 Programmable Clock Output Output – – - Internal pull-up enabled - Schmitt Trigger enabled ICE and JTAG TCK Test Clock Input – VDDIO No pull-up resistor TDI Test Data In Input – VDDIO No pull-up resistor TDO Test Data Out Output – VDDIO – TRACESWO Trace Asynchronous Data Out Output – VDDIO – SWDIO Serial Wire Input/Output I/O – VDDIO – SWCLK Serial Wire Clock Input – VDDIO – TMS Test Mode Select Input – VDDIO No pull-up resistor JTAGSEL JTAG Selection Input High VDDIO Pull-down resistor High VDDIO Pull-down (15 kΩ) resistor Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Input SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 5 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage Reference I/O Low VDDIO Pull-up resistor Input – VDDIO Pull-down resistor Comments Reset/Test NRST Microcontroller Reset TST Test Mode Select Universal Ansynchronous Receiver Transceiver - UARTx URXDx UART Receive Data Input – – – UTXDx UART Transmit Data Output – – – PIO Controller - PIOA - PIOB PA0 - PA24 Parallel I/O Controller A I/O – VDDIO Pulled-up input at reset. No pull-down for PA3/PA4/PA14. PB0 - PB12 Parallel I/O Controller B I/O – VDDIO Pulled-up input at reset I/O – VDDIO Wake-up pins are used also as External Interrupt Wake-up Pins WKUP 0-15 Wake-up Pin / External Interrupt Universal Synchronous Asynchronous Receiver Transmitter USART SCK USART Serial Clock I/O – – – TXD USART Transmit Data I/O – – – RXD USART Receive Data Input – – – RTS USART Request To Send Output – – – CTS USART Clear To Send Input – – – Input – – – Timer/Counter - TCx TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A I/O – – – TIOBx TC Channel x I/O Line B I/O – – – Serial Peripheral Interface - SPI MISO Master In Slave Out I/O – – – MOSI Master Out Slave In I/O – – – SPCK SPI Serial Clock I/O – – NPCS0 SPI Peripheral Chip Select 0 I/O Low – – NPCS1 SPI Peripheral Chip Select 1 Output Low – – 6 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 High-speed pad Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage Reference Comments Two-Wire Interface- TWIx TWDx TWIx Two-wire Serial Data I/O – – High-speed pad for TWD0 TWCKx TWIx Two-wire Serial Clock I/O – – High-speed pad for TWDCK0 10-bit Analog-to-Digital Converter - ADCC AD0 - AD7 Analog Inputs Analog – – – ADTRG ADC Trigger Input – – – Inter-IC Sound Controller - I2SCx I2SMCKx Master Clock Output – – – I2SCKx Serial Clock I/O – – – I2SWSx I2S Word Select I/O – – – I2SDIx Serial Data Input Input – – – I2SDOx Serial Data Output Output – – – PDMCLK0 Pulse Density Modulation Clock Output – – – PDMDAT0 Pulse Density Modulation Data Input – – – SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 7 4. Package and Pinout Table 4-1. 4.1 Device Package SAM G53G19 WLCSP49 SAM G53N19 LQFP100 49-ball WLCSP Pinout Table 4-2. 8 SAM G53 Packages SAM G53G19 49-ball WLCSP Pinout A1 PA9 C1 VDDCORE E1 PB2/AD6 G1 VDDIO A2 GND C2 PA11 E2 PB0/AD4 G2 VDDOUT A3 PA24 C3 PA12 E3 PA18/AD1 G3 GND A4 PB8/XOUT C4 PB6 E4 PA14 G4 VDDIO A5 PB9/XIN C5 PA4 E5 PA10 G5 PA22 A6 PB4 C6 PA3 E6 TST G6 PA15 A7 VDDIO C7 PA0 E7 PA7/XIN32 G7 PA6 B1 PB11 D1 PA13 F1 PA20/AD3 B2 PB5 D2 PB3/AD7 F2 PA19/AD2 B3 PB7 D3 PB1/AD5 F3 PA17/AD0 B4 PA2 D4 PB10 F4 PA21 B5 JTAGSEL D5 PA1 F5 PA23 B6 NRST D6 PA5 F6 PA16 B7 PB12 D7 VDDCORE F7 PA8/XOUT32 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 4.2 100-lead LQFP Pinout Table 4-3. SAM G53N19 100-pin LQFP Pinout 1 NC 26 NC 51 NC 76 NC 2 NC 27 NC 52 NC 77 NC 3 NC 28 PA6 53 PA17 78 NC 4 NC 29 VDDIO 54 PA18 79 PA9 5 VDDIO 30 PA16 55 PA19 80 PB5 6 VDDIO 31 PA15 56 PA20 81 GND 7 NRST 32 PA23 57 PB0 82 GND 8 PB12 33 NC 58 PB1 83 GND 9 PA4 34 NC 59 PB2 84 PB6 10 PA3 35 PA22 60 PB3 85 PB7 11 PA0 36 PA21 61 VDDIO 86 PA24 12 PA1 37 VDDIO 62 PA14 87 PB8 13 PA5 38 VDDIO 63 PA13 88 PB9 14 VDDIO 39 GND 64 PA12 89 VDDIO 15 VDDCORE 40 GND 65 PA11 90 PA2 16 VDDCORE 41 GND 66 VDDCORE 91 PB4 17 TEST 42 GND 67 VDDCORE 92 NC 18 PA7 43 GND 68 PB10 93 JTAGSEL 19 PA8 44 VDDOUT 69 PB11 94 VDDIO 20 GND 45 VDDOUT 70 GND 95 VDDIO 21 NC 46 VDDIO 71 GND 96 NC 22 NC 47 VDDIO 72 PA10 97 NC 23 NC 48 VDDIO 73 NC 98 NC 24 NC 49 NC 74 NC 99 NC 25 NC 50 NC 75 NC 100 NC SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 9 5. Power Considerations 5.1 Power Supplies The SAM G53 has several types of power supply pins: VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals. VDDCORE must be connected to VDDOUT. VDDIO pins: Power the peripheral I/O lines, voltage regulator and ADC; voltage ranges from 1.62V to 3.6V. The ground pins GND are common to VDDCORE and VDDIO. 5.2 Voltage Regulator The SAM G53 embeds a core voltage regulator that is managed by the Supply Controller and that supplies the Cortex-M4 core, internal memories (SRAM and Flash logic) and the peripherals. An internal adaptative biasing adjusts the regulator quiescent current depending on the required load current. For adequate input and output power supply decoupling/bypassing, refer to Table 37-4 “VDDCORE Voltage Regulator Characteristics” in the Electrical Characteristics section of the datasheet. 5.3 Typical Powering Schematics The SAM G53 supports a 1.62V to 3.6V single supply mode. The internal regulator input is connected to the source and its output feeds VDDCORE. Power schematics are illustrated in Figure 5-1. To achieve the system performance levels, the internal regulator must be used. Figure 5-1. Single Supply VDDIO Main Supply (1.62V to 3.6V) VDDIO Voltage Regulator VDDOUT VDDCORE 5.4 Functional Modes 5.4.1 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLL. The Power Management Controller can be used to adapt the frequency and to disable the peripheral clocks. 10 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 5.4.2 Wait Mode Wait mode allows the device to achieve very low power consumption levels while remaining in a powered state with a wake-up time of less than 5 µs. Current consumption in Wait mode is typically less than 8 µA (total current consumption). In Wait mode, the clocks of the core, the peripherals and memories are stopped. However, power supplies are maintained to ensure memory and CPU context retention. The wake-up time of 5 µs is achieved when entry into and exit from Wait mode are performed in internal SRAM. The wake-up time increases to 70 µs if entry into Wake-up mode is performed in internal Flash. Wait mode is entered using either the WAITMODE bit in the PMC Clock Generator Main Oscillator register (CKGR_MOR) or the Wait for Event (WFE) instruction. Detailed sequences are provided below. Note that the WFE instruction can add complexity in application state machines due to the fact that the WFE instruction goes along with an event flag of the Cortex core (cannot be managed by the software application). The event flag can be set by interrupts, a debug event or an event signal from another processor. Since an interrupt can take place just before the execution of WFE, WFE takes into account events that happened in the past. As a result, WFE prevents the device from entering Wait mode if an interrupt event has occurred. To work around this complexity, follow the sequence using the WAITMODE bit described below. The Cortex-M4 processor is able to handle external or internal events in order to wake up the core. This is done by configuring the external lines WKUP0–15 as fast start-up wake-up pins (refer to Section 5.5 “Fast Start-up”) or the RTT and RTC alarms for internal events. To enter Wait mode using the WAITMODE bit: 1. Select the 8/16/24 MHz fast RC oscillator as the Main Clock. If frequency of 24 MHz is selected and the code is running from the SRAM, wake-up time is less than 5 µs. 2. Program the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR)(1). 3. Set the number of Flash wait states to 0 by writing a zero to the FWS field in the EEFC Flash Mode Register (EEFC_MR). 4. Write a one to the WAITMODE bit in the PMC Clock Generator Main Oscillator Register (CKGR_MOR). 5. Wait for MCKRDY = 1 in the PMC Status Register (PMC_SR). To enter Wait mode using the WFE instruction: 1. Select the 8/16/24 MHz fast RC oscillator as the Main Clock. If 24 MHz is selected and the code is running on the SRAM, wake-up time is less than 5 µs. 2. Program the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR)(1). 3. Set the number of Flash wait states to 0 by writing a zero to the FWS field in the EEFC Flash Mode Register (EEFC_MR). 4. Write a one to the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR). 5. Ensure that the SLEEPDEEP bit in the System Control Register (SCB_SCR) is cleared. 6. Execute the Wait For Event (WFE) instruction of the processor. Note: 5.4.3 1. Depending on the value of the field FLPM, the Flash enters three different modes: FLPM = 0: Flash in Stand-by mode (low power consumption levels) FLPM = 1: Flash in Deep power-down mode (extra low power consumption levels) FLPM = 2: Flash in Idle mode. Memory ready for Read access. Sleep Mode In Sleep mode, power consumption of the device versus response time is optimized. Only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in Sleep mode is application-dependent. Sleep mode is entered via Wait for Interrupt (WFI) instructions. The processor can be awakened from an interrupt if the WFI instruction of the Cortex-M4 is used. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 11 5.4.4 Low-Power Mode Configuration Summary Table 5-1 summarizes the power consumption, wake-up time and system state in low-power modes. Table 5-1. Mode Low-Power Mode Configuration Summary SUPC 32 kHz Oscillator RTT POR Regulator POR Supply Monitor on VDDIO RAM Power Switch Core Memory Peripherals All RAM powered Wait Mode with Flash in Deeppower-down mode ON OFF 64 Kbytes RAM powered Powered (Not clocked) 32 Kbytes RAM powered Sleep Mode Notes: ON ON Powered Mode Entry FLPM = 1 + WAITMODE = 1 or SLEEPDEEP = 0 +FLPM = 1 + LPM = 1 + WFE Potential Wake-up Sources Core at Wake-up PIO State while in LowPower Mode PIO State at Wake-up Consumptio n (2) (3) <12 µA Any event from: Fast startup through WKUP0–15 pins RTT alarm RTC alarm Clocked back Previous state saved Unchanged <10 µA <8 µA Powered (Not clocked) WFI + SLEEPDEEP = 0 + LPM = 0 Entry mode =WFI interrupt only; any enabled interrupt Clocked back Previous state saved Unchanged (6) Wake-up Time (1) (5) < 5 µs (5) < 5 µs (5) (4) (4) (4) < 5 µs – SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 8/16/24 MHz Fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first instruction is fetched. 2. The external loads on PIOs are not taken into account in the calculation. 3. BOD current consumption is not included. 4. Wake-up from RAM if 24 MHz fast RC oscillator is selected. 5. Values give are typical values. 6. Refer to the section “Power Consumption” in the “Electrical Characteristics”. 12 5.5 Fast Start-up The SAM G53 allows the processor to restart in a few microseconds while the processor is in Wait mode. A fast start-up can occur upon detection of a low level on one of the 18 sources of wake-up (2 internal and 16 external). The fast restart circuitry is fully asynchronous and provides a fast start-up signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the PMC restarts from the last fast RC selected (the embedded 24 MHz fast RC oscillator), switches the master clock on the last clock of RC oscillator and reenables the processor clock. At the wake-up of the Wait mode, the code is executed in the SRAM. Figure 5-2. Start-up Sequence Standby Mode cpu_clock Startup Time cpu clock t<5us PLL stdby PLL startup<200us 8/16/24 MHz PLL t<70us Flash Ready Reset signals resynchronized on specific clocks SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 13 6. Architecture 6.1 Peripheral DMA Controller The Peripheral DMA Controller handles transfer requests from the channel. Priorities are defined in Table 6-1, with Channel Number 0 as highest priority. Table 6-1. 14 Peripheral DMA Controller Instance Name Channel T/R Channel Number MEM2MEM Transmit 27 SPI Transmit 26 TWI1 Transmit 25 TWI2 Transmit 24 UART0 Transmit 23 UART1 Transmit 22 USART Transmit 21 I2SC1 Transmit 19, 20 I2SC0 Transmit 17, 18 TWI0 Transmit 16 MEM2MEM Receive 15 TC0::TC0 Receive 14 SPI Receive 13 TWI1 Receive 12 TWI2 Receive 11 UART0 Receive 10 UART1 Receive 9 USART Receive 8 PDMIC1 Receive 7 PDMIC0 Receive 6 I2SC1 Receive 4, 5 I2SC0 Receive 2, 3 ADC Receive 1 TWI0 Receive 0 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 7. Product Mapping Figure 7-1. SAM G53 Product Mapping 0x00000000 Address memory space Code 0x00000000 0x400E0000 System Controller Boot Memory Code Reserved 0x00400000 0x400E0200 Internal Flash 0x20000000 MATRIX 0x400E0400 0x00800000 Internal ROM Internal SRAM PMC 5 0x400E0600 0x00C00000 Reserved 0x40000000 UART0 0x1FFFFFFF Peripherals 8 0x400E0740 CHIPID Internal SRAM 0x20000000 0x400E0800 SRAM 0x60000000 UART1 9 0x400E0A00 0x20080000 Undefined (Abort) Reserved 0x40000000 6 Reserved Peripherals 0x40000000 0xE0000000 EFC 0x400E0C00 0x400E0E00 I2SC0 System 11 0x400E1000 I2SC1 17 0x40008000 SPI 0xFFFFFFFF PIOA 16 0x40004000 21 0x4000C000 PIOB 12 0x400E1200 Reserved Reserved 0x40010000 TC0 0x400E1400 SYSC TC0 23 +0x40 TC0 offset block peripheral ID (+ : wired-or) TC2 25 0x40014000 TC1 1 SYSC 24 +0x80 TC0 RSTC +0x10 TC1 SUPC +0x30 SYSC TC3 RTT 26 +0x40 TC1 3 +0x50 SYSC TC4 27 +0x80 TC1 WDT 4 +0x60 TC5 28 0x40018000 Reserved TWI0 19 0x4001C000 +0x90 SYSC TWI1 20 0x40020000 GPBR 0x400E1600 Reserved Reserved 0x40024000 0x4007FFFF USART 14 0x40028000 MEM2MEM 15 0x4002C000 PDMIC0 13 0x40030000 PDMIC1 18 0x40034000 Reserved 0x40038000 ADC 29 0x4003C000 Reserved 0x40040000 TWI2 22 0x40044000 Reserved 0x40048000 Reserved 0x4004C000 Reserved 0x400E0000 System Controller 0x400E2600 Reserved 0x60000000 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 15 8. Boot Loader The SAM G53 devices ship with a factory-programmed boot loader in Flash. The Flash loader downloads code either through the SPI or through the TWI0. The Boot loader mode is entered automatically on power-up if no valid firmware is detected in the Flash. A valid firmware is detected by performing a CRC on the content of the Flash. If the CRC is correct, the application is started. Otherwise, the Boot loader mode is entered. Alternatively, the Boot loader mode can be forced by applying low pulses on the NRST line. The NRST should be asserted 10 times for a minimum of 1 µs at an interval less than 50 ms. When the boot loader detects this sequence, it asserts the pin PA01 (NCHG) low as an acknowledge. The Boot loader mode initializes the TWI0 in Slave Mode with the I2C address 0x26 and the SPI in Slave Mode, 8bit data length, SPI Mode 1. Table 8-1 provides information on the pins used by the boot loader. Table 8-1. Boot Loader Pin Description Pin Name Function Boot Loader Use Description PA01 NCHG Driven at 0 or pulled up Boot loader handshake PA03 TWD Open drain input/output TWI/I2C data line PA04 TWCK Open drain input/output TWI/I2C clock PA11 NPCS0/NSS Input NSS, SPI slave select PA12 MISO Push-pull output SPI master in slave out PA13 MOSI Input SPI master out slave in PA14 SPCK Input SPI clock For further details on boot loader operations, refer to the application note AT09002 – Atmel SAM I²C - SPI Bootloader" on www.atmel.com. 16 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 9. Memories 9.1 Internal SRAM The SAM G53 embeds a total of 96 Kbytes of high-speed SRAM. The SRAM is accessible over the Cortex-M4 system bus at address 0x2000 0000. The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 and 0x23FF FFFF. The SRAM is composed of three blocks of 32 Kbytes. The second and third blocks have a power switch. Each power switch controls the supply of the SRAM block to save power. The control of the power switch (PSWITCHx) is in the SUPC_MR register. 9.2 Embedded Flash 9.2.1 Flash Overview The memory is organized in sectors. Each sector comprises 64 Kbytes. The first sector of 64 Kbytes is divided into three smaller sectors. The three smaller sectors are comprised of two sectors of 8 Kbytes and one sector of 48 Kbytes. Refer to Figure 91. Figure 9-1. Global Flash Organization Flash Organization Sector size Sector name 8 Kbytes Small Sector 0 8 Kbytes Small Sector 1 48 Kbytes Larger Sector 64 Kbytes Sector 1 64 Kbytes Sector n Sector 0 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 17 Each sector is organized in pages of 512 bytes. For sector 0: The smaller sector 0 has 16 pages of 512 bytes. The smaller sector 1 has 16 pages of 512 bytes. The larger sector has 96 pages of 512 bytes. From sector 1 to n: The rest of the array is composed of 64 Kbytes sectors of 128 pages of 512 bytes each. Refer to Figure 9-2. Figure 9-2. Flash Sector Organization Flash Sector Organization A sector size is 64 Kbytes Sector 0 Sector n 16 pages of 512 bytes Smaller sector 0 16 pages of 512 bytes Smaller sector 1 96 pages of 512 bytes Larger sector 128 pages of 512 bytes The SAM G53 Flash size is 512 Kbytes. Refer to Figure 9-3 for the organization of the Flash. Figure 9-3. Flash Size Flash 512 Kbytes 2 * 8 Kbytes 1 * 48 Kbytes 7 * 64 Kbytes The following erase commands can be used depending on the sector size: 18 8 Kbyte small sector ̶ Erase and write page(EWP) ̶ Erase and write page and lock (EWPL) ̶ Erase sector (ES) with FARG set to a page number in the sector to erase ̶ Erase pages (EPA) with FARG [1:0] = 0 to erase four pages or FARG [1:0] = 1 to erase eight pages. FARG [1:0] = 2 and FARG [1:0] = 3 must not be used. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 48 Kbyte and 64 Kbyte sectors ̶ One block of 8 pages inside any sector, with the command Erase pages (EPA) with FARG[1:0] = 1 ̶ One block of 16 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 2 ̶ One block of 32 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 3 ̶ One sector with the command Erase sector (ES) and FARG set to a page number in the sector to erase Entire memory plane ̶ The entire Flash, with the command Erase all (EA) The memory has one additional reprogrammable page that can be used as page signature by the user. It is accessible through specific modes, for erase, write and read operations. Erase pin assertion will not erase the user signature page. 9.2.2 Enhanced Embedded Flash Controller The Enhanced Embedded Flash Controller manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB. The Enhanced Embedded Flash Controller ensures the interface of the Flash block. It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 9.2.3 Flash Speed The user must set the number of wait states depending on the frequency used: For more details, refer to the section “AC Characteristics” in the “Electrical Characteristics”. 9.2.4 Lock Regions Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 9-1. Lock Bit Number Product Number of Lock Bits Lock Region Size SAM G53 64 8 Kbytes If the erase or program command of a locked region occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 9.2.5 User Signature Each device contains a user signature of 512 bytes. It can be used by the user to store user information such as trimming, keys, etc., that the customer does not want to be erased by asserting the ERASE pin or by software ERASE command. Read, write and erase of this area is allowed. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 19 9.2.6 Unique Identifier The SAMG53 Flash contains 2 pages of 512bytes called unique identifier. These 2 pages are read-only and cannot be erased even by the Erase pin. Each device integrates its own 128-bit unique identifier. These bits are factory-configured and cannot be changed by the user. Some bytes of the user signature page are reserved for the trimming information of the 32 kHz RC Oscillator and the internal regulator. The mapping is as follows: 9.2.7 Bytes [15..0]: 128 bits for unique identifier Bytes [47..16]: Atmel reserved Bytes [49..48]: Measured frequency (on tester) of the internal 32 kHz RC with VVDDIO range [1.62V to 2.5V] (measurement performed at 25°C) Bytes[511..50]: Atmel reserved. General-Purpose Non-Volatile Memory Bits The SAM G53 features three GPNVM bits that can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. Table 9-2. 9.2.8 General-purpose Non-volatile Memory Bits GPNVM Bit[#] Function 0 Security bit 1 Flash BOOT mode selection 2 Reserved (do not use, must be always @0x0) Boot Strategies The general-purpose NVM, GPNVM bit 1, is used to boot from the Flash. The GPNVM bits can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. Setting GPNVM bit 1 selects the boot from the Flash. Asserting ERASE clears the GPNVM bit 1. Thus GPNVM1 must be set to BOOT on Flash and the boot loader is removed from Flash. 9.2.9 Calibration Bits The GPNVM bits are used to calibrate the POR, the voltage regulator and the 8/16/24 MHz RC oscillator. These bits are factory-configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 9.2.10 Security Bit The SAM G53 features a security bit, based on a specific general-purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, core registers and internal peripherals through the ICE interface is forbidden. This ensures the confidentiality of the code programmed in the Flash. The security bit can only be enabled, through the command “Set GPNVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin to 1, and after a full Flash erase is 20 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 performed. When the security bit is deactivated, all accesses to the Flash, SRAM, core registers, internal peripherals are permitted. The ERASE pin integrates a permanent pull-down. Consequently, it can be left unconnected during normal operation. However, it is recommended, in harsh environments, to connect it directly to GND if the erase operation is not used in the application. To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in Table 37-41 “AC Flash Characteristics”. The erase operation is not performed when the system is in Wait mode with the Flash in Deep-power-down mode. To make sure that the erase operation is performed after power-up, the system must not reconfigure the ERASE pin as GPIO or enter Wait mode with Flash in Deep-power-down mode before the ERASE pin assertion time has elapsed. With the following sequence, in any case, the erase operation is performed: 1. Assert the ERASE pin (High) 2. Assert the NRST pin (Low) 3. Power cycle the device Maintain the ERASE pin high for at least the minimum assertion time. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 21 10. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. Refer to the section on the Supply Controller (SUPC). 10.1 System Controller and Peripherals Mapping Refer to Section 7-1 “SAM G53 Product Mapping”. All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on Reset, Supply Monitor The SAM G53 embeds three features to monitor, warn and/or reset the chip: 10.3 Power-on reset on VDDIO Power-on reset on VDDCORE Supply monitor on VDDIO Reset Controller The Reset Controller is based on a power-on reset cell. The Reset Controller returns the source of the last reset to software: general reset, wake-up reset, software reset, user reset or watchdog reset. The Reset Controller controls the internal resets of the system and the input/output of the NRST pin. It shapes a reset signal for the external devices, simplifying the connection of a push-button on the NRST pin to implemement a manual reset. By default, the NRST pin is configured as an input. The configuration of the Reset Controller is saved as supplied on VDDIO. 10.4 Supply Controller (SUPC) The Supply Controller controls the power supplies of each section of the processor and the peripherals (via voltage regulator control). The Supply Controller has its own reset circuitry and is clocked by the 32 kHz slow clock generator. The reset circuitry is based on a zero-power power-on reset cell and a POR (power-on reset) cell. The zero-power power-on reset allows the Supply Controller to start properly, while the software-programmable POR allows detection of either a battery discharge or main voltage loss. The slow clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The user can also set the crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The slow clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the slow clock source. The Supply Controller starts up the device by sequentially enabling the internal power switches and the voltage regulator, then it generates the proper reset signals to the core power supply. It is also used to set the system in different low power modes and to wake it up from a wide range of events. 22 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 10.5 Clock Generator The Clock Generator is made up of: One low-power 32768 Hz slow clock oscillator with Bypass mode One low-power RC oscillator One factory-programmed fast RC oscillator with three selectable output frequencies: 8, 16 or 24 MHz. At startup, 8 MHz is selected. One 24 to 48 MHz programmable PLL that provides the clock MCK to the processor and to the peripherals. The PLL has an input divider to offer a wider range of output frequencies from the main clock input Figure 10-1. Clock Generator Block Diagram Clock Generator XTALSEL On Chip 32k RC OSC XIN32 XOUT32 XIN XOUT Slow Clock SLCK Slow Clock Oscillator 3-20 MHz Main Oscillator Main Clock MAINCK On Chip 12/8/4 MHz RC OSC MAINSEL PLLA Clock PLLACK PLL and Divider A Status Control Power Management Controller The 32 kHz RC oscillator frequency is measured at ambient temperature during device test. Its value is stored in the Flash signature page. The frequency accuracy is given in Table 37-16 “32 kHz RC Oscillator Characteristics”. When the application uses the 32 kHz RC oscillator, the value of the frequency accuracy of the 32 kHz RC oscillator must be read and included in the API to use the 32 kHz RC oscillator at 32 kHz. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 23 10.6 Power Management Controller The Power Management Controller provides clock signals to the system: Processor clock HCLK Free-running processor clock FCLK Cortex SysTick external clock Master clock MCK, specifically to the matrix and the memory interfaces Independent peripheral clocks, typically at the frequency of MCK Three programmable clock outputs: PCK0, PCK1 and PCK2 The Supply Controller selects either the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at start-up the chip runs out of the master clock using the fast RC oscillator running at 8 MHz. The user can trim the 8, 16 and 24 MHz RC oscillator frequency by software. Figure 10-2. SAM G53 Power Management Controller Block Diagram Processor Clock Controller HCK int Sleep Mode Divider /8 SystTick FCLK Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 MCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller SLCK MAINCK PLLCK ON/OFF Prescaler /1,/2,/3/4,...,/64 pck[..] The SysTick calibration value is fixed to 6000 which allows the generation of a time base of 1 ms with SystTick clock to MHz (max HCLK 48 MHz/8 = 6000, so STCALIB = 0x1770). 10.7 24 Watchdog Timer 16-bit key-protected only-once-programmable counter Windowed, prevents the processor to be in a dead-lock on the watchdog access SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 10.8 10.9 SysTick Timer 24-bit down counter Self-reload capability Flexible system timer Real-Time Timer Real-Time Timer, allowing backup of time with different accuracies 32-bit free-running backup counter ̶ Integrates a 16-bit programmable prescaler running on slow clock ̶ Alarm register generates a wake-up of the system through the Shutdown Controller ̶ ̶ Wake-up from Wait mode through the Power Management Controller 10.10 Real Time Clock Low power consumption Full asynchronous design Two hundred year calendar Programmable periodic interrupt Alarm and update parallel load Control of alarm and update Time/Calendar Data In 10.11 General-Purpose Registers Eight 32-bit general-purpose registers 10.12 Nested Vectored Interrupt Controller Forty-seven maskable interrupts, external to NVIC Sixteen priority levels Dynamic reprioritization of interrupts Priority grouping Support for tail-chaining and late arrival of interrupts ̶ ̶ Selection of preempting interrupt levels and non-preempting interrupt levels Back-to-back interrupt processing without the overhead of state saving and restoration between interrupts Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25 10.13 Chip Identification Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. SAM G53 Chip ID Registers Chip Name CHIPID_CIDR CHIPID_EXID SAM G53G19 Rev A 0X247E_0AE0 0x0 SAM G53N19 Rev A 0X247E_0AE8 0x0 SAM G53G19 Rev B 0X247E_0AE1 0x0 SAM G53N19 Rev B 0X247E_0AE9 0x0 JTAG ID: 0x05B3_C03F 10.14 PIO Controllers Two PIO Controllers, PIOA and PIOB, that control a maximum of 25 I/O lines Fully programmable through Set/Clear Registers Table 10-2. 26 PIO Lines Available Depending on Pin Count Version 49 Pins 100 Pins PIOA 25 25 PIOB 13 13 Multiplexing of four peripheral functions per I/O line For each I/O line (whether assigned to a peripheral or used as general purpose I/O): ̶ Input change, rising edge, falling edge, low level and level interrupt ̶ Debouncing and glitch filter ̶ Multi-drive option enables driving in open drain ̶ Programmable pull-up on each I/O line ̶ Pin data status register, supplies visibility of the level on the pin at any time ̶ Additional interrupt modes on a programmable event: rising edge, falling edge, low level or high level ̶ Lock of the configuration by the connected peripheral Selection of the drive level Synchronous output, provides Set and Clear of several I/O lines in a single write Write Protect Registers Programmable Schmitt trigger inputs SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 10.15 Peripheral Identifiers Table 10-3 defines the peripheral identifiers of the SAM G53. A peripheral identifier is required: for the control of the peripheral interrupts by the Nested Vectored Interrupt Controller to enable/disable the peripheral clocks by means of the Peripheral Clock Enable and Disable registers (PMC_PCERx, PMC_PCDRx) in the Power Management Controller. The external interrupts are connected to WKUP pins. Table 10-3. Peripheral Identifiers Instance ID Instance Name NVIC Interrupt PMC Clock Control Instance Description 0 SUPC X – Supply Controller 1 RSTC X – Reset Controller 2 – X – Reserved 3 RTT X – Real Time Timer 4 WDT X – Watchdog Timer 5 PMC X – Power Management Controller 6 EFC X – Enhanced Flash Controller 7 – – – Reserved 8 UART0 X X UART 0 9 UART1 X X UART 1 10 – – – Reserved 11 PIOA X X Parallel I/O Controller A 12 PIOB X X Parallel I/O Controller B 13 PDMIC0 X X PDM 0 14 USART X X USART 15 MEM2MEM X X MEM2MEM 16 I2SC0 X X I2SC0 17 I2SC1 X X I2SC1 18 PDMIC1 X X PDM 1 19 TWI0 X X Two-Wire Interface 0 HS 20 TWI1 X X Two-Wire Interface 1 21 SPI X X Serial Peripheral Interface 22 TWI2 X X Two-Wire Interface 2 23 TC0 X X Timer/Counter 0 24 TC1 X X Timer/Counter 1 25 TC2 X X Timer/Counter 2 26 TC3 X X Timer/Counter 3 27 TC4 X X Timer/Counter 4 28 TC5 X X Timer/Counter 5 29 ADC X X Analog-to-Digital Converter SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27 Table 10-3. 28 Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt PMC Clock Control Instance Description 30 ARM X – FPU 31 WKUP0 X – External interrupt 0 32 WKUP1 X – External interrupt 1 33 WKUP2 X – External interrupt 2 34 WKUP3 X – External interrupt 3 35 WKUP4 X – External interrupt 4 36 WKUP5 X – External interrupt 5 37 WKUP6 X – External interrupt 6 38 WKUP7 X – External interrupt 7 39 WKUP8 X – External interrupt 8 40 WKUP9 X – External interrupt 9 41 WKUP10 X – External interrupt 10 42 WKUP11 X – External interrupt 11 43 WKUP12 X – External interrupt 12 44 WKUP13 X – External interrupt 13 45 WKUP14 X – External interrupt 14 46 WKUP15 X – External interrupt 15 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 10.16 Peripherals Signals Multiplexing on I/O Lines The SAM G53 features two PIO controllers, PIOA and PIOB, which multiplex the I/O lines of the peripheral set. Each line can be assigned to one of two peripheral functions: A or B. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO controllers. Note that some peripheral functions which are output only, might be duplicated within both tables. 10.16.1 PIO Controller A Multiplexing Table 10-4. Note: Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B Extra Function System Function PA0 I2SCK0 TIOA0 WKUP0 – PA1 I2SWS0 TIOB0 WKUP1 – PA2 TCLK0 I2SDI0 WKUP2 – PA3 TWD0 I2SDO0 – – PA4 TWCK0 I2SMCK0 – – PA5 RXD NPCS1 WKUP4 – PA6 TXD PCK0 – – PA7 – – – XIN32 PA8 – ADTRG WKUP5 XOUT32 PA9 URXD0 PDMDAT0 WKUP6 – PA10 UTXD0 PDMCLK0 – – PA11 NPCS0 – – – PA12 MISO – – – PA13 MOSI – – – PA14 SPCK – WKUP8 – PA15 RTS(1) SCK – – PA16 CTS TIOB1 WKUP7 – PA17 I2SDO0 PCK1 AD0 – PA18 I2SMCK0 PCK2 AD1 – PA19 TCLK1 I2SCK1 AD2 – PA20 TCLK2 I2SWS1 AD3 – PA21 TIOA2 PCK1 WKUP9 – PA22 TIOB2 I2SDI1 WKUP10 – PA23 I2SDO1 TIOA1 WKUP3 – PA24 I2SMCK1 – WKUP11 – 1. In USART SPI Master mode, RTS cannot be used. Management of the Slave Select (NSS) must be done with a GPIO. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29 10.16.2 PIO Controller B Multiplexing Table 10-5. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B Extra Function System Function PB0 – TWD2 AD4 – PB1 – TWCK2 AD5 – PB2 URXD1 NPCS1 AD6/WKUP12 – PB3 UTXD1 PCK2 AD7/WKUP13 – PB4 – – – TDI PB5 – – – TDO/ TRACESWO PB6 – – – TMS/SWDIO PB7 – – – TCK/SWCLK PB8 TWD1 – WKUP14 XOUT PB9 TWCK1 – WKUP15 XIN PB10 TWD1(Note:) TWD2(Note:) – – – – – ERASE PB11 TWCK1 PB12 (Note:) – (Note:) TWCK2 – Note: Each TWI (TWI1,TWI2) can be routed on two different pairs of IOs. TWI1 and TWI2 share one pair of IOs (PB10 and PB11). The configuration of the shared IOs determine which TWI is selected. 10.16.2.1 TWI Muxing on PB10 and PB11 The selection of the TWI used in PB10 and PB11 is determined by the configuration of PB10 and PB11. Three modes are possible: Normal mode, Alternative mode TWI1 and Alternative mode TWI2. Normal Mode Only TWI1 used: PB09 and PB08 must be configured as PIO Peripheral A Only TWI2 used: PB00 and PB01 must be configured as PIO Peripheral B Both TWI1 and TWI2 used: PB09 and PB08 must be configured as PIO Peripheral A and PB00 and PB01 must be configured as PIO Peripheral B Alternative Mode TWI1 TWI1 is muxing on PB10 and PB11: PB10 and PB11 must be configured as PIO Peripheral A. PB8 and PB9 can be configured as GPIO, WKUP pin or XIN, XOUT. PB8 and PB9 cannot be used as peripherals Alternative Mode TWI2 TWI2 is muxing on PB10 and PB11: PB10 and PB11 must be configured as PIO Peripheral B. PB0 and PB1 can be configured as GPIO, Analog Input. PB0 and PB1 cannot be used as peripherals Example: Alternative Mode TWI1 30 PB10 is driven by TWD1 signal if the PB10 is configured as peripheral (PIO_PSR[10]=1 and PIO_ABCDSR1[10]=PIO_ABCDSR2[10]=0). PB11 is driven by TWCK1 signal if the PB11 is configured as peripheral (PIO_PSR[11]=1 and PIO_ABCDSR1[11]=PIO_ABCDSR2[11]=0). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 10-6. TWI Multiplexing Requirement Configuration Normal mode TWI1 and/or TWI2 Used Alternative mode TWI1 Alternative mode TWI2 Note: PIO Config PB0 PB1 PB8 PB9 PB10 PB11 TWD2 TWCK2 TWD1 TWCK1 GPIO GPIO GPIO or WKUP pin or XIN(1) TWD1 TWCK1 TWCK1 TWD2 TWCK2 Configuration of PB10 Configuration of PB11 Enable Enable PIO_PER[10] PIO_PER[11] Config PB10 as Peripheral A Config PB11 as Peripheral A TWD2 TWCK2 GPIO or WKUP pin or XOUT(1) Config PB10 as Peripheral B Config PB10 as Peripheral B GPIO or AD Input(1) GPIO or AD Input(1) TWD1 1. Configuration of PBx can be done after the configuration of PB10 and PB11. Figure 10-3. TWI Master PIO Muxing Selection Mux Selection (PIO_ABCDSR1/2) PB8 TWI1 PB9 A B PB10 A B TWI2 PB11 PB0 PB1 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 31 11. Event System The events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processor intervention. Peripherals receiving events contain logic by which to select the one required. 11.1 32 Embedded Characteristics Timers, IO, peripherals generate event triggers which are directly routed to event managers such as ADC, to start measurement/conversion without processor intervention. UART, USART, SPI, TWI, ADC also generate event triggers directly connected to Peripheral DMA Controller (PDC) for data transfer without processor intervention. PMC security event (clock failure detection) can be programmed to switch the MCK on a reliable main RC internal clock without processor intervention. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 11.2 Real-Time Event Mapping Table 11-1. Real-time Event Mapping List Event Generator Event Manager Function IO (WKUP0/1) General Purpose Register (GPBR) Security / Immediate GPBR clear (asynchronous) on tamper detection through WKUP0/1 IO pins Power Management Controller (PMC) PMC Safety / Automatic switch to reliable main RC oscillator in case of main crystal clock failure IO (ADTRG) Analog-to-Digital Converter (ADC) TC Output 0 ADC TC Output 1 ADC TC Output 2 ADC RTCOUT0 ADC RTTINC ADC UART PDC Triggers 1 word transfer USART PDC Triggers 1 word transfer TWI0/1/2 PDC Triggers 1 word transfer ADC PDC Triggers 1 word transfer Timer Counter PDC Triggers 1 word transfer SPI PDC Triggers 1 word transfer I2SC0 PDC Triggers 1 word transfer I2SC1 PDC Triggers 1 word transfer PDMIC0 PDC Triggers 1 word transfer PDMIC1 PDC Triggers 1 word transfer Trigger for measurement. Selection in ADC module. Trigger for measurement. Selection in ADC module. Trigger for measurement. Selection in ADC module. Trigger for measurement. Selection in ADC module. Trigger for measurement. Selection in ADC module. Trigger for measurement. Selection in ADC module. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 33 12. ARM Cortex-M4 Processor 12.1 Description The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including outstanding processing performance combined with fast interrupt handling, enhanced system debug with extensive breakpoint and trace capabilities, efficient processor core, system and memories, ultra-low power consumption with integrated sleep modes, and platform security robustness, with integrated memory protection unit (MPU). The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including IEEE754-compliant single-precision floating-point computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M4 processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M4 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down while still retaining program state. 12.1.1 System Level Interface The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. The Cortex-M4 processor has a Memory Protection Unit (MPU) that provides fine grain memory control, enabling applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task basis. Such requirements are becoming critical in many embedded applications such as automotive. 12.1.2 Integrated Configurable Debug The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. 34 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored on a non-erasable, ROM-based microcontroller to be patched if a small programmable memory, for example flash, is available in the device. During initialization, the application in ROM detects, from the programmable memory, whether a patch is required. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration, which means the program in the nonmodifiable ROM can be patched. 12.2 Embedded Characteristics Tight integration of system peripherals reduces area and development costs Thumb instruction set combines high code density with 32-bit performance IEEE754-compliant single-precision FPU Code-patch ability for ROM system updates Power control optimization of system components Integrated sleep modes for low power consumption Fast code execution permits slower processor clock or increases sleep mode time Hardware division and fast digital-signal-processing oriented multiply accumulate Saturating arithmetic for signal processing Deterministic, high-performance interrupt handling for time-critical applications Memory Protection Unit (MPU) for safety-critical applications Extensive debug and trace capabilities: ̶ 12.3 Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing, and code profiling. Block Diagram Figure 12-1. Typical Cortex-M4F Implementation Cortex-M4F Processor FPU NVIC Debug Access Port Processor Core Memory Protection Unit Flash Patch Serial Wire Viewer Data Watchpoints Bus Matrix Code Interface SRAM and Peripheral Interface SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 35 12.4 Cortex-M4 Models 12.4.1 Programmers Model This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 12.4.1.1 Processor Modes and Privilege Levels for Software Execution The processor modes are: Thread mode Used to execute application software. The processor enters the Thread mode when it comes out of reset. Handler mode Used to handle exceptions. The processor returns to the Thread mode when it has finished exception processing. The privilege levels for software execution are: Unprivileged The software: ̶ Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction ̶ Cannot access the System Timer, NVIC, or System Control Block ̶ Might have a restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level. Privileged The software can use all the instructions and has access to all resources. Privileged software executes at the privileged level. In Thread mode, the Control Register controls whether the software execution is privileged or unprivileged, see “Control Register”. In Handler mode, software execution is always privileged. Only privileged software can write to the Control Register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 12.4.1.2 Stacks The processor uses a full descending stack. This means the stack pointer holds the address of the last stacked item in memory When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks, the main stack and the process stack, with a pointer for each held in independent registers, see “Stack Pointer”. In Thread mode, the Control Register controls whether the processor uses the main stack or the process stack, see “Control Register”. In Handler mode, the processor always uses the main stack. 36 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 The options for processor operations are: Table 12-1. Processor Mode Used to Execute Privilege Level for Software Execution Thread Applications Privileged or unprivileged Handler Exception handlers Always privileged Note: 12.4.1.3 Summary of processor mode, execution privilege level, and stack use options 1. Stack Used (1) Main stack or process stack(1) Main stack See “Control Register”. Core Registers Figure 12-2. Processor Core Registers R0 R1 R2 Low registers R3 R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP‡ MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL CONTROL register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 37 Table 12-2. Core Processor Registers Register Name Access(1) Required Privilege(2) Reset General-purpose registers R0–R12 Read/Write Either Unknown Stack Pointer MSP Read/Write Privileged See description Stack Pointer PSP Read/Write Either Unknown Link Register LR Read/Write Either 0xFFFFFFFF Program Counter PC Read/Write Either See description Program Status Register PSR Read/Write Privileged 0x01000000 Application Program Status Register APSR Read/Write Either 0x00000000 Interrupt Program Status Register IPSR Read-only Privileged 0x00000000 Execution Program Status Register EPSR Read-only Privileged 0x01000000 Priority Mask Register PRIMASK Read/Write Privileged 0x00000000 Fault Mask Register FAULTMASK Read/Write Privileged 0x00000000 Base Priority Mask Register BASEPRI Read/Write Privileged 0x00000000 Control Register CONTROL Read/Write Privileged 0x00000000 Notes: 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ. 2. An entry of Either means privileged and unprivileged software can access the register. 12.4.1.4 General-purpose Registers R0–R12 are 32-bit general-purpose registers for data operations. 12.4.1.5 Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the Control Register indicates the stack pointer to use: 0 = Main Stack Pointer (MSP). This is the reset value. 1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000. 12.4.1.6 Link Register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF. 12.4.1.7 Program Counter The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1. 38 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.4.1.8 Program Status Register Name: PSR Access: Read/Write Reset: 0x000000000 31 N 30 Z 29 C 28 V 27 Q 26 23 22 21 20 25 24 T 19 18 17 16 12 11 10 9 – 8 ISR_NUMBER 4 3 2 1 0 ICI/IT – 15 14 13 ICI/IT 7 6 5 ISR_NUMBER The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR. The PSR accesses these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: • Read of all the registers using PSR with the MRS instruction • Write to the APSR N, Z, C, V and Q bits using APSR_nzcvq with the MSR instruction. The PSR combinations and attributes are: Name Access Combination PSR Read/Write(1)(2) APSR, EPSR, and IPSR IEPSR Read-only EPSR and IPSR IAPSR APSR and IPSR (2) APSR and EPSR Read/Write EAPSR Notes: (1) Read/Write 1. The processor ignores writes to the IPSR bits. 2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. See the instruction descriptions “MRS” and “MSR” for more information about how to access the program status registers. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 39 12.4.1.9 Application Program Status Register Name: APSR Access: Read/Write Reset: 0x000000000 31 N 30 Z 23 22 29 C 28 V 27 Q 26 21 20 19 18 – 15 14 25 – 24 17 16 GE[3:0] 13 12 11 10 9 8 3 2 1 0 – 7 6 5 4 – The APSR contains the current state of the condition flags from previous instruction executions. • N: Negative Flag 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than. • Z: Zero Flag 0: Operation result was not zero 1: Operation result was zero. • C: Carry or Borrow Flag Carry or borrow flag: 0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit. • V: Overflow Flag 0: Operation did not result in an overflow 1: Operation resulted in an overflow. • Q: DSP Overflow and Saturation Flag Sticky saturation flag: 0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1: Indicates when an SSAT or USAT instruction results in saturation. This bit is cleared to zero by software using an MRS instruction. • GE[19:16]: Greater Than or Equal Flags See “SEL” for more information. 40 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.4.1.10 Interrupt Program Status Register Name: IPSR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 – 23 22 21 20 – 15 14 13 12 – 11 10 9 8 ISR_NUMBER 7 6 5 4 3 2 1 0 ISR_NUMBER The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). • ISR_NUMBER: Number of the Current Exception 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault 4 = Memory management fault 5 = Bus fault 6 = Usage fault 7–10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 61 = IRQ46 See “Exception Types” for more information. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 41 12.4.1.11 Execution Program Status Register Name: EPSR Access: Read/Write Reset: 0x000000000 31 30 23 22 29 – 28 21 20 27 26 25 24 T 16 ICI/IT 19 18 17 11 10 9 – 15 14 13 12 ICI/IT 7 6 5 8 – 4 3 2 1 0 – The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR value in the stacked PSR to indicate the operation that is at fault. See “Exception Entry and Return”. • ICI: Interruptible-continuable Instruction When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor: – Stops the load multiple or store multiple instruction operation temporarily – Stores the next register operand in the multiple operation to EPSR bits[15:12]. After servicing the interrupt, the processor: – Returns to the register pointed to by bits[15:12] – Resumes the execution of the multiple load or store instruction. When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero. • IT: If-Then Instruction Indicates the execution state bits of the IT instruction. The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See “IT” for more information. • T: Thumb State The Cortex-M4 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0: – Instructions BLX, BX and POP{PC} – Restoration from the stacked xPSR value on an exception return – Bit[0] of the vector value on an exception entry or reset. Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See “Lockup” for more information. 42 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.4.1.12 Exception Mask Registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See “MRS”, “MSR”, and “CPS” for more information. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 43 12.4.1.13 Priority Mask Register Name: PRIMASK Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRIMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The PRIMASK register prevents the activation of all exceptions with a configurable priority. • PRIMASK 0: No effect 1: Prevents the activation of all exceptions with a configurable priority. 44 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.4.1.14 Fault Mask Register Name: FAULTMASK Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FAULTMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI). • FAULTMASK 0: No effect. 1: Prevents the activation of all exceptions except for NMI. The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 45 12.4.1.15 Base Priority Mask Register Name: BASEPRI Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 BASEPRI The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. • BASEPRI Priority mask bits: 0x0000: No effect Nonzero: Defines the base priority for exception processing The processor does not process any exception with a priority value greater than or equal to BASEPRI. This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” for more information. Remember that higher priority field values correspond to lower exception priorities. 46 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.4.1.16 Control Register Name: CONTROL Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 FPCA 1 SPSEL 0 nPRIV – 23 22 21 20 – 15 14 13 12 – 7 6 5 – 4 The Control Register controls the stack used and the privilege level for software execution when the processor is in Thread mode and indicates whether the FPU state is active. • FPCA: Floating-point Context Active Indicates whether the floating-point context is currently active: 0: No floating-point context active. 1: Floating-point context active. The Cortex-M4 uses this bit to determine whether to preserve the floating-point state when processing an exception. • SPSEL: Active Stack Pointer Defines the current stack: 0: MSP is the current stack pointer. 1: PSP is the current stack pointer. In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4 updates this bit automatically on exception return. • nPRIV: Thread Mode Privilege Level Defines the Thread mode privilege level: 0: Privileged. 1: Unprivileged. Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the Control Register when in Handler mode. The exception entry and return mechanisms update the Control Register based on the EXC_RETURN value. In an OS environment, ARM recommends that threads running in Thread mode use the process stack, and the kernel and exception handlers use the main stack. By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either: • Use the MSR instruction to set the Active stack pointer bit to 1, see “MSR”, or • Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 12-10. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 47 Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See “ISB”. 12.4.1.17 Exceptions and Interrupts The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry” and “Exception Return” for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” for more information. 12.4.1.18 Data Types The processor supports the following data types: 32-bit words 16-bit halfwords 8-bit bytes The processor manages all data memory accesses as little-endian. Instruction memory and Private Peripheral Bus (PPB) accesses are always little-endian. See “Memory Regions, Types and Attributes” for more information. 12.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS) For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines: A common way to: ̶ Access peripheral registers ̶ Define exception vectors The names of: ̶ The registers of the core peripherals ̶ The core exception vectors A device-independent interface for RTOS kernels, including a debug channel. The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor. The CMSIS simplifies the software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals. This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals. Note: This document uses the register short names defined by the CMSIS. In a few cases, these differ from the architectural short names that might be used in other documents. The following sections give more information about the CMSIS: 48 Section 12.5.3 ”Power Management Programming Hints” Section 12.6.2 ”CMSIS Functions” Section 12.8.2.1 ”NVIC Programming Hints”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.4.2 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. Figure 12-3. Memory Map 0xFFFFFFFF Vendor-specific 511 MB memory Private peripheral 1.0 MB bus External device 0xE0100000 0xE00FFFFF 0xE000 0000 0x DFFFFFFF 1.0 GB 0xA0000000 0x9FFFFFFF External RAM 0x43FFFFFF 1.0 GB 32 MB Bit-band alias 0x60000000 0x5FFFFFFF 0x42000000 0x400FFFFF 0x40000000 Peripheral 0.5 GB 1 MB Bit-band region 0x40000000 0x3FFFFFFF 0x23FFFFFF 32 MB Bit-band alias SRAM 0.5 GB 0x20000000 0x1FFFFFFF 0x22000000 Code 0x200FFFFF 0x20000000 1 MB Bit-band region 0.5 GB 0x00000000 The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data, see “Bit-banding”. The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers. This memory mapping is generic to ARM Cortex-M4 products. To get the specific memory mapping of this product, refer to the Memories section of the datasheet. 12.4.2.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 49 Memory Types Normal The processor can re-order transactions for efficiency, or perform speculative reads. Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. Strongly-ordered The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. Additional Memory Attributes Shareable For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, the software must ensure data coherency between the bus masters. Execute Never (XN) Means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. 12.4.2.2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, the software must insert a memory barrier instruction between the memory access instructions, see “Software Ordering of Memory Accesses”. However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses is described below. Table 12-3. Ordering of the Memory Accesses Caused by Two Instructions A2 Device Access Normal Access Nonshareable Shareable Stronglyordered Access Normal Access – – – – Device access, non-shareable – < – < Device access, shareable – – < < Strongly-ordered access – < < < A1 Where: 50 – Means that the memory system does not guarantee the ordering of the accesses. < Means that accesses are observed in program order, that is, A1 is always observed before A2. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.4.2.3 Behavior of Memory Accesses The following table describes the behavior of accesses to each region in the memory map. Table 12-4. Memory Access Behavior Address Range Memory Region Memory Type XN 0x00000000–0x1FFFFFFF Code Normal(1) – Executable region for program code. Data can also be put here. 0x20000000–0x3FFFFFFF SRAM Normal (1) – Executable region for data. Code can also be put here. This region includes bit band and bit band alias areas, see Table 12-6. 0x40000000–0x5FFFFFFF Peripheral Device (1) XN This region includes bit band and bit band alias areas, see Table 12-6. 0x60000000–0x9FFFFFFF External RAM Normal (1) – 0xA0000000–0xDFFFFFFF External device Device 0xE0000000–0xE00FFFFF Private Peripheral Bus 0xE0100000–0xFFFFFFFF Reserved Note: (1) Description Executable region for data XN External Device memory Stronglyordered (1) XN This region includes the NVIC, system timer, and system control block. Device (1) XN Reserved 1. See “Memory Regions, Types and Attributes” for more information. The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)”. Additional Memory Access Constraints For Shared Memory When a system includes shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 12-5 shows. Table 12-5. Memory Region Shareability Policies Address Range Memory Region Memory Type Shareability (1) – 0x00000000–0x1FFFFFFF Code Normal 0x20000000–0x3FFFFFFF SRAM Normal (1) – 0x40000000–0x5FFFFFFF Peripheral Device (1) – External RAM Normal (1) – External device Device (1) 0xE0000000–0xE00FFFFF Private Peripheral Bus Strongly-ordered(1) Shareable (1) 0xE0100000–0xFFFFFFFF Vendor-specific device Device (1) – 0x60000000–0x7FFFFFFF 0x80000000–0x9FFFFFFF 0xA0000000–0xBFFFFFFF Shareable (1) Non-shareable (1) 0xC0000000–0xDFFFFFFF Notes: 1. See “Memory Regions, Types and Attributes” for more information. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 51 Instruction Prefetch and Branch Prediction The Cortex-M4 processor: Prefetches instructions ahead of execution Speculatively prefetches from branch target addresses. 12.4.2.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because: The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. The processor has multiple bus interfaces Memory or devices in the memory map have different wait states Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions: DMB The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See “DMB”. DSB The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See “DSB”. ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See “ISB”. MPU Programming Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by subsequent instructions. 12.4.2.5 Bit-banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions: 52 Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 12-6. Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table 12-7. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 12-6. SRAM Memory Bit-banding Regions Address Range Memory Region Instruction and Data Accesses 0x20000000–0x200FFFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit-addressable through bit-band alias. 0x22000000–0x23FFFFFF SRAM bit-band alias Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. Table 12-7. Peripheral Memory Bit-banding Regions Address Range Memory Region Instruction and Data Accesses 0x40000000–0x400FFFFF Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit-addressable through bit-band alias. 0x42000000–0x43FFFFFF Peripheral bit-band region Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Notes: 1. A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band region. 2. Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer size of the instruction making the bit-band access. The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: Bit_word_offset is the position of the target bit in the bit-band memory region. Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. Bit_band_base is the starting address of the alias region. Byte_offset is the number of the byte in the bit-band region that contains the targeted bit. Bit_number is the bit position, 0–7, of the targeted bit. Figure 12-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bitband region: The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF: 0x23FFFFE0 = 0x22000000 + (0xFFFFF*32) + (0*4). The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4). The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 = 0x22000000 + (0*32) + (0*4). The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C = 0x22000000+ (0*32) + (7*4). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 53 Figure 12-4. Bit-band Mapping 32 MB alias region 0x23FFFFFC 0x23FFFFF8 0x23FFFFF4 0x23FFFFF0 0x23FFFFEC 0x23FFFFE8 0x23FFFFE4 0x23FFFFE0 0x2200001C 0x22000018 0x22000014 0x22000010 0x2200000C 0x22000008 0x22000004 0x22000000 1 MB SRAM bit-band region 7 6 5 4 3 2 1 0 7 6 0x200FFFFF 7 6 5 4 3 2 5 4 3 2 1 0 7 6 0x200FFFFE 1 0 7 6 0x20000003 5 4 3 2 0x20000002 5 4 3 2 1 0 7 6 0x200FFFFD 1 0 7 6 5 4 3 2 5 4 3 2 1 0 1 0 0x200FFFFC 1 0 7 0x20000001 6 5 4 3 2 0x20000000 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bitband region. Writing a value with bit[0] set to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit. Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. Reading a word in the alias region: 0x00000000 indicates that the targeted bit in the bit-band region is set to 0 0x00000001 indicates that the targeted bit in the bit-band region is set to 1 Directly Accessing a Bit-band Region “Behavior of Memory Accesses” describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 12.4.2.6 Memory Endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0–3 hold the first stored word, and bytes 4–7 hold the second stored word. “Little-endian Format” describes how words of data are stored in memory. Little-endian Format In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and the most significant byte at the highest-numbered byte. For example: 54 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 12-5. Little-endian Format Memory 7 Register 0 31 12.4.2.7 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Synchronization Primitives The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism. A pair of synchronization primitives comprises: A Load-exclusive Instruction, used to read the value of a memory location, requesting exclusive access to that location. A Store-Exclusive instruction, used to attempt to write to the same memory location, returning a status bit to a register. If this bit is: 0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds, 1: It indicates that the thread or process did not gain exclusive access to the memory, and no write is performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: The word instructions LDREX and STREX The halfword instructions LDREXH and STREXH The byte instructions LDREXB and STREXB. The software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform an exclusive read-modify-write of a memory location, the software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location 4. Test the returned status bit. If this bit is: 0: The read-modify-write completed successfully. 1: No write was performed. This indicates that the value returned at step 1 might be out of date. The software must retry the read-modify-write sequence. The software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the semaphore address. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 55 3. If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the software has claimed the semaphore. However, if the Store-Exclusive instruction failed, another process might have claimed the semaphore after the software performed the first step. The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a LoadExclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory locations addressed by exclusive accesses by each processor. The processor removes its exclusive access tag if: It executes a CLREX instruction It executes a Store-Exclusive instruction, regardless of whether the write succeeds. An exception occurs. This means that the processor can resolve semaphore conflicts between different threads. In a multiprocessor implementation: Executing a CLREX instruction removes only the local exclusive access tag for the processor Executing a Store-Exclusive instruction, or an exception, removes the local exclusive access tags, and all global exclusive access tags for the processor. For more information about the synchronization primitive instructions, see “LDREX and STREX” and “CLREX”. 12.4.2.8 Programming Hints for the Synchronization Primitives ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for generation of these instructions: Table 12-8. CMSIS Functions for Exclusive Access Instructions Instruction CMSIS Function LDREX uint32_t __LDREXW (uint32_t *addr) LDREXH uint16_t __LDREXH (uint16_t *addr) LDREXB uint8_t __LDREXB (uint8_t *addr) STREX uint32_t __STREXW (uint32_t value, uint32_t *addr) STREXH uint32_t __STREXH (uint16_t value, uint16_t *addr) STREXB uint32_t __STREXB (uint8_t value, uint8_t *addr) CLREX void __CLREX (void) The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic function. For example, the following C code generates the required LDREXB operation: __ldrex((volatile char *) 0xFF); 56 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.4.3 Exception Model This section describes the exception model. 12.4.3.1 Exception States Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. Active An exception is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. Active and Pending The exception is being serviced by the processor and there is a pending exception from the same source. 12.4.3.2 Exception Types The exception types are: Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. Non Maskable Interrupt (NMI) A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be: Masked or prevented from activation by any other exception. Preempted by any exception other than Reset. Hard Fault A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard Faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. Memory Management Fault (MemManage) A Memory Management Fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. Bus Fault A Bus Fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 57 Usage Fault A Usage Fault is an exception that occurs because of a fault related to an instruction execution. This includes: An undefined instruction An illegal unaligned access An invalid state on instruction execution An error on exception return. The following can cause a Usage Fault when the core is configured to report them: An unaligned address on word and halfword memory access A division by zero. SVCall A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. PendSV PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. SysTick A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick. Interrupt (IRQ) A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 12-9. Properties of the Different Exception Types Exception Number (1) Irq Number (1) Exception Type Priority Vector Address or Offset (2) Activation 1 – Reset -3, the highest 0x00000004 Asynchronous 2 -14 NMI -2 0x00000008 Asynchronous 3 -13 Hard fault -1 0x0000000C – 4 -12 Memory management fault Configurable (3) 0x00000010 Synchronous 5 -11 Bus fault Configurable (3) 0x00000014 Synchronous when precise, asynchronous when imprecise 6 -10 Usage fault Configurable (3) 0x00000018 Synchronous 7–10 – – – Reserved – 0x0000002C Synchronous Reserved – Asynchronous (3) 11 -5 SVCall Configurable 12–13 – – – 14 -2 PendSV Configurable (3) 0x00000038 SysTick (3) 0x0000003C 15 -1 16 and above Notes: 58 0 and above Interrupt (IRQ) Configurable (4) Configurable 0x00000040 and above Asynchronous (5) Asynchronous 1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register”. 2. See “Vector Table” for more information SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 3. See “System Handler Priority Registers” 4. See “Interrupt Priority Registers” 5. Increasing in steps of 4. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 12-9 shows as having configurable priority, see: “System Handler Control and State Register” “Interrupt Clear-enable Registers”. For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling”. 12.4.3.3 Exception Handlers The processor handles exceptions using: 12.4.3.4 Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ46 are the exceptions handled by ISRs. Fault Handlers Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers. System Handlers NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. Vector Table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 12-6 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 59 Figure 12-6. Vector Table Exception number IRQ number 255 239 . . . 18 2 17 1 16 0 15 -1 14 -2 13 IRQ239 0x03FC . . . 0x004C . . . IRQ2 0x0048 IRQ1 0x0044 IRQ0 0x0040 SysTick 0x003C PendSV 0x0038 12 11 Vector Offset Reserved Reserved for Debug -5 10 SVCall 0x002C 9 Reserved 8 7 6 -10 5 -11 4 -12 3 -13 2 -14 1 Usage fault 0x0018 0x0014 0x0010 Bus fault Memory management fault Hard fault 0x000C NMI 0x0008 0x0004 0x0000 Reset Initial SP value On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the SCB_VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, see “Vector Table Offset Register”. 12.4.3.5 Exception Priorities As Table 12-9 shows, all exceptions have an associated priority, with: A lower priority value indicating a higher priority Configurable priorities for all exceptions except Reset, Hard fault and NMI. If the software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities see “System Handler Priority Registers”, and “Interrupt Priority Registers”. Note: Configurable priority values are in the range 0–15. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. 60 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 12.4.3.6 Interrupt Priority Grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt priority register entry into two fields: An upper field that defines the group priority A lower field that defines a subpriority within the group. Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see “Application Interrupt and Reset Control Register”. 12.4.3.7 Exception Entry and Return Descriptions of exception handling use the following terms: Preemption When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” more information. Return This occurs when the exception handler is completed, and: There is no pending exception with sufficient priority to be serviced The completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” for more information. Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. Late-arriving This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. Exception Entry SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 61 An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode, or the new exception is of a higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means that the exception has more priority than any limits set by the mask registers, see “Exception Mask Registers”. An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred as stacking and the structure of eight data words is referred to as stack frame. When using floating-point routines, the Cortex-M4 processor automatically stacks the architected floating-point state on exception entry. Figure 12-7 ”Exception Stack Frame” shows the Cortex-M4 stack frame layout when floating-point state is preserved on the stack as the result of an interrupt or an exception. Note: Where stack space for floating-point state is not allocated, the stack frame is the same as that of ARMv7-M implementations without an FPU. Figure 12-7 ”Exception Stack Frame” shows this stack frame also. Figure 12-7. Exception Stack Frame ... {aligner} FPSCR S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack Decreasing memory address IRQ top of stack Exception frame with floating-point storage ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Exception frame without floating-point storage Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the stack frame is controlled via the STKALIGN bit of the Configuration Control Register (CCR). The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. 62 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher priority exception occurs during the exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher priority exception occurs during the exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case. Exception Return An Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: An LDM or POP instruction that loads the PC An LDR instruction with the PC as the destination. A BX instruction using any register. EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. Table 12-10 shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 12-10. Exception Return Behavior EXC_RETURN[31:0] Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. 12.4.3.8 Fault Handling Faults are a subset of the exceptions, see “Exception Model”. The following generate a fault: A bus error on: ̶ An instruction fetch or vector table load ̶ A data access An internally-detected error such as an undefined instruction An attempt to execute an instruction from a memory region marked as Non-Executable (XN). A privilege violation or an attempt to access an unmanaged region causing an MPU fault. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 63 Fault Types Table 12-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred. See “Configurable Fault Status Register” for more information about the fault status registers. Table 12-11. Faults Fault Handler Bus error on a vector read Bit Name Fault Status Register VECTTBL Hard fault “Hard Fault Status Register” Fault escalated to a hard fault FORCED MPU or default memory map mismatch: – on instruction access on data access during exception stacking IACCVIOL Memory management fault – (1) DACCVIOL(2) MSTKERR during exception unstacking MUNSTKERR during lazy floating-point state preservation MLSPERR(3) Bus error: – during exception stacking STKERR during exception unstacking UNSTKERR during instruction prefetch Bus fault Precise data bus error PRECISERR Imprecise data bus error IMPRECISERR Attempt to access a coprocessor NOCP Undefined instruction UNDEFINSTR Attempt to enter an invalid instruction set state “BFSR: Bus Fault Status Subregister” INVSTATE Usage fault “UFSR: Usage Fault Status Subregister” Invalid EXC_RETURN value INVPC Illegal unaligned load or store UNALIGNED Divide By 0 DIVBYZERO Notes: – IBUSERR LSPERR(3) during lazy floating-point state preservation “MMFSR: Memory Management Fault Status Subregister” 1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled. 2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction with ICI continuation. 3. Only present in a Cortex-M4F device Fault Escalation and Hard Faults All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority Registers”. The software can disable the execution of the handlers for these faults, see “System Handler Control and State Register”. Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler, as described in “Exception Model”. In some situations, a fault with configurable priority is treated as a hard fault. This is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when: 64 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself; it must have the same priority as the current priority level. A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the handler for the new fault cannot preempt the currently executing fault handler. An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 12-12. Table 12-12. Fault Status and Fault Address Registers Handler Status Register Name Address Register Name Register Description Hard fault SCB_HFSR – “Hard Fault Status Register” Memory management fault MMFSR SCB_MMFAR Bus fault BFSR SCB_BFAR Usage fault UFSR – “MMFSR: Memory Management Fault Status Subregister” “MemManage Fault Address Register” “BFSR: Bus Fault Status Subregister” “Bus Fault Address Register” “UFSR: Usage Fault Status Subregister” Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in lockup state, it does not execute any instructions. The processor remains in lockup state until either: It is reset An NMI occurs It is halted by a debugger. Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 65 12.5 Power Management The Cortex-M4 processor sleep modes reduce the power consumption: Sleep mode stops the processor clock Deep sleep mode stops the system clock and switches off the PLL and flash memory. The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register”. This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 12.5.1 Entering Sleep Mode This section describes the mechanisms software can use to put the processor into sleep mode. The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore, the software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. 12.5.1.1 Wait for Interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI instruction it stops executing instructions and enters sleep mode. See “WFI” for more information. 12.5.1.2 Wait for Event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event register. When the processor executes a WFE instruction, it checks this register: If the register is 0, the processor stops executing instructions and enters sleep mode If the register is 1, the processor clears the register to 0 and continues executing instructions without entering sleep mode. See “WFE” for more information. 12.5.1.3 Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an exception handler, it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that only require the processor to run when an exception occurs. 12.5.2 Wakeup from Sleep Mode The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 12.5.2.1 Wakeup from WFI or Sleep-on-exit Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than the current exception priority, the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULTMASK, see “Exception Mask Registers”. 66 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.5.2.2 Wakeup from WFE The processor wakes up if: It detects an exception with sufficient priority to cause an exception entry It detects an external event signal. See “External Event Input” In a multiprocessor system, another processor in the system executes an SEV instruction. In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause an exception entry. For more information about the SCR, see “System Control Register”. 12.5.2.3 External Event Input The processor provides an external event input signal. Peripherals can drive this signal, either to wake the processor from WFE, or to set the internal WFE event register to 1 to indicate that the processor must not enter sleep mode on a later WFE instruction. See “Wait for Event” for more information. 12.5.3 Power Management Programming Hints ISO/IEC C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following functions for these instructions: void __WFE(void) // Wait for Event void __WFI(void) // Wait for Interrupt SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 67 12.6 Cortex-M4 Instruction Set 12.6.1 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 12-13 lists the supported instructions. Angle brackets, <>, enclose alternative forms of the operand Braces, {}, enclose optional operands The Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix. For more information on the instructions and operands, see the instruction descriptions. Table 12-13. Cortex-M4 Instructions Mnemonic Operands Description Flags ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V ADR Rd, label Load PC-relative address – AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C B label Branch – BFC Rd, #lsb, #width Bit Field Clear – BFI Rd, Rn, #lsb, #width Bit Field Insert – BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C BKPT #imm Breakpoint – BL label Branch with Link – BLX Rm Branch indirect with Link – BX Rm Branch indirect – CBNZ Rn, label Compare and Branch if Non Zero – CBZ Rn, label Compare and Branch if Zero – CLREX – Clear Exclusive – CLZ Rd, Rm Count leading zeros – CMN Rn, Op2 Compare Negative N,Z,C,V CMP Rn, Op2 Compare N,Z,C,V CPSID i Change Processor State, Disable Interrupts – CPSIE i Change Processor State, Enable Interrupts – DMB – Data Memory Barrier – DSB – Data Synchronization Barrier – EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C ISB – Instruction Synchronization Barrier – IT – If-Then condition block – LDM Rn{!}, reglist Load Multiple registers, increment after – 68 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before – LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after – LDR Rt, [Rn, #offset] Load Register with word – LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte – LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes – LDREX Rt, [Rn, #offset] Load Register Exclusive – LDREXB Rt, [Rn] Load Register Exclusive with byte – LDREXH Rt, [Rn] Load Register Exclusive with halfword – LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword – LDRSB, DRSBT Rt, [Rn, #offset] Load Register with signed byte – LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword – LDRT Rt, [Rn, #offset] Load Register with word – LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result – MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result – MOV, MOVS Rd, Op2 Move N,Z,C MOVT Rd, #imm16 Move Top – MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C MRS Rd, spec_reg Move from special register to general register – MSR spec_reg, Rm Move from general register to special register N,Z,C,V MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z MVN, MVNS Rd, Op2 Move NOT N,Z,C NOP – No Operation – ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack Halfword – POP reglist Pop registers from stack – PUSH reglist Push registers onto stack – QADD {Rd,} Rn, Rm Saturating double and Add Q QADD16 {Rd,} Rn, Rm Saturating Add 16 – QADD8 {Rd,} Rn, Rm Saturating Add 8 – QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange – QDADD {Rd,} Rn, Rm Saturating Add Q QDSUB {Rd,} Rn, Rm Saturating double and Subtract Q QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange – QSUB {Rd,} Rn, Rm Saturating Subtract Q SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 69 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 – QSUB8 {Rd,} Rn, Rm Saturating Subtract 8 – RBIT Rd, Rn Reverse Bits – REV Rd, Rn Reverse byte order in a word – REV16 Rd, Rn Reverse byte order in each halfword – REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend – ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V SADD16 {Rd,} Rn, Rm Signed Add 16 GE SADD8 {Rd,} Rn, Rm Signed Add 8 and Subtract with Exchange GE SASX {Rd,} Rn, Rm Signed Add GE SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract – SDIV {Rd,} Rn, Rm Signed Divide – SEL {Rd,} Rn, Rm Select bytes – SEV – Send Event – SHADD16 {Rd,} Rn, Rm Signed Halving Add 16 – SHADD8 {Rd,} Rn, Rm Signed Halving Add 8 – SHASX {Rd,} Rn, Rm Signed Halving Add and Subtract with Exchange – SHSAX {Rd,} Rn, Rm Signed Halving Subtract and Add with Exchange – SHSUB16 {Rd,} Rn, Rm Signed Halving Subtract 16 – SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8 – SMLABB, SMLABT, SMLATB, SMLATT Rd, Rn, Rm, Ra Signed Multiply Accumulate Long (halfwords) Q SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dual Q SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 × 32 + 64), 64-bit result – SMLALBB, SMLALBT, SMLALTB, SMLALTT RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long, halfwords – SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long Dual – SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed Multiply Accumulate, word by halfword Q SMLSD Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q SMLSLD RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual SMMLA Rd, Rn, Rm, Ra Signed Most significant word Multiply Accumulate – SMMLS, SMMLR Rd, Rn, Rm, Ra Signed Most significant word Multiply Subtract – SMMUL, SMMULR {Rd,} Rn, Rm Signed Most significant word Multiply – SMUAD {Rd,} Rn, Rm Signed dual Multiply Add Q 70 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags SMULBB, SMULBT SMULTB, SMULTT {Rd,} Rn, Rm Signed Multiply (halfwords) – SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 × 32), 64-bit result – SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword – SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual Multiply Subtract – SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q SSAT16 Rd, #n, Rm Signed Saturate 16 Q SSAX {Rd,} Rn, Rm Signed Subtract and Add with Exchange GE SSUB16 {Rd,} Rn, Rm Signed Subtract 16 – SSUB8 {Rd,} Rn, Rm Signed Subtract 8 – STM Rn{!}, reglist Store Multiple registers, increment after – STMDB, STMEA Rn{!}, reglist Store Multiple registers, decrement before – STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after – STR Rt, [Rn, #offset] Store Register word – STRB, STRBT Rt, [Rn, #offset] Store Register byte – STRD Rt, Rt2, [Rn, #offset] Store Register two words – STREX Rd, Rt, [Rn, #offset] Store Register Exclusive – STREXB Rd, Rt, [Rn] Store Register Exclusive byte – STREXH Rd, Rt, [Rn] Store Register Exclusive halfword – STRH, STRHT Rt, [Rn, #offset] Store Register halfword – STRT Rt, [Rn, #offset] Store Register word – SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V SVC #imm Supervisor Call – SXTAB {Rd,} Rn, Rm,{,ROR #} Extend 8 bits to 32 and add – SXTAB16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add – SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add – SXTB16 {Rd,} Rm {,ROR #n} Signed Extend Byte 16 – SXTB {Rd,} Rm {,ROR #n} Sign extend a byte – SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword – TBB [Rn, Rm] Table Branch Byte – TBH [Rn, Rm, LSL #1] Table Branch Halfword – TEQ Rn, Op2 Test Equivalence N,Z,C TST Rn, Op2 Test N,Z,C UADD16 {Rd,} Rn, Rm Unsigned Add 16 GE UADD8 {Rd,} Rn, Rm Unsigned Add 8 GE USAX {Rd,} Rn, Rm Unsigned Subtract and Add with Exchange GE SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 71 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags UHADD16 {Rd,} Rn, Rm Unsigned Halving Add 16 – UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8 – UHASX {Rd,} Rn, Rm Unsigned Halving Add and Subtract with Exchange – UHSAX {Rd,} Rn, Rm Unsigned Halving Subtract and Add with Exchange – UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 – UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 – UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract – UDIV {Rd,} Rn, Rm Unsigned Divide – UMAAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32), 64-bit result – UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply with Accumulate (32 × 32 + 64), 64-bit result – UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 × 32), 64-bit result – UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 – UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 – UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract with Exchange – UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add with Exchange – UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 – UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 – USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences – USADA8 {Rd,} Rn, Rm, Ra Unsigned Sum of Absolute Differences and Accumulate – USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q USAT16 Rd, #n, Rm Unsigned Saturate 16 Q UASX {Rd,} Rn, Rm Unsigned Add and Subtract with Exchange GE USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE UXTAB {Rd,} Rn, Rm,{,ROR #} Rotate, extend 8 bits to 32 and Add – UXTAB16 {Rd,} Rn, Rm,{,ROR #} Rotate, dual extend 8 bits to 16 and Add – UXTAH {Rd,} Rn, Rm,{,ROR #} Rotate, unsigned extend and Add Halfword – UXTB {Rd,} Rm {,ROR #n} Zero extend a byte – UXTB16 {Rd,} Rm {,ROR #n} Unsigned Extend Byte 16 – UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword – VABS.F32 Sd, Sm Floating-point Absolute – VADD.F32 {Sd,} Sn, Sm Floating-point Add – VCMP.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or one floating-point register and zero FPSCR VCMPE.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or one floating-point register and zero with Invalid Operation check FPSCR VCVT.S32.F32 Sd, Sm Convert between floating-point and integer – 72 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed point – VCVTR.S32.F32 Sd, Sm Convert between floating-point and integer with rounding – VCVT<B|H>.F32.F16 Sd, Sm Converts half-precision value to single-precision – VCVTT<B|T>.F32.F16 Sd, Sm Converts single-precision register to half-precision – VDIV.F32 {Sd,} Sn, Sm Floating-point Divide – VFMA.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate – VFNMA.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate – VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract – VFNMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract – VLDM.F<32|64> Rn{!}, list Load Multiple extension registers – VLDR.F<32|64> <Dd|Sd>, [Rn] Load an extension register from memory – VLMA.F32 {Sd,} Sn, Sm Floating-point Multiply Accumulate – VLMS.F32 {Sd,} Sn, Sm Floating-point Multiply Subtract – VMOV.F32 Sd, #imm Floating-point Move immediate – VMOV Sd, Sm Floating-point Move register – VMOV Sn, Rt Copy ARM core register to single precision – VMOV Sm, Sm1, Rt, Rt2 Copy 2 ARM core registers to 2 single precision – VMOV Dd[x], Rt Copy ARM core register to scalar – VMOV Rt, Dn[x] Copy scalar to ARM core register – VMRS Rt, FPSCR Move FPSCR to ARM core register or APSR N,Z,C,V VMSR FPSCR, Rt Move to FPSCR from ARM Core register FPSCR VMUL.F32 {Sd,} Sn, Sm Floating-point Multiply – VNEG.F32 Sd, Sm Floating-point Negate – VNMLA.F32 Sd, Sn, Sm Floating-point Multiply and Add – VNMLS.F32 Sd, Sn, Sm Floating-point Multiply and Subtract – VNMUL {Sd,} Sn, Sm Floating-point Multiply – VPOP list Pop extension registers – VPUSH list Push extension registers – VSQRT.F32 Sd, Sm Calculates floating-point Square Root – VSTM Rn{!}, list Floating-point register Store Multiple – VSTR.F<32|64> Sd, [Rn] Stores an extension register to memory – VSUB.F<32|64> {Sd,} Sn, Sm Floating-point Subtract – WFE – Wait For Event – WFI – Wait For Interrupt – SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 73 12.6.2 CMSIS Functions ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, the user might have to use inline assembler to access some instructions. The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access: Table 12-14. CMSIS Functions to Generate some Cortex-M4 Instructions Instruction CMSIS Function CPSIE I void __enable_irq(void) CPSID I void __disable_irq(void) CPSIE F void __enable_fault_irq(void) CPSID F void __disable_fault_irq(void) ISB void __ISB(void) DSB void __DSB(void) DMB void __DMB(void) REV uint32_t __REV(uint32_t int value) REV16 uint32_t __REV16(uint32_t int value) REVSH uint32_t __REVSH(uint32_t int value) RBIT uint32_t __RBIT(uint32_t int value) SEV void __SEV(void) WFE void __WFE(void) WFI void __WFI(void) The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 12-15. CMSIS Intrinsic Functions to Access the Special Registers Special Register Access CMSIS Function Read uint32_t __get_PRIMASK (void) Write void __set_PRIMASK (uint32_t value) Read uint32_t __get_FAULTMASK (void Write void __set_FAULTMASK (uint32_t value) Read uint32_t __get_BASEPRI (void) Write void __set_BASEPRI (uint32_t value) Read uint32_t __get_CONTROL (void) Write void __set_CONTROL (uint32_t value) Read uint32_t __get_MSP (void) Write void __set_MSP (uint32_t TopOfMainStack) Read uint32_t __get_PSP (void) Write void __set_PSP (uint32_t TopOfProcStack) PRIMASK FAULTMASK BASEPRI CONTROL MSP PSP 74 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.3 Instruction Descriptions 12.6.3.1 Operands An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand”. 12.6.3.2 Restrictions when Using PC or SP Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP) for the operands or destination register can be used. See instruction descriptions for more information. Note: 12.6.3.3 Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M4 processor only supports Thumb instructions. Flexible Second Operand Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the descriptions of the syntax of each instruction. Operand2 can be a: “Constant” “Register with Optional Shift” Constant Specify an Operand2 constant in the form: #constant where constant can be: Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word Any constant of the form 0x00XY00XY Any constant of the form 0xXY00XY00 Any constant of the form 0xXYXYXYXY. Note: In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions. When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant. Instruction Substitution The assembler might be able to produce an equivalent instruction in cases where the user specifies a constant that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 75 Register with Optional Shift Specify an Operand2 register in the form: Rm {, shift} where: Rm is the register holding the data for the second operand. shift is an optional shift to be applied to Rm. It can be one of: ASR #n arithmetic shift right n bits, 1 ≤ n ≤ 32. LSL #n logical shift left n bits, 1 ≤ n ≤ 31. LSR #n logical shift right n bits, 1 ≤ n ≤ 32. ROR #n rotate right n bits, 1 ≤ n ≤ 31. RRX rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to LSL #0. If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm. If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also updates the carry flag when used with certain instructions. For information on the shift operations and how they affect the carry flag, see “Flexible Second Operand”. 12.6.3.4 Shift Operations Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed: Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register During the calculation of Operand2 by the instructions that specify the second operand as a register with shift. See “Flexible Second Operand”. The result is used by the instruction. The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following subsections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift length. ASR Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the result. See Figure 12-8. The ASR #n operation can be used to divide the value in the register Rm by 2n, with the result being rounded towards negative-infinity. When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm. 76 If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm. If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 12-8. ASR #3 LSR Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the righthand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 12-9. The LSR #n operation can be used to divide the value in the register Rm by 2n, if the value is regarded as an unsigned integer. When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm. If n is 32 or more, then all the bits in the result are cleared to 0. If n is 33 or more and the carry flag is updated, it is updated to 0. Figure 12-9. LSR #3 &DUU\ )ODJ LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 12-10. The LSL #n operation can be used to multiply the value in the register Rm by 2n, if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning. When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0. If n is 32 or more, then all the bits in the result are cleared to 0. If n is 33 or more and the carry flag is updated, it is updated to 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 77 Figure 12-10. LSL #3 &DUU\ )ODJ ROR Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result; and it moves the right-hand n bits of the register into the left-hand n bits of the result. See Figure 12-11. When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm. If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm. ROR with shift length, n, more than 32 is the same as ROR with shift length n-32. Figure 12-11. ROR #3 &DUU\ )ODJ RRX Rotate right with extend moves the bits of the register Rm to the right by one bit; and it copies the carry flag into bit[31] of the result. See Figure 12-12. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm. Figure 12-12. RRX &DUU\ )ODJ 78 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.3.5 Address Alignment An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned. The Cortex-M4 processor supports unaligned access only for the following instructions: LDR, LDRT LDRH, LDRHT LDRSH, LDRSHT STR, STRT STRH, STRHT All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address-aligned. For more information about usage faults, see “Fault Handling”. Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses, see “Configuration and Control Register”. 12.6.3.6 PC-relative Expressions A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the label and the address of the current instruction. If the offset is too big, the assembler produces an error. For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes. For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned. Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number]. 12.6.3.7 Conditional Execution Most data processing instructions can optionally update the condition flags in the Application Program Status Register (APSR) according to the result of the operation, see “Application Program Status Register”. Some instructions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect. An instruction can be executed conditionally, based on the condition flags set in another instruction, either: Immediately after the instruction that updated the flags After any number of intervening instructions that have not updated the flags. Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 12-16 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction: Does not execute Does not write any value to its destination register Does not affect any of the flags Does not generate any exception. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 79 Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” for more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might automatically insert an IT instruction if there are conditional instructions outside the IT block. The CBZ and CBNZ instructions are used to compare the value of a register against zero and branch on the result. This section describes: “Condition Flags” “Condition Code Suffixes”. Condition Flags The APSR contains the following condition flags: N Set to 1 when the result of the operation was negative, cleared to 0 otherwise. Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise. C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise. V Set to 1 when the operation caused overflow, cleared to 0 otherwise. For more information about the APSR, see “Program Status Register”. A carry occurs: If the result of an addition is greater than or equal to 232 If the result of a subtraction is positive or zero As the result of an inline barrel shifter operation in a move or logical instruction. An overflow occurs when the sign of the result, in bit[31], does not match the sign of the result, had the operation been performed at infinite precision, for example: If adding two negative values results in a positive value If adding two positive values results in a negative value If subtracting a positive value from a negative value generates a positive value If subtracting a negative value from a positive value generates a negative value. The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is discarded. See the instruction descriptions for more information. Note: Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more information. Condition Code Suffixes The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition. Table 12-16 shows the condition codes to use. A conditional execution can be used with the IT instruction to reduce the number of branch instructions in code. Table 12-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags. Table 12-16. 80 Condition Code Suffixes Suffix Flags Meaning EQ Z=1 Equal NE Z=0 Not equal CS or HS C=1 Higher or same, unsigned ≥ CC or LO C=0 Lower, unsigned < MI N=1 Negative SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 12-16. Condition Code Suffixes (Continued) Suffix Flags Meaning PL N=0 Positive or zero VS V=1 Overflow VC V=0 No overflow HI C = 1 and Z = 0 Higher, unsigned > LS C = 0 or Z = 1 Lower or same, unsigned ≤ GE N=V Greater than or equal, signed ≥ LT N != V Less than, signed < GT Z = 0 and N = V Greater than, signed > LE Z = 1 and N != V Less than or equal, signed ≤ AL Can have any value Always. This is the default when no suffix is specified. Absolute Value The example below shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1). MOVS R0, R1 ; R0 = R1, setting flags IT MI ; IT instruction for the negative condition RSBMI R0, R1, #0 ; If negative, R0 = -R1 Compare and Update Value The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater than R1 and R2 is greater than R3. CMP R0, R1 ; Compare R0 and R1, setting flags ITT GT ; IT instruction for the two GT conditions CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags MOVGT R4, R5 ; If still 'greater than', do R4 = R5 12.6.3.8 Instruction Width Selection There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register specified. For some of these instructions, the user can force a specific instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction encoding. If the user specifies an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error. Note: In some cases, it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding. To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The example below shows instructions with the instruction width suffix. BCS.W label ; creates a 32-bit instruction even for a short ; branch ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 81 12.6.4 Memory Access Instructions The table below shows the memory access instructions. Table 12-17. 82 Memory Access Instructions Mnemonic Description ADR Load PC-relative address CLREX Clear Exclusive LDM{mode} Load Multiple registers LDR{type} Load Register using immediate offset LDR{type} Load Register using register offset LDR{type}T Load Register with unprivileged access LDR Load Register using PC-relative address LDRD Load Register Dual LDREX{type} Load Register Exclusive POP Pop registers from stack PUSH Push registers onto stack STM{mode} Store Multiple registers STR{type} Store Register using immediate offset STR{type} Store Register using register offset STR{type}T Store Register with unprivileged access STREX{type} Store Register Exclusive SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.4.1 ADR Load PC-relative address. Syntax ADR{cond} Rd, label where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. label is a PC-relative expression. See “PC-relative Expressions”. Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative. If ADR is used to generate a target address for a BX or BLX instruction, ensure that bit[0] of the address generated is set to 1 for correct execution. Values of label must be within the range of −4095 to +4095 from the address in the PC. Note: The user might have to use the .W suffix to get the maximum offset range or to generate addresses that are not wordaligned. See “Instruction Width Selection”. Restrictions Rd must not be SP and must not be PC. Condition Flags This instruction does not change the flags. Examples ADR R1, TextMessage ; Write address value of a location labelled as ; TextMessage to R1 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 83 12.6.4.2 LDR and STR, Immediate Offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. Syntax op{type}{cond} Rt, op{type}{cond} Rt, op{type}{cond} Rt, opD{cond} Rt, Rt2, opD{cond} Rt, Rt2, opD{cond} Rt, Rt2, [Rn {, #offset}] [Rn, #offset]! [Rn], #offset [Rn {, #offset}] [Rn, #offset]! [Rn], #offset ; ; ; ; ; ; immediate offset pre-indexed post-indexed immediate offset, two words pre-indexed, two words post-indexed, two words where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional Execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn. If offset is omitted, the address is the contents of Rn. Rt2 is the additional register to load or store for two-word operations. Operation LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory. Load and store instructions with immediate offset can use the following addressing modes: Offset Addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is: [Rn, #offset] 84 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Pre-indexed Addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! Post-indexed Addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: [Rn], #offset The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See “Address Alignment”. The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms. Table 12-18. Offset Ranges Instruction Type Immediate Offset Pre-indexed Post-indexed Word, halfword, signed halfword, byte, or signed byte -255 to 4095 -255 to 255 -255 to 255 Two words multiple of 4 in the range -1020 to 1020 multiple of 4 in the range -1020 to 1020 multiple of 4 in the range -1020 to 1020 Restrictions For load instructions: Rt can be SP or PC for word loads only Rt must be different from Rt2 for two-word loads Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. When Rt is PC in a word load instruction: Bit[0] of the loaded value must be 1 for correct execution A branch occurs to the address created by changing bit[0] of the loaded value to 0 If the instruction is conditional, it must be the last instruction in the IT block. For store instructions: Rt can be SP for word stores only Rt must not be PC Rn must not be PC Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 85 Examples LDR LDRNE R8, [R10] R2, [R5, #960]! STR R2, [R9,#const-struc] STRH R3, [R4], #4 LDRD R8, R9, [R3, #0x20] STRD R0, R1, [R8], #-16 12.6.4.3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; Loads R8 from the address in R10. Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960. const-struc is an expression evaluating to a constant in the range 0-4095. Store R3 as halfword data into address in R4, then increment R4 by 4 Load R8 from a word 32 bytes above the address in R3, and load R9 from a word 36 bytes above the address in R3 Store R0 to address in R8, and store R1 to a word 4 bytes above the address in R8, and then decrement R8 by 16. LDR and STR, Register Offset Load and Store with register offset. Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional Execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. Rm is a register containing a value to be used as the offset. LSL #n is an optional shift, with n in the range 0 to 3. Operation LDR instructions load a register with a value from memory. STR instructions store a register value into memory. The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See “Address Alignment”. 86 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Restrictions In these instructions: Rn must not be PC Rm must not be SP and must not be PC Rt can be SP only for word loads and word stores Rt can be PC only for word loads. When Rt is PC in a word load instruction: Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples STR LDRSB STR R0, [R5, R1] ; ; R0, [R5, R1, LSL #1] ; ; ; R0, [R1, R2, LSL #2] ; ; Store value of R0 into an address equal to sum of R5 and R1 Read byte value from an address equal to sum of R5 and two times R1, sign extended it to a word value and put it in R0 Stores R0 to an address equal to sum of R1 and four times R2 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 87 12.6.4.4 LDR and STR, Unprivileged Load and Store with unprivileged access. Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional Execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn. Operation These load and store instructions perform the same function as the memory access instructions with immediate offset, see “LDR and STR, Immediate Offset”. The difference is that these instructions have only unprivileged access even when used in privileged software. When used in unprivileged software, these instructions behave in exactly the same way as normal memory access instructions with immediate offset. Restrictions In these instructions: Rn must not be PC Rt must not be SP and must not be PC. Condition Flags These instructions do not change the flags. Examples 88 STRBTEQ R4, [R7] LDRHT R2, [R2, #8] ; ; ; ; Conditionally store least significant byte in R4 to an address in R7, with unprivileged access Load halfword value from an address equal to sum of R2 and 8 into R2, with unprivileged access SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.4.5 LDR, PC-relative Load register from memory. Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where: type is one of: B unsigned byte, zero extend to 32 bits. SB signed byte, sign extend to 32 bits. H unsigned halfword, zero extend to 32 bits. SH signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see “Conditional Execution”. Rt is the register to load or store. Rt2 is the second register to load or store. label is a PC-relative expression. See “PC-relative Expressions”. Operation LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by an offset from the PC. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See “Address Alignment”. label must be within a limited range of the current instruction. The table below shows the possible offsets between label and the PC. Table 12-19. Offset Ranges Instruction Type Offset Range Word, halfword, signed halfword, byte, signed byte -4095 to 4095 Two words -1020 to 1020 The user might have to use the .W suffix to get the maximum offset range. See “Instruction Width Selection”. Restrictions In these instructions: Rt can be SP or PC only for word loads Rt2 must not be SP and must not be PC Rt must be different from Rt2. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 89 When Rt is PC in a word load instruction: Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples LDR R0, LookUpTable LDRSB R7, localdata 12.6.4.6 ; ; ; ; ; Load R0 with a word of data from an address labelled as LookUpTable Load a byte value from an address labelled as localdata, sign extend it to a word value, and put it in R7 LDM and STM Load and Store Multiple registers. Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM Load Multiple registers. STM Store Multiple registers. addr_mode is any one of the following: IA Increment address After each access. This is the default. DB Decrement address Before each access. cond is an optional condition code, see “Conditional Execution”. Rn is the register on which the memory addresses are based. ! is an optional writeback suffix. If ! is present, the final address, that is loaded from or stored to, is written back into Rn. reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range, see “Examples”. LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending stacks. LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks. STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending stacks. STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks Operation LDM instructions load the registers in reglist with word values from memory addresses based on Rn. STM instructions store the word values in the registers in reglist to memory addresses based on Rn. For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the 90 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn. For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form. See “PUSH and POP”for details. Restrictions In these instructions: Rn must not be PC reglist must not contain SP In any STM instruction, reglist must not contain PC In any LDM instruction, reglist must not contain PC if it contains LR reglist must not contain Rn if the writeback suffix is specified. When PC is in reglist in an LDM instruction: Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples LDM STMDB R8,{R0,R2,R9} ; LDMIA is a synonym for LDM R1!,{R3-R6,R11,R12} Incorrect Examples STM LDM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable R2, {} ; There must be at least one register in the list SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 91 12.6.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional Execution”. reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range. PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based on SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred mnemonics in these cases. Operation PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. See “LDM and STM” for more information. Restrictions In these instructions: reglist must not contain SP For the PUSH instruction, reglist must not contain PC For the POP instruction, reglist must not contain PC if it contains LR. When PC is in reglist in a POP instruction: Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples PUSH PUSH POP 92 {R0,R4-R7} {R2,LR} {R0,R10,PC} SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.4.8 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an optional offset applied to the value in Rn. If offset is omitted, the address is the value in Rn. Operation LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address. STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address. The address used in any Store-Exclusive instruction must be the same as the address in the most recently executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same data size as the value loaded by the preceding Load-exclusive instruction. This means software must always use a Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see “Synchronization Primitives”. If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is guaranteed that no other process in the system has accessed the memory location between the Load-exclusive and Store-Exclusive instructions. For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and StoreExclusive instruction to a minimum. The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding Load-Exclusive instruction is unpredictable. Restrictions In these instructions: Do not use PC Do not use SP for Rd and Rt For STREX, Rd must be different from both Rt and Rn The value of offset must be a multiple of four in the range 0–1020. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 93 Condition Flags These instructions do not change the flags. Examples MOV LDREX CMP ITT STREXEQ CMPEQ BNE .... 12.6.4.9 R1, R0, R0, EQ R0, R0, try #0x1 [LockAddr] #0 R1, [LockAddr] #0 ; ; ; ; ; ; ; ; Initialize the ‘lock taken’ value try Load the lock value Is the lock free? IT instruction for STREXEQ and CMPEQ Try and claim the lock Did this succeed? No – try again Yes – we have the lock CLREX Clear Exclusive. Syntax CLREX{cond} where: cond is an optional condition code, see “Conditional Execution”. Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write a 1 to its destination register and fail to perform the store. It is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization operation. See “Synchronization Primitives” for more information. Condition Flags These instructions do not change the flags. Examples CLREX 94 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5 General Data Processing Instructions The table below shows the data processing instructions. Table 12-20. Data Processing Instructions Mnemonic Description ADC Add with Carry ADD Add ADDW Add AND Logical AND ASR Arithmetic Shift Right BIC Bit Clear CLZ Count leading zeros CMN Compare Negative CMP Compare EOR Exclusive OR LSL Logical Shift Left LSR Logical Shift Right MOV Move MOVT Move Top MOVW Move 16-bit constant MVN Move NOT ORN Logical OR NOT ORR Logical OR RBIT Reverse Bits REV Reverse byte order in a word REV16 Reverse byte order in each halfword REVSH Reverse byte order in bottom halfword and sign extend ROR Rotate Right RRX Rotate Right with Extend RSB Reverse Subtract SADD16 Signed Add 16 SADD8 Signed Add 8 SASX Signed Add and Subtract with Exchange SSAX Signed Subtract and Add with Exchange SBC Subtract with Carry SHADD16 Signed Halving Add 16 SHADD8 Signed Halving Add 8 SHASX Signed Halving Add and Subtract with Exchange SHSAX Signed Halving Subtract and Add with Exchange SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 95 Table 12-20. 96 Data Processing Instructions (Continued) Mnemonic Description SHSUB16 Signed Halving Subtract 16 SHSUB8 Signed Halving Subtract 8 SSUB16 Signed Subtract 16 SSUB8 Signed Subtract 8 SUB Subtract SUBW Subtract TEQ Test Equivalence TST Test UADD16 Unsigned Add 16 UADD8 Unsigned Add 8 UASX Unsigned Add and Subtract with Exchange USAX Unsigned Subtract and Add with Exchange UHADD16 Unsigned Halving Add 16 UHADD8 Unsigned Halving Add 8 UHASX Unsigned Halving Add and Subtract with Exchange UHSAX Unsigned Halving Subtract and Add with Exchange UHSUB16 Unsigned Halving Subtract 16 UHSUB8 Unsigned Halving Subtract 8 USAD8 Unsigned Sum of Absolute Differences USADA8 Unsigned Sum of Absolute Differences and Accumulate USUB16 Unsigned Subtract 16 USUB8 Unsigned Subtract 8 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD Add. ADC Add with Carry. SUB Subtract. SBC Subtract with Carry. RSB Reverse Subtract. S is an optional suffix. If S is specified, the condition code flags are updated on the result operation, see “Conditional Execution”. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. imm12 is any value in the range 0–4095. of the Operation The ADD instruction adds the value of Operand2 or imm12 to the value in Rn. The ADC instruction adds the values in Rn and Operand2, together with the carry flag. The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn. The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one. The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2. Use ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples on. See also “ADR”. Note: ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses the imm12 operand. Restrictions In these instructions: Operand2 must not be SP and must not be PC Rd can be SP only in ADD and SUB, and only with the additional restrictions: ̶ Rn must also be SP ̶ Any shift in Operand2 must be limited to a maximum of 3 bits using LSL Rn can be SP only in ADD and SUB Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where: ̶ The user must not specify the S suffix ̶ Rm must not be PC and must not be SP SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 97 ̶ If the instruction is conditional, it must be the last instruction in the IT block With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions: ̶ The user must not specify the S suffix ̶ The second operand must be a constant in the range 0 to 4095. ̶ Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before performing the calculation, making the base address for the calculation word-aligned. ̶ Note: To generate the address of an instruction, the constant based on the value of the PC must be adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the PC, because the assembler automatically calculates the correct constant for the ADR instruction. When Rd is PC in the ADD{cond} PC, PC, Rm instruction: Bit[0] of the value written to the PC is ignored A branch occurs to the address created by forcing bit[0] of that value to 0. Condition Flags If S is specified, these instructions update the N, Z, C and V flags according to the result. Examples ADD SUBS RSB ADCHI R2, R1, R3 R8, R6, #240 R4, R4, #1280 R11, R0, R3 ; ; ; ; Sets the flags on the result Subtracts contents of R4 from 1280 Only executed if C flag set and Z flag clear. Multiword Arithmetic Examples The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5. 64-bit Addition Example ADDS R4, R0, R2 ADC R5, R1, R3 ; add the least significant words ; add the most significant words with carry Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2. 96-bit Subtraction Example SUBS R6, R6, R9 SBCS R9, R2, R1 SBC R2, R8, R11 98 ; subtract the least significant words ; subtract the middle words with carry ; subtract the most significant words with carry SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND logical AND. ORR logical OR, or bit set. EOR logical Exclusive OR. BIC logical AND NOT, or bit clear. ORN logical OR NOT. S is an optional suffix. If S is specified, the condition code flags are updated on the result operation, see “Conditional Execution”. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. of the Operation The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2. The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. Restrictions Do not use SP and do not use PC. Condition Flags If S is specified, these instructions: Update the N and Z flags according to the result Can update the C flag during the calculation of Operand2, see “Flexible Second Operand” Do not affect the V flag. Examples AND ORREQ ANDS EORS BIC ORN ORNS R9, R2, #0xFF00 R2, R0, R5 R9, R8, #0x19 R7, R11, #0x18181818 R0, R1, #0xab R7, R11, R14, ROR #4 R7, R11, R14, ASR #32 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 99 12.6.5.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR Arithmetic Shift Right. LSL Logical Shift Left. LSR Logical Shift Right. ROR Rotate Right. S is an optional suffix. If S is specified, the condition code flags are updated on the result operation, see “Conditional Execution”. Rd is the destination register. Rm is the register holding the value to be shifted. Rs is the register holding the shift length to apply to the value in Rm. Only the least of the significant byte is used and can be in the range 0 to 255. n is the shift length. The range of shift length depends on the instruction: ASR shift length from 1 to 32 LSL shift length from 0 to 31 LSR shift length from 1 to 32 ROR shift length from 0 to 31 MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0. Operation ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by constant n or register Rs. RRX moves the bits in register Rm to the right by 1. In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on what result is generated by the different instructions, see “Shift Operations”. Restrictions Do not use SP and do not use PC. Condition Flags If S is specified: These instructions update the N and Z flags according to the result The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations”. Examples ASR SLS LSR ROR RRX 100 R7, R1, R4, R4, R4, R8, R2, R5, R5, R5 #9 #3 #6 R6 ; ; ; ; ; Arithmetic shift right by 9 bits Logical shift left by 3 bits with flag update Logical shift right by 6 bits Rotate right by the value in the bottom byte of R6 Rotate right with extend. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.4 CLZ Count Leading Zeros. Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rm is the operand register. Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set and zero if bit[31] is set. Restrictions Do not use SP and do not use PC. Condition Flags This instruction does not change the flags. Examples CLZ CLZNE R4,R9 R2,R3 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 101 12.6.5.5 CMP and CMN Compare and Compare Negative. Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional Execution”. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. Operation These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do not write the result to a register. The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS instruction, except that the result is discarded. The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction, except that the result is discarded. Restrictions In these instructions: Do not use PC Operand2 must not be SP. Condition Flags These instructions update the N, Z, C and V flags according to the result. Examples CMP CMN CMPGT 102 R2, R9 R0, #6400 SP, R7, LSL #2 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.6 MOV and MVN Move and Move NOT. Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result operation, see “Conditional Execution”. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. imm16 is any value in the range 0–65535. of the Operation The MOV instruction copies the value of Operand2 into Rd. When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the corresponding shift instruction: ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0 LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX. Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions: MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs See “ASR, LSL, LSR, ROR, and RRX”. The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd. The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 operand. Restrictions SP and PC only can be used in the MOV instruction, with the following restrictions: The second operand must be a register without shift The S suffix must not be specified. When Rd is PC in a MOV instruction: Bit[0] of the value written to the PC is ignored A branch occurs to the address created by forcing bit[0] of that value to 0. Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX instruction to branch for software portability to the ARM instruction set. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 103 Condition Flags If S is specified, these instructions: Update the N and Z flags according to the result Can update the C flag during the calculation of Operand2, see “Flexible Second Operand” Do not affect the V flag. Examples MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated MOVS R10, R12 ; Write value in R12 to R10, flags get updated MOV R3, #23 ; Write value of 23 to R3 MOV R8, SP ; Write value of stack pointer to R8 MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF) ; to the R2 and update flags. 12.6.5.7 MOVT Move Top. Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. imm16 is a 16-bit immediate constant. Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The MOV, MOVT instruction pair enables to generate any 32-bit constant. Restrictions Rd must not be SP and must not be PC. Condition Flags This instruction does not change the flags. Examples MOVT 104 R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword ; and APSR are unchanged. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits. RBIT Reverse the bit order in a 32-bit word. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the register holding the operand. Operation Use these instructions to change endianness of data: REV converts either: 32-bit big-endian data into little-endian data 32-bit little-endian data into big-endian data. REV16 converts either: 16-bit big-endian data into little-endian data 16-bit little-endian data into big-endian data. REVSH converts either: 16-bit signed big-endian data into 32-bit signed little-endian data 16-bit signed little-endian data into 32-bit signed big-endian data. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples REV REV16 REVSH REVHS RBIT R3, R0, R0, R3, R7, R7; R0; R5; R7; R8; Reverse Reverse Reverse Reverse Reverse byte order of value in R7 and write it to R3 byte order of each 16-bit halfword in R0 Signed Halfword with Higher or Same condition bit order of value in R8 and write the result to R7. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 105 12.6.5.9 SADD16 and SADD8 Signed Add 16 and Signed Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SADD16 Performs two 16-bit signed integer additions. SADD8 Performs four 8-bit signed integer additions. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation Use these instructions to perform a halfword or byte add in parallel: The SADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Writes the result in the corresponding halfwords of the destination register. The SADD8 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. Writes the result in the corresponding bytes of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SADD16 R1, R0 SADD8 106 ; ; ; R4, R0, R5 ; ; Adds the halfwords in R0 to the corresponding halfwords of R1 and writes to corresponding halfword of R1. Adds bytes of R0 to the corresponding byte in R5 and writes to the corresponding byte in R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.10 SHADD16 and SHADD8 Signed Halving Add 16 and Signed Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHADD16 Signed Halving Add 16. SHADD8 Signed Halving Add 8. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register: The SHADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Shuffles the result by one bit to the right, halving the data. 3. Writes the halfword results in the destination register. The SHADDB8 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. 2. Shuffles the result by one bit to the right, halving the data. 3. Writes the byte results in the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SHADD16 R1, R0 SHADD8 ; ; ; R4, R0, R5 ; ; Adds halfwords in R0 to corresponding halfword of R1 and writes halved result to corresponding halfword in R1 Adds bytes of R0 to corresponding byte in R5 and writes halved result to corresponding byte in R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 107 12.6.5.11 SHASX and SHSAX Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is any of: SHASX Add and Subtract with Exchange and Halving. SHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SHASX instruction: 1. Adds the top halfword of the first operand with the bottom halfword of the second operand. 2. Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving. 3. Subtracts the top halfword of the second operand from the bottom highword of the first operand. 4. Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving. The SHSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Writes the halfword result of the addition to the bottom halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving. 3. Adds the bottom halfword of the first operand with the top halfword of the second operand. 4. Writes the halfword result of the division in the top halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. 108 Examples SHASX R7, R4, R2 SHSAX R0, R3, R5 ; ; ; ; ; ; ; ; Adds top halfword of R4 to bottom halfword of R2 and writes halved result to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4 and writes halved result to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3 and writes halved result to top halfword of R0 Adds top halfword of R5 to bottom halfword of R3 and writes halved result to bottom halfword of R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.12 SHSUB16 and SHSUB8 Signed Halving Subtract 16 and Signed Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHSUB16 Signed Halving Subtract 16. SHSUB8 Signed Halving Subtract 8. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register: The SHSUB16 instruction: 1. Subtracts each halfword of the second operand from the corresponding halfwords of the first operand. 2. Shuffles the result by one bit to the right, halving the data. 3. Writes the halved halfword results in the destination register. The SHSUBB8 instruction: 1. Subtracts each byte of the second operand from the corresponding byte of the first operand, 2. Shuffles the result by one bit to the right, halving the data, 3. Writes the corresponding signed byte results in the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SHSUB16 R1, R0 SHSUB8 ; ; R4, R0, R5 ; ; Subtracts halfwords in R0 from corresponding halfword of R1 and writes to corresponding halfword of R1 Subtracts bytes of R0 from corresponding byte in R5, and writes to corresponding byte in R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 109 12.6.5.13 SSUB16 and SSUB8 Signed Subtract 16 and Signed Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SSUB16 Performs two 16-bit signed integer subtractions. SSUB8 Performs four 8-bit signed integer subtractions. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to change endianness of data: The SSUB16 instruction: 1. Subtracts each halfword from the second operand from the corresponding halfword of the first operand 2. Writes the difference result of two signed halfwords in the corresponding halfword of the destination register. The SSUB8 instruction: 1. Subtracts each byte of the second operand from the corresponding byte of the first operand 2. Writes the difference result of four signed bytes in the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SSUB16 R1, R0 SSUB8 110 ; ; R4, R0, R5 ; ; Subtracts halfwords in R0 from corresponding halfword of R1 and writes to corresponding halfword of R1 Subtracts bytes of R5 from corresponding byte in R0, and writes to corresponding byte of R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.14 SASX and SSAX Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rm, Rn where: op is any of: SASX Signed Add and Subtract with Exchange. SSAX Signed Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SASX instruction: 1. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand. 2. Writes the signed result of the addition to the top halfword of the destination register. 3. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand. 4. Writes the signed result of the subtraction to the bottom halfword of the destination register. The SSAX instruction: 1. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand. 2. Writes the signed result of the addition to the bottom halfword of the destination register. 3. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand. 4. Writes the signed result of the subtraction to the top halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples SASX SSAX R0, R4, R5 ; ; ; ; R7, R3, R2 ; ; ; ; Adds top halfword of R4 to bottom halfword of R5 and writes to top halfword of R0 Subtracts bottom halfword of R5 from top halfword of R4 and writes to bottom halfword of R0 Subtracts top halfword of R2 from bottom halfword of R3 and writes to bottom halfword of R7 Adds top halfword of R3 with bottom halfword of R2 and writes to top halfword of R7. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 111 12.6.5.15 TST and TEQ Test bits and Test Equivalence. Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where cond is an optional condition code, see “Conditional Execution”. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. Operation These instructions test the value in a register against Operand2. They update the condition flags based on the result, but do not write the result to a register. The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as the ANDS instruction, except that it discards the result. To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0. The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2. This is the same as the EORS instruction, except that it discards the result. Use the TEQ instruction to test if two values are equal without affecting the V or C flags. TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the sign bits of the two operands. Restrictions Do not use SP and do not use PC. Condition Flags These instructions: Update the N and Z flags according to the result Can update the C flag during the calculation of Operand2, see “Flexible Second Operand” Do not affect the V flag. Examples TST TEQEQ 112 R0, #0x3F8 ; ; R10, R9 ; ; Perform bitwise AND of R0 value to 0x3F8, APSR is updated but result is discarded Conditionally test if value in R10 is equal to value in R9, APSR is updated but result is discarded. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.16 UADD16 and UADD8 Unsigned Add 16 and Unsigned Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UADD16 Performs two 16-bit unsigned integer additions. UADD8 Performs four 8-bit unsigned integer additions. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation Use these instructions to add 16- and 8-bit unsigned data: The UADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Writes the unsigned result in the corresponding halfwords of the destination register. The UADD16 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. 2. Writes the unsigned result in the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples UADD16 R1, R0 UADD8 R4, R0, R5 ; ; ; ; Adds halfwords in R0 to corresponding halfword of R1, writes to corresponding halfword of R1 Adds bytes of R0 to corresponding byte in R5 and writes to corresponding byte in R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 113 12.6.5.17 UASX and USAX Add and Subtract with Exchange and Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UASX Add and Subtract with Exchange. USAX Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UASX instruction: 1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand. 2. Writes the unsigned result from the subtraction to the bottom halfword of the destination register. 3. Adds the top halfword of the first operand with the bottom halfword of the second operand. 4. Writes the unsigned result of the addition to the top halfword of the destination register. The USAX instruction: 1. Adds the bottom halfword of the first operand with the top halfword of the second operand. 2. Writes the unsigned result of the addition to the bottom halfword of the destination register. 3. Subtracts the bottom halfword of the second operand from the top halfword of the first operand. 4. Writes the unsigned result from the subtraction to the top halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples UASX USAX 114 R0, R4, R5 ; ; ; ; R7, R3, R2 ; ; ; ; Adds top halfword of R4 to bottom halfword of R5 and writes to top halfword of R0 Subtracts bottom halfword of R5 from top halfword of R0 and writes to bottom halfword of R0 Subtracts top halfword of R2 from bottom halfword of R3 and writes to bottom halfword of R7 Adds top halfword of R3 to bottom halfword of R2 and writes to top halfword of R7. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.18 UHADD16 and UHADD8 Unsigned Halving Add 16 and Unsigned Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHADD16 Unsigned Halving Add 16. UHADD8 Unsigned Halving Add 8. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the register holding the first operand. Rm is the register holding the second operand. Operation Use these instructions to add 16- and 8-bit data and then to halve the result before writing the result to the destination register: The UHADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Shuffles the halfword result by one bit to the right, halving the data. 3. Writes the unsigned results to the corresponding halfword in the destination register. The UHADD8 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. 2. Shuffles the byte result by one bit to the right, halving the data. 3. Writes the unsigned results in the corresponding byte in the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples UHADD16 R7, R3 UHADD8 R4, R0, R5 ; ; ; ; ; Adds halfwords in R7 to corresponding halfword of R3 and writes halved result to corresponding halfword in R7 Adds bytes of R0 to corresponding byte in R5 and writes halved result to corresponding byte in R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 115 12.6.5.19 UHASX and UHSAX Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UHASX Add and Subtract with Exchange and Halving. UHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UHASX instruction: 1. Adds the top halfword of the first operand with the bottom halfword of the second operand. 2. Shifts the result by one bit to the right causing a divide by two, or halving. 3. Writes the halfword result of the addition to the top halfword of the destination register. 4. Subtracts the top halfword of the second operand from the bottom highword of the first operand. 5. Shifts the result by one bit to the right causing a divide by two, or halving. 6. Writes the halfword result of the division in the bottom halfword of the destination register. The UHSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Shifts the result by one bit to the right causing a divide by two, or halving. 3. Writes the halfword result of the subtraction in the top halfword of the destination register. 4. Adds the bottom halfword of the first operand with the top halfword of the second operand. 5. Shifts the result by one bit to the right causing a divide by two, or halving. 6. Writes the halfword result of the addition to the bottom halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples UHASX UHSAX 116 R7, R4, R2 ; ; ; ; R0, R3, R5 ; ; ; ; Adds top halfword of R4 with bottom halfword of R2 and writes halved result to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R7 and writes halved result to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3 and writes halved result to top halfword of R0 Adds top halfword of R5 to bottom halfword of R3 and writes halved result to bottom halfword of R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.20 UHSUB16 and UHSUB8 Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHSUB16 Performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register: The UHSUB16 instruction: 1. Subtracts each halfword of the second operand from the corresponding halfword of the first operand. 2. Shuffles each halfword result to the right by one bit, halving the data. 3. Writes each unsigned halfword result to the corresponding halfwords in the destination register. The UHSUB8 instruction: 1. Subtracts each byte of second operand from the corresponding byte of the first operand. 2. Shuffles each byte result by one bit to the right, halving the data. 3. Writes the unsigned byte results to the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples UHSUB16 R1, R0 UHSUB8 R4, R0, R5 ; ; ; ; Subtracts halfwords in R0 from corresponding halfword of R1 and writes halved result to corresponding halfword in R1 Subtracts bytes of R5 from corresponding byte in R0 and writes halved result to corresponding byte in R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 117 12.6.5.21 SEL Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. Syntax SEL{<c>}{<q>} {<Rd>,} <Rn>, <Rm> where: c, q are standard assembler syntax fields. Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation The SEL instruction: 1. Reads the value of each bit of APSR.GE. 2. Depending on the value of APSR.GE, assigns the destination register the value of either the first or second operand register. Restrictions None. Condition Flags These instructions do not change the flags. Examples SADD16 R0, R1, R2 SEL R0, R0, R3 118 ; Set GE bits based on result ; Select bytes from R0 or R3, based on GE. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.22 USAD8 Unsigned Sum of Absolute Differences Syntax USAD8{cond}{Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation The USAD8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Adds the absolute values of the differences together. 3. Writes the result to the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples USAD8 R1, R4, R0 ; ; USAD8 R0, R5 ; ; Subtracts each byte in R0 from corresponding byte of R4 adds the differences and writes to R1 Subtracts bytes of R5 from corresponding byte in R0, adds the differences and writes to R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 119 12.6.5.23 USADA8 Unsigned Sum of Absolute Differences and Accumulate Syntax USADA8{cond}{Rd,} Rn, Rm, Ra where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Ra is the register that contains the accumulation value. Operation The USADA8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Adds the unsigned absolute differences together. 3. Adds the accumulation value to the sum of the absolute differences. 4. Writes the result to the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples USADA8 R1, R0, R6 USADA8 R4, R0, R5, R2 120 ; ; ; ; Subtracts bytes in R0 from corresponding halfword of R1 adds differences, adds value of R6, writes to R1 Subtracts bytes of R5 from corresponding byte in R0 adds differences, adds value of R2 writes to R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.5.24 USUB16 and USUB8 Unsigned Subtract 16 and Unsigned Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where op is any of: USUB16 Unsigned Subtract 16. USUB8 Unsigned Subtract 8. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register: The USUB16 instruction: 1. Subtracts each halfword from the second operand register from the corresponding halfword of the first operand register. 2. Writes the unsigned result in the corresponding halfwords of the destination register. The USUB8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Writes the unsigned byte result in the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples USUB16 R1, R0 ; ; ; ; Subtracts halfwords in R0 from corresponding halfword of R1 and writes to corresponding halfword in R1USUB8 R4, R0, R5 Subtracts bytes of R5 from corresponding byte in R0 and writes to the corresponding byte in R4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 121 12.6.6 Multiply and Divide Instructions The table below shows the multiply and divide instructions. Table 12-21. Multiply and Divide Instructions Mnemonic Description MLA Multiply with Accumulate, 32-bit result MLS Multiply and Subtract, 32-bit result MUL Multiply, 32-bit result SDIV Signed Divide SMLA[B,T] Signed Multiply Accumulate (halfwords) SMLAD, SMLADX Signed Multiply Accumulate Dual SMLAL Signed Multiply with Accumulate (32 × 32 + 64), 64-bit result SMLAL[B,T] Signed Multiply Accumulate Long (halfwords) SMLALD, SMLALDX Signed Multiply Accumulate Long Dual SMLAW[B|T] Signed Multiply Accumulate (word by halfword) SMLSD Signed Multiply Subtract Dual SMLSLD Signed Multiply Subtract Long Dual SMMLA Signed Most Significant Word Multiply Accumulate SMMLS, SMMLSR Signed Most Significant Word Multiply Subtract SMUAD, SMUADX Signed Dual Multiply Add SMUL[B,T] Signed Multiply (word by halfword) SMMUL, SMMULR Signed Most Significant Word Multiply SMULL Signed Multiply (32x32), 64-bit result SMULWB, SMULWT Signed Multiply (word by halfword) SMUSD, SMUSDX Signed Dual Multiply Subtract UDIV Unsigned Divide UMAAL Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32), 64-bit result UMLAL Unsigned Multiply with Accumulate (32 × 32 + 64), 64-bit result UMULL Unsigned Multiply (32 × 32), 64-bit result 122 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see “Conditional Execution”. S is an optional suffix. If S is specified, the condition code flags are updated on the result operation, see “Conditional Execution”. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn, Rm are registers holding the values to be multiplied. Ra is a register holding the value to be added or subtracted from. of the Operation The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd. The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least significant 32 bits of the result in Rd. The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra, and places the least significant 32 bits of the result in Rd. The results of these instructions do not depend on whether the operands are signed or unsigned. Restrictions In these instructions, do not use SP and do not use PC. If the S suffix is used with the MUL instruction: Rd, Rn, and Rm must all be in the range R0 to R7 Rd must be the same as Rm The cond suffix must not be used. Condition Flags If S is specified, the MUL instruction: Updates the N and Z flags according to the result Does not affect the C and V flags. Examples MUL MLA MULS MULLT MLS R10, R2, R5 R10, R2, R1, R5 R0, R2, R2 R2, R3, R2 R4, R5, R6, R7 ; ; ; ; ; Multiply, R10 Multiply with Multiply with Conditionally Multiply with = R2 x R5 accumulate, R10 = flag update, R0 = multiply, R2 = R3 subtract, R4 = R7 (R2 x R1) + R5 R2 x R2 x R2 - (R5 x R6) SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 123 12.6.6.2 UMULL, UMAAL, UMLAL Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMAAL Unsigned Long Multiply with Accumulate Accumulate. UMLAL Unsigned Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution”. RdHi, RdLo are the destination registers. For UMAAL, UMLAL and UMLAL they also hold the accumulating value. Rn, Rm are registers holding the first and second operands. Operation These instructions interpret the values from Rn and Rm as unsigned 32-bit integers. The UMULL instruction: Multiplies the two unsigned integers in the first and second operands. Writes the least significant 32 bits of the result in RdLo. Writes the most significant 32 bits of the result in RdHi. The UMAAL instruction: Multiplies the two unsigned 32-bit integers in the first and second operands. Adds the unsigned 32-bit integer in RdHi to the 64-bit result of the multiplication. Adds the unsigned 32-bit integer in RdLo to the 64-bit result of the addition. Writes the top 32-bits of the result to RdHi. Writes the lower 32-bits of the result to RdLo. The UMLAL instruction: Multiplies the two unsigned integers in the first and second operands. Adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo. Writes the result back to RdHi and RdLo. Restrictions In these instructions: Do not use SP and do not use PC. RdHi and RdLo must be different registers. Condition Flags These instructions do not affect the condition code flags. Examples UMULL R0, R4, R5, R6 UMAAL R3, R6, R2, R7 UMLAL R2, R1, R3, R5 124 ; ; ; ; ; Multiplies R5 and R6, writes the top 32 bits to R4 and the bottom 32 bits to R0 Multiplies R2 and R7, adds R6, adds R3, writes the top 32 bits to R6, and the bottom 32 bits to R3 Multiplies R5 and R3, adds R1:R2, writes to R1:R2. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.6.3 SMLA and SMLAW Signed Multiply Accumulate (halfwords). Syntax op{XY}{cond} Rd, Rn, Rm op{Y}{cond} Rd, Rn, Rm, Ra where: op is one of: SMLA Signed Multiply Accumulate Long (halfwords). X and Y specifies which half of the source registers Rn and Rm are used as the first and second multiply operand. If X is B, then the bottom halfword, bits [15:0], of Rn is used. If X is T, then the top halfword, bits [31:16], of Rn is used. If Y is B, then the bottom halfword, bits [15:0], of Rm is used. If Y is T, then the top halfword, bits [31:16], of Rm is used SMLAW Signed Multiply Accumulate (word by halfword). Y specifies which half of the source register Rm is used as the second multiply operand. If Y is T, then the top halfword, bits [31:16] of Rm is used. If Y is B, then the bottom halfword, bits [15:0] of Rm is used. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn, Rm are registers holding the values to be multiplied. Ra is a register holding the value to be added or subtracted from. Operation The SMALBB, SMLABT, SMLATB, SMLATT instructions: Multiplies the specified signed halfword, top or bottom, values from Rn and Rm. Adds the value in Ra to the resulting 32-bit product. Writes the result of the multiplication and addition in Rd. The non-specified halfwords of the source registers are ignored. The SMLAWB and SMLAWT instructions: Multiply the 32-bit signed values in Rn with: ̶ ̶ The top signed halfword of Rm, T instruction suffix. The bottom signed halfword of Rm, B instruction suffix. Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product Writes the result of the multiplication and addition in Rd. The bottom 16 bits of the 48-bit product are ignored. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No overflow can occur during the multiplication. Restrictions In these instructions, do not use SP and do not use PC. Condition Flags If an overflow is detected, the Q flag is set. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 125 Examples SMLABB SMLATB SMLATT SMLABT SMLABT SMLAWB SMLAWT 126 R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R4, R3, R2 ; ; R10, R2, R5, R3 ; ; R10, R2, R1, R5 ; ; Multiplies bottom halfwords of R6 and R4, adds R1 and writes to R5 Multiplies top halfword of R6 with bottom halfword of R4, adds R1 and writes to R5 Multiplies top halfwords of R6 and R4, adds R1 and writes the sum to R5 Multiplies bottom halfword of R6 with top halfword of R4, adds R1 and writes to R5 Multiplies bottom halfword of R4 with top halfword of R3, adds R2 and writes to R4 Multiplies R2 with bottom halfword of R5, adds R3 to the result and writes top 32-bits to R10 Multiplies R2 with top halfword of R1, adds R5 and writes top 32-bits to R10. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.6.4 SMLAD Signed Multiply Accumulate Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra ; where: op is one of: SMLAD Signed Multiply Accumulate Dual. SMLADX Signed Multiply Accumulate Dual Reverse. X specifies which halfword of the source register Rn is used as the multiply operand. If X is omitted, the multiplications are bottom × bottom and top × top. If X is present, the multiplications are bottom × top and top × bottom. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register holding the values to be multiplied. Rm the second operand register. Ra is the accumulate value. Operation The SMLAD and SMLADX instructions regard the two operands as four halfword 16-bit values. The SMLAD and SMLADX instructions: If X is not present, multiply the top signed halfword value in Rn with the top signed halfword of Rm and the bottom signed halfword values in Rn with the bottom signed halfword of Rm. Or if X is present, multiply the top signed halfword value in Rn with the bottom signed halfword of Rm and the bottom signed halfword values in Rn with the top signed halfword of Rm. Add both multiplication results to the signed 32-bit value in Ra. Writes the 32-bit signed result of the multiplication and addition to Rd. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SMLAD R10, R2, R1, R5 ; ; ; SMLALDX R0, R2, R4, R6 ; ; ; ; Multiplies two halfword values in R2 with corresponding halfwords in R1, adds R5 and writes to R10 Multiplies top halfword of R2 with bottom halfword of R4, multiplies bottom halfword of R2 with top halfword of R4, adds R6 and writes to R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 127 12.6.6.5 SMLAL and SMLALD Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate Long Dual. Syntax op{cond} RdLo, RdHi, Rn, Rm op{XY}{cond} RdLo, RdHi, Rn, Rm op{X}{cond} RdLo, RdHi, Rn, Rm where: op is one of: MLAL Signed Multiply Accumulate Long. SMLAL Signed Multiply Accumulate Long (halfwords, X and Y). X and Y specify which halfword of the source registers Rn and Rm are used as the first and second multiply operand: If X is B, then the bottom halfword, bits [15:0], of Rn is used. If X is T, then the top halfword, bits [31:16], of Rn is used. If Y is B, then the bottom halfword, bits [15:0], of Rm is used. If Y is T, then the top halfword, bits [31:16], of Rm is used. SMLALD Signed Multiply Accumulate Long Dual. SMLALDX Signed Multiply Accumulate Long Dual Reversed. If the X is omitted, the multiplications are bottom × bottom and top × top. If X is present, the multiplications are bottom × top and top × bottom. cond is an optional condition code, see “Conditional Execution”. RdHi, RdLo are the destination registers. RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64-bit integer. For SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD and SMLA LDX, they also hold the accumulating value. Rn, Rm are registers holding the first and second operands. Operation The SMLAL instruction: Multiplies the two’s complement signed word values from Rn and Rm. Adds the 64-bit value in RdLo and RdHi to the resulting 64-bit product. Writes the 64-bit result of the multiplication and addition in RdLo and RdHi. The SMLALBB, SMLALBT, SMLALTB and SMLALTT instructions: Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm. Adds the resulting sign-extended 32-bit product to the 64-bit value in RdLo and RdHi. Writes the 64-bit result of the multiplication and addition in RdLo and RdHi. The non-specified halfwords of the source registers are ignored. The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement signed 16-bit integers. These instructions: 128 If X is not present, multiply the top signed halfword value of Rn with the top signed halfword of Rm and the bottom signed halfword values of Rn with the bottom signed halfword of Rm. Or if X is present, multiply the top signed halfword value of Rn with the bottom signed halfword of Rm and the bottom signed halfword values of Rn with the top signed halfword of Rm. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit product. Write the 64-bit product in RdLo and RdHi. Restrictions In these instructions: Do not use SP and do not use PC. RdHi and RdLo must be different registers. Condition Flags These instructions do not affect the condition code flags. Examples SMLAL R4, R5, R3, R8 SMLALBT R2, R1, R6, R7 SMLALTB R2, R1, R6, R7 SMLALD R6, R8, R5, R1 SMLALDX R6, R8, R5, R1 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Multiplies R3 and R8, adds R5:R4 and writes to R5:R4 Multiplies bottom halfword of R6 with top halfword of R7, sign extends to 32-bit, adds R1:R2 and writes to R1:R2 Multiplies top halfword of R6 with bottom halfword of R7,sign extends to 32-bit, adds R1:R2 and writes to R1:R2 Multiplies top halfwords in R5 and R1 and bottom halfwords of R5 and R1, adds R8:R6 and writes to R8:R6 Multiplies top halfword in R5 with bottom halfword of R1, and bottom halfword of R5 with top halfword of R1, adds R8:R6 and writes to R8:R6. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 129 12.6.6.6 SMLSD and SMLSLD Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra where: op is one of: SMLSD Signed Multiply Subtract Dual. SMLSDX Signed Multiply Subtract Dual Reversed. SMLSLD Signed Multiply Subtract Long Dual. SMLSLDX Signed Multiply Subtract Long Dual Reversed. SMLAW Signed Multiply Accumulate (word by halfword). If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Ra is the register holding the accumulate value. Operation The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This instruction: Optionally rotates the halfwords of the second operand. Performs two signed 16 × 16-bit halfword multiplications. Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication. Adds the signed accumulate value to the result of the subtraction. Writes the result of the addition to the destination register. The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords. This instruction: Optionally rotates the halfwords of the second operand. Performs two signed 16 × 16-bit halfword multiplications. Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication. Adds the 64-bit value in RdHi and RdLo to the result of the subtraction. Writes the 64-bit result of the addition to the RdHi and RdLo. Restrictions In these instructions: Do not use SP and do not use PC. Condition Flags This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. For the Thumb instruction set, these instructions do not affect the condition code flags. 130 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Examples SMLSD R0, R4, R5, R6 ; ; ; ; SMLSDX R1, R3, R2, R0 ; ; ; ; SMLSLD R3, R6, R2, R7 ; ; ; ; SMLSLDX R3, R6, R2, R7 ; ; ; ; Multiplies bottom halfword of R4 with bottom halfword of R5, multiplies top halfword of R4 with top halfword of R5, subtracts second from first, adds R6, writes to R0 Multiplies bottom halfword of R3 with top halfword of R2, multiplies top halfword of R3 with bottom halfword of R2, subtracts second from first, adds R0, writes to R1 Multiplies bottom halfword of R6 with bottom halfword of R2, multiplies top halfword of R6 with top halfword of R2, subtracts second from first, adds R6:R3, writes to R6:R3 Multiplies bottom halfword of R6 with top halfword of R2, multiplies top halfword of R6 with bottom halfword of R2, subtracts second from first, adds R6:R3, writes to R6:R3. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 131 12.6.6.7 SMMLA and SMMLS Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract Syntax op{R}{cond} Rd, Rn, Rm, Ra where: op is one of: SMMLA Signed Most Significant Word Multiply Accumulate. SMMLS Signed Most Significant Word Multiply Subtract. If the X is omitted, the multiplications are bottom × bottom and top × top. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the high word is extracted. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second multiply operands. Ra is the register holding the accumulate value. Operation The SMMLA instruction interprets the values from Rn and Rm as signed 32-bit words. The SMMLA instruction: Multiplies the values in Rn and Rm. Optionally rounds the result by adding 0x80000000. Extracts the most significant 32 bits of the result. Adds the value of Ra to the signed extracted value. Writes the result of the addition in Rd. The SMMLS instruction interprets the values from Rn and Rm as signed 32-bit words. The SMMLS instruction: Multiplies the values in Rn and Rm. Optionally rounds the result by adding 0x80000000. Extracts the most significant 32 bits of the result. Subtracts the extracted value of the result from the value in Ra. Writes the result of the subtraction in Rd. Restrictions In these instructions: Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. 132 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Examples SMMLA R0, R4, R5, R6 SMMLAR R6, R2, R1, R4 SMMLSR R3, R6, R2, R7 SMMLS 12.6.6.8 R4, R5, R3, R8 ; ; ; ; ; ; ; ; Multiplies R4 and R5, extracts top R6, truncates and writes to R0 Multiplies R2 and R1, extracts top R4, rounds and writes to R6 Multiplies R6 and R2, extracts top subtracts R7, rounds and writes to Multiplies R5 and R3, extracts top subtracts R8, truncates and writes 32 bits, adds 32 bits, adds 32 bits, R3 32 bits, to R4. SMMUL Signed Most Significant Word Multiply Syntax op{R}{cond} Rd, Rn, Rm where: op is one of: SMMUL Signed Most Significant Word Multiply. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the high word is extracted. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The SMMUL instruction: Multiplies the values from Rn and Rm. Optionally rounds the result, otherwise truncates the result. Writes the most significant signed 32 bits of the result in Rd. Restrictions In this instruction: do not use SP and do not use PC. Condition Flags This instruction does not affect the condition code flags. Examples SMULL SMULLR R0, R4, R5 R6, R2 ; ; ; ; Multiplies and writes Multiplies and writes R4 to R6 to and R5, truncates top 32 bits R0 and R2, rounds the top 32 bits R6. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 133 12.6.6.9 SMUAD and SMUSD Signed Dual Multiply Add and Signed Dual Multiply Subtract Syntax op{X}{cond} Rd, Rn, Rm where: op is one of: SMUAD Signed Dual Multiply Add. SMUADX Signed Dual Multiply Add Reversed. SMUSD Signed Dual Multiply Subtract. SMUSDX Signed Dual Multiply Subtract Reversed. If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each operand. This instruction: Optionally rotates the halfwords of the second operand. Performs two signed 16 × 16-bit multiplications. Adds the two multiplication results together. Writes the result of the addition to the destination register. The SMUSD instruction interprets the values from the first and second operands as two’s complement signed integers. This instruction: Optionally rotates the halfwords of the second operand. Performs two signed 16 × 16-bit multiplications. Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication. Writes the result of the subtraction to the destination register. Restrictions In these instructions: Do not use SP and do not use PC. Condition Flags Sets the Q flag if the addition overflows. The multiplications cannot overflow. 134 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Examples SMUAD R0, R4, R5 SMUADX R3, R7, R4 SMUSD R3, R6, R2 SMUSDX R4, R5, R3 12.6.6.10 ; ; ; ; ; ; ; ; ; ; ; ; Multiplies bottom halfword of R4 with the bottom halfword of R5, adds multiplication of top halfword of R4 with top halfword of R5, writes to R0 Multiplies bottom halfword of R7 with top halfword of R4, adds multiplication of top halfword of R7 with bottom halfword of R4, writes to R3 Multiplies bottom halfword of R4 with bottom halfword of R6, subtracts multiplication of top halfword of R6 with top halfword of R3, writes to R3 Multiplies bottom halfword of R5 with top halfword of R3, subtracts multiplication of top halfword of R5 with bottom halfword of R3, writes to R4. SMUL and SMULW Signed Multiply (halfwords) and Signed Multiply (word by halfword) Syntax op{XY}{cond} Rd,Rn, Rm op{Y}{cond} Rd. Rn, Rm For SMULXY only: op is one of: SMUL{XY} Signed Multiply (halfwords). X and Y specify which halfword of the source registers Rn and Rm is used as the first and second multiply operand. If X is B, then the bottom halfword, bits [15:0] of Rn is used. If X is T, then the top halfword, bits [31:16] of Rn is used.If Y is B, then the bot tom halfword, bits [15:0], of Rm is used. If Y is T, then the top halfword, bits [31:16], of Rm is used. SMULW{Y} Signed Multiply (word by halfword). Y specifies which halfword of the source register Rm is used as the second mul tiply operand. If Y is B, then the bottom halfword (bits [15:0]) of Rm is used. If Y is T, then the top halfword (bits [31:16]) of Rm is used. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SMULBB, SMULTB, SMULBT and SMULTT instructions interprets the values from Rn and Rm as four signed 16-bit integers. These instructions: Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm. Writes the 32-bit result of the multiplication in Rd. The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two halfword 16-bit signed integers. These instructions: Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand. Writes the signed most significant 32 bits of the 48-bit result in the destination register. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 135 Restrictions In these instructions: 136 Do not use SP and do not use PC. RdHi and RdLo must be different registers. Examples SMULBT R0, R4, R5 SMULBB R0, R4, R5 SMULTT R0, R4, R5 SMULTB R0, R4, R5 SMULWT R4, R5, R3 SMULWB R4, R5, R3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Multiplies the bottom halfword of R4 with the top halfword of R5, multiplies results and writes to R0 Multiplies the bottom halfword of R4 with the bottom halfword of R5, multiplies results and writes to R0 Multiplies the top halfword of R4 with the top halfword of R5, multiplies results and writes to R0 Multiplies the top halfword of R4 with the bottom halfword of R5, multiplies results and and writes to R0 Multiplies R5 with the top halfword of R3, extracts top 32 bits and writes to R4 Multiplies R5 with the bottom halfword of R3, extracts top 32 bits and writes to R4. 12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, with Accumulate. SMULL Signed Long Multiply. SMLAL Signed Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution”. RdHi, RdLo are the destination registers. For UMLAL and SMLAL they also hold the accu mulating value. Rn, Rm are registers holding the operands. Operation The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. Restrictions In these instructions: Do not use SP and do not use PC RdHi and RdLo must be different registers. Condition Flags These instructions do not affect the condition code flags. Examples UMULL SMLAL R0, R4, R5, R6 R4, R5, R3, R8 ; Unsigned (R4,R0) = R5 x R6 ; Signed (R5,R4) = (R5,R4) + R3 x R8 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 137 12.6.6.12 SDIV and UDIV Signed Divide and Unsigned Divide. Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. Operation SDIV performs a signed integer division of the value in Rn by the value in Rm. UDIV performs an unsigned integer division of the value in Rn by the value in Rm. For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SDIV UDIV 138 R0, R2, R4 R8, R8, R1 ; Signed divide, R0 = R2/R4 ; Unsigned divide, R8 = R8/R1 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.7 Saturating Instructions The table below shows the saturating instructions. Table 12-22. Saturating Instructions Mnemonic Description SSAT Signed Saturate SSAT16 Signed Saturate Halfword USAT Unsigned Saturate USAT16 Unsigned Saturate Halfword QADD Saturating Add QSUB Saturating Subtract QSUB16 Saturating Subtract 16 QASX Saturating Add and Subtract with Exchange QSAX Saturating Subtract and Add with Exchange QDADD Saturating Double and Add QDSUB Saturating Double and Subtract UQADD16 Unsigned Saturating Add 16 UQADD8 Unsigned Saturating Add 8 UQASX Unsigned Saturating Add and Subtract with Exchange UQSAX Unsigned Saturating Subtract and Add with Exchange UQSUB16 Unsigned Saturating Subtract 16 UQSUB8 Unsigned Saturating Subtract 8 For signed n-bit saturation, this means that: If the value to be saturated is less than -2n-1, the result returned is -2n-1 If the value to be saturated is greater than 2n-1-1, the result returned is 2n-1-1 Otherwise, the result returned is the same as the value to be saturated. For unsigned n-bit saturation, this means that: If the value to be saturated is less than 0, the result returned is 0 If the value to be saturated is greater than 2n-1, the result returned is 2n-1 Otherwise, the result returned is the same as the value to be saturated. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, the MSR instruction must be used; see “MSR”. To read the state of the Q flag, the MRS instruction must be used; see “MRS”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 139 12.6.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 31 for USAT. to 32 for SSAT Rm is the register containing the value to saturate. shift #s is an optional shift applied to Rm before saturating. It must be one of the following: ASR #s where s is in the range 1 to 31. LSL #s where s is in the range 0 to 31. Operation These instructions saturate to a signed or unsigned n-bit value. The SSAT instruction applies the specified shift, then saturates to the signed range -2n–1 ≤ x ≤ 2n–1-1. The USAT instruction applies the specified shift, then saturates to the unsigned range 0 ≤ x ≤ 2n-1. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. Examples 140 SSAT R7, #16, R7, LSL #4 USATNE R0, #7, R5 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 ; ; ; ; ; Logical shift left value in R7 by 4, then saturate it as a signed 16-bit value and write it back to R7 Conditionally saturate value in R5 as an unsigned 7 bit value and write it to R0. 12.6.7.2 SSAT16 and USAT16 Signed Saturate and Unsigned Saturate to any bit position for two halfwords. Syntax op{cond} Rd, #n, Rm where: op is one of: SSAT16 Saturates a signed halfword value to a signed range. USAT16 Saturates a signed halfword value to an unsigned range. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 15 for USAT. to 16 for SSAT Rm is the register containing the value to saturate. Operation The SSAT16 instruction: Saturates two signed 16-bit halfword values of the register with the value to saturate from selected by the bit position in n. Writes the results as two signed 16-bit halfwords to the destination register. The USAT16 instruction: Saturates two unsigned 16-bit halfword values of the register with the value to saturate from selected by the bit position in n. Writes the results as two unsigned halfwords in the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. Examples SSAT16 USAT16NE R7, #9, R2 R0, #13, R5 ; ; ; ; ; ; Saturates the top and bottom highwords of R2 as 9-bit values, writes to corresponding halfword of R7 Conditionally saturates the top and bottom halfwords of R5 as 13-bit values, writes to corresponding halfword of R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 141 12.6.7.3 QADD and QSUB Saturating Add and Saturating Subtract, signed. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op is one of: QADD Saturating 32-bit add. QADD8 Saturating four 8-bit integer additions. QADD16 Saturating two 16-bit integer additions. QSUB Saturating 32-bit subtraction. QSUB8 Saturating four 8-bit integer subtraction. QSUB16 Saturating two 16-bit integer subtraction. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation These instructions add or subtract two, four or eight values from the first and second operands and then writes a signed saturated value in the destination register. The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed range -2n–1 ≤ x ≤ 2n–1-1, where x is given by the number of bits applied in the instruction, 32, 16 or 8. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit and 16-bit QADD and QSUB instructions always leave the Q flag unchanged. To clear the Q flag to 0, the MSR instruction must be used; see “MSR”. To read the state of the Q flag, the MRS instruction must be used; see “MRS”. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. 142 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Examples QADD16 12.6.7.4 R7, R4, R2 QADD8 R3, R1, R6 QSUB16 R4, R2, R3 QSUB8 R4, R2, R5 ; ; ; ; ; ; ; ; ; ; ; ; Adds halfwords of R4 with corresponding halfword of R2, saturates to 16 bits and writes to corresponding halfword of R7 Adds bytes of R1 to the corresponding bytes of R6, saturates to 8 bits and writes to corresponding byte of R3 Subtracts halfwords of R3 from corresponding halfword of R2, saturates to 16 bits, writes to corresponding halfword of R4 Subtracts bytes of R5 from the corresponding byte in R2, saturates to 8 bits, writes to corresponding byte of R4. QASX and QSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed. Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QASX Add and Subtract with Exchange and Saturate. QSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The QASX instruction: 1. Adds the top halfword of the source operand with the bottom halfword of the second operand. 2. Subtracts the top halfword of the second operand from the bottom highword of the first operand. 3. Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register. 4. Saturates the results of the sum and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register. The QSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Adds the bottom halfword of the source operand with the top halfword of the second operand. 3. Saturates the results of the sum and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register. 4. Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 143 Examples QASX QSAX 144 R7, R4, R2 ; ; ; ; ; R0, R3, R5 ; ; ; ; Adds top halfword of R4 to bottom halfword of R2, saturates to 16 bits, writes to top halfword of R7 Subtracts top highword of R2 from bottom halfword of R4, saturates to 16 bits and writes to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3, saturates to 16 bits, writes to top halfword of R0 Adds bottom halfword of R3 to top halfword of R5, saturates to 16 bits, writes to bottom halfword of R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.7.5 QDADD and QDSUB Saturating Double and Add and Saturating Double and Subtract, signed. Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QDADD Saturating Double and Add. QDSUB Saturating Double and Subtract. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rm, Rn are registers holding the first and second operands. Operation The QDADD instruction: Doubles the second operand value. Adds the result of the doubling to the signed saturated value in the first operand. Writes the result to the destination register. The QDSUB instruction: Doubles the second operand value. Subtracts the doubled value from the signed saturated value in the first operand. Writes the result to the destination register. Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range – 231 ≤ x ≤ 231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR. Restrictions Do not use SP and do not use PC. Condition Flags If saturation occurs, these instructions set the Q flag to 1. Examples QDADD R7, R4, R2 QDSUB R0, R3, R5 ; ; ; ; Doubles and saturates R4 to 32 bits, adds R2, saturates to 32 bits, writes to R7 Subtracts R3 doubled and saturated to 32 bits from R5, saturates to 32 bits, writes to R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 145 12.6.7.6 UQASX and UQSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned. Syntax op{cond} {Rd}, Rm, Rn where: type is one of: UQASX Add and Subtract with Exchange and Saturate. UQSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UQASX instruction: 1. Adds the bottom halfword of the source operand with the top halfword of the second operand. 2. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 3. Saturates the results of the sum and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register. 4. Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the bottom halfword of the destination register. The UQSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Adds the bottom halfword of the first operand with the top halfword of the second operand. 3. Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register. 4. Saturates the results of the addition and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the bottom halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples UQASX R7, R4, R2 UQSAX R0, R3, R5 146 ; ; ; ; ; ; ; ; Adds top halfword of R4 with bottom halfword of R2, saturates to 16 bits, writes to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4, saturates to 16 bits, writes to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3, saturates to 16 bits, writes to top halfword of R0 Adds bottom halfword of R4 to top halfword of R5 saturates to 16 bits, writes to bottom halfword of R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.7.7 UQADD and UQSUB Saturating Add and Saturating Subtract Unsigned. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op is one of: UQADD8 Saturating four unsigned 8-bit integer additions. UQADD16 Saturating two unsigned 16-bit integer additions. UDSUB8 Saturating four unsigned 8-bit integer subtractions. UQSUB16 Saturating two unsigned 16-bit integer subtractions. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation These instructions add or subtract two or four values and then writes an unsigned saturated value in the destination register. The UQADD16 instruction: Adds the respective top and bottom halfwords of the first and second operands. Saturates the result of the additions for each halfword in the destination register to the unsigned range 0 ≤ x ≤ 216-1, where x is 16. The UQADD8 instruction: Adds each respective byte of the first and second operands. Saturates the result of the addition for each byte in the destination register to the unsigned range 0 ≤ x ≤ 281, where x is 8. The UQSUB16 instruction: Subtracts both halfwords of the second operand from the respective halfwords of the first operand. Saturates the result of the differences in the destination register to the unsigned range 0 ≤ x ≤ 216-1, where x is 16. The UQSUB8 instructions: Subtracts the respective bytes of the second operand from the respective bytes of the first operand. Saturates the results of the differences for each byte in the destination register to the unsigned range 0 ≤ x ≤ 28-1, where x is 8. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 147 Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples UQADD16 R7, R4, R2 UQADD8 R4, R2, R5 UQSUB16 R6, R3, R0 UQSUB8 R1, R5, R6 ; ; ; ; ; ; ; ; ; Adds halfwords in R4 to corresponding halfword in R2, saturates to 16 bits, writes to corresponding halfword of R7 Adds bytes of R2 to corresponding byte of R5, saturates to 8 bits, writes to corresponding bytes of R4 Subtracts halfwords in R0 from corresponding halfword in R3, saturates to 16 bits, writes to corresponding halfword in R6 Subtracts bytes in R6 from corresponding byte of R5, saturates to 8 bits, writes to corresponding byte of R1. 12.6.8 Packing and Unpacking Instructions The table below shows the instructions that operate on packing and unpacking data. Table 12-23. 148 Packing and Unpacking Instructions Mnemonic Description PKH Pack Halfword SXTAB Extend 8 bits to 32 and add SXTAB16 Dual extend 8 bits to 16 and add SXTAH Extend 16 bits to 32 and add SXTB Sign extend a byte SXTB16 Dual extend 8 bits to 16 and add SXTH Sign extend a halfword UXTAB Extend 8 bits to 32 and add UXTAB16 Dual extend 8 bits to 16 and add UXTAH Extend 16 bits to 32 and add UXTB Zero extend a byte UXTB16 Dual zero extend 8 bits to 16 and add UXTH Zero extend a halfword SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.8.1 PKHBT and PKHTB Pack Halfword Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm} op{cond} {Rd}, Rn, Rm {, ASR #imm} where: op is one of: PKHBT Pack Halfword, bottom and top with shift. PKHTB Pack Halfword, top and bottom with shift. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register Rm is the second operand register holding the value to be optionally shifted. imm is the shift length. The type of shift length depends on the instruction: For PKHBT LSL a left shift with a shift length from 1 to 31, 0 means no shift. For PKHTB ASR an arithmetic shift right with a shift length from 1 to 32, a shift of 32-bits is encoded as 0b00000. Operation The PKHBT instruction: 1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register. 2. If shifted, the shifted value of the second operand is written to the top halfword of the destination register. The PKHTB instruction: 1. Writes the value of the top halfword of the first operand to the top halfword of the destination register. 2. If shifted, the shifted value of the second operand is written to the bottom halfword of the destination register. Restrictions Rd must not be SP and must not be PC. Condition Flags This instruction does not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 149 Examples PKHBT R3, R4, R5 LSL #0 PKHTB R4, R0, R2 ASR #1 12.6.8.2 ; ; ; ; ; ; Writes bottom halfword of R4 to bottom halfword of R3, writes top halfword of R5, unshifted, to top halfword of R3 Writes R2 shifted right by 1 bit to bottom halfword of R4, and writes top halfword of R0 to top halfword of R4. SXT and UXT Sign extend and Zero extend. Syntax op{cond} {Rd,} Rm {, ROR #n} op{cond} {Rd}, Rm {, ROR #n} where: op is one of: SXTB Sign extends an 8-bit value to a 32-bit value. SXTH Sign extends a 16-bit value to a 32-bit value. SXTB16 Sign extends two 8-bit values to two 16-bit values. UXTB Zero extends an 8-bit value to a 32-bit value. UXTH Zero extends a 16-bit value to a 32-bit value. UXTB16 Zero extends two 8-bit values to two 16-bit values. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. Operation These instructions do the following: 1. Rotate the value from Rm right by 0, 8, 16 or 24 bits. 2. Extract bits from the resulting value: ̶ SXTB extracts bits[7:0] and sign extends to 32 bits. ̶ UXTB extracts bits[7:0] and zero extends to 32 bits. ̶ SXTH extracts bits[15:0] and sign extends to 32 bits. ̶ UXTH extracts bits[15:0] and zero extends to 32 bits. ̶ SXTB16 extracts bits[7:0] and sign extends to 16 bits, and extracts bits [23:16] and sign extends to 16 bits. ̶ UXTB16 extracts bits[7:0] and zero extends to 16 bits, and extracts bits [23:16] and zero extends to 16 bits. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. 150 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Examples SXTH R4, R6, ROR #16 UXTB R3, R10 12.6.8.3 ; ; ; ; Rotates R6 right by 16 bits, obtains bottom halfword of of result, sign extends to 32 bits and writes to R4 Extracts lowest byte of value in R10, zero extends, and writes to R3. SXTA and UXTA Signed and Unsigned Extend and Add Syntax op{cond} {Rd,} Rn, Rm {, ROR #n} op{cond} {Rd,} Rn, Rm {, ROR #n} where: op is one of: SXTAB Sign extends an 8-bit value to a 32-bit value and add. SXTAH Sign extends a 16-bit value to a 32-bit value and add. SXTAB16 Sign extends two 8-bit values to two 16-bit values and add. UXTAB Zero extends an 8-bit value to a 32-bit value and add. UXTAH Zero extends a 16-bit value to a 32-bit value and add. UXTAB16 Zero extends two 8-bit values to two 16-bit values and add. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the first operand register. Rm is the register holding the value to rotate and extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. ROR #16 Value from Rm is rotated right 16 bits. ROR #24 Value from Rm is rotated right 24 bits. If ROR #n is omitted, no rotation is performed. Operation These instructions do the following: 1. Rotate the value from Rm right by 0, 8, 16 or 24 bits. 2. Extract bits from the resulting value: ̶ ̶ ̶ ̶ 3. ̶ SXTAB extracts bits[7:0] from Rm and sign extends to 32 bits. ̶ UXTAB extracts bits[7:0] from Rm and zero extends to 32 bits. SXTAH extracts bits[15:0] from Rm and sign extends to 32 bits. UXTAH extracts bits[15:0] from Rm and zero extends to 32 bits. SXTAB16 extracts bits[7:0] from Rm and sign extends to 16 bits, and extracts bits [23:16] from Rm and sign extends to 16 bits. UXTAB16 extracts bits[7:0] from Rm and zero extends to 16 bits, and extracts bits [23:16] from Rm and zero extends to 16 bits. Adds the signed or zero extended value to the word or corresponding halfword of Rn and writes the result in Rd. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 151 Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. Examples SXTAH UXTAB 152 R4, R8, R6, ROR #16 ; ; ; R3, R4, R10 ; ; SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Rotates R6 right by 16 bits, obtains bottom halfword, sign extends to 32 bits, adds R8,and writes to R4 Extracts bottom byte of R10 and zero extends to 32 bits, adds R4, and writes to R3. 12.6.9 Bitfield Instructions The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields. Table 12-24. Packing and Unpacking Instructions Mnemonic Description BFC Bit Field Clear BFI Bit Field Insert SBFX Signed Bit Field Extract SXTB Sign extend a byte SXTH Sign extend a halfword UBFX Unsigned Bit Field Extract UXTB Zero extend a byte UXTH Zero extend a halfword SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 153 12.6.9.1 BFC and BFI Bit Field Clear and Bit Field Insert. Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb. Operation BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are unchanged. BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. Examples BFC BFI 154 R4, #8, #12 R9, R2, #8, #12 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0 ; Replace bit 8 to bit 19 (12 bits) of R9 with ; bit 0 to bit 11 from R2. 12.6.9.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb. Operation SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination register. UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. Examples SBFX UBFX R0, R1, #20, #4 ; ; R8, R11, #9, #10 ; ; Extract bit 20 to bit 23 (4 bits) from R1 and sign extend to 32 bits and then write the result to R0. Extract bit 9 to bit 18 (10 bits) from R11 and zero extend to 32 bits and then write the result to R8. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 155 12.6.9.3 SXT and UXT Sign extend and Zero extend. Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B Extends an 8-bit value to a 32-bit value. H Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. ROR #16 Value from Rm is rotated right 16 bits. ROR #24 Value from Rm is rotated right 24 bits. If ROR #n is omitted, no rotation is performed. Operation These instructions do the following: 1. Rotate the value from Rm right by 0, 8, 16 or 24 bits. 2. Extract bits from the resulting value: ̶ SXTB extracts bits[7:0] and sign extends to 32 bits. ̶ UXTB extracts bits[7:0] and zero extends to 32 bits. ̶ SXTH extracts bits[15:0] and sign extends to 32 bits. ̶ UXTH extracts bits[15:0] and zero extends to 32 bits. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. Examples 156 SXTH R4, R6, ROR #16 UXTB R3, R10 ; ; ; ; ; Rotate R6 right by 16 bits, then obtain the lower halfword of the result and then sign extend to 32 bits and write the result to R4. Extract lowest byte of the value in R10 and zero extend it, and write the result to R3. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.10 Branch and Control Instructions The table below shows the branch and control instructions. Table 12-25. Branch and Control Instructions Mnemonic Description B Branch BL Branch with Link BLX Branch indirect with Link BX Branch indirect CBNZ Compare and Branch if Non Zero CBZ Compare and Branch if Zero IT If-Then TBB Table Branch Byte TBH Table Branch Halfword SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 157 12.6.10.1 B, BL, BX, and BLX Branch instructions. Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see “Conditional Execution”. label is a PC-relative expression. See “PC-relative Expressions”. Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm must be 1, but the address to branch to is created by changing bit[0] to 0. Operation All these instructions cause a branch to label, or to the address indicated in Rm. In addition: The BL and BLX instructions write the address of the next instruction to LR (the link register, R14). The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0. Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT”. The table below shows the ranges for the various branch instructions. Table 12-26. Branch Ranges Instruction Branch Range B label −16 MB to +16 MB Bcond label (outside IT block) −1 MB to +1 MB Bcond label (inside IT block) −16 MB to +16 MB BL{cond} label −16 MB to +16 MB BX{cond} Rm Any value in register BLX{cond} Rm Any value in register The .W suffix might be used to get the maximum branch range. See “Instruction Width Selection”. Restrictions The restrictions are: Do not use PC in the BLX instruction For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0 When any of these instructions is inside an IT block, it must be the last instruction of the IT block. Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer branch range when it is inside an IT block. 158 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Condition Flags These instructions do not change the flags. Examples B BLE B.W BEQ BEQ.W BL loopA ng target target target funC BX BXNE BLX LR R0 R0 ; ; ; ; ; ; ; ; ; ; Branch to loopA Conditionally branch to label ng Branch to target within 16MB range Conditionally branch to target Conditionally branch to target within 1MB Branch with link (Call) to function funC, return address stored in LR Return from function call Conditionally branch to address stored in R0 Branch with link and exchange (Call) to a address stored in R0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 159 12.6.10.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions. CBZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BEQ label CBNZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BNE label Restrictions The restrictions are: Rn must be in the range of R0 to R7 The branch destination must be within 4 to 130 bytes after the instruction These instructions must not be used inside an IT block. Condition Flags These instructions do not change the flags. Examples CBZ CBNZ 160 R5, target R0, target ; Forward branch if R5 is zero ; Forward branch if R0 is not zero SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.10.3 IT If-Then condition instruction. Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T Then. Applies the condition cond to the instruction. E Else. Applies the inverse condition of cond to the instruction. It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E. Operation The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT block. The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their syntax. The assembler might be able to generate the required IT instructions for conditional instructions automatically, so that the user does not have to write them. See the assembler documentation for details. A BKPT instruction in an IT block is always executed, even if its condition fails. Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked PSR. Instructions designed for use for exception returns can be used as normal to return from the exception, and execution of the IT block resumes correctly. This is the only way that a PC-modifying instruction is permitted to branch to an instruction in an IT block. Restrictions The following instructions are not permitted in an IT block: IT CBZ and CBNZ CPSID and CPSIE. Other restrictions when using an IT block are: A branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: ̶ ADD PC, PC, Rm ̶ MOV PC, Rm ̶ B, BL, BX, BLX ̶ Any LDM, LDR, or POP instruction that writes to the PC ̶ TBB and TBH Do not branch to any instruction inside an IT block, except when returning from an exception handler SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 161 All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside an IT block but has a larger branch range if it is inside one Each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the block. Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them. Condition Flags This instruction does not change the flags. Example 12.6.10.4 ITTE ANDNE ADDSNE MOVEQ NE R0, R0, R1 R2, R2, #1 R2, R3 ; ; ; ; Next 3 instructions are conditional ANDNE does not update condition flags ADDSNE updates condition flags Conditional move CMP R0, #9 ITE ADDGT ADDLE GT R1, R0, #55 R1, R0, #48 ; ; ; ; ; Convert R0 hex value (0 to 15) into ASCII ('0'-'9', 'A'-'F') Next 2 instructions are conditional Convert 0xA -> 'A' Convert 0x0 -> '0' IT ADDGT GT R1, R1, #1 ; IT block with only one conditional instruction ; Increment R1 conditionally ITTEE MOVEQ ADDEQ ANDNE BNE.W EQ R0, R1 R2, R2, #10 R3, R3, #1 dloop ; ; ; ; ; ; IT ADD NE R0, R0, R1 ; Next instruction is conditional ; Syntax error: no condition code used in IT block Next 4 instructions are conditional Conditional move Conditional add Conditional AND Branch instruction can only be used in the last instruction of an IT block TBB and TBH Table Branch Byte and Table Branch Halfword. Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction. Rm 162 is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the value in Rm to form the right offset into the table. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Operation These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the address of the byte immediately after the TBB or TBH instruction. Restrictions The restrictions are: Rn must not be SP Rm must not be SP and must not be PC When any of these instructions is used inside an IT block, it must be the last instruction of the IT block. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 163 Examples ADR.W TBB R0, BranchTable_Byte [R0, R1] ; R1 is the index, R0 is the base address of the ; branch table Case1 ; an instruction sequence follows Case2 ; an instruction sequence follows Case3 ; an instruction sequence follows BranchTable_Byte DCB 0 ; Case1 offset calculation DCB ((Case2-Case1)/2) ; Case2 offset calculation DCB ((Case3-Case1)/2) ; Case3 offset calculation TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H DCI ((CaseA - BranchTable_H)/2) DCI ((CaseB - BranchTable_H)/2) DCI ((CaseC - BranchTable_H)/2) CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows 164 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 ; CaseA offset calculation ; CaseB offset calculation ; CaseC offset calculation 12.6.11 Floating-point Instructions The table below shows the floating-point instructions. These instructions are only available if the FPU is included, and enabled, in the system. See “Enabling the FPU” for information about enabling the floating-point unit. Table 12-27. Floating-point Instructions Mnemonic Description VABS Floating-point Absolute VADD Floating-point Add VCMP Compare two floating-point registers, or one floating-point register and zero VCMPE Compare two floating-point registers, or one floating-point register and zero with Invalid Operation check VCVT Convert between floating-point and integer VCVT Convert between floating-point and fixed point VCVTR Convert between floating-point and integer with rounding VCVTB Converts half-precision value to single-precision VCVTT Converts single-precision register to half-precision VDIV Floating-point Divide VFMA Floating-point Fused Multiply Accumulate VFNMA Floating-point Fused Negate Multiply Accumulate VFMS Floating-point Fused Multiply Subtract VFNMS Floating-point Fused Negate Multiply Subtract VLDM Load Multiple extension registers VLDR Loads an extension register from memory VLMA Floating-point Multiply Accumulate VLMS Floating-point Multiply Subtract VMOV Floating-point Move Immediate VMOV Floating-point Move Register VMOV Copy ARM core register to single precision VMOV Copy 2 ARM core registers to 2 single precision VMOV Copies between ARM core register to scalar VMOV Copies between Scalar to ARM core register VMRS Move to ARM core register from floating-point System Register VMSR Move to floating-point System Register from ARM Core register VMUL Multiply floating-point VNEG Floating-point negate VNMLA Floating-point multiply and add VNMLS Floating-point multiply and subtract VNMUL Floating-point multiply VPOP Pop extension registers SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 165 Table 12-27. 166 Floating-point Instructions (Continued) Mnemonic Description VPUSH Push extension registers VSQRT Floating-point square root VSTM Store Multiple extension registers VSTR Stores an extension register to memory VSUB Floating-point Subtract SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.1 VABS Floating-point Absolute. Syntax VABS{cond}.F32 Sd, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd, Sm are the destination floating-point value and the operand floating-point value. Operation This instruction: 1. Takes the absolute value of the operand floating-point register. 2. Places the results in the destination floating-point register. Restrictions There are no restrictions. Condition Flags The floating-point instruction clears the sign bit. Examples VABS.F32 S4, S6 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 167 12.6.11.2 VADD Floating-point Add Syntax VADD{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd, is the destination floating-point value. Sn, Sm are the operand floating-point values. Operation This instruction: 1. Adds the values in the two floating-point operand registers. 2. Places the results in the destination floating-point register. Restrictions There are no restrictions. Condition Flags This instruction does not change the flags. Examples VADD.F32 S4, S6, S7 168 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.3 VCMP, VCMPE Compares two floating-point registers, or one floating-point register and zero. Syntax VCMP{E}{cond}.F32 Sd, Sm VCMP{E}{cond}.F32 Sd, #0.0 where: cond is an optional condition code, see “Conditional Execution”. E If present, any NaN operand causes an Invalid Operation exception. Otherwise, only a signaling NaN causes the exception. Sd is the floating-point operand to compare. Sm is the floating-point operand that is compared with. Operation This instruction: 1. Compares: 2. ̶ Two floating-point registers. ̶ One floating-point register and zero. Writes the result to the FPSCR flags. Restrictions This instruction can optionally raise an Invalid Operation exception if either operand is any type of NaN. It always raises an Invalid Operation exception if either operand is a signaling NaN. Condition Flags When this instruction writes the result to the FPSCR flags, the values are normally transferred to the ARM flags by a subsequent VMRS instruction, see “”. Examples VCMP.F32 VCMP.F32 S4, #0.0 S4, S2 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 169 12.6.11.4 VCVT, VCVTR between Floating-point and Integer Converts a value in a register from floating-point to a 32-bit integer. Syntax VCVT{R}{cond}.Tm.F32 Sd, Sm VCVT{cond}.F32.Tm Sd, Sm where: R If R is specified, the operation uses the rounding mode specified by the FPSCR. If R is omitted. the operation uses the Round towards Zero rounding mode. cond is an optional condition code, see “Conditional Execution”. Tm is the data type for the operand. It must be one of: S32 signed 32- U32 unsigned 32-bit value. bit value. Sd, Sm are the destination register and the operand register. Operation These instructions: 1. Either 2. ̶ Converts a value in a register from floating-point value to a 32-bit integer. ̶ Converts from a 32-bit integer to floating-point value. Places the result in a second register. The floating-point to integer operation normally uses the Round towards Zero rounding mode, but can optionally use the rounding mode specified by the FPSCR. The integer to floating-point operation uses the rounding mode specified by the FPSCR. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. 170 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.5 VCVT between Floating-point and Fixed-point Converts a value in a register from floating-point to and from fixed-point. Syntax VCVT{cond}.Td.F32 Sd, Sd, #fbits VCVT{cond}.F32.Td Sd, Sd, #fbits where: cond is an optional condition code, see “Conditional Execution”. Td is the data type for the fixed-point number. It must be one of: S16 U16 signed 16-bit value. unsigned 16-bit value. S32 U32 signed 32-bit value. unsigned 32-bit value. Sd is the destination register and the operand register. fbits is the number of fraction bits in the fixed-point number: If Td is S16 or U16, fbits must be in the range 0–16. If Td is S32 or U32, fbits must be in the range 1–32. Operation These instructions: 1. Either ̶ ̶ 2. Converts a value in a register from floating-point to fixed-point. Converts a value in a register from fixed-point to floating-point. Places the result in a second register. The floating-point values are single-precision. The fixed-point value can be 16-bit or 32-bit. Conversions from fixed-point values take their operand from the loworder bits of the source register and ignore any remaining bits. Signed conversions to fixed-point values sign-extend the result value to the destination register width. Unsigned conversions to fixed-point values zero-extend the result value to the destination register width. The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floatingpoint operation uses the Round to Nearest rounding mode. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 171 12.6.11.6 VCVTB, VCVTT Converts between a half-precision value and a single-precision value. Syntax VCVT{y}{cond}.F32.F16 Sd, Sm VCVT{y}{cond}.F16.F32 Sd, Sm where: y Specifies which half of the operand register Sm or destination register Sd is used for the operand or destination: - If y is B, then the bottom half, bits [15:0], of Sm or Sd is used. - If y is T, then the top half, bits [31:16], of Sm or Sd is used. cond is an optional condition code, see “Conditional Execution”. Sd is the destination register. Sm is the operand register. Operation This instruction with the.F16.32 suffix: 1. Converts the half-precision value in the top or bottom half of a single-precision. register to singleprecision. 2. Writes the result to a single-precision register. This instruction with the.F32.F16 suffix: 1. Converts the value in a single-precision register to half-precision. 2. Writes the result into the top or bottom half of a single-precision register, preserving the other half of the target register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. 172 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.7 VDIV Divides floating-point values. Syntax VDIV{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination register. Sn, Sm are the operand registers. Operation This instruction: 1. Divides one floating-point value by another floating-point value. 2. Writes the result to the floating-point destination register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 173 12.6.11.8 VFMA, VFMS Floating-point Fused Multiply Accumulate and Subtract. Syntax VFMA{cond}.F32 {Sd,} Sn, Sm VFMS{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination register. Sn, Sm are the operand registers. Operation The VFMA instruction: 1. Multiplies the floating-point values in the operand registers. 2. Accumulates the results into the destination register. The result of the multiply is not rounded before the accumulation. The VFMS instruction: 1. Negates the first operand register. 2. Multiplies the floating-point values of the first and second operand registers. 3. Adds the products to the destination register. 4. Places the results in the destination register. The result of the multiply is not rounded before the addition. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. 174 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.9 VFNMA, VFNMS Floating-point Fused Negate Multiply Accumulate and Subtract. Syntax VFNMA{cond}.F32 {Sd,} Sn, Sm VFNMS{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination register. Sn, Sm are the operand registers. Operation The VFNMA instruction: 1. Negates the first floating-point operand register. 2. Multiplies the first floating-point operand with second floating-point operand. 3. Adds the negation of the floating -point destination register to the product 4. Places the result into the destination register. The result of the multiply is not rounded before the addition. The VFNMS instruction: 1. Multiplies the first floating-point operand with second floating-point operand. 2. Adds the negation of the floating-point value in the destination register to the product. 3. Places the result in the destination register. The result of the multiply is not rounded before the addition. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 175 12.6.11.10 VLDM Floating-point Load Multiple Syntax VLDM{mode}{cond}{.size} Rn{!}, list where: mode is the addressing mode: - IA Increment After. The consecutive addresses start at the address speci fied in Rn. - DB Decrement Before. The consecutive addresses end just before the address specified in Rn. cond is an optional condition code, see “Conditional Execution”. size is an optional data size specifier. Rn is the base register. The SP can be used ! is the command to the instruction to write a modified value back to Rn. This is required if mode == DB, and is optional if mode == IA. list is the list of extension registers to be loaded, as a list of consecutively numbered doubleword or singleword registers, separated by commas and surrounded by brackets. Operation This instruction loads: Multiple extension registers from consecutive memory locations using an address from an ARM core register as the base address. Restrictions The restrictions are: If size is present, it must be equal to the size in bits, 32 or 64, of the registers in list. For the base address, the SP can be used. In the ARM instruction set, if ! is not specified the PC can be used. list must contain at least one register. If it contains doubleword registers, it must not contain more than 16 registers. If using the Decrement Before addressing mode, the write back flag, !, must be appended to the base register specification. Condition Flags These instructions do not change the flags. 176 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.11 VLDR Loads a single extension register from memory Syntax VLDR{cond}{.64} VLDR{cond}{.64} VLDR{cond}{.64} VLDR{cond}{.32} VLDR{cond}{.32} VLDR{cond}{.32} Dd, Dd, Dd, Sd, Sd, Sd, [Rn{#imm}] label [PC, #imm}] [Rn {, #imm}] label [PC, #imm] where: cond is an optional condition code, see “Conditional Execution”. 64, 32 are the optional data size specifiers. Dd is the destination register for a doubleword load. Sd is the destination register for a singleword load. Rn is the base register. The SP can be used. imm is the + or - immediate offset used to form the address. Permitted address values are multiples of 4 in the range 0 to 1020. label is the label of the literal data item to be loaded. Operation This instruction: Loads a single extension register from memory, using a base address from an ARM core register, with an optional offset. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 177 12.6.11.12 VLMA, VLMS Multiplies two floating-point values, and accumulates or subtracts the results. Syntax VLMA{cond}.F32 Sd, Sn, Sm VLMS{cond}.F32 Sd, Sn, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination floating-point value. Sn, Sm are the operand floating-point values. Operation The floating-point Multiply Accumulate instruction: 1. Multiplies two floating-point values. 2. Adds the results to the destination floating-point value. The floating-point Multiply Subtract instruction: 1. Multiplies two floating-point values. 2. Subtracts the products from the destination floating-point value. 3. Places the results in the destination register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. 178 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.13 VMOV Immediate Move floating-point Immediate Syntax VMOV{cond}.F32 Sd, #imm where: cond is an optional condition code, see “Conditional Execution”. Sd is the branch destination. imm is a floating-point constant. Operation This instruction copies a constant value to a floating-point register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 179 12.6.11.14 VMOV Register Copies the contents of one register to another. Syntax VMOV{cond}.F64 Dd, Dm VMOV{cond}.F32 Sd, Sm where: cond is an optional condition code, see “Conditional Execution”. Dd is the destination register, for a doubleword operation. Dm is the source register, for a doubleword operation. Sd is the destination register, for a singleword operation. Sm is the source register, for a singleword operation. Operation This instruction copies the contents of one floating-point register to another. Restrictions There are no restrictions Condition Flags These instructions do not change the flags. 180 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.15 VMOV Scalar to ARM Core Register Transfers one word of a doubleword floating-point register to an ARM core register. Syntax VMOV{cond} Rt, Dn[x] where: cond is an optional condition code, see “Conditional Execution”. Rt is the destination ARM core register. Dn is the 64-bit doubleword register. x Specifies which half of the doubleword register to use: - If x is 0, use lower half of doubleword register - If x is 1, use upper half of doubleword register. Operation This instruction transfers: One word from the upper or lower half of a doubleword floating-point register to an ARM core register. Restrictions Rt cannot be PC or SP. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 181 12.6.11.16 VMOV ARM Core Register to Single Precision Transfers a single-precision register to and from an ARM core register. Syntax VMOV{cond} Sn, Rt VMOV{cond} Rt, Sn where: cond is an optional condition code, see “Conditional Execution”. Sn is the single-precision floating-point register. Rt is the ARM core register. Operation This instruction transfers: The contents of a single-precision register to an ARM core register. The contents of an ARM core register to a single-precision register. Restrictions Rt cannot be PC or SP. Condition Flags These instructions do not change the flags. 182 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.17 VMOV Two ARM Core Registers to Two Single Precision Transfers two consecutively numbered single-precision registers to and from two ARM core registers. Syntax VMOV{cond} Sm, Sm1, Rt, Rt2 VMOV{cond} Rt, Rt2, Sm, Sm where: cond is an optional condition code, see “Conditional Execution”. Sm is the first single-precision register. Sm1 is the second single-precision register. This is the next single-precision register after Sm. Rt is the ARM core register that Sm is transferred to or from. Rt2 is the The ARM core register that Sm1 is transferred to or from. Operation This instruction transfers: The contents of two consecutively numbered single-precision registers to two ARM core registers. The contents of two ARM core registers to a pair of single-precision registers. Restrictions The restrictions are: The floating-point registers must be contiguous, one after the other. The ARM core registers do not have to be contiguous. Rt cannot be PC or SP. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 183 12.6.11.18 VMOV ARM Core Register to Scalar Transfers one word to a floating-point register from an ARM core register. Syntax VMOV{cond}{.32} Dd[x], Rt where: cond is an optional condition code, see “Conditional Execution”. 32 is an optional data size specifier. Dd[x] is the destination, where [x] defines which half of the doubleword is transferred, as follows: If x is 0, the lower half is extracted If x is 1, the upper half is extracted. Rt is the source ARM core register. Operation This instruction transfers one word to the upper or lower half of a doubleword floating-point register from an ARM core register. Restrictions Rt cannot be PC or SP. Condition Flags These instructions do not change the flags. 184 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.19 VMRS Move to ARM Core register from floating-point System Register. Syntax VMRS{cond} Rt, FPSCR VMRS{cond} APSR_nzcv, FPSCR where: cond is an optional condition code, see “Conditional Execution”. Rt is the destination ARM core register. This register can be R0–R14. APSR_nzcv Transfer floating-point flags to the APSR flags. Operation This instruction performs one of the following actions: Copies the value of the FPSCR to a general-purpose register. Copies the value of the FPSCR flag bits to the APSR N, Z, C, and V flags. Restrictions Rt cannot be PC or SP. Condition Flags These instructions optionally change the flags: N, Z, C, V SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 185 12.6.11.20 VMSR Move to floating-point System Register from ARM Core register. Syntax VMSR{cond} FPSCR, Rt where: cond is an optional condition code, see “Conditional Execution”. Rt is the general-purpose register to be transferred to the FPSCR. Operation This instruction moves the value of a general-purpose register to the FPSCR. See “Floating-point Status Control Register” for more information. Restrictions The restrictions are: Rt cannot be PC or SP. Condition Flags This instruction updates the FPSCR. 186 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.21 VMUL Floating-point Multiply. Syntax VMUL{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination floating-point value. Sn, Sm are the operand floating-point values. Operation This instruction: 1. Multiplies two floating-point values. 2. Places the results in the destination register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 187 12.6.11.22 VNEG Floating-point Negate. Syntax VNEG{cond}.F32 Sd, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination floating-point value. Sm is the operand floating-point value. Operation This instruction: 1. Negates a floating-point value. 2. Places the results in a second floating-point register. The floating-point instruction inverts the sign bit. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. 188 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.23 VNMLA, VNMLS, VNMUL Floating-point multiply with negation followed by add or subtract. Syntax VNMLA{cond}.F32 Sd, Sn, Sm VNMLS{cond}.F32 Sd, Sn, Sm VNMUL{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination floating-point register. Sn, Sm are the operand floating-point registers. Operation The VNMLA instruction: 1. Multiplies two floating-point register values. 2. Adds the negation of the floating-point value in the destination register to the negation of the product. 3. Writes the result back to the destination register. The VNMLS instruction: 1. Multiplies two floating-point register values. 2. Adds the negation of the floating-point value in the destination register to the product. 3. Writes the result back to the destination register. The VNMUL instruction: 1. Multiplies together two floating-point register values. 2. Writes the negation of the result to the destination register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 189 12.6.11.24 VPOP Floating-point extension register Pop. Syntax VPOP{cond}{.size} list where: cond is an optional condition code, see “Conditional Execution”. size is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list. list is the list of extension registers to be loaded, as a list of consecutively numbered doubleword or singleword registers, separated by commas and surrounded by brackets. Operation This instruction loads multiple consecutive extension registers from the stack. Restrictions The list must contain at least one register, and not more than sixteen registers. Condition Flags These instructions do not change the flags. 190 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.25 VPUSH Floating-point extension register Push. Syntax VPUSH{cond}{.size} list where: cond is an optional condition code, see “Conditional Execution”. size is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list. list is a list of the extension registers to be stored, as a list of consecutively num bered doubleword or singleword registers, separated by commas and sur rounded by brackets. Operation This instruction: Stores multiple consecutive extension registers to the stack. Restrictions The restrictions are: list must contain at least one register, and not more than sixteen. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 191 12.6.11.26 VSQRT Floating-point Square Root. Syntax VSQRT{cond}.F32 Sd, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination floating-point value. Sm is the operand floating-point value. Operation This instruction: Calculates the square root of the value in a floating-point register. Writes the result to another floating-point register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. 192 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.27 VSTM Floating-point Store Multiple. Syntax VSTM{mode}{cond}{.size} Rn{!}, list where: mode is the addressing mode: - IA Increment After. The consecutive addresses start at the address speci fied in Rn. This is the default and can be omitted. - DB Decrement Before. The consecutive addresses end just before the address specified in Rn. cond is an optional condition code, see “Conditional Execution”. size is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list. Rn is the base register. The SP can be used ! is the function that causes the instruction to write a modified value back to Rn. Required if mode == DB. list is a list of the extension registers to be stored, as a list of consecutively num bered doubleword or singleword registers, separated by commas and sur rounded by brackets. Operation This instruction: Stores multiple extension registers to consecutive memory locations using a base address from an ARM core register. Restrictions The restrictions are: list must contain at least one register. If it contains doubleword registers it must not contain more than 16 registers. Use of the PC as Rn is deprecated. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 193 12.6.11.28 VSTR Floating-point Store. Syntax VSTR{cond}{.32} Sd, [Rn{, #imm}] VSTR{cond}{.64} Dd, [Rn{, #imm}] where cond is an optional condition code, see “Conditional Execution”. 32, 64 are the optional data size specifiers. Sd is the source register for a singleword store. Dd is the source register for a doubleword store. Rn is the base register. The SP can be used. imm is the + or - immediate offset used to form the address. Values are multiples of 4 in the range 0–1020. imm can be omitted, meaning an offset of +0. Operation This instruction: Stores a single extension register to memory, using an address from an ARM core register, with an optional offset, defined in imm. Restrictions The restrictions are: The use of PC for Rn is deprecated. Condition Flags These instructions do not change the flags. 194 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.11.29 VSUB Floating-point Subtract. Syntax VSUB{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution”. Sd is the destination floating-point value. Sn, Sm are the operand floating-point value. Operation This instruction: 1. Subtracts one floating-point value from another floating-point value. 2. Places the results in the destination floating-point register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 195 12.6.12 Miscellaneous Instructions The table below shows the remaining Cortex-M4 instructions. Table 12-28. 196 Miscellaneous Instructions Mnemonic Description BKPT Breakpoint CPSID Change Processor State, Disable Interrupts CPSIE Change Processor State, Enable Interrupts DMB Data Memory Barrier DSB Data Synchronization Barrier ISB Instruction Synchronization Barrier MRS Move from special register to register MSR Move from register to special register NOP No Operation SEV Send Event SVC Supervisor Call WFE Wait For Event WFI Wait For Interrupt SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.12.1 BKPT Breakpoint. Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0–255 (8-bit value). Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition specified by the IT instruction. Condition Flags This instruction does not change the flags. Examples BKPT 0xAB Note: ; Breakpoint with immediate value set to 0xAB (debugger can ; extract the immediate value by locating it using the PC) ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other than Semi-hosting. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 197 12.6.12.2 CPS Change Processor State. Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register. iflags is a sequence of one or more flags: i Set or clear PRIMASK. f Set or clear FAULTMASK. Operation CPS changes the PRIMASK and FAULTMASK special register values. See “Exception Mask Registers” for more information about these registers. Restrictions The restrictions are: Use CPS only from privileged software, it has no effect if used in unprivileged software CPS cannot be conditional and so must not be used inside an IT block. Condition Flags This instruction does not change the condition flags. Examples CPSID CPSID CPSIE CPSIE 198 i f i f ; ; ; ; Disable interrupts and configurable fault handlers (set PRIMASK) Disable interrupts and all fault handlers (set FAULTMASK) Enable interrupts and configurable fault handlers (clear PRIMASK) Enable interrupts and fault handlers (clear FAULTMASK) SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.12.3 DMB Data Memory Barrier. Syntax DMB{cond} where: cond is an optional condition code, see “Conditional Execution”. Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory. Condition Flags This instruction does not change the flags. Examples DMB ; Data Memory Barrier SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 199 12.6.12.4 DSB Data Synchronization Barrier. Syntax DSB{cond} where: cond is an optional condition code, see “Conditional Execution”. Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete. Condition Flags This instruction does not change the flags. Examples DSB ; Data Synchronisation Barrier 200 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.12.5 ISB Instruction Synchronization Barrier. Syntax ISB{cond} where: cond is an optional condition code, see “Conditional Execution”. Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ISB instruction has been completed. Condition Flags This instruction does not change the flags. Examples ISB ; Instruction Synchronisation Barrier SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 201 12.6.12.6 MRS Move the contents of a special register to a general-purpose register. Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see “Conditional Execution”. Rd is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. Operation Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag. In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence. Note: BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction. See “MSR”. Restrictions Rd must not be SP and must not be PC. Condition Flags This instruction does not change the flags. Examples MRS 202 R0, PRIMASK ; Read PRIMASK value and write it to R0 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.12.7 MSR Move the contents of a general-purpose register into the specified special register. Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see “Conditional Execution”. Rn is the source register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. Operation The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR. See “Application Program Status Register”. Privileged software can access all special registers. In unprivileged software writes to unallocated or execution state bits in the PSR are ignored. Note: When the user writes to BASEPRI_MAX, the instruction writes to BASEPRI only if either: Rn is non-zero and the current BASEPRI value is 0 Rn is non-zero and less than the current BASEPRI value. See “MRS”. Restrictions Rn must not be SP and must not be PC. Condition Flags This instruction updates the flags explicitly based on the value in Rn. Examples MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 203 12.6.12.8 NOP No Operation. Syntax NOP{cond} where: cond is an optional condition code, see “Conditional Execution”. Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary. Condition Flags This instruction does not change the flags. Examples NOP 204 ; No operation SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.12.9 SEV Send Event. Syntax SEV{cond} where: cond is an optional condition code, see “Conditional Execution”. Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see “Power Management”. Condition Flags This instruction does not change the flags. Examples SEV ; Send Event SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 205 12.6.12.10 SVC Supervisor Call. Syntax SVC{cond} #imm where: cond is an optional condition code, see “Conditional Execution”. imm is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested. Condition Flags This instruction does not change the flags. Examples SVC 206 0x32 ; Supervisor Call (SVC handler can extract the immediate value ; by locating it via the stacked PC) SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.6.12.11 WFE Wait For Event. Syntax WFE{cond} where: cond is an optional condition code, see “Conditional Execution”. Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs: An exception, unless masked by the exception mask registers or the current priority level An exception enters the Pending state, if SEVONPEND in the System Control Register is set A Debug Entry request, if Debug is enabled An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction. If the event register is 1, WFE clears it to 0 and returns immediately. For more information, see “Power Management”. Condition Flags This instruction does not change the flags. Examples WFE ; Wait for event SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 207 12.6.12.12 WFI Wait for Interrupt. Syntax WFI{cond} where: cond is an optional condition code, see “Conditional Execution”. Operation WFI is a hint instruction that suspends execution until one of the following events occurs: An exception A Debug Entry request, regardless of whether Debug is enabled. Condition Flags This instruction does not change the flags. Examples WFI ; Wait for interrupt 208 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.7 Cortex-M4 Core Peripherals 12.7.1 Peripherals Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. See Section 12.8 ”Nested Vectored Interrupt Controller (NVIC)”. System Control Block (SCB) The System Control Block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. See Section 12.9 ”System Control Block (SCB)”. System Timer (SysTick) The System Timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter. See Section 12.10 ”System Timer (SysTick)”. Memory Protection Unit (MPU) The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different memory regions. It provides up to eight different regions, and an optional predefined background region. See Section 12.11 ”Memory Protection Unit (MPU)”. Floating-point Unit (FPU) The Floating-point Unit (FPU) provides IEEE754-compliant operations on single-precision, 32-bit, floatingpoint values. See Section 12.12 ”Floating Point Unit (FPU)”. 12.7.2 Address Map The address map of the Private peripheral bus (PPB) is given in the following table. Table 12-29. Core Peripheral Register Regions Address Core Peripheral 0xE000E008–0xE000E00F System Control Block 0xE000E010–0xE000E01F System Timer 0xE000E100–0xE000E4EF Nested Vectored Interrupt Controller 0xE000ED00–0xE000ED3F System control block 0xE000ED90–0xE000EDB8 Memory Protection Unit 0xE000EF00–0xE000EF03 Nested Vectored Interrupt Controller 0xE000EF30–0xE000EF44 Floating-point Unit In register descriptions: The required privilege gives the privilege level required to access the register, as follows: ̶ Privileged: Only privileged software can access the register. ̶ Unprivileged: Both unprivileged and privileged software can access the register. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 209 12.8 Nested Vectored Interrupt Controller (NVIC) This section describes the NVIC and the registers it uses. The NVIC supports: Up to 47 interrupts A programmable priority level of 0–15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. Level detection of interrupt signals Dynamic reprioritization of interrupts Grouping of priority values into group priority and subpriority fields Interrupt tail-chaining An external Non-maskable interrupt (NMI) The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. 12.8.1 Level-sensitive Interrupts The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts”). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing. 12.8.1.1 Hardware and Software Control of Interrupts The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: The NVIC detects that the interrupt signal is HIGH and the interrupt is not active The NVIC detects a rising edge on the interrupt signal A software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending Registers”, or to the NVIC_STIR to make an interrupt pending, see “Software Trigger Interrupt Register”. A pending interrupt remains pending until one of the following: The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then: ̶ For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. Software writes to the corresponding interrupt clear-pending register bit. For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. 12.8.2 NVIC Design Hints and Tips Ensure that the software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt. 210 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Before programming SCB_VTOR to relocate the vector table, ensure that the vector table entries of the new vector table are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the “Vector Table Offset Register”. 12.8.2.1 NVIC Programming Hints The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: Table 12-30. CMSIS Functions for NVIC Control CMSIS Interrupt Control Function Description void NVIC_SetPriorityGrouping(uint32_t priority_grouping) Set the priority grouping void NVIC_EnableIRQ(IRQn_t IRQn) Enable IRQn void NVIC_DisableIRQ(IRQn_t IRQn) Disable IRQn uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn) Return true (IRQ-Number) if IRQn is pending void NVIC_SetPendingIRQ (IRQn_t IRQn) Set IRQn pending void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status uint32_t NVIC_GetActive (IRQn_t IRQn) Return the IRQ number of the active interrupt void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn void NVIC_SystemReset (void) Reset the system The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS documentation. To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS: The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit integers, so that: ̶ The array ISER[0] to ISER[1] corresponds to the registers ISER0–ISER1 ̶ The array ICER[0] to ICER[1] corresponds to the registers ICER0–ICER1 ̶ The array ISPR[0] to ISPR[1] corresponds to the registers ISPR0–ISPR1 ̶ The array ICPR[0] to ICPR[1] corresponds to the registers ICPR0–ICPR1 ̶ The array IABR[0] to IABR[1] corresponds to the registers IABR0–IABR1 The Interrupt Priority Registers (IPR0–IPR11) provide an 8-bit priority field for each interrupt and each register holds four priority fields. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 211 The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. Table 12-31 shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt. Table 12-31. Mapping of Interrupts CMSIS Array Elements (1) Interrupts Set-enable Clear-enable Set-pending Clear-pending Active Bit 0–31 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0] 32–47 ISER[1] ICER[1] ISPR[1] ICPR[1] IABR[1] Note: 212 1. Each array element corresponds to a single NVIC register, for example the ICER[0] element corresponds to the ICER0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface Table 12-32. Nested Vectored Interrupt Controller (NVIC) Register Mapping Offset Register Name Access Reset 0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read/Write 0x00000000 0XE000E180 Interrupt Clear-enable Register 0 NVIC_ICER0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E19C Interrupt Clear-enable Register 7 NVIC_ICER7 Read/Write 0x00000000 0XE000E200 Interrupt Set-pending Register 0 NVIC_ISPR0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E21C Interrupt Set-pending Register 7 NVIC_ISPR7 Read/Write 0x00000000 0XE000E280 Interrupt Clear-pending Register 0 NVIC_ICPR0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E29C Interrupt Clear-pending Register 7 NVIC_ICPR7 Read/Write 0x00000000 0xE000E300 Interrupt Active Bit Register 0 NVIC_IABR0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E31C Interrupt Active Bit Register 7 NVIC_IABR7 Read/Write 0x00000000 0xE000E400 Interrupt Priority Register 0 NVIC_IPR0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E42C Interrupt Priority Register 11 NVIC_IPR11 Read/Write 0x00000000 0xE000EF00 Software Trigger Interrupt Register NVIC_STIR Write-only 0x00000000 Note: If an offset is not listed in the table, it must be considered as reserved. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 213 12.8.3.1 Interrupt Set-enable Registers Name: NVIC_ISERx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETENA 23 22 21 20 SETENA 15 14 13 12 SETENA 7 6 5 4 SETENA These registers enable interrupts and show which interrupts are enabled. • SETENA: Interrupt Set-enable Write: 0: No effect. 1: Enables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled. Notes: 214 1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. 2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never activates the interrupt, regardless of its priority. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.8.3.2 Interrupt Clear-enable Registers Name: NVIC_ICERx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRENA 23 22 21 20 CLRENA 15 14 13 12 CLRENA 7 6 5 4 CLRENA These registers disable interrupts, and show which interrupts are enabled. • CLRENA: Interrupt Clear-enable Write: 0: No effect. 1: Disables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 215 12.8.3.3 Interrupt Set-pending Registers Name: NVIC_ISPRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETPEND 23 22 21 20 SETPEND 15 14 13 12 SETPEND 7 6 5 4 SETPEND These registers force interrupts into the pending state, and show which interrupts are pending. • SETPEND: Interrupt Set-pending Write: 0: No effect. 1: Changes the interrupt state to pending. Read: 0: Interrupt is not pending. 1: Interrupt is pending. Notes: 216 1. Writing a 1 to an ISPR bit corresponding to an interrupt that is pending has no effect. 2. Writing a 1 to an ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to pending. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.8.3.4 Interrupt Clear-pending Registers Name: NVIC_ICPRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRPEND 23 22 21 20 CLRPEND 15 14 13 12 CLRPEND 7 6 5 4 CLRPEND These registers remove the pending state from interrupts, and show which interrupts are pending. • CLRPEND: Interrupt Clear-pending Write: 0: No effect. 1: Removes the pending state from an interrupt. Read: 0: Interrupt is not pending. 1: Interrupt is pending. Note: Writing a 1 to an ICPR bit does not affect the active state of the corresponding interrupt. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 217 12.8.3.5 Interrupt Active Bit Registers Name: NVIC_IABRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACTIVE 23 22 21 20 ACTIVE 15 14 13 12 ACTIVE 7 6 5 4 ACTIVE These registers indicate which interrupts are active. • ACTIVE: Interrupt Active Flags 0: Interrupt is not active. 1: Interrupt is active. Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending. 218 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.8.3.6 Interrupt Priority Registers Name: NVIC_IPRx [x=0..11] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI3 23 22 21 20 PRI2 15 14 13 12 PRI1 7 6 5 4 PRI0 The NVIC_IPR0–NVIC_IPR11 registers provide a 8-bit priority field for each interrupt. These registers are byte-accessible. Each register holds four priority fields that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[46]. • PRI3: Priority (4m+3) Priority, Byte Offset 3, refers to register bits [31:24]. • PRI2: Priority (4m+2) Priority, Byte Offset 2, refers to register bits [23:16]. • PRI1: Priority (4m+1) Priority, Byte Offset 1, refers to register bits [15:8]. • PRI0: Priority (4m) Priority, Byte Offset 0, refers to register bits [7:0]. Notes: 1. Each priority field holds a priority value, 0–15. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:4] of each field; bits[3:0] read as zero and ignore writes. 2. For more information about the IP[0] to IP[46] interrupt priority array, that provides the software view of the interrupt priorities, see Table 12-30, “CMSIS Functions for NVIC Control” . 3. The corresponding IPR number n is given by n = m DIV 4. 4. The byte offset of the required Priority field in this register is m MOD 4. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 219 12.8.3.7 Software Trigger Interrupt Register Name: NVIC_STIR Access: Write-only Reset: 0x000000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INTID 7 6 5 4 3 2 1 0 INTID Write to this register to generate an interrupt from the software. • INTID: Interrupt ID Interrupt ID of the interrupt to trigger, in the range 0–239. For example, a value of 0x03 specifies interrupt IRQ3. 220 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9 System Control Block (SCB) The System Control Block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. Ensure that the software uses aligned accesses of the correct size to access the system control block registers: Except for the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it must use aligned word accesses For the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. In a fault handler, to determine the true faulting address: 1. Read and save the MMFAR or SCB_BFAR value. 2. Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the BFSR subregister. The SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1. The software must follow this sequence because another higher priority exception might change the SCB_MMFAR or SCB_BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the SCB_MMFAR or SCB_BFAR value. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 221 12.9.1 System Control Block (SCB) User Interface Table 12-33. System Control Block (SCB) Register Mapping Offset Register Name Access Reset 0xE000E008 Auxiliary Control Register SCB_ACTLR Read/Write 0x00000000 0xE000ED00 CPUID Base Register SCB_CPUID Read-only 0x410FC240 0xE000ED04 Interrupt Control and State Register SCB_ICSR Read/Write(1) 0x00000000 0xE000ED08 Vector Table Offset Register SCB_VTOR Read/Write 0x00000000 0xE000ED0C Application Interrupt and Reset Control Register SCB_AIRCR Read/Write 0xFA050000 0xE000ED10 System Control Register SCB_SCR Read/Write 0x00000000 0xE000ED14 Configuration and Control Register SCB_CCR Read/Write 0x00000200 0xE000ED18 System Handler Priority Register 1 SCB_SHPR1 Read/Write 0x00000000 0xE000ED1C System Handler Priority Register 2 SCB_SHPR2 Read/Write 0x00000000 0xE000ED20 System Handler Priority Register 3 SCB_SHPR3 Read/Write 0x00000000 0xE000ED24 System Handler Control and State Register SCB_SHCSR Read/Write 0x00000000 (2) Read/Write 0x00000000 0xE000ED28 Configurable Fault Status Register SCB_CFSR 0xE000ED2C HardFault Status Register SCB_HFSR Read/Write 0x00000000 0xE000ED34 MemManage Fault Address Register SCB_MMFAR Read/Write Unknown 0xE000ED38 BusFault Address Register SCB_BFAR Read/Write Unknown 0xE000ED3C Auxiliary Fault Status Register SCB_AFSR Read/Write 0x00000000 Notes: 222 1. See the register description for more information. 2. This register contains the subregisters: “MMFSR: Memory Management Fault Status Subregister” (0xE000ED28 - 8 bits), “BFSR: Bus Fault Status Subregister” (0xE000ED29 - 8 bits), “UFSR: Usage Fault Status Subregister” (0xE000ED2A - 16 bits). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.1 Auxiliary Control Register Name: SCB_ACTLR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 DISOOFP 8 DISFPCA 7 – 6 – 5 – 4 – 3 – 2 DISFOLD 1 DISDEFWBUF 0 DISMCYCINT The SCB_ACTLR provides disable bits for the following processor functions: • IT folding • Write buffer use for accesses to the default memory map • Interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally require modification. • DISOOFP: Disable Out Of Order Floating Point Disables floating point instructions that complete out of order with respect to integer instructions. • DISFPCA: Disable FPCA Disables an automatic update of CONTROL.FPCA. • DISFOLD: Disable Folding When set to 1, disables the IT folding. Note: In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding. • DISDEFWBUF: Disable Default Write Buffer When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise but decreases the performance, as any store to memory must complete before the processor can execute the next instruction. This bit only affects write buffers implemented in the Cortex-M4 processor. • DISMCYCINT: Disable Multiple Cycle Interruption When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the interrupt latency of the processor, as any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 223 12.9.1.2 CPUID Base Register Name: SCB_CPUID Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 9 8 1 0 Implementer 23 22 21 20 Variant 15 14 Constant 13 12 11 10 3 2 PartNo 7 6 5 4 PartNo Revision The SCB_CPUID register contains the processor part number, version, and implementation information. • Implementer: Implementer Code 0x41: ARM. • Variant: Variant Number It is the r value in the rnpn product revision identifier: 0x0: Revision 0. • Constant: Reads as 0xF Reads as 0xF. • PartNo: Part Number of the Processor 0xC24 = Cortex-M4. • Revision: Revision Number It is the p value in the rnpn product revision identifier: 0x0: Patch 0. 224 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.3 Interrupt Control and State Register Name: SCB_ICSR Access: Read/Write 31 NMIPENDSET 30 29 28 PENDSVSET 23 – 22 ISRPENDING 21 20 15 14 13 VECTPENDING 12 7 6 4 – 5 27 PENDSVCLR 26 PENDSTSET 19 18 VECTPENDING 25 PENDSTCLR 24 – 17 16 11 RETTOBASE 10 – 9 – 8 VECTACTIVE 3 2 1 0 VECTACTIVE The SCB_ICSR provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and clearpending bits for the PendSV and SysTick exceptions. It indicates: • The exception number of the exception being processed, and whether there are preempted active exceptions, • The exception number of the highest priority pending exception, and whether any interrupts are pending. • NMIPENDSET: NMI Set-pending Write: PendSV set-pending bit. Write: 0: No effect. 1: Changes NMI exception state to pending. Read: 0: NMI exception is not pending. 1: NMI exception is pending. As NMI is the highest-priority exception, the processor normally enters the NMI exception handler as soon as it registers a write of 1 to this bit. Entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. • PENDSVSET: PendSV Set-pending Write: 0: No effect. 1: Changes PendSV exception state to pending. Read: 0: PendSV exception is not pending. 1: PendSV exception is pending. Writing a 1 to this bit is the only way to set the PendSV exception state to pending. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 225 • PENDSVCLR: PendSV Clear-pending Write: 0: No effect. 1: Removes the pending state from the PendSV exception. • PENDSTSET: SysTick Exception Set-pending Write: 0: No effect. 1: Changes SysTick exception state to pending. Read: 0: SysTick exception is not pending. 1: SysTick exception is pending. • PENDSTCLR: SysTick Exception Clear-pending Write: 0: No effect. 1: Removes the pending state from the SysTick exception. This bit is Write-only. On a register read, its value is Unknown. • ISRPENDING: Interrupt Pending Flag (Excluding NMI and Faults) 0: Interrupt not pending. 1: Interrupt pending. • VECTPENDING: Exception Number of the Highest Priority Pending Enabled Exception 0: No pending exceptions. Nonzero: The exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. • RETTOBASE: Preempted Active Exceptions Present or Not 0: There are preempted active exceptions to execute. 1: There are no active exceptions, or the currently-executing exception is the only active exception. • VECTACTIVE: Active Exception Number Contained 0: Thread mode. Nonzero: The exception number of the currently active exception. The value is the same as IPSR bits [8:0]. See “Interrupt Program Status Register”. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, ClearPending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register”. Note: When the user writes to the SCB_ICSR, the effect is unpredictable if: - Writing a 1 to the PENDSVSET bit and writing a 1 to the PENDSVCLR bit - Writing a 1 to the PENDSTSET bit and writing a 1 to the PENDSTCLR bit. 226 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.4 Vector Table Offset Register Name: SCB_VTOR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 – TBLOFF 23 22 21 20 TBLOFF 15 14 13 12 TBLOFF 7 TBLOFF 6 – 5 – 4 – The SCB_VTOR indicates the offset of the vector table base address from memory address 0x00000000. • TBLOFF: Vector Table Base Offset It contains bits [29:7] of the offset of the table base from the bottom of the memory map. Bit [29] determines whether the vector table is in the code or SRAM memory region: 0: Code. 1: SRAM. It is sometimes called the TBLBASE bit. Note: When setting TBLOFF, the offset must be aligned to the number of exception entries in the vector table. Configure the next statement to give the information required for your implementation; the statement reminds the user of how to determine the alignment requirement. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if 21 interrupts are required, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64. Table alignment requirements mean that bits[6:0] of the table offset are always zero. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 227 12.9.1.5 Application Interrupt and Reset Control Register Name: SCB_AIRCR Access: Read/Write 31 30 29 28 27 VECTKEYSTAT/VECTKEY 26 25 24 23 22 21 20 19 VECTKEYSTAT/VECTKEY 18 17 16 15 ENDIANNESS 14 – 13 – 12 – 11 – 10 9 PRIGROUP 8 7 – 6 – 5 – 4 – 3 – 2 1 0 SYSRESETREQ VECTCLRACTIVE VECTRESET The SCB_AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, write 0x5FA to the VECTKEY field, otherwise the processor ignores the write. • VECTKEYSTAT: Register Key (Read) Reads as 0xFA05. • VECTKEY: Register Key (Write) Writes 0x5FA to VECTKEY, otherwise the write is ignored. • ENDIANNESS: Data Endianness 0: Little-endian. 1: Big-endian. • PRIGROUP: Interrupt Priority Grouping This field determines the split of group priority from subpriority. It shows the position of the binary point that splits the PRI_n fields in the Interrupt Priority Registers into separate group priority and subpriority fields. The table below shows how the PRIGROUP value controls this split. Interrupt Priority Level Value, PRI_N[7:0] Number of PRIGROUP Binary Point (1) Group Priority Bits Subpriority Bits Group Priorities Subpriorities 0b000 bxxxxxxx.y [7:1] None 128 2 0b001 bxxxxxx.yy [7:2] [4:0] 64 4 0b010 bxxxxx.yyy [7:3] [4:0] 32 8 0b011 bxxxx.yyyy [7:4] [4:0] 16 16 0b100 bxxx.yyyyy [7:5] [4:0] 8 32 0b101 bxx.yyyyyy [7:6] [5:0] 4 64 0b110 bx.yyyyyyy [7] [6:0] 2 128 0b111 b.yyyyyyy None [7:0] 1 256 Note: 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Determining preemption of an exception uses only the group priority field. 228 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • SYSRESETREQ: System Reset Request 0: No system reset request. 1: Asserts a signal to the outer system that requests a reset. This is intended to force a large system reset of all major components except for debug. This bit reads as 0. • VECTCLRACTIVE: Reserved for Debug use This bit reads as 0. When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable. • VECTRESET: Reserved for Debug use This bit reads as 0. When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 229 12.9.1.6 System Control Register Name: SCB_SCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 SEVONPEND 3 – 2 SLEEPDEEP 1 SLEEPONEXIT 0 – • SEVONPEND: Send Event on Pending Bit 0: Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or an interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. • SLEEPDEEP: Sleep or Deep Sleep Controls whether the processor uses sleep or deep sleep as its low power mode: 0: Sleep. 1: Deep sleep. • SLEEPONEXIT: Sleep-on-exit Indicates sleep-on-exit when returning from the Handler mode to the Thread mode: 0: Do not sleep when returning to Thread mode. 1: Enter sleep, or deep sleep, on return from an ISR. Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application. 230 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.7 Configuration and Control Register Name: SCB_CCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 STKALIGN 8 BFHFNMIGN 7 6 5 4 3 2 1 0 – – – DIV_0_TRP UNALIGN_TRP – NONBASETHRDE USERSETMPEND NA The SCB_CCR controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the access to the NVIC_STIR by unprivileged software (see “Software Trigger Interrupt Register”). • STKALIGN: Stack Alignment Indicates the stack alignment on exception entry: 0: 4-byte aligned. 1: 8-byte aligned. On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. • BFHFNMIGN: Bus Faults Ignored Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the hard fault and FAULTMASK escalated handlers: 0: Data bus faults caused by load and store instructions cause a lock-up. 1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. • DIV_0_TRP: Division by Zero Trap Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: Do not trap divide by 0. 1: Trap divide by 0. When this bit is set to 0, a divide by zero returns a quotient of 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 231 • UNALIGN_TRP: Unaligned Access Trap Enables unaligned access traps: 0: Do not trap unaligned halfword and word accesses. 1: Trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. • USERSETMPEND: Unprivileged Software Access Enables unprivileged software access to the NVIC_STIR, see “Software Trigger Interrupt Register”: 0: Disable. 1: Enable. • NONBASETHRDENA: Thread Mode Enable Indicates how the processor enters Thread mode: 0: The processor can enter the Thread mode only when no exception is active. 1: The processor can enter the Thread mode from any level under the control of an EXC_RETURN value, see “Exception Return”. 232 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.8 System Handler Priority Registers The SCB_SHPR1–SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. They are byte-accessible. The system fault handlers and the priority field and register for each handler are: Table 12-34. System Fault Handler Priority Fields Handler Field Memory management fault (MemManage) PRI_4 Bus fault (BusFault) PRI_5 Usage fault (UsageFault) PRI_6 SVCall PRI_11 PendSV PRI_14 SysTick PRI_15 Register Description System Handler Priority Register 1 System Handler Priority Register 2 System Handler Priority Register 3 Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and ignore writes. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 233 12.9.1.9 System Handler Priority Register 1 Name: SCB_SHPR1 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 PRI_6 15 14 13 12 PRI_5 7 6 5 4 PRI_4 • PRI_6: Priority Priority of system handler 6, UsageFault. • PRI_5: Priority Priority of system handler 5, BusFault. • PRI_4: Priority Priority of system handler 4, MemManage. 234 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.10 System Handler Priority Register 2 Name: SCB_SHPR2 Access: Read/Write 31 30 29 28 27 26 25 24 PRI_11 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PRI_11: Priority Priority of system handler 11, SVCall. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 235 12.9.1.11 System Handler Priority Register 3 Name: SCB_SHPR3 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 PRI_15 23 22 21 20 PRI_14 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PRI_15: Priority Priority of system handler 15, SysTick exception. • PRI_14: Priority Priority of system handler 14, PendSV. 236 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.12 System Handler Control and State Register Name: SCB_SHCSR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 23 – 22 – 21 – 20 – 19 – 15 14 13 12 11 SVCALLPENDED 7 SVCALLACT 26 – 5 – 4 – 24 – 18 17 16 USGFAULTENA BUSFAULTENA MEMFAULTENA BUSFAULTPEND MEMFAULTPEND USGFAULTPEND SYSTICKACT ED ED ED 6 – 25 – 3 USGFAULTACT 10 9 8 PENDSVACT – MONITORACT 2 – 1 0 BUSFAULTACT MEMFAULTACT The SHCSR enables the system handlers, and indicates the pending status of the bus fault, memory management fault, and SVC exceptions; it also indicates the active status of the system handlers. • USGFAULTENA: Usage Fault Enable 0: Disables the exception. 1: Enables the exception. • BUSFAULTENA: Bus Fault Enable 0: Disables the exception. 1: Enables the exception. • MEMFAULTENA: Memory Management Fault Enable 0: Disables the exception. 1: Enables the exception. • SVCALLPENDED: SVC Call Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • BUSFAULTPENDED: Bus Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 237 • MEMFAULTPENDED: Memory Management Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • USGFAULTPENDED: Usage Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • SYSTICKACT: SysTick Exception Active Read: 0: The exception is not active. 1: The exception is active. Note: The user can write to these bits to change the active status of the exceptions. - Caution: A software that changes the value of an active bit in this register without a correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure that the software writing to this register retains and subsequently restores the current active status. - Caution: After enabling the system handlers, to change the value of a bit in this register, the user must use a read-modify-write procedure to ensure that only the required bit is changed. • PENDSVACT: PendSV Exception Active 0: The exception is not active. 1: The exception is active. • MONITORACT: Debug Monitor Active 0: Debug monitor is not active. 1: Debug monitor is active. • SVCALLACT: SVC Call Active 0: SVC call is not active. 1: SVC call is active. • USGFAULTACT: Usage Fault Exception Active 0: Usage fault exception is not active. 1: Usage fault exception is active. • BUSFAULTACT: Bus Fault Exception Active 0: Bus fault exception is not active. 1: Bus fault exception is active. 238 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • MEMFAULTACT: Memory Management Fault Exception Active 0: Memory management fault exception is not active. 1: Memory management fault exception is active. If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault. The user can write to this register to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 239 12.9.1.13 Configurable Fault Status Register Name: SCB_CFSR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 DIVBYZERO 24 UNALIGNED 23 – 22 – 21 – 20 – 19 NOCP 18 INVPC 17 INVSTATE 16 UNDEFINSTR 15 BFARVALID 14 – 13 LSPERR 12 STKERR 11 UNSTKERR 10 IMPRECISERR 9 PRECISERR 8 IBUSERR 7 MMARVALID 6 – 4 MSTKERR 3 MUNSTKERR 2 – 1 DACCVIOL 0 IACCVIOL 5 MLSPERR • IACCVIOL: Instruction Access Violation Flag This is part of “MMFSR: Memory Management Fault Status Subregister”. 0: No instruction access violation fault. 1: The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not written a fault address to the SCB_MMFAR. • DACCVIOL: Data Access Violation Flag This is part of “MMFSR: Memory Management Fault Status Subregister”. 0: No data access violation fault. 1: The processor attempted a load or store at a location that does not permit the operation. When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded the SCB_MMFAR with the address of the attempted access. • MUNSTKERR: Memory Manager Fault on Unstacking for a Return From Exception This is part of “MMFSR: Memory Management Fault Status Subregister”. 0: No unstacking fault. 1: Unstack for an exception return has caused one or more access violations. This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The processor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a fault address to the SCB_MMFAR. • MSTKERR: Memory Manager Fault on Stacking for Exception Entry This is part of “MMFSR: Memory Management Fault Status Subregister”. 0: No stacking fault. 1: Stacking for an exception entry has caused one or more access violations. When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor has not written a fault address to SCB_MMFAR. 240 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • MLSPERR: MemManage During Lazy State Preservation This is part of “MMFSR: Memory Management Fault Status Subregister”. 0: No MemManage fault occurred during the floating-point lazy state preservation. 1: A MemManage fault occurred during the floating-point lazy state preservation. • MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag This is part of “MMFSR: Memory Management Fault Status Subregister”. 0: The value in SCB_MMFAR is not a valid fault address. 1: SCB_MMFAR holds a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose SCB_MMFAR value has been overwritten. • IBUSERR: Instruction Bus Error This is part of “BFSR: Bus Fault Status Subregister”. 0: No instruction bus error. 1: Instruction bus error. The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it attempts to issue the faulting instruction. When the processor sets this bit to 1, it does not write a fault address to the BFAR. • PRECISERR: Precise Data Bus Error This is part of “BFSR: Bus Fault Status Subregister”. 0: No precise data bus error. 1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR. • IMPRECISERR: Imprecise Data Bus Error This is part of “BFSR: Bus Fault Status Subregister”. 0: No imprecise data bus error. 1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR. This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both this bit and one of the precise fault status bits are set to 1. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 241 • UNSTKERR: Bus Fault on Unstacking for a Return From Exception This is part of “BFSR: Bus Fault Status Subregister”. 0: No unstacking fault. 1: Unstack for an exception return has caused one or more bus faults. This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write a fault address to the BFAR. • STKERR: Bus Fault on Stacking for Exception Entry This is part of “BFSR: Bus Fault Status Subregister”. 0: No stacking fault. 1: Stacking for an exception entry has caused one or more bus faults. When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the SCB_BFAR. • LSPERR: Bus Error During Lazy Floating-point State Preservation This is part of “BFSR: Bus Fault Status Subregister”. 0: No bus fault occurred during floating-point lazy state preservation 1: A bus fault occurred during floating-point lazy state preservation. • BFARVALID: Bus Fault Address Register (BFAR) Valid flag This is part of “BFSR: Bus Fault Status Subregister”. 0: The value in SCB_BFAR is not a valid fault address. 1: SCB_BFAR holds a valid fault address. The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems if returning to a stacked active bus fault handler whose SCB_BFAR value has been overwritten. • UNDEFINSTR: Undefined Instruction Usage Fault This is part of “UFSR: Usage Fault Status Subregister”. 0: No undefined instruction usage fault. 1: The processor has attempted to execute an undefined instruction. When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. • INVSTATE: Invalid State Usage Fault This is part of “UFSR: Usage Fault Status Subregister”. 0: No invalid state usage fault. 1: The processor has attempted to execute an instruction that makes illegal use of the EPSR. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR. This bit is not set to 1 if an undefined instruction uses the EPSR. 242 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • INVPC: Invalid PC Load Usage Fault This is part of “UFSR: Usage Fault Status Subregister”. It is caused by an invalid PC load by EXC_RETURN: 0: No invalid PC load usage fault. 1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. • NOCP: No Coprocessor Usage Fault This is part of “UFSR: Usage Fault Status Subregister”. The processor does not support coprocessor instructions: 0: No usage fault caused by attempting to access a coprocessor. 1: The processor has attempted to access a coprocessor. • UNALIGNED: Unaligned Access Usage Fault This is part of “UFSR: Usage Fault Status Subregister”. 0: No unaligned access fault, or unaligned access trapping not enabled. 1: The processor has made an unaligned memory access. Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR to 1. See “Configuration and Control Register”. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP. • DIVBYZERO: Divide by Zero Usage Fault This is part of “UFSR: Usage Fault Status Subregister”. 0: No divide by zero fault, or divide by zero trapping not enabled. 1: The processor has executed an SDIV or UDIV instruction with a divisor of 0. When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR to 1. See “Configuration and Control Register”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 243 12.9.1.14 Configurable Fault Status Register (Byte Access) Name: SCB_CFSR (BYTE) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UFSR 23 22 21 20 UFSR 15 14 13 12 BFSR 7 6 5 4 MMFSR • MMFSR: Memory Management Fault Status Subregister The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section 12.9.1.13. • BFSR: Bus Fault Status Subregister The flags in the BFSR subregister indicate the cause of a bus access fault. See bitfield [14..8] description in Section 12.9.1.13. • UFSR: Usage Fault Status Subregister The flags in the UFSR subregister indicate the cause of a usage fault. See bitfield [31..15] description in Section 12.9.1.13. Note: The UFSR bits are sticky. This means that as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by wrting a 1 to that bit, or by a reset. The SCB_CFSR indicates the cause of a memory management fault, bus fault, or usage fault. It is byte accessible. The user can access the SCB_CFSR or its subregisters as follows: • Access complete SCB_CFSR with a word access to 0xE000ED28 • Access MMFSR with a byte access to 0xE000ED28 • Access MMFSR and BFSR with a halfword access to 0xE000ED28 • Access BFSR with a byte access to 0xE000ED29 • Access UFSR with a halfword access to 0xE000ED2A. 244 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.15 Hard Fault Status Register Name: SCB_HFSR Access: Read/Write 31 DEBUGEVT 30 FORCED 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 VECTTBL 0 – The SCB_HFSR gives information about events that activate the hard fault handler. This register is read, write to clear. This means that bits in the register read normally, but wrting a 1 to any bit clears that bit to 0. • DEBUGEVT: Reserved for Debug Use When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable. • FORCED: Forced Hard Fault It indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled: 0: No forced hard fault. 1: Forced hard fault. When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault. • VECTTBL: Bus Fault on a Vector Table It indicates a bus fault on a vector table read during an exception processing: 0: No bus fault on vector table read. 1: Bus fault on vector table read. This error is always handled by the hard fault handler. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the exception. Note: The HFSR bits are sticky. This means that, as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by wrting a 1 to that bit, or by a reset. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 245 12.9.1.16 MemManage Fault Address Register Name: SCB_MMFAR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The SCB_MMFAR contains the address of the location that generated a memory management fault. • ADDRESS: Memory Management Fault Generation Location Address When the MMARVALID bit of the MMFSR subregister is set to 1, this field holds the address of the location that generated the memory management fault. Notes: 246 1. When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. 2. Flags in the MMFSR subregister indicate the cause of the fault, and whether the value in the SCB_MMFAR is valid. See “MMFSR: Memory Management Fault Status Subregister”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.9.1.17 Bus Fault Address Register Name: SCB_BFAR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The SCB_BFAR contains the address of the location that generated a bus fault. • ADDRESS: Bus Fault Generation Location Address When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the bus fault. Notes: 1. When an unaligned access faults, the address in the SCB_BFAR is the one requested by the instruction, even if it is not the address of the fault. 2. Flags in the BFSR indicate the cause of the fault, and whether the value in the SCB_BFAR is valid. See “BFSR: Bus Fault Status Subregister”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 247 12.10 System Timer (SysTick) The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the SYST_RVR on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging, the counter does not decrement. The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure that the software uses aligned word accesses to access the SysTick registers. The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the SysTick counter is: 1. Program the reload value. 248 2. Clear the current value. 3. Program the Control and Status register. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.10.1 System Timer (SysTick) User Interface Table 12-35. System Timer (SYST) Register Mapping Offset Register Name Access Reset 0xE000E010 SysTick Control and Status Register SYST_CSR Read/Write 0x00000000 0xE000E014 SysTick Reload Value Register SYST_RVR Read/Write Unknown 0xE000E018 SysTick Current Value Register SYST_CVR Read/Write Unknown 0xE000E01C SysTick Calibration Value Register SYST_CALIB Read-only 0x00001770 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 249 12.10.1.1 SysTick Control and Status Register Name: SYST_CSR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 COUNTFLAG 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 CLKSOURCE 1 TICKINT 0 ENABLE The SysTick SYST_CSR enables the SysTick features. • COUNTFLAG: Count Flag Returns 1 if the timer counted to 0 since the last time this was read. • CLKSOURCE: Clock Source Indicates the clock source: 0: External Clock. 1: Processor Clock. • TICKINT: SysTick Exception Request Enable Enables a SysTick exception request: 0: Counting down to zero does not assert the SysTick exception request. 1: Counting down to zero asserts the SysTick exception request. The software can use COUNTFLAG to determine if SysTick has ever counted to zero. • ENABLE: Counter Enable Enables the counter: 0: Counter disabled. 1: Counter enabled. When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then loads the RELOAD value again, and begins counting. 250 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.10.1.2 SysTick Reload Value Registers Name: SYST_RVR Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 RELOAD 15 14 13 12 RELOAD 7 6 5 4 RELOAD The SYST_RVR specifies the start value to load into the SYST_CVR. • RELOAD: SYST_CVR Load Value Value to load into the SYST_CVR when the counter is enabled and when it reaches 0. The RELOAD value can be any value in the range 0x00000001–0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0. The RELOAD value is calculated according to its use: For example, to generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 251 12.10.1.3 SysTick Current Value Register Name: SYST_CVR Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CURRENT 15 14 13 12 CURRENT 7 6 5 4 CURRENT The SysTick SYST_CVR contains the current value of the SysTick counter. • CURRENT: SysTick Counter Current Value Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0. 252 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.10.1.4 SysTick Calibration Value Register Name: SYST_CALIB Access: Read/Write 31 NOREF 30 SKEW 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 TENMS 15 14 13 12 TENMS 7 6 5 4 TENMS The SysTick SYST_CSR indicates the SysTick calibration properties. • NOREF: No Reference Clock It indicates whether the device provides a reference clock to the processor: 0: Reference clock provided. 1: No reference clock provided. If your device does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one and ignores writes. • SKEW: TENMS Value Verification It indicates whether the TENMS value is exact: 0: TENMS value is exact. 1: TENMS value is inexact, or not given. An inexact TENMS value can affect the suitability of SysTick as a software real time clock. • TENMS: Ten Milliseconds The reload value for 10 ms (100 Hz) timing is subject to system clock skew errors. If the value reads as zero, the calibration value is not known. The TENMS field default value is 0x00001770 (6000 decimal). In order to achieve a 1 ms timebase on SystTick, the TENMS field must be programmed to a value corresponding to the processor clock frequency (in kHz) divided by 8. For example, for devices running the processor clock at 48 MHz, the TENMS field value must be 0x0001770 (48000 kHz/8). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 253 12.11 Memory Protection Unit (MPU) The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: Independent attribute settings for each region Overlapping regions Export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines: Eight separate memory regions, 0–7 A background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault. This causes a fault exception, and might cause the termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. The configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes”). Table 12-36 shows the possible MPU region attributes. These include Share ability and cache behavior attributes that are not relevant to most microcontroller implementations. See “MPU Configuration for a Microcontroller” for guidelines for programming such an implementation. Table 12-36. Memory Attributes Summary Memory Type Shareability Other Attributes Description Strongly-ordered – – All accesses to Strongly-ordered memory occur in program order. All Strongly-ordered regions are assumed to be shared. Shared – Memory-mapped peripherals that several processors share. Non-shared – Memory-mapped peripherals that only a single processor uses. Shared – Normal memory that is shared between several processors. Non-shared – Normal memory that only a single processor uses. Device Normal 254 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.11.1 MPU Access Permission Attributes This section describes the MPU access permission attributes. The access permission bits (TEX, C, B, S, AP, and XN) of the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The table below shows the encodings for the TEX, C, B, and S access permission bits. Table 12-37. TEX C 0 TEX, C, B, and S Encoding B S (1) 0 x 1 x (1) Memory Type Shareability Other Attributes Strongly-ordered Shareable – Device Shareable – Normal Not shareable 0 0 b000 1 Shareable 0 Not shareable Outer and inner write-through. No write allocate. 1 1 0 Normal 1 Shareable 0 Not shareable 0 Normal 1 x (1) Reserved encoding – 0 x (1) Implementation defined attributes. – 1 0 1 Normal 1 A 1. Not shareable x (1) Device 1 x (1) Reserved encoding – (1) Reserved encoding – x (1) x A Normal 1 Note: Outer and inner write-back. Write and read allocate. 0 0 b1BB Not shareable Shareable 0 1 – Shareable 1 b001 b010 Outer and inner write-back. No write allocate. Not shareable Nonshared Device. – Shareable The MPU ignores the value of this bit. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 255 Table 12-38 shows the cache policy for memory attribute encodings with a TEX value is in the range 4–7. Table 12-38. Cache Policy for Memory Attribute Encoding Encoding, AA or BB Corresponding Cache Policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate Table 12-39 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 12-39. 12.11.1.1 AP Encoding AP[2:0] Privileged Permissions Unprivileged Permissions Description 000 No access No access All accesses generate a permission fault 001 RW No access Access from privileged software only 010 RW RO Writes by unprivileged software generate a permission fault 011 RW RW Full access 100 Unpredictable Unpredictable Reserved 101 RO No access Reads by privileged software only 110 RO RO Read only, by privileged or unprivileged software 111 RO RO Read only, by privileged or unprivileged software MPU Mismatch When an access violates the MPU permissions, the processor generates a memory management fault, see “Exceptions and Interrupts”. The MMFSR indicates the cause of the fault. See “MMFSR: Memory Management Fault Status Subregister” for more information. 12.11.1.2 Updating an MPU Region To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASRs. Each register can be programed separately, or a multiple-word write can be used to program all of these registers. MPU_RBAR and MPU_RASR aliases can be used to program up to four regions simultaneously using an STM instruction. 12.11.1.3 Updating an MPU Region Using Separate Words Simple code to configure one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR STR R1, [R0, #0x0] STR R4, [R0, #0x4] STRH R2, [R0, #0x8] STRH R3, [R0, #0xA] 256 ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Region Base Address Region Size and Enable Region Attribute SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Disable a region before writing new region settings to the MPU, if the region being changed was previously enabled. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable STRH R2, [R0, #0x8] ; Region Size and Enable The software must use memory barrier instructions: Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings After the MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanisms cause memory barrier behavior. The software does not need any memory barrier instructions during an MPU setup, because it accesses the MPU through the PPB, which is a Strongly-Ordered memory region. For example, if the user wants all of the memory access behavior to take effect immediately after the programming sequence, a DSB instruction and an ISB instruction must be used. A DSB is required after changing MPU settings, such as at the end of a context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. 12.11.1.4 Updating an MPU Region Using Multi-word Writes The user can program directly using multi-word writes, depending on how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable Use an STM instruction to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region Number, address, attribute, size and enable SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 257 This can be done in two words for pre-packed information. This means that the MPU_RBAR contains the required region number and had the VALID bit set to 1. See “MPU Region Base Address Register”. Use this when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPU_RBAR ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and ; region number combined with VALID (bit 4) set to 1 STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Use an STM instruction to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPU_RBAR ; 0xE000ED9C, MPU Region Base register STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable 12.11.1.5 Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register”. The least significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be set to 0x00, otherwise the MPU behavior is unpredictable. 12.11.1.6 Example of SRD Use Two regions with the same base address overlap. Region 1 is 128 KB, and region 2 is 512 KB. To ensure the attributes from region 1 apply to the first 128 KB region, set the SRD field for region 2 to b00000011 to disable the first two subregions, as in Figure 12-13 below: Figure 12-13. SRD Use Region 2, with subregions Region 1 Base address of both regions 12.11.1.7 Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB Disabled subregion 64KB Disabled subregion 0 MPU Design Hints And Tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure the software uses aligned accesses of the correct size to access MPU registers: Except for the MPU_RASR, it must use aligned word accesses For the MPU_RASR, it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to MPU registers. 258 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. MPU Configuration for a Microcontroller Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as follows: Table 12-40. Memory Region Attributes for a Microcontroller Memory Region TEX C B S Memory Type and Attributes Flash memory b000 1 0 0 Normal memory, non-shareable, write-through Internal SRAM b000 1 0 1 Normal memory, shareable, write-through External SRAM b000 1 1 1 Normal memory, shareable, write-back, write-allocate Peripherals b000 0 1 1 Device memory, shareable In most microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. In special systems, such as multiprocessor designs or designs with a separate DMA engine, the shareability attribute might be important. In these cases, refer to the recommendations of the memory device manufacturer. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 259 12.11.2 Memory Protection Unit (MPU) User Interface Table 12-41. Memory Protection Unit (MPU) Register Mapping Offset Register Name Access Reset 0xE000ED90 MPU Type Register MPU_TYPE Read-only 0x00000800 0xE000ED94 MPU Control Register MPU_CTRL Read/Write 0x00000000 0xE000ED98 MPU Region Number Register MPU_RNR Read/Write 0x00000000 0xE000ED9C MPU Region Base Address Register MPU_RBAR Read/Write 0x00000000 0xE000EDA0 MPU Region Attribute and Size Register MPU_RASR Read/Write 0x00000000 0xE000EDA4 MPU Region Base Address Register Alias 1 MPU_RBAR_A1 Read/Write 0x00000000 0xE000EDA8 MPU Region Attribute and Size Register Alias 1 MPU_RASR_A1 Read/Write 0x00000000 0xE000EDAC MPU Region Base Address Register Alias 2 MPU_RBAR_A2 Read/Write 0x00000000 0xE000EDB0 MPU Region Attribute and Size Register Alias 2 MPU_RASR_A2 Read/Write 0x00000000 0xE000EDB4 MPU Region Base Address Register Alias 3 MPU_RBAR_A3 Read/Write 0x00000000 0xE000EDB8 MPU Region Attribute and Size Register Alias 3 MPU_RASR_A3 Read/Write 0x00000000 260 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.11.2.1 MPU Type Register Name: MPU_TYPE Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 SEPARATE IREGION 15 14 13 12 DREGION 7 – 6 – 5 – 4 – The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. • IREGION: Instruction Region Indicates the number of supported MPU instruction regions. Always contains 0x00. The MPU memory map is unified and is described by the DREGION field. • DREGION: Data Region Indicates the number of supported MPU data regions: 0x08 = Eight MPU regions. • SEPARATE: Separate Instruction Indicates support for unified or separate instruction and date memory maps: 0: Unified. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 261 12.11.2.2 MPU Control Register Name: MPU_CTRL Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 PRIVDEFENA 1 HFNMIENA 0 ENABLE The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. • PRIVDEFENA: Privileged Default Memory Map Enable Enables privileged software access to the default memory map: 0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as a region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. • HFNMIENA: Hard Fault and NMI Enable Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers. When the MPU is enabled: 0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit. 1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable. • ENABLE: MPU Enable Enables the MPU: 0: MPU disabled. 1: MPU enabled. When ENABLE and PRIVDEFENA are both set to 1: • For privileged accesses, the default memory map is as described in “Memory Model”. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. • Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. 262 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged software can operate. When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the MPU is not implemented. The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFENA is set to 1. Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 263 12.11.2.3 MPU Region Number Register Name: MPU_RNR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 REGION The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASRs. • REGION: MPU Region Referenced by the MPU_RBAR and MPU_RASRs Indicates the MPU region referenced by the MPU_RBAR and MPU_RASRs. The MPU supports 8 memory regions, so the permitted values of this field are 0–7. Normally, the required region number is written to this register before accessing the MPU_RBAR or MPU_RASR. However, the region number can be changed by writing to the MPU_RBAR with the VALID bit set to 1; see “MPU Region Base Address Register”. This write updates the value of the REGION field. 264 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.11.2.4 MPU Region Base Address Register Name: MPU_RBAR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. • ADDR: Region Base Address Software must ensure that the value written to the ADDR field aligns with the size of the selected region (SIZE field in the MPU_RASR). If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. • VALID: MPU Region Number Valid Write: 0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores the value of the REGION field. 1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the region specified in the REGION field. Always reads as zero. • REGION: MPU Region For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 265 12.11.2.5 MPU Region Attribute and Size Register Name: MPU_RASR Access: Read/Write 31 – 30 – 29 – 28 XN 27 – 26 25 AP 24 23 – 22 – 21 20 TEX 19 18 S 17 C 16 B 15 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE SRD 7 – 6 – 5 4 The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: • The most significant halfword holds the region attributes. • The least significant halfword holds the region size, and the region and subregion enable bits. • XN: Instruction Access Disable 0: Instruction fetches enabled. 1: Instruction fetches disabled. • AP: Access Permission See Table 12-39. • TEX, C, B: Memory Access Attributes See Table 12-37. • S: Shareable See Table 12-37. • SRD: Subregion Disable For each bit in this field: 0: Corresponding subregion is enabled. 1: Corresponding subregion is disabled. See “Subregions” for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. 266 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR. SIZE Value Region Size Value of N (1) Note b00100 (4) 32 B 5 Minimum permitted size b01001 (9) 1 KB 10 – b10011 (19) 1 MB 20 – b11101 (29) 1 GB 30 – b11111 (31) 4 GB b01100 Maximum possible size Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register” • ENABLE: Region Enable Note: For information about access permission, see “MPU Access Permission Attributes”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 267 12.11.2.6 MPU Region Base Address Register Alias 1 Name: MPU_RBAR_A1 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. • ADDR: Region Base Address Software must ensure that the value written to the ADDR field aligns with the size of the selected region. The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. • VALID: MPU Region Number Valid Write: 0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores the value of the REGION field. 1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the region specified in the REGION field. Always reads as zero. • REGION: MPU Region For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR. 268 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.11.2.7 MPU Region Attribute and Size Register Alias 1 Name: MPU_RASR_A1 Access: Read/Write 31 – 23 30 – 29 – 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 – 6 – 5 4 The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: • The most significant halfword holds the region attributes. • The least significant halfword holds the region size, and the region and subregion enable bits. • XN: Instruction Access Disable 0: Instruction fetches enabled. 1: Instruction fetches disabled. • AP: Access Permission See Table 12-39. • TEX, C, B: Memory Access Attributes See Table 12-37. • S: Shareable See Table 12-37. • SRD: Subregion Disable For each bit in this field: 0: Corresponding subregion is enabled. 1: Corresponding subregion is disabled. See “Subregions” for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 269 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR. SIZE Value Region Size Value of N (1) Note b00100 (4) 32 B 5 Minimum permitted size b01001 (9) 1 KB 10 – b10011 (19) 1 MB 20 – b11101 (29) 1 GB 30 – b11111 (31) 4 GB b01100 Maximum possible size Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register” • ENABLE: Region Enable Note: For information about access permission, see “MPU Access Permission Attributes”. 270 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.11.2.8 MPU Region Base Address Register Alias 2 Name: MPU_RBAR_A2 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. • ADDR: Region Base Address Software must ensure that the value written to the ADDR field aligns with the size of the selected region. The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. • VALID: MPU Region Number Valid Write: 0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores the value of the REGION field. 1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the region specified in the REGION field. Always reads as zero. • REGION: MPU Region For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 271 12.11.2.9 MPU Region Attribute and Size Register Alias 2 Name: MPU_RASR_A2 Access: Read/Write 31 – 30 – 29 – 28 XN 27 – 26 25 AP 24 23 – 22 – 21 20 TEX 19 18 S 17 C 16 B 15 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE SRD 7 – 6 – 5 4 The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: • The most significant halfword holds the region attributes. • The least significant halfword holds the region size, and the region and subregion enable bits. • XN: Instruction Access Disable 0: Instruction fetches enabled. 1: Instruction fetches disabled. • AP: Access Permission See Table 12-39. • TEX, C, B: Memory Access Attributes See Table 12-37. • S: Shareable See Table 12-37. • SRD: Subregion Disable For each bit in this field: 0: Corresponding subregion is enabled. 1: Corresponding subregion is disabled. See “Subregions” for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. 272 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR. SIZE Value Region Size Value of N (1) Note b00100 (4) 32 B 5 Minimum permitted size b01001 (9) 1 KB 10 – b10011 (19) 1 MB 20 – b11101 (29) 1 GB 30 – b11111 (31) 4 GB b01100 Maximum possible size Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register” • ENABLE: Region Enable Note: For information about access permission, see “MPU Access Permission Attributes”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 273 12.11.2.10 MPU Region Base Address Register Alias 3 Name: MPU_RBAR_A3 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. • ADDR: Region Base Address Software must ensure that the value written to the ADDR field aligns with the size of the selected region. The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. • VALID: MPU Region Number Valid Write: 0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores the value of the REGION field. 1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the region specified in the REGION field. Always reads as zero. • REGION: MPU Region For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR. 274 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.11.2.11 MPU Region Attribute and Size Register Alias 3 Name: MPU_RASR_A3 Access: Read/Write 31 – 30 – 29 – 28 XN 27 – 26 25 AP 24 23 – 22 – 21 20 TEX 19 18 S 17 C 16 B 15 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE SRD 7 – 6 – 5 4 The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: • The most significant halfword holds the region attributes. • The least significant halfword holds the region size, and the region and subregion enable bits. • XN: Instruction Access Disable 0: Instruction fetches enabled. 1: Instruction fetches disabled. • AP: Access Permission See Table 12-39. • TEX, C, B: Memory Access Attributes See Table 12-37. • S: Shareable See Table 12-37. • SRD: Subregion Disable For each bit in this field: 0: Corresponding subregion is enabled. 1: Corresponding subregion is disabled. See “Subregions” for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 275 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR. SIZE Value Region Size Value of N (1) Note b00100 (4) 32 B 5 Minimum permitted size b01001 (9) 1 KB 10 – b10011 (19) 1 MB 20 – b11101 (29) 1 GB 30 – b11111 (31) 4 GB b01100 Maximum possible size Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register” • ENABLE: Region Enable Note: For information about access permission, see “MPU Access Permission Attributes”. 276 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.12 Floating Point Unit (FPU) The Cortex-M4F FPU implements the FPv4-SP floating-point extension. The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU contains 32 single-precision extension registers, which can also be accessed as 16 doubleword registers for load, store, and move operations. 12.12.1 Enabling the FPU The FPU is disabled from reset. It must be enabled before any floating-point instructions can be used. Example 41 shows an example code sequence for enabling the FPU in both privileged and user modes. The processor must be in privileged mode to read from and write to the CPACR. Example of Enabling the FPU: ; CPACR is located at address 0xE000ED88 LDR.W R0, =0xE000ED88 ; Read CPACR LDR R1, [R0] ; Set bits 20-23 to enable CP10 and CP11 coprocessors ORR R1, R1, #(0xF << 20) ; Write back the modified value to the CPACR STR R1, [R0]; wait for store to complete DSB ;reset pipeline now the FPU is enabled ISB SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 277 12.12.2 Floating Point Unit (FPU) User Interface Table 12-42. Floating Point Unit (FPU) Register Mapping Offset Register Name Access Reset 0xE000ED88 Coprocessor Access Control Register CPACR Read/Write 0x00000000 0xE000EF34 Floating-point Context Control Register FPCCR Read/Write 0xC0000000 0xE000EF38 Floating-point Context Address Register FPCAR Read/Write – – Floating-point Status Control Register FPSCR Read/Write – 0xE000E01C Floating-point Default Status Control Register FPDSCR Read/Write 0x00000000 278 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.12.2.1 Coprocessor Access Control Register Name: CPACR Access: Read/Write 31 – 23 30 – 29 – 22 21 CP11 28 – 27 – 26 – 25 – 24 – 20 19 – 18 – 17 – 16 – CP10 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – The CPACR specifies the access privileges for coprocessors. • CP10: Access Privileges for Coprocessor 10 The possible values of each field are: 0: Access denied. Any attempted access generates a NOCP UsageFault. 1: Privileged access only. An unprivileged access generates a NOCP fault. 2: Reserved. The result of any access is unpredictable. 3: Full access. • CP11: Access Privileges for Coprocessor 11 The possible values of each field are: 0: Access denied. Any attempted access generates a NOCP UsageFault. 1: Privileged access only. An unprivileged access generates a NOCP fault. 2: Reserved. The result of any access is unpredictable. 3: Full access. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 279 12.12.2.2 Floating-point Context Control Register Name: FPCCR Access: Read/Write 31 ASPEN 30 LSPEN 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 MONRDY 7 – 6 BFRDY 5 MMRDY 4 HFRDY 3 THREAD 2 – 1 USER 0 LSPACT The FPCCR sets or returns FPU control data. • ASPEN: Automatic Hardware State Preservation And Restoration Enables CONTROL bit [2] setting on execution of a floating-point instruction. This results in an automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. 0: Disable CONTROL bit [2] setting on execution of a floating-point instruction. 1: Enable CONTROL bit [2] setting on execution of a floating-point instruction. • LSPEN: Automatic Lazy State Preservation 0: Disable automatic lazy state preservation for floating-point context. 1: Enable automatic lazy state preservation for floating-point context. • MONRDY: Debug Monitor Ready 0: DebugMonitor is disabled or the priority did not permit to set MON_PEND when the floating-point stack frame was allocated. 1: DebugMonitor is enabled and the priority permitted to set MON_PEND when the floating-point stack frame was allocated. • BFRDY: Bus Fault Ready 0: BusFault is disabled or the priority did not permit to set the BusFault handler to the pending state when the floating-point stack frame was allocated. 1: BusFault is enabled and the priority permitted to set the BusFault handler to the pending state when the floating-point stack frame was allocated. • MMRDY: Memory Management Ready 0: MemManage is disabled or the priority did not permit to set the MemManage handler to the pending state when the floating-point stack frame was allocated. 1: MemManage is enabled and the priority permitted to set the MemManage handler to the pending state when the floating-point stack frame was allocated. 280 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • HFRDY: Hard Fault Ready 0: The priority did not permit to set the HardFault handler to the pending state when the floating-point stack frame was allocated. 1: The priority permitted to set the HardFault handler to the pending state when the floating-point stack frame was allocated. • THREAD: Thread Mode 0: The mode was not the Thread Mode when the floating-point stack frame was allocated. 1: The mode was the Thread Mode when the floating-point stack frame was allocated. • USER: User Privilege Level 0: The privilege level was not User when the floating-point stack frame was allocated. 1: The privilege level was User when the floating-point stack frame was allocated. • LSPACT: Lazy State Preservation Active 0: The lazy state preservation is not active. 1: The lazy state preservation is active. The floating-point stack frame has been allocated but saving the state to it has been deferred. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 281 12.12.2.3 Floating-point Context Address Register Name: FPCAR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 – 1 – 0 – ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 ADDRESS 4 The FPCAR holds the location of the unpopulated floating-point register space allocated on an exception stack frame. • ADDRESS: Location of Unpopulated Floating-point Register Space Allocated on an Exception Stack Frame The location of the unpopulated floating-point register space allocated on an exception stack frame. 282 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.12.2.4 Floating-point Status Control Register Name: FPSCR Access: Read/Write 31 N 30 Z 29 C 28 V 27 – 26 AHP 25 DN 24 FZ 22 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 IDC 6 – 5 – 4 IXC 3 UFC 2 OFC 1 DZC 0 IOC 23 RMode The FPSCR provides all necessary User level control of the floating-point system. • N: Negative Condition Code Flag Floating-point comparison operations update this flag. • Z: Zero Condition Code Flag Floating-point comparison operations update this flag. • C: Carry Condition Code Flag Floating-point comparison operations update this flag. • V: Overflow Condition Code Flag Floating-point comparison operations update this flag. • AHP: Alternative Half-precision Control 0: IEEE half-precision format selected. 1: Alternative half-precision format selected. • DN: Default NaN Mode Control 0: NaN operands propagate through to the output of a floating-point operation. 1: Any operation involving one or more NaNs returns the Default NaN. • FZ: Flush-to-zero Mode Control 0: Flush-to-zero mode disabled. The behavior of the floating-point system is fully compliant with the IEEE 754 standard. 1: Flush-to-zero mode enabled. • RMode: Rounding Mode Control The encoding of this field is: 0b00: Round to Nearest (RN) mode 0b01: Round towards Plus Infinity (RP) mode. 0b10: Round towards Minus Infinity (RM) mode. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 283 0b11: Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions. • IDC: Input Denormal Cumulative Exception IDC is a cumulative exception bit for floating-point exception; see also bits [4:0]. This bit is set to 1 to indicate that the corresponding exception has occurred since 0 was last written to it. • IXC: Inexact Cumulative Exception IXC is a cumulative exception bit for floating-point exception; see also bit [7]. This bit is set to 1 to indicate that the corresponding exception has occurred since 0 was last written to it. • UFC: Underflow Cumulative Exception UFC is a cumulative exception bit for floating-point exception; see also bit [7]. This bit is set to 1 to indicate that the corresponding exception has occurred since 0 was last written to it. • OFC: Overflow Cumulative Exception OFC is a cumulative exception bit for floating-point exception; see also bit [7]. This bit is set to 1 to indicate that the corresponding exception has occurred since 0 was last written to it. • DZC: Division by Zero Cumulative Exception DZC is a cumulative exception bit for floating-point exception; see also bit [7]. This bit is set to 1 to indicate that the corresponding exception has occurred since 0 was last written to it. • IOC: Invalid Operation Cumulative Exception IOC is a cumulative exception bit for floating-point exception; see also bit [7]. This bit is set to 1 to indicate that the corresponding exception has occurred since 0 was last written to it. 284 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 12.12.2.5 Floating-point Default Status Control Register Name: FPDSCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 AHP 25 DN 24 FZ 22 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – 23 RMode The FPDSCR holds the default values for the floating-point status control data. • AHP: FPSCR.AHP Default Value Default value for FPSCR.AHP. • DN: FPSCR.DN Default Value Default value for FPSCR.DN. • FZ: FPSCR.FZ Default Value Default value for FPSCR.FZ. • RMode: FPSCR.RMode Default Value Default value for FPSCR.RMode. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 285 12.13 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are divisible by four and two respectively. Banked register A register that has multiple physical copies, where the state of the processor determines which copy is used. The Stack Pointer, SP (R13) is a banked register. Base register In instruction descriptions, a register specified by a load or store instruction that is used to hold the base value for the instruction’s address calculation. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the address that is sent to memory. See also “Index register”. Big-endian (BE) Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory. See also “Byte-invariant”, “Endianness”, “Little-endian (LE)”. Big-endian memory Memory in which: a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the most significant byte within the halfword at that address. See also “Little-endian memory”. Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested. Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses. It expects multi-word accesses to be word-aligned. Condition field A four-bit field in an instruction that specifies a condition under which the instruction can execute. 286 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Conditional execution If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing. Context The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions. Coprocessor A processor that supplements the main processor. Cortex-M4 does not support any coprocessors. Debugger A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging. Direct Memory Access (DMA) An operation that accesses main memory directly, without the processor performing any accesses to the data concerned. Doubleword A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated. Doubleword-aligned A data item having a memory address that is divisible by eight. Endianness Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping. See also “Little-endian (LE)” and “Big-endian (BE)”. Exception An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address contains the first instruction of the handler for the exception. An exception can be an interrupt request, a fault, or a software-generated system exception. Faults include attempting an invalid memory access, attempting to execute an instruction in an invalid processor state, and attempting to execute an undefined instruction. Exception service routine See “Interrupt handler”. Exception vector See “Interrupt vector”. Flat address mapping A system of organizing memory in which each physical address in the memory space is the same as the corresponding virtual address. Halfword A 16-bit data item. Illegal instruction An instruction that is architecturally Undefined. Implementation-defined The behavior is not architecturally defined, but is defined and documented by individual implementations. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 287 Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility. Index register In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory. Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction. See also “Base register”. Instruction cycle count The number of cycles that an instruction occupies the Execute stage of the pipeline. Interrupt handler A program that control of the processor is passed to when an interrupt occurs. Interrupt vector One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler. Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also “Big-endian (BE)”, “Byte-invariant”, “Endianness”. Little-endian memory Memory in which: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the least significant byte within the halfword at that address. See also “Big-endian memory”. Load/store architecture A processor architecture where data-processing operations only operate on register contents, not directly on memory contents. Memory Protection Unit (MPU) Hardware that controls access permissions to blocks of memory. An MPU does not perform any address translation. Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. Prefetching an instruction does not mean that the instruction has to be executed. Preserved Preserved by writing the same value back that has been previously read from the same field on the same processor. Read Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP. 288 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Region A partition of memory space. Reserved A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as 0. Thread-safe In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts. Thumb instruction One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be halfword-aligned. Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four. Undefined Indicates an instruction that generates an Undefined instruction exception. Unpredictable One cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system. Warm reset Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if debugging features of a processor. Word A 32-bit data item. Write Writes are defined as operations that have the semantics of a store. Writes include the Thumb instructions STM, STR, STRH, STRB, and PUSH. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 289 13. Debug and Test Features 13.1 Description The SAM G53 features a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug Port (JTAG-DP) is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 13.2 Embedded Characteristics Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted or in sleep state, or held in reset. Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access. Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches. Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling. Instrumentation Trace Macrocell (ITM) for support of printf style debugging. IEEE1149.1 JTAG Boundary-scan on all digital pins. Figure 13-1. Debug and Test Block Diagram TMS TCK/SWCLK TDI Boundary TAP JTAGSEL SWJ-DP TDO/TRACESWO Reset and Test 290 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 POR TST 13.3 Application Examples 13.3.1 Debug Environment Figure 13-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program, and viewing core and peripheral registers. Figure 13-2. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM4 SAM4-based Application Board 13.3.2 Test Environment Figure 13-3 shows a test environment example (JTAG boundary scan). Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 291 Figure 13-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector Chip n SAM4 Chip 2 Chip 1 SAM4-based Application Board In Test 13.4 Debug and Test Pin Description Table 13-1. Debug and Test Signal List Signal Name Function Type Active Level Input/Output Low Reset/Test NRST Microcontroller Reset TST Test Select Input SWD/JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input TDI Test Data In Input TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input JTAGSEL JTAG Selection Input Note: 292 1. Output (1) High TDO pin is set in input mode when the Cortex-M4 Core is not in debug mode. Thus the internal pull-up corresponding to this PIO line must be enabled to avoid current consumption due to floating input. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 13.5 Functional Description 13.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during powerup, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal operation. Note that when setting the TST pin to low or high level at power up, it must remain in the same state during the duration of the whole operation. 13.5.2 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input. 13.5.3 ERASE Pin The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as logic level 1). The ERASE pin ensures an in-situ reprogrammability of the Flash content without the use of a debug tool. When the security bit is activated, the ERASE pin provides the capability to reprogram the Flash content. It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal operations. This pin is debounced by SCLK to improve the glitch tolerance. To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in Table 37-41, “AC Flash Characteristics,” on page 915. The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, start-up level of this pin must be low to prevent unwanted erasing. Also, if the ERASE pin is used as a standard I/O output, asserting the pin to low does not erase the Flash. For details, please refer to Section 10.16 “Peripherals Signals Multiplexing on I/O Lines”. 13.5.4 Debug Architecture Figure 13-4 shows the Debug Architecture used in the SAM G53. The Cortex-M4 embeds four functional units for debug: SWJ-DP (Serial Wire/JTAG Debug Port). FPB (Flash Patch Breakpoint. DWT (Data Watchpoint and Trace). ITM (Instrumentation Trace Macrocell). TPIU (Trace Port Interface Unit). The debug architecture information that follows is mainly dedicated to developers of SWJ-DP emulators/probes and debugging tool vendors for Cortex M4-based microcontrollers. For further details on SWJ-DP see the Cortex M4 technical reference manual. Figure 13-4. Debug Architecture SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 293 DWT 4 watchpoints FPB SWJ-DP PC sampler 6 breakpoints data address sampler SWD/JTAG ITM data sampler software trace 32 channels interrupt trace SWO trace TPIU time stamping CPU statistics 13.5.5 Serial Wire/JTAG Debug Port (SWJ-DP) The Cortex-M4 embeds a SWJ-DP debug port which is the standard CoreSight™ debug port. It combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG Debug Port(JTAG-DP), 5 pins. By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and enables SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. Table 13-2. SWJ-DP Pin List Pin Name JTAG Port Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI - TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed. 13.5.5.1 SW-DP and JTAG-DP Selection Mechanism Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by default after reset. Switch from JTAG-DP to SW-DP. The sequence is: ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 ̶ Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first) ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 Switch from SWD to JTAG. The sequence is: ̶ 294 Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 ̶ Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first) ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 13.5.6 FPB (Flash Patch Breakpoint) The FPB: Implements hardware breakpoints. Patches code and data from code space to system space. The FPB unit contains: Two literal comparators for matching against literal loads from code space, and remapping to a corresponding area in system space. Six instruction comparators for matching against instruction fetches from code space and remapping to a corresponding area in system space. Alternatively, comparators can also be configured to generate a breakpoint instruction to the processor core on a match. 13.5.7 DWT (Data Watchpoint and Trace) The DWT contains four comparators which can be configured to generate the following: PC sampling packets at set intervals. PC or data watchpoint packets. Watchpoint event to halt core. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 295 The DWT contains counters for the items that follow: Clock cycle (CYCCNT). Folded instructions. Load Store Unit (LSU) operations. Sleep cycles. CPI (all instruction cycles except for the first cycle). Interrupt overhead. 13.5.8 ITM (Instrumentation Trace Macrocell) The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated by three different sources with several priority levels: Software trace: Software can write directly to ITM stimulus registers. This can be done thanks to the “printf” function. For more information, refer to Section 13.5.8.1 “How to Configure the ITM”. Hardware trace: The ITM emits packets generated by the DWT. Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. 13.5.8.1 How to Configure the ITM The following example describes how to output trace data in asynchronous trace mode. Configure the TPIU for asynchronous trace mode (refer to Section 13.5.8.3 “How to Configure the TPIU”). Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register (address: 0xE0000FB0). Write 0x00010015 into the Trace Control Register: ̶ Enable ITM. ̶ Enable synchronization packets. ̶ Enable SWO behavior. ̶ Fix the ATB ID to 1. Write 0x1 into the Trace Enable Register: ̶ Enable the stimulus port 0. Write 0x1 into the Trace Privilege Register: ̶ Write into the Stimulus Port 0 Register: TPIU (Trace Port Interface Unit). ̶ ̶ 13.5.8.2 Stimulus port 0 only accessed in privileged mode (clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode). The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM). The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core. Asynchronous Mode The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, asynchronous trace mode is only available when the serial wire debug mode is selected since TDO signal is used in JTAG debug mode. Two encoding formats are available for the single pin output: 296 Manchester encoded stream. This is the reset value. NRZ-based UART byte structure. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 13.5.8.3 How to Configure the TPIU This example only concerns the asynchronous trace mode. Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace and debug blocks. Write 0x2 into the Selected Pin Protocol Register. ̶ Select the Serial Wire Output – NRZ. Write 0x100 into the Formatter and Flush Control Register. Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool). 13.5.9 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAG SEL is high during power-up and must be kept in this state during the whole boundary scan operation. The SAMPLE, EXTEST and BYPASS functions are implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided on Atmel’s web site to set up the test. 13.5.9.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains a number of bits which corresponds to active pins and associated control signals. Each SAM G53 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. For more information, refer to BSDL files available for the SAMG53 Series. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 297 13.5.10 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name Chip ID SAM G53G19 0X247E_0AE0 SAM G53N19 0X247E_0AE8 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. Chip Name JTAG ID Code SAM G53 0x05B3_C03F 298 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 0 1 14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.2 Embedded Characteristics Management of All System Resets, Including ̶ Processor Reset ̶ Processor Peripheral Set Reset Based on Embedded Power-on Cell Reset Source Status 14.3 External Devices through the NRST Pin ̶ ̶ Status of the Last Reset ̶ Either Software Reset, User Reset, Watchdog Reset External Reset Signal Shaping Block Diagram Figure 14-1. Reset Controller Block Diagram Reset Controller core_backup_reset rstc_irq vddcore_nreset user_reset NRST nrst_out NRST Manager Reset State Manager proc_nreset periph_nreset exter_nreset WDRPROC wd_fault SLCK SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 299 14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made up of an NRST manager and a reset state manager. It runs at slow clock and generates the following reset signals: proc_nreset: processor reset line (also resets the Watchdog Timer) periph_nreset: affects the whole set of embedded peripherals nrst_out: drives the NRST pin These reset signals are asserted by the Reset Controller, either on events generated by peripherals, events on NRST pin, or on software action. The reset state manager controls the generation of reset signals and provides a signal to the NRST manager when an assertion of the NRST pin is required. The NRST manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The Reset Controller Mode Register (RSTC_MR), used to configure the Reset Controller, is powered with VDDIO, so that its configuration is saved as long as VDDIO is on. 14.4.2 NRST Manager The NRST manager samples the NRST input pin and drives this pin low when required by the reset state manager. Figure 14-2 shows the block diagram of the NRST manager. Figure 14-2. NRST Manager RSTC_MR URSTIEN RSTC_SR URSTS NRSTL rstc_irq RSTC_MR URSTEN Other interrupt sources user_reset NRST RSTC_MR ERSTL nrst_out 14.4.2.1 External Reset Timer exter_nreset NRST Signal or Interrupt The NRST manager samples the NRST pin at slow clock speed. When the line is detected low, a User Reset is reported to the reset state manager. However, the NRST manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing a 0 to the URSTEN bit in the RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in the Reset Controller Status Register (RSTC_SR). As soon as the NRST pin is asserted, bit URSTS in the RSTC_SR is set. This bit is cleared only when the RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, set the URSTIEN bit in the RSTC_MR. 300 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 14.4.2.2 NRST External Reset Control The reset state manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST manager for a time programmed by field ERSTL in the RSTC_MR. This assertion duration, named External Reset Length, lasts 2(ERSTL+1) slow clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. RSTC_MR is backed up, making it possible to use the ERSTL field to shape the system power-up reset for devices requiring a longer startup time than that of the slow clock oscillator. 14.4.3 Reset States The reset state manager handles the different reset sources and generates the internal reset signals. It reports the reset status in field RSTTYP of the Status Register (RSTC_SR). The update of RSTC_SR.RSTTYP is performed when the processor reset is released. 14.4.3.1 General Reset A general reset occurs when a VDDIO power-on-reset is detected, a brownout or a voltage regulation loss is detected by the Supply Controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs. All the reset signals are released and field RSTC_SR.RSTTYP reports a general reset. As the RSTC_MR is reset, the NRST line rises two cycles after the vddcore_nreset, as ERSTL defaults at value 0x0. Figure 14-3 shows how the general reset affects the reset signals. Figure 14-3. General Reset State SLCK Any Freq. MCK vddio_nreset Processor Startup = 2 cycles proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) External Reset Length = 2 cycles 14.4.3.2 Watchdog Reset The watchdog reset is entered when a watchdog fault occurs. This reset lasts three slow clock cycles. When in watchdog reset, assertion of the reset signals depends on the WDRPROC bit in the WDT_MR: SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 301 If WDRPROC = 0, the processor reset and the peripheral reset are asserted. The NRST line is also asserted, depending on how field RSTC_MR.ERSTL is programmed. However, the resulting low level on NRST does not result in a user reset state. If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN in the WDT_MR is set, the Watchdog Timer is always reset after a watchdog reset, and the Watchdog is enabled by default and with a period set to a maximum. When bit WDT_MR.WDRSTEN is reset, the watchdog fault has no impact on the Reset Controller. Figure 14-4. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 14.4.3.3 Software Reset The Reset Controller offers commands to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: RSTC_CR.PROCRST: Writing a 1 to PROCRST resets the processor and the watchdog timer. RSTC_CR.PERRST: Writing a 1 to PERRST resets all the embedded peripherals including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously). RSTC_CR.EXTRST: Writing a 1 to EXTRST asserts low the NRST pin during a time defined by the field RSTC_MR.ERSTL. The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts three slow clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset has ended, i.e., synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the configuration of field RSTC_MR.ERSTL. However, the resulting falling edge on NRST does not lead to a user reset. 302 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 If and only if the PROCRST bit is set, the Reset Controller reports the software status in field RSTC_SR.RSTTYP. Other software resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the RSTC_SR. SRCMP is cleared at the end of the software reset. No other software reset can be performed while the SRCMP bit is set, and writing any value in the RSTC_CR has no effect. Figure 14-5. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. Processor Startup 1 cycle = 2 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 14.4.3.4 User Reset The user reset is entered when a low level is detected on the NRST pin and bit URSTEN in the RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The user reset is entered as soon as a low level is detected on NRST. The processor reset and the peripheral reset are asserted. The user reset ends when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, field RSTC_SR.RSTTYP is loaded with the value 0x4, indicating a user reset. The NRST manager guarantees that the NRST line is asserted for External Reset Length slow clock cycles, as programmed in field RSTC_MR.ERSTL. However, if NRST does not rise after External Reset Length because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 303 Figure 14-6. User Reset State SLCK Any Freq. MCK NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 14.4.4 Reset State Priorities The reset state manager manages the priorities among the different reset sources. The resets are listed in order of priority as follows: 1. General reset 2. Watchdog reset 3. Software reset 4. User reset Particular cases are listed below: When in user reset: ̶ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. ̶ 304 A software reset is impossible, since the processor reset is being activated. When in software reset: ̶ A watchdog event has priority over the current state. ̶ The NRST has no effect. When in watchdog reset: ̶ The processor reset is active and so a software reset cannot be programmed. ̶ A user reset cannot be entered. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 14.5 Reset Controller (RSTC) User Interface Table 14-1. Offset Note: Register Mapping Register Name Access Reset 0x00 Control Register RSTC_CR Write-only – 0x04 Status Register RSTC_SR Read-only 0x0000_0000(1) 0x08 Mode Register RSTC_MR Read/Write 0x0000 0001 1. This value assumes that a general reset has been performed, subject to change if other types of reset are generated. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 305 14.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0x400E1400 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect 1: If KEY is correct, resets the processor • PERRST: Peripheral Reset 0: No effect 1: If KEY is correct, resets the peripherals • EXTRST: External Reset 0: No effect 1: If KEY is correct, asserts the NRST pin • KEY: System Reset Key 306 Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 14.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0x400E1404 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the MCK rising edge. If the user reset is disabled (URSTEN = 0 in RSTC_MR) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR, the URSTS bit triggers an interrupt. Reading the RSTC_SR resets the URSTS bit and clears the interrupt. 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type This field reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. Value Name Description 0 GENERAL_RST First power-up reset 1 – Reserved 2 WDT_RST Watchdog fault occurred 3 SOFT_RST Processor reset required by the software 4 USER_RST NRST pin detected low 5 – Reserved 6 – Reserved 7 – Reserved • NRSTL: NRST Pin Level This bit registers the NRST pin level sampled on each Master Clock (MCK) rising edge. • SRCMP: Software Reset Command in Progress When set, this bit indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. 0: No software command is being performed by the Reset Controller. The Reset Controller is ready for a software command. 1: A software reset command is being performed by the Reset Controller. The Reset Controller is busy. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 307 14.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0x400E1408 Access: Read/Write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 – 4 URSTIEN 3 – ERSTL 2 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • URSTEN: User Reset Enable 0: The detection of a low level on the NRST pin does not generate a user reset. 1: The detection of a low level on the NRST pin triggers a user reset. • URSTIEN: User Reset Interrupt Enable 0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) slow clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. Note that synchronization cycles must also be considered when calculating the actual reset length as previously described. • KEY: Write Access Password 308 Value Name 0xA5 PASSWD Description Writing any other value in this field aborts the write operation. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 15. Real-time Timer (RTT) 15.1 Description The Real-time Timer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16bit prescaler driven from the 32-kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. The RTT can also be configured to be driven by the 1Hz RTC signal, thus taking advantage of a calibrated 1Hz clock. The slow clock source can be fully disabled to reduce power consumption when only an elapsed seconds count is required. 15.2 15.3 Embedded Characteristics 32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1Hz clock 16-bit Configurable Prescaler Interrupt on Alarm or Counter Increment Block Diagram Figure 15-1. RTT_MR RTTDIS Real-time Timer RTT_MR RTT_MR RTTRST RTPRES RTT_MR reload 16-bit Prescaler SLCK RTTINCIEN set 0 RTT_MR RTC 1Hz RTTRST RTT_MR RTC1HZ 1 RTTINC RTT_SR 1 reset 0 rtt_int 0 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR reset CRTV RTT_SR ALMS set rtt_alarm = RTT_AR ALMV SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 309 15.4 Functional Description The programmable 16-bit prescaler value can be configured through the RTPRES field in the “Real-time Timer Mode Register” (RTT_MR). Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a 1Hz signal (if the slow clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. Bit RTTINC in the “Real-time Timer Status Register” (RTT_SR) is set each time there is a prescaler roll-over (see Figure 15-2) The real-time 32-bit counter can also be supplied by the 1Hz RTC clock. This mode is interesting when the RTC 1Hz is calibrated (CORRECTION field ≠ 0 in RTC_MR) in order to guaranty the synchronism between RTC and RTT counters. Setting the RTC1HZ bit in the RTT_MR drives the 32-bit RTT counter from the 1Hz RTC clock. In this mode, the RTPRES field has no effect on the 32-bit counter. The prescaler roll-over generates an increment of the real-time timer counter if RTC1HZ = 0. Otherwise, if RTC1HZ = 1, the real-time timer counter is incremented every second. The RTTINC bit is set independently from the 32-bit counter increment. The real-time timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3 in RTT_MR. Programming RTPRES to 1 or 2 is forbidden. If the RTT is configured to trigger an interrupt, the interrupt occurs two slow clock cycles after reading the RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the RTT_SR is cleared. The CRTV field can be read at any time in the “Real-time Timer Value Register” (RTT_VR). As this value can be updated asynchronously with the Master Clock, the CRTV field must be read twice at the same value to read a correct value. The current value of the counter is compared with the value written in the “Real-time Timer Alarm Register” (RTT_AR). If the counter value matches the alarm, the ALMS bit in the RTT_SR is set. The RTT_AR is set to its maximum value (0xFFFF_FFFF) after a reset. The ALMS flag is always a source of the RTT alarm signal that may be used to exit the system from low power modes (see Figure 15-1). The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value in the RTT_AR. The RTTINC bit can be used to start a periodic interrupt, the period being one second when the RTPRES field value = 0x8000 and the slow clock = 32.768 kHz. The RTTINCIEN bit must be cleared prior to writing a new RTPRES value in the RTT_MR. Reading the RTT_SR automatically clears the RTTINC and ALMS bits. Writing the RTTRST bit in the RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this module. This can be achieved by setting the RTTDIS bit in the RTT_MR. 310 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 15-2. RTT Counting SLCK RTPRES - 1 Prescaler 0 CRTV 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface APB cycle read RTT_SR APB cycle SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 311 15.5 Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read/Write 0x0000_8000 0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000 312 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 15.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0x400E1430 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 RTC1HZ 23 – 22 – 21 – 20 RTTDIS 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SLCK periods. RTPRES = 1 or 2: forbidden. RTPRES ≠ 0,1 or 2: The prescaler period is equal to RTPRES * SLCK periods. Note: The RTTINCIEN bit must be cleared prior to writing a new RTPRES value. • ALMIEN: Alarm Interrupt Enable 0: The bit ALMS in RTT_SR has no effect on interrupt. 1: The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0: The bit RTTINC in RTT_SR has no effect on interrupt. 1: The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 0: No effect. 1: Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. • RTTDIS: Real-time Timer Disable 0: The real-time timer is enabled. 1: The real-time timer is disabled (no dynamic power consumption). • RTC1HZ: Real-Time Clock 1Hz Clock Selection 0: The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events. 1: The RTT 32-bit counter is driven by the 1Hz RTC clock. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 313 15.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0x400E1434 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value When the CRTV value in RTT_VR equals the ALMV field, the ALMS flag is set in RTT_SR. As soon as the ALMS flag rises, the CRTV value equals ALMV+1 (refer to Figure 15-2). Note: 314 The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 15.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0x400E1438 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. Note: As CRTV can be updated asynchronously, it must be read twice at the same value. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 315 15.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0x400E143C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status (cleared on read) 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Prescaler Roll-over Status (cleared on read) 0: No prescaler roll-over occurred since the last read of the RTT_SR. 1: Prescaler roll-over occurred since the last read of the RTT_SR. 316 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16. Real-time Clock (RTC) 16.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator. It combines a complete time-of-day clock with alarm and a Gregorian or Persian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. A clock divider calibration circuitry can be used to compensate for crystal oscillator frequency variations. 16.2 Embedded Characteristics Full Asynchronous Design for Ultra Low Power Consumption Gregorian and Persian Modes Supported Programmable Periodic Interrupt Safety/security Features: ̶ Valid Time and Date Programmation Check ̶ On-The-Fly Time and Date Validity Check Counters Calibration Circuitry to Compensate for Crystal Oscillator Variations Waveform Generation for Trigger Event Register Write Protection SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 317 16.3 Block Diagram Figure 16-1. Real-time Clock Block Diagram Slow Clock: SLCK 32768 Divider Time Wave Generator Date Clock Calibration System Bus 16.4 User Interface Entry Control Alarm RTCOUT0 (e.g ADC AD[7:0] trigger) RTCOUT1 (e.g ADC AD[7] trigger) Interrupt Control RTC Interrupt Product Dependencies 16.4.1 Power Management The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller has no effect on RTC behavior. 16.4.2 Interrupt RTC interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. Table 16-1. 16.5 Peripheral IDs Instance ID RTC 2 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds reported in RTC Time Register (RTC_TIMR) and RTC Calendar Register (RTC_CALR). The valid year range is up to 2099 in Gregorian mode (or 1300 to 1499 in Persian mode). The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years except 1900). This is correct up to the year 2099. The RTC can generate events to trigger ADC measurements. 16.5.1 Reference Clock The reference clock is the Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 318 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.5.2 Timing The RTC is updated in real time at one-second intervals in Normal mode for the counters of seconds, at oneminute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 16.5.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition: If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC, MIN, HOUR fields. Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR or RTC_CALALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN, DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREn, DATEEN, MTHEN fields. 16.5.4 Error Checking when Programming Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is followed for the alarm. The following checks are performed: 1. Century (check if it is in range 19–20 or 13–14 in Persian mode) 2. Year (BCD entry check) 3. Date (check range 01–31) 4. Month (check if it is in BCD range 01–12, check validity regarding “date”) 5. Day (check range 1–7) 6. Hour (BCD checks: in 24-hour mode, check range 00–23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01–12) 7. Minute (check BCD and range 00–59) 8. Second (check BCD and range 00–59) Note: If the 12-hour mode is selected by means of the RTC Mode Register (RTC_MR), a 12-hour value can be programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIMR) to determine the range to be checked. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 319 16.5.5 RTC Internal Free Running Counter Error Checking To improve the reliability and security of the RTC, a permanent check is performed on the internal free running counters to report non-BCD or invalid date/time values. An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The flag can be cleared by setting the TDERRCLR bit in the Status Clear Command Register (RTC_SCCR). Anyway the TDERR error flag will be set again if the source of the error has not been cleared before clearing the TDERR flag. The clearing of the source of such error can be done by reprogramming a correct value on RTC_CALR and/or RTC_TIMR. The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e., every 10 seconds for SECONDS[3:0] field in RTC_TIMR). In this case the TDERR is held high until a clear command is asserted by TDERRCLR bit in RTC_SCCR. 16.5.6 Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register (RTC_CR). Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). The ACKUPD bit is automatically set within a second after setting the UPDTIM and/or UPDCAL bit (meaning one second is the maximum duration of the polling or wait for interrupt period). Once ACKUPD is set, it is mandatory to clear this flag by writing the corresponding bit in the RTC_SCCR, after which the user can write to the Time Register, the Calendar Register, or both. Once the update is finished, the user must clear UPDTIM and/or UPDCAL in the RTC_CR. When entering the programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these bits again. This is done by waiting for the SEC flag in the RTC_SR before setting UPDTIM/UPDCAL bit. After clearing UPDTIM/UPDCAL, the SEC flag must also be cleared. 320 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 16-2. Update Sequence Begin Prepare Time or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD =1? No Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 321 16.5.7 RTC Accurate Clock Calibration The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift. To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal frequency accuracy at room temperature (20–25°C). The typical clock drift range at room temperature is ±20 ppm. In the device operating temperature range, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200 ppm. The RTC clock calibration circuitry allows positive or negative correction in a range of 1.5 ppm to 1950 ppm. The calibration circuitry is fully digital. Thus, the configured correction is independent of temperature, voltage, process, etc., and no additional measurement is required to check that the correction is effective. If the correction value configured in the calibration circuitry results from an accurate crystal frequency measure, the remaining accuracy is bounded by the values listed below: Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 20 ppm, and from 30 ppm to 90 ppm Below 2 ppm, for an initial crystal drift between 20 ppm up to 30 ppm, and from 90 ppm to 130 ppm Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm The calibration circuitry does not modify the 32.768 kHz crystal oscillator clock frequency but it acts by slightly modifying the 1 Hz clock period from time to time. The correction event occurs every 1 + [(20 (19 x HIGHPPM)) x CORRECTION] seconds. When the period is modified, depending on the sign of the correction, the 1 Hz clock period increases or reduces by around 4 ms. Depending on the CORRECTION, NEGPPM and HIGHPPM values configured in RTC_MR, the period interval between two correction events differs. Figure 16-3. Calibration Circuitry RTC Divider by 32768 32.768 kHz Oscillator Add 32.768 kHz Integrator Comparator Other Logic 322 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 1Hz Time/Calendar Suppress CORRECTION, HIGHPPM NEGPPM Figure 16-4. Calibration Circuitry Waveforms Monotonic 1 Hz Counter value 32.768 kHz +50 ppm Phase adjustment (~4 ms) Nominal 32.768 kHz 32.768 kHz -50 ppm -25 ppm Crystal frequency remains unadjusted -50 ppm Internal 1 Hz clock is adjusted Time User configurable period (integer multiple of 1s or 20s) -50 ppm correction period -25 ppm correction period Time NEGATIVE CORRECTION Crystal clock Internally divided clock (256 Hz) Clock pulse periodically suppressed when correction period elapses Internally divided clock (128 Hz) 1.000 second 128 Hz clock edge delayed by 3.906 ms when correction period elapses POSITIVE CORRECTION 1.003906 second Internally divided clock (256 Hz) Internally divided clock (128 Hz) Clock edge periodically added when correction period elapses Internally divided clock (64 Hz) 128 Hz clock edge delayed by 3.906 ms when correction period elapses 0.996094 second 1.000 second The inaccuracy of a crystal oscillator at typical room temperature (±20 ppm at 20–25 °C) can be compensated if a reference clock/signal is used to measure such inaccuracy. This kind of calibration operation can be set up during the final product manufacturing by means of measurement equipment embedding such a reference clock. The correction of value must be programmed into the (RTC_MR), and this value is kept as long as the circuitry is powered (backup area). Removing the backup power supply cancels this calibration. This room temperature calibration can be further processed by means of the networking capability of the target application. In any event, this adjustment does not take into account the temperature variation. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 323 The frequency drift (up to -200 ppm) due to temperature variation can be compensated using a reference time if the application can access such a reference. If a reference time cannot be used, a temperature sensor can be placed close to the crystal oscillator in order to get the operating temperature of the crystal oscillator. Once obtained, the temperature may be converted using a lookup table (describing the accuracy/temperature curve of the crystal oscillator used) and RTC_MR configured accordingly. The calibration can be performed on-the-fly. This adjustment method is not based on a measurement of the crystal frequency/drift and therefore can be improved by means of the networking capability of the target application. If no crystal frequency adjustment has been done during manufacturing, it is still possible to do it. In the case where a reference time of the day can be obtained through LAN/WAN network, it is possible to calculate the drift of the application crystal oscillator by comparing the values read on RTC Time Register (RTC_TIMR) and programming the HIGHPPM and CORRECTION fields on RTC_MR according to the difference measured between the reference time and those of RTC_TIMR. 16.5.8 Waveform Generation Waveforms can be generated by the RTC in order to take advantage of the RTC inherent prescalers while the RTC is the only powered circuitry (Low-power mode of operation, Backup mode) or in any active mode. Going into Backup or Low-power operating modes does not affect the waveform generation outputs. The RTC waveforms are internally routed to ADC trigger events and those events have a source driver selected among five possibilities. Two different triggers can be generated at a time, the first one is configurable through field OUT0 in RTC_MR while the second trigger is configurable through field OUT1 in RTC_MR. OUT0 field manages the trigger for channel AD[7:0] while OUT1 manages the channel AD[7] only for specific modes. See the ADC section for selection of the measurement triggers and associated mode of operations. The first selection choice sticks the associated output at 0 (This is the reset value and it can be used at any time to disable the waveform generation). Selection choices 1 to 4 respectively select 1 Hz, 32 Hz, 64 Hz and 512 Hz. Selection choice 6 provides a copy of the alarm flag, so the associated output is set high (logical 1) when an alarm occurs and immediately cleared when software clears the alarm interrupt source. 324 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 16-5. Waveform Generation for ADC Trigger Event ‘0’ 0 ‘0’ 0 1 Hz 1 1 Hz 1 32 Hz 2 32 Hz 2 64 Hz 3 64 Hz 3 512 Hz 4 512 Hz 4 reserved 5 reserved 5 flag_alarm 6 To ADC trigger event for all channels flag_alarm RTC_MR(OUT0) alarm match event 1 To ADC trigger event for AD[n] n = higher index available 6 RTC_MR(OUT1) alarm match event 2 flag_alarm RTC_SCCR(ALRCLR) RTC_SCCR(ALRCLR) SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 325 16.6 Real-time Clock (RTC) User Interface Table 16-2. Offset Register Mapping Register Name Access Reset 0x00 Control Register RTC_CR Read/Write 0x00000000 0x04 Mode Register RTC_MR Read/Write 0x00000000 0x08 Time Register RTC_TIMR Read/Write 0x00000000 0x0C Calendar Register RTC_CALR Read/Write 0x01A11020 0x10 Time Alarm Register RTC_TIMALR Read/Write 0x00000000 0x14 Calendar Alarm Register RTC_CALALR Read/Write 0x01010000 0x18 Status Register RTC_SR Read-only 0x00000000 0x1C Status Clear Command Register RTC_SCCR Write-only – 0x20 Interrupt Enable Register RTC_IER Write-only – 0x24 Interrupt Disable Register RTC_IDR Write-only – 0x28 Interrupt Mask Register RTC_IMR Read-only 0x00000000 0x2C Valid Entry Register RTC_VER Read-only 0x00000000 0x30–0xC8 Reserved – – – 0xCC Reserved – – – 0xD0 Reserved – – – 0xD4–0xF8 Reserved – – – 0xFC Reserved – – – Note: If an offset is not listed in the table it must be considered as reserved. 326 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.6.1 RTC Control Register Name: RTC_CR Address: 0x400E1460 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • UPDTIM: Update Request Time Register 0: No effect or, if UPDTIM has been previously written to 1, stops the update procedure. 1: Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR. • UPDCAL: Update Request Calendar Register 0: No effect or, if UPDCAL has been previously written to 1, stops the update procedure. 1: Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR. • TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR depends on the value of TIMEVSEL. Value Name Description 0 MINUTE Minute change 1 HOUR Hour change 2 MIDNIGHT Every day at midnight 3 NOON Every day at noon SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 327 • CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) 328 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.6.2 RTC Mode Register Name: RTC_MR Address: 0x400E1464 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – 15 OUT1 14 13 – 12 HIGHPPM OUT0 11 10 9 8 CORRECTION 7 6 5 4 3 2 1 0 – – – NEGPPM – – PERSIAN HRMOD This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected. 1: 12-hour mode is selected. • PERSIAN: PERSIAN Calendar 0: Gregorian calendar. 1: Persian calendar. • NEGPPM: NEGative PPM Correction 0: Positive correction (the divider will be slightly higher than 32768). 1: Negative correction (the divider will be slightly lower than 32768). Refer to CORRECTION and HIGHPPM field descriptions. Note: NEGPPM must be cleared to correct a crystal slower than 32.768 kHz. • CORRECTION: Slow Clock Correction 0: No correction 1–127: The slow clock will be corrected according to the formula given in HIGHPPM description. • HIGHPPM: HIGH PPM Correction 0: Lower range ppm correction with accurate correction. 1: Higher range ppm correction with accurate correction. If the absolute value of the correction to be applied is lower than 30 ppm, it is recommended to clear HIGHPPM. HIGHPPM set to 1 is recommended for 30 ppm correction and above. Formula: If HIGHPPM = 0, then the clock frequency correction range is from 1.5 ppm up to 98 ppm. The RTC accuracy is less than 1 ppm for a range correction from 1.5 ppm up to 30 ppm. The correction field must be programmed according to the required correction in ppm; the formula is as follows: SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 329 3906 CORRECTION = ----------------------- – 1 20 × ppm The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field. If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm. The correction field must be programmed according to the required correction in ppm; the formula is as follows: 3906 CORRECTION = ------------ – 1 ppm The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field. If NEGPPM is set to 1, the ppm correction is negative (used to correct crystals that are faster than the nominal 32.768 kHz). • OUT0: All ADC Channel Trigger Event Source Selection Value Name Description 0 NO_WAVE No waveform, stuck at ‘0’ 1 FREQ1HZ 1 Hz square wave 2 FREQ32HZ 32 Hz square wave 3 FREQ64HZ 64 Hz square wave 4 FREQ512HZ 512 Hz square wave 6 ALARM_FLAG Output is a copy of the alarm flag • OUT1: ADC Last Channel Trigger Event Source Selection Value 330 Name Description 0 NO_WAVE No waveform, stuck at ‘0’ 1 FREQ1HZ 1 Hz square wave 2 FREQ32HZ 32 Hz square wave 3 FREQ64HZ 64 Hz square wave 4 FREQ512HZ 512 Hz square wave 6 ALARM_FLAG Output is a copy of the alarm flag SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.6.3 RTC Time Register Name: RTC_TIMR Address: 0x400E1468 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set is 1–12 (BCD) in 12-hour mode or 0–23 (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0: AM. 1: PM. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 331 16.6.4 RTC Calendar Register Name: RTC_CALR Address: 0x400E146C Access: Read/Write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19–20 (Gregorian) or 13–14 (Persian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00–99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MONTH: Current Month The range that can be set is 01–12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • DAY: Current Day in Current Week The range that can be set is 1–7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Day in Current Month The range that can be set is 01–31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. 332 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0x400E1470 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Note: To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then reenable it after the change has been made. This requires up to three accesses to the RTC_TIMALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREN fields. • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0: The second-matching alarm is disabled. 1: The second-matching alarm is enabled. • MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. • MINEN: Minute Alarm Enable 0: The minute-matching alarm is disabled. 1: The minute-matching alarm is enabled. • HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0: The hour-matching alarm is disabled. 1: The hour-matching alarm is enabled. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 333 16.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0x400E1474 Access: Read/Write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Note: To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_CALALR. The first access clears the enable corresponding to the field to change (DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in DATEEN, MTHEN fields. • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0: The month-matching alarm is disabled. 1: The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0: The date-matching alarm is disabled. 1: The date-matching alarm is enabled. 334 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.6.7 RTC Status Register Name: RTC_SR Address: 0x400E1478 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERR CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update Value Name Description 0 FREERUN Time and calendar registers cannot be updated. 1 UPDATE Time and calendar registers can be updated. • ALARM: Alarm Flag Value Name Description 0 NO_ALARMEVENT No alarm matching condition occurred. 1 ALARMEVENT An alarm matching condition has occurred. • SEC: Second Event Value Name Description 0 NO_SECEVENT No second event has occurred since the last clear. 1 SECEVENT At least one second event has occurred since the last clear. • TIMEV: Time Event Value Name Description 0 NO_TIMEVENT No time event has occurred since the last clear. 1 TIMEVENT At least one time event has occurred since the last clear. Note: The time event is selected in the TIMEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: minute change, hour change, noon, midnight (day change). • CALEV: Calendar Event Value Name Description 0 NO_CALEVENT No calendar event has occurred since the last clear. 1 CALEVENT At least one calendar event has occurred since the last clear. Note: The calendar event is selected in the CALEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: week change, month change and year change. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 335 • TDERR: Time and/or Date Free Running Error Value 336 Name Description 0 CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). 1 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0x400E147C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • SECCLR: Second Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • TDERRCLR: Time and/or Date Free Running Error Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 337 16.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0x400E1480 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERREN CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0: No effect. 1: The alarm interrupt is enabled. • SECEN: Second Event Interrupt Enable 0: No effect. 1: The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable 0: No effect. 1: The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable 0: No effect. 1: The selected calendar event interrupt is enabled. • TDERREN: Time and/or Date Error Interrupt Enable 0: No effect. 1: The time and date error interrupt is enabled. 338 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0x400E1484 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0: No effect. 1: The alarm interrupt is disabled. • SECDIS: Second Event Interrupt Disable 0: No effect. 1: The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable 0: No effect. 1: The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable 0: No effect. 1: The selected calendar event interrupt is disabled. • TDERRDIS: Time and/or Date Error Interrupt Disable 0: No effect. 1: The time and date error interrupt is disabled. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 339 16.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0x400E1488 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERR CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled. • ALR: Alarm Interrupt Mask 0: The alarm interrupt is disabled. 1: The alarm interrupt is enabled. • SEC: Second Event Interrupt Mask 0: The second periodic interrupt is disabled. 1: The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0: The selected time event interrupt is disabled. 1: The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0: The selected calendar event interrupt is disabled. 1: The selected calendar event interrupt is enabled. • TDERR: Time and/or Date Error Mask 0: The time and/or date error event is disabled. 1: The time and/or date error event is enabled. 340 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 16.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0x400E148C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed. • NVCAL: Non-valid Calendar 0: No invalid data has been detected in RTC_CALR (Calendar Register). 1: RTC_CALR has contained invalid data since it was last programmed. • NVTIMALR: Non-valid Time Alarm 0: No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1: RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non-valid Calendar Alarm 0: No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1: RTC_CALALR has contained invalid data since it was last programmed. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 341 17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in Debug mode or Idle mode. 17.2 342 Embedded Characteristics 12-bit Key-protected Programmable Counter Watchdog Clock is Independent from Processor Clock Provides Reset or Interrupt Signals to the System Counter May Be Stopped while the Processor is in Debug State or in Idle Mode SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 17.3 Block Diagram Figure 17-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDV WDT_CR WDRSTT reload 1 0 12-bit Down Counter WDT_MR WDD reload Current Value 1/128 SLCK <= WDD WDT_MR WDRSTEN =0 wdt_fault (to Reset Controller) set set read WDT_SR or reset WDERR reset WDUNF reset wdt_int WDFIEN WDT_MR SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 343 17.4 Functional Description The Watchdog Timer is used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz). After a processor reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a backup reset). This means that a default watchdog is running at reset, i.e., at power-up. The user can either disable the WDT by setting bit WDT_MR.WDDIS or reprogram the WDT to meet the maximum watchdog period the application requires. When the WDDIS bit is set, the fields WDV and WDD must not be modified. If the watchdog is restarted by writing into the Control Register (WDT_CR), WDT_MR must not be programmed during a period of time of three slow clock periods following the WDT_CR write access. In any case, programming a new value in WDT_MR automatically initiates a restart instruction. WDT_MR can be written only once. Only a processor reset resets it. Writing WDT_MR reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by setting bit WDT_CR.WDRSTT. The watchdog counter is then immediately reloaded from WDT_MR and restarted, and the slow clock 128 divider is reset and restarted. WDT_CR is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if bit WDT_MR.WDRSTEN is set. Moreover, the bit WDUNF is set in the Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur while the watchdog counter is within a window between 0 and WDD. WDD is defined in WDT_MR. Any attempt to restart the watchdog while the watchdog counter is between WDV and WDD results in a watchdog error, even if the watchdog is disabled. The bit WDT_SR.WDERR is updated and the “wdt_fault” signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDT_MR.WDFIEN is set. The signal “wdt_fault” to the Reset Controller causes a watchdog reset if the WDRSTEN bit is set as already explained in the Reset Controller documentation. In this case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in WDT_MR. 344 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 17-2. Watchdog Behavior Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF if WDRSTEN is 0 Normal behavior WDV Forbidden Window WDD Permitted Window 0 WDT_CR.WDRSTT=1 Watchdog Fault SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 345 17.5 Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 346 Access Reset WDT_CR Write-only – Mode Register WDT_MR Read/Write Once 0x3FFF_2FFF Status Register WDT_SR Read-only 0x0000_0000 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 17.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0x400E1450 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT Note: The WDT_CR register values must not be modified within three slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected. • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the watchdog if KEY is written to 0xA5. • KEY: Password Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 347 17.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0x400E1454 Access: Read/Write Once 31 – 30 – 29 WDIDLEHLT 28 WDDBGHLT 27 23 22 21 20 19 11 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV Note: The first write access prevents any further modification of the value of this register. Read accesses remain possible. Note: The WDT_MR register values must not be modified within three slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected. • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit watchdog counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A watchdog fault (underflow or error) has no effect on interrupt. 1: A watchdog fault (underflow or error) asserts interrupt. • WDRSTEN: Watchdog Reset Enable 0: A watchdog fault (underflow or error) has no effect on the resets. 1: A watchdog fault (underflow or error) triggers a watchdog reset. • WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a watchdog fault (underflow or error) activates the processor reset. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. Note: When the WDDIS bit is set, the fields WDV and WDD must not be modified. • WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, setting bit WDT_CR.WDRSTT restarts the timer. If the Watchdog Timer value is greater than WDD, setting bit WDT_CR.WDRSTT causes a watchdog error. 348 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • WDDBGHLT: Watchdog Debug Halt 0: The watchdog runs when the processor is in debug state. 1: The watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The watchdog runs when the system is in idle state. 1: The watchdog stops when the system is in idle state. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 349 17.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0x400E1458 Access Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow (cleared on read) 0: No watchdog underflow occurred since the last read of WDT_SR. 1: At least one watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error (cleared on read) 0: No watchdog error occurred since the last read of WDT_SR. 1: At least one watchdog error occurred since the last read of WDT_SR. 350 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 18. Supply Controller (SUPC) Description The Supply Controller (SUPC) controls the supply voltages of the system. The SUPC also generates the slow clock by selecting either the low-power RC oscillator or the low-power crystal oscillator. 18.1 Embedded Characteristics Supply Monitor Detection on VDDIO or a POR (Power-On Reset) on VDDCORE Can Trigger a Core Reset Generates the Slow Clock SLCK, by Selecting Either the 32 kHz Low-power RC Oscillator or the 32 kHz Low-power Crystal Oscillator SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 351 18.2 Block Diagram Figure 18-1. Supply Controller Block Diagram VDDIO PIOx VDDIO Power Supply PIOA/B Input/Output Buffers Supply Controller Zero-Power Power-on Reset ADC Analog Circuitry ADx ON Supply Monitor out WKUP0 - WKUP15 VDDOUT General Purpose Backup Registers SLCK RTC SLCK RTT Voltage Regulator rtc_alarm RTTDIS rtt_alarm BODDIS osc32k_xtal_en Power-on Reset Core XTALSEL XIN32 XOUT32 Xtal 32 kHz Oscillator Slow Clock SLCK VDDCORE Embedded 32 kHz RC Oscillator osc32k_rc_en SRAM vddcore_nreset Peripherals VDDIO Power Supply Reset Controller proc_nreset periph_nreset Matrix Peripheral Bridge NRST FSTT0 - FSTT15 (1) Cortex-M4 SLCK Flash Embedded 24/16/8 MHz RC Oscillator XIN XOUT Main Clock MAINCK 3 - 20 MHz XTAL Oscillator Power Management Controller Master Clock MCK VDDIO PLLACK SLCK PLL SLCK Watchdog Timer Core Power Supply Note 1: FSTT0 - FSTT15 are possible Fast Startup sources, generated by WKUP0 - WKUP15 pins, but are not physical pins. 352 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 18.3 Supply Controller Functional Description 18.3.1 Supply Controller Overview The device can be divided into two power supply areas: VDDIO power supply: includes the Supply Controller, part of the Reset Controller, the slow clock switch, the General-purpose Backup Registers, the Supply Monitor and the clock which includes the Real-time Timer and the Real-time Clock Core power supply: includes part of the Reset Controller, the POR core, the processor, the SRAM memory, the Flash memory and the peripherals The SUPC intervenes when the VDDIO power supply rises (when the system is starting). The SUPC also integrates the slow clock generator which is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The slow clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the slow clock source. The SUPC and the VDDIO power supply have a reset circuitry based on a zero-power power-on reset cell. The zero-power power-on reset allows the SUPC to start properly as soon as the VDDIO voltage becomes valid. At start-up of the system, once the backup voltage VDDIO is valid and the embedded 32 kHz RC oscillator is stabilized, the SUPC starts up the core by sequentially enabling the internal voltage regulator, waiting for the core voltage VDDCORE to be valid, then releasing the reset signal of the core “vddcore_nreset” signal. Once the system has started, the user can program a supply monitor and/or a brownout detector. If the supply monitor detects a voltage on VDDIO that is too low, the SUPC can assert the reset signal of the core “vddcore_nreset” signal until VDDIO is valid. Likewise, if the POR core detects a core voltage VDDCORE that is too low, the SUPC can assert the reset signal “vddcore_nreset” until VDDCORE is valid. 18.3.2 Slow Clock Generator The SUPC embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency. The command is made by writing the SUPC Control Register (SUPC_CR) with the XTALSEL bit at 1.This results in a sequence which first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the oscillator, then enables the crystal oscillator, then counts a number of slow RC oscillator clock periods to cover the start-up time of the crystal oscillator (refer to the section “Electrical Characteristics” for details of 32 kHz crystal oscillator start-up time), then switches the slow clock on the output of the crystal oscillator and then disables the RC oscillator to save power. The switching time may vary according to the slow RC oscillator clock frequency range. The switch of the slow clock source is glitch free. The OSCSEL bit of the SUPC Status Register (SUPC_SR) allows knowing when the switch sequence is done. Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply. If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected. The user can also set the crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the product electrical characteristics section. In order to set the Bypass mode, the OSCBYPASS bit of the SUPC Mode Register (SUPC_MR) needs to be set to 1 prior to writing a 1 in bit XTALSEL. 18.3.3 Supply Monitor The SUPC embeds a supply monitor which is located in the VDDIO power supply and which monitors VDDIO power supply. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 353 The supply monitor can be used to prevent the processor from falling into an unpredictable state if the main power supply drops below a certain level. The threshold of the supply monitor is programmable (refer to the “VDDIO Supply Monitor” characteristics in the “Electrical Characteristics” section of the datasheet). This threshold is programmed in the SMTH field of the SUPC Supply Monitor Mode Register (SUPC_SMMR). The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock periods, depending on the choice of the user. This is configured by programming the SMSMPL field in SUPC_SMMR. By enabling the supply monitor for such reduced times, the typical supply monitor power consumption is divided, respectively, by factors of 2, 16 and 128, if the user does not require continuous monitoring of the VDDIO power supply. A supply monitor detection can generate a reset of the core power supply. Generating a core reset when a supply monitor detection occurs is enabled by writing the SMRSTEN bit to 1 in SUPC_SMMR. The SUPC provides two status bits in the SUPC_SR for the supply monitor: The SMOS bit provides real-time information, which is updated at each measurement cycle, or at each slow clock cycle if the measurement is continuous. The SMS bit provides saved information and shows a supply monitor detection has occurred since the last read of SUPC_SR. The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in SUPC_SMMR. Figure 18-2. Supply Monitor Status Bit and Associated Interrupt Continuous Sampling (SMSMPL = 1) Periodic Sampling Supply Monitor ON 3.3V Threshold 0V Read SUPC_SR SMS and SUPC interrupt 18.3.4 Power Supply Reset 18.3.4.1 Raising the Power Supply As soon as the voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset cell maintains its output low as long as VDDIO has not reached its target voltage. During this time, the SUPC is entirely reset. When the VDDIO voltage becomes valid and zero-power power-on reset signal is released, a counter is started for 5 slow clock cycles. This is the time it takes for the 32 kHz RC oscillator to stabilize. 354 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 After this time, the voltage regulator is enabled. The core power supply rises and the POR core provides the bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releasing the vddcore_nreset signal to the Reset Controller after the bodcore_in signal has been confirmed as valid for at least one slow clock cycle. Figure 18-3. Raising the VDDIO Power Supply TON Voltage 7 x Slow Clock Cycles (5 for startup slow RC + 2 for synchro.) Regulator Backup Power Supply 3 x Slow Clock Cycles 2 x Slow Clock Cycles 6.5 x Slow Clock Cycles Zero-Power POR Zero-Power Power-On Reset Cell output 22 - 42 kHz RC Oscillator output vr_on Core Power Supply Fast RC Oscillator output bodcore_in (POR Core output) vddcore_nreset RSTC.ERSTL default = 2 NRST (no ext. drive assumed) periph_nreset proc_nreset Note: After “proc_nreset” rising, the core starts fetching instructions from Flash at 8 MHz. 18.3.5 Core Reset The SUPC manages the vddcore_nreset signal to the Reset Controller, as described in Section 18.3.4 ”Power Supply Reset”. The vddcore_nreset signal is normally asserted before shutting down the core power supply and released as soon as the core power supply is correctly regulated. There are two additional sources which can be programmed to activate vddcore_nreset: 18.3.5.1 VDDIO supply monitor detection POR core detection Supply Monitor Reset The supply monitor is capable of generating a reset of the system. This can be enabled by setting the SMRSTEN bit in SUPC_SMMR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 355 If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately activated for a minimum of one slow clock cycle. 18.3.5.2 POR Core Reset The POR Core provides the bodcore_in signal to the SUPC which indicates that the voltage regulation is operating as programmed. If this signal is lost for longer than one slow clock period while the voltage regulator is enabled, the SUPC can assert vddcore_nreset. This feature is enabled by writing the bit BODRSTEN (POR Core Reset Enable) to 1 in SUPC_MR. If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset signal is asserted for a minimum of one slow clock cycle and then released if bodcore_in has been reactivated. The BODRSTS bit is set in SUPC_SR so that the user can know the source of the last reset. While the POR core output (bodcore_in) is cleared, the vddcore_nreset signal remains active. 18.3.6 Register Write Protection To prevent any single software error from corrupting SUPC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the System Controller Write Protection Mode Register (SYSC_WPMR). The following registers can be write-protected: RSTC Mode Register RTT Mode Register RTT Alarm Register RTC Control Register RTC Mode Register RTC Time Alarm Register RTC Calendar Alarm Register General Purpose Backup Registers Supply Controller Control Register Supply Controller Supply Monitor Mode Register Supply Controller Mode Register 18.3.7 Register Bits in Backup Domain (VDDIO) The following configuration registers are physically located in the product backup domain: 356 RSTC Mode Register RTT Mode Register RTT Alarm Register RTC Control Register RTC Mode Register RTC Time Alarm Register RTC Calendar Alarm Register General Purpose Backup Registers Supply Controller Control Register Supply Controller Supply Monitor Mode Register Supply Controller Mode Register Supply Controller Status Register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 18.4 Supply Controller (SUPC) User Interface The user interface of the Supply Controller is part of the System Controller User Interface. 18.4.1 System Controller (SYSC) User Interface Table 18-1. System Controller Registers Offset System Controller Peripheral Name 0x00-0x0c Reset Controller RSTC 0x10-0x2C Supply Controller SUPC 0x30-0x3C Real-Time Timer RTT 0x50-0x5C Watchdog Timer WDT 0x60-0x8C Real-Time Clock RTC 0x90-0xDC General-Purpose Backup Register GPBR 0xE0 Reserved – 0xE4 Write Protection Mode Register SYSC_WPMR 0xE8-0xF8 Reserved – 18.4.2 Supply Controller (SUPC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Supply Controller Control Register 0x04 Name Access Reset SUPC_CR Write-only – Supply Controller Supply Monitor Mode Register SUPC_SMMR Read/Write 0x0000_0000 0x08 Supply Controller Mode Register SUPC_MR Read/Write 0x00E0_5A00 0x0C-0x10 Reserved – – – 0x14 Supply Controller Status Register SUPC_SR Read-only 0x0000_0000 0x18-0x2C Reserved – – – SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 357 18.4.3 Supply Controller Control Register Name: SUPC_CR Address: 0x400E1410 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 XTALSEL 2 ZERO 1 – 0 – • ZERO: This bit must always be written to 0. This bit must always be written to 0. • XTALSEL: Crystal Oscillator Select 0 (NO_EFFECT): No effect. 1 (CRYSTAL_SEL): If KEY is correct, switches the slow clock on the crystal oscillator output. • KEY: Password 358 Value Name 0xA5 PASSWD Description Writing any other value in this field aborts the write operation. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 18.4.4 Supply Controller Supply Monitor Mode Register Name: SUPC_SMMR Address: 0x400E1414 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 SMIEN 12 SMRSTEN 11 – 10 9 SMSMPL 8 7 – 6 – 5 – 4 – 3 2 1 0 SMTH • SMTH: Supply Monitor Threshold Selects the threshold voltage of the supply monitor. Refer to the section “Electrical Characteristics” for voltage values. • SMSMPL: Supply Monitor Sampling Period Value Name Description 0 SMD Supply Monitor disabled 1 CSM Continuous Supply Monitor 2 32SLCK Supply Monitor enables one SLCK period every 32 SLCK periods 3 256SLCK Supply Monitor enables one SLCK period every 256 SLCK periods 4 2048SLCK Supply Monitor enables one SLCK period every 2,048 SLCK periods • SMRSTEN: Supply Monitor Reset Enable 0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. 1 (ENABLE): The core reset signal vddcore_nreset is asserted when a supply monitor detection occurs. • SMIEN: Supply Monitor Interrupt Enable 0 (NOT_ENABLE): The SUPC interrupt signal is not affected when a supply monitor detection occurs. 1 (ENABLE): The SUPC interrupt signal is asserted when a supply monitor detection occurs. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 359 18.4.5 Supply Controller Mode Register Name: SUPC_MR Address: 0x400E1418 Access: Read/Write 31 30 29 28 27 26 25 24 KEY 23 PSWITCH2 22 PSWITCH1 21 – 20 OSCBYPASS 19 – 18 – 17 – 16 – 15 – 14 – 13 BODDIS 12 BODRSTEN 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • BODRSTEN: POR Core Reset Enable 0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a brownout detection occurs. 1 (ENABLE): The core reset signal vddcore_nreset is asserted when a brownout detection occurs. • BODDIS: POR Core Disable 0 (ENABLE): The core brownout detector is enabled. 1 (DISABLE): The core brownout detector is disabled. • OSCBYPASS: Oscillator Bypass 0 (NO_EFFECT): No effect. Clock selection depends on XTALSEL value. 1 (BYPASS): The 32 kHz crystal oscillator is bypassed if XTALSEL=1. OSCBYPASS must be set prior to write XTALSEL=1. • PSWITCH1: SRAM1 Power Switch 0 (OFF): The SRAM1 is not powered. 1 (ON): The SRAM1 is powered. Refer to “Internal SRAM” in the section “Memories”. • PSWITCH2: SRAM2 Power Switch 0 (OFF): The SRAM2 is not powered. 1 (ON): The SRAM2 is powered. Refer to “Internal SRAM” in the section “Memories”. • KEY: Password Key 360 Value Name 0xA5 PASSWD Description Writing any other value in this field aborts the write operation. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 18.4.6 Supply Controller Status Register Name: SUPC_SR Address: 0x400E1424 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 OSCSEL 6 SMOS 5 SMS 4 SMRSTS 3 BODRSTS 2 – 1 – 0 – Note: Because of the asynchronism between the slow clock (SLCK) and the system clock (MCK), the status register flag reset is taken into account only two slow clock cycles after the read of the SUPC_SR. • BODRSTS: Brownout Detector Reset Status (cleared on read) 0 (NO): No core brownout rising edge event has been detected since the last read of SUPC_SR. 1 (PRESENT): At least one brownout output rising edge event has been detected since the last read of SUPC_SR. When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detection cell. The rising edge event occurs only when there is a voltage transition below the threshold. • SMRSTS: Supply Monitor Reset Status (cleared on read) 0 (NO): No supply monitor detection has generated a core reset since the last read of SUPC_SR. 1 (PRESENT): At least one supply monitor detection has generated a core reset since the last read of SUPC_SR. • SMS: Supply Monitor Status (cleared on read) 0 (NO): No supply monitor detection since the last read of SUPC_SR. 1 (PRESENT): At least one supply monitor detection since the last read of SUPC_SR. • SMOS: Supply Monitor Output Status 0 (HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement. 1 (LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement. • OSCSEL: 32-kHz Oscillator Selection Status 0 (RC): The slow clock SLCK is generated by the embedded 32 kHz RC oscillator. 1 (CRYST): The slow clock SLCK is generated by the 32 kHz crystal oscillator. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 361 18.4.7 System Controller Write Protection Mode Register Name: SYSC_WPMR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). See Section 18.3.6 ”Register Write Protection” for the list of registers that can be write-protected. • WPKEY: Write Protection Key Value Name 0x525443 PASSWD 362 Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 19. General Purpose Backup Registers (GPBR) 19.1 Description The System Controller embeds 256 bits of General Purpose Backup registers organized as Eight 32-bit registers. 19.2 Embedded Characteristics 256 bits of General Purpose Backup Registers SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 363 19.3 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Offset 0x0 ... 0xAC 364 Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 7 SYS_GPBR7 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Access Reset Read/Write 0x00000000 ... ... Read/Write 0x00000000 19.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0x400E1490 Access: Read/Write 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 GPBR_VALUE 23 22 21 20 19 GPBR_VALUE 15 14 13 12 11 GPBR_VALUE 7 6 5 4 3 GPBR_VALUE These registers are reset at first power-up and on each loss of VDDIO. • GPBR_VALUE: Value of GPBR x SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 365 20. Memory to Memory (MEM2MEM) 20.1 Description The Memory to Memory (MEM2MEM) module allows the Peripheral DMA Controller (PDC) to perform memory to memory transfer without CPU intervention. The transfer size can be configured in byte, half-word or word. Two PDC channels are required to perform the transfer; one channel defines the source of the transfer and the other defines the destination. 20.2 366 Embedded Characteristics Allows PDC to perform memory to memory transfer Supports byte, half-word and word transfer Interrupt for End of Transfer SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 20.3 Block Diagram Figure 20-1. Memory to Memory Block Diagram PDC MEM2MEM Receive Channel MEM2MEM Transmit Channel MEM2MEM RXEND RXBUFF Interrupt Controller Control Logic peripheral clock User Interface PMC THR APB SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 367 20.4 Product Dependencies 20.4.1 Power Management The MEM2MEM is not continuously clocked. The user must first configure the Power Management Controller (PMC) to enable the MEM2MEM clock. 20.4.2 Interrupt Sources The MEM2MEM interface has an interrupt line connected to the Interrupt Controller. Handling the MEM2MEM interrupt requires programming the Interrupt Controller before configuring the MEM2MEM. Table 20-1. 20.5 Peripheral IDs Instance ID MEM2MEM 15 Functional Description The memory to memory transfer requires two operations. The PDC receive channel associated to the MEM2MEM module must be configured with the transfer destination address and buffer size. The PDC transmit channel associated to the MEM2MEM module must be configured with the source address and buffer size. The transmit channel buffer size must be equal to the receive channel buffer size. The two PDC channels exchange data through the Memory to Memory Transfer Holding Register (MEM2MEM_THR) which appears fully transparent from configuration. This register can be used as a general purpose register in case the memory to memory transfer capability is not used. The size of each element of the data buffer can be configured in byte, half-word or word by writing TSIZE field in the Memory to Memory Mode Register (MEM2MEM_MR). Word transfer (32-bit) is the default size. The transfer ends when either RXEND rises and/or RXBUFF rises in the Memory to Memory Interrupt Status Register (MEM2MEM_ISR). An interrupt can be triggered at the end of transfer by configuring the Memory to Memory Interrupt Enable Register (MEM2MEM_IER). Refer to the PDC section of the product datasheet for detailed information. 368 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 20.6 Memory to Memory (MEM2MEM) User Interface Table 20-2. Register Mapping Offset Register Name Access Reset 0x00 Memory to Memory Transfer Holding Register MEM2MEM_THR Read/Write 0x0000_0000 0x04 Memory to Memory Mode Register MEM2MEM_MR Read/Write 0x0000_0002 0x08 Memory to Memory Interrupt Enable Register MEM2MEM_IER Write-only – 0x0C Memory to Memory Interrupt Disable Register MEM2MEM_IDR Write-only – 0x10 Memory to Memory Interrupt Mask Register MEM2MEM_IMR Read-only 0x0000_0000 0x14 Memory to Memory Interrupt Status Register MEM2MEM_ISR Read-only 0x0000_0000 0x18–0xFC Reserved – – – 0x100–0x124 Reserved for PDC Registers – – – SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 369 20.6.1 Memory to Memory Transfer Holding Register Name: MEM2MEM_THR Address: 0x40028000 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 THDATA 23 22 21 20 THDATA 15 14 13 12 THDATA 7 6 5 4 THDATA • THDATA: Transfer Holding Data Must be written by the PDC transmit channel and read by the PDC receive channel. 370 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 20.6.2 Memory to Memory Mode Register Name: MEM2MEM_MR Address: 0x40028004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0 TSIZE • TSIZE: Transfer Size Value Name Description 0x0 T_8BIT The buffer size is defined in byte. 0x1 T_16BIT The buffer size is defined in half-word (16-bit). 0x2 T_32BIT The buffer size is defined in word (32-bit). Default value. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 371 20.6.3 Memory to Memory Interrupt Enable Register Name: MEM2MEM_IER Address: 0x40028008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RXBUFF 0 RXEND • RXEND: End of Transfer Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. • RXBUFF: Buffer Full Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. 372 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 20.6.4 Memory to Memory Interrupt Disable Register Name: MEM2MEM_IDR Address: 0x4002800C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RXBUFF 0 RXEND • RXEND: End of Transfer Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. • RXBUFF: Buffer Full Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 373 20.6.5 Memory to Memory Interrupt Mask Register Name: MEM2MEM_IMR Address: 0x40028010 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RXBUFF 0 RXEND • RXEND: End of Transfer Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. • RXBUFF: Buffer Full Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. 374 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 20.6.6 Memory to Memory Interrupt Status Register Name: MEM2MEM_ISR Address: 0x40028014 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RXBUFF 0 RXEND • RXEND: End of Transfer 0: The End of Transfer signal from the PDC receive channel is inactive. 1: The End of Transfer signal from the PDC receive channel is active. • RXBUFF: Buffer Full 0: The signal Buffer Full from the PDC receive channel is inactive. 1: The signal Buffer Full from the PDC receive channel is active. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 375 21. Enhanced Embedded Flash Controller (EEFC) 21.1 Description The Enhanced Embedded Flash Controller (EEFC) provides the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 21.2 21.3 Embedded Characteristics Increases Performance in Thumb-2 Mode with 128-bit or 64-bit-wide Memory Interface up to 48 MHz Code Loop Optimization 64 Lock Bits, Each Protecting a Lock Region 8 General-purpose GPNVM Bits One-by-one Lock Bit Programming Commands Protected by a Keyword Erase the Entire Flash Erase by Plane Erase by Sector Erase by Page Provides Unique Identifier Provides 512-byte User Signature Area Supports Erasing before Programming Locking and Unlocking Operations Supports Read of the Calibration Bits Product Dependencies 21.3.1 Power Management The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has no effect on its behavior. 21.3.2 Interrupt Sources The EEFC interrupt line is connected to the interrupt controller. Using the EEFC interrupt requires the interrupt controller to be programmed first. The EEFC interrupt is generated only if the value of bit EEFC_FMR.FRDY is 1. Table 21-1. 21.4 Peripheral IDs Instance ID EFC 6 Functional Description 21.4.1 Embedded Flash Organization The embedded Flash interfaces directly with the internal bus. The embedded Flash is composed of: 376 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 One memory plane organized in several pages of the same size for the code A separate 2 x 512-byte memory area which includes the unique chip identifier A separate 512-byte memory area for the user signature Two 128-bit or 64-bit read buffers used for code read optimization One 128-bit or 64-bit read buffer used for data read optimization One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 Mbyte address space, so that each word can be written to its final address. Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with a lock region composed of several pages in the memory plane. Several bits that may be set and cleared through the EEFC interface, called general-purpose non-volatile memory bits (GPNVM bits) The embedded Flash size, the page size, the organization of lock regions and the definition of GPNVM bits are specific to the device. The EEFC returns a descriptor of the Flash controller after a ‘Get Flash Descriptor’ command has been issued by the application (see Section 21.4.3.1 ”Get Flash Descriptor Command”). C od e Ar ea Flash Memory Areas @FBA+0x010 @FBA+0x000 Write “Stop Unique Identifier” (Flash Command SPUI) Write “Start Unique Identifier” (Flash Command STUI) U ni qu e Id en tif ie rA re a @FBA+0x3FF @FBA+0x010 Unique Identifier @FBA+0x000 Write “Stop User signature” (Flash Command SPUS) Write “Start User Signature” (Flash Command STUS) se rS ig na tu re Ar ea @FBA+0x1FF U Figure 21-1. @FBA+0x000 FBA = Flash Base Address SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 377 Figure 21-2. Organization of Embedded Flash for Code Memory Plane Start Address Page 0 Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock Bit (n-1) Page (m-1) Start Address + Flash size -1 378 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Page (n*m-1) 21.4.2 Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb-2 mode by means of the 128- or 64-bit-wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. The read operations can be performed with or without wait states. Wait states must be programmed in the field FWS in the Flash Mode register (EEFC_FMR). Defining FWS as 0 enables the single-cycle access of the embedded Flash. For mre details, refer to the section “Electrical Characteristics” of this datasheet. 21.4.2.1 128- or 64-bit Access Mode By default, the read accesses of the Flash are performed through a 128-bit wide memory interface. It improves system performance especially when two or three wait states are needed. For systems requiring only 1 wait state, or to focus on current consumption rather than performance, the user can select a 64-bit wide memory access via the bit EEFC_FMR.FAM. For more details, refer to the section “Electrical Characteristics” of this datasheet. 21.4.2.2 Code Read Optimization Code read optimization is enabled if the bit EEFC_FMR.SCOD is cleared. A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential code fetch. Note: Immediate consecutive code read accesses are not mandatory to benefit from this optimization. The sequential code read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set to 1, these buffers are disabled and the sequential code read is no longer optimized. Another system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize loop code fetch. Refer to Section 21.4.2.3 ”Code Loop Optimization” for more details. Figure 21-3. Code Read Optimization for FWS = 0 Master Clock ARM Request (32-bit) @0 @+4 @ +8 @+12 @+16 @+20 @+24 @+28 @+32 anticipation of @16-31 Flash Access Buffer 0 (128 bits) Buffer 1 (128 bits) Data to ARM XXX Bytes 0–15 Bytes 16–31 XXX Bytes 32–47 Bytes 32–47 Bytes 0–15 XXX Bytes 0–3 Bytes 16–31 Bytes 4–7 Bytes 8–11 Bytes 12–15 Bytes 16–19 Bytes 20–23 Bytes 24–27 Bytes 28–31 Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 379 Figure 21-4. Code Read Optimization for FWS = 3 Master Clock ARM Request (32-bit) @+4 @+8 @+12 @+16 @+20 @+24 @+28 @+32 @+36 @+40 @+44 @+48 @+52 @0 wait 3 cycles before 128-bit data is stable @0/4/8/12 are ready Flash Access anticipation of @32-47 anticipation of @16-31 @16/20/24/28 are ready Bytes 0–15 Bytes 16–31 Buffer 0 (128 bits) Bytes 32–47 Bytes 0–15 Buffer 1 (128 bits) Bytes 32–47 Bytes 16–31 XXX XXX Data to ARM 0–3 Bytes 48–6 4–7 8–11 12–15 16–19 20–23 24–27 28–31 32–35 36–39 40–43 44–47 48–51 Note: When FWS is between 1 and 3, in case of sequential reads, the first access takes (FWS + 1) cycles. The following accesses take only one cycle. 21.4.2.3 Code Loop Optimization Code loop optimization is enabled when the bit EEFC_FMR.CLOE is set to 1. When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken and becomes inefficient. In this case, the loop code read optimization takes over from the sequential code read optimization to prevent the insertion of wait states. The loop code read optimization is enabled by default. In EEFC_FMR, if the bit CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized. When code loop optimization is enabled, if inner loop body instructions L0 to Ln are positioned from the 128-bit Flash memory cell Mb0 to the memory cell Mp1, after recognition of a first backward branch, the first two Flash memory cells Mb0 and Mb1 targeted by this branch are cached for fast access from the processor at the next loop iteration. Then by combining the sequential prefetch (described in Section 21.4.2.2 ”Code Read Optimization”) through the loop body with the fast read access to the loop entry cache, the entire loop can be iterated with no wait state. Figure 21-5 illustrates code loop optimization. Figure 21-5. Code Loop Optimization Backward address jump Flash Memory 128-bit words Mb0 B0 B1 Mb1 Mp0 L0 L1 L2 L3 L4 L5 Ln-5 Ln-4 Ln-3 Ln-2 Ln-1 Ln B2 B3 B4 B5 B6 B7 P0 P1 P2 P3 P4 P5 2x128-bit loop entry cache 380 Mp1 2x128-bit prefetch buffer Mb0 Branch Cache 0 L0 Loop Entry instruction Mp0 Prefetch Buffer 0 Mb1 Branch Cache 1 Ln Loop End instruction Mp1 Prefetch Buffer 1 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 P6 P7 21.4.2.4 Data Read Optimization The organization of the Flash in 128 bits or 64 bits is associated with two 128-bit or 64-bit prefetch buffers and one 128-bit or 64-bit data read buffer, thus providing maximum system performance. This buffer is added in order to store the requested data plus all the data contained in the 128-bit or 64-bit aligned data. This speeds up sequential data reads if, for example, FWS is equal to 1 (see Figure 21-6). The data read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set to 1, this buffer is disabled and the data read is no longer optimized. Note: Figure 21-6. No consecutive data read accesses are mandatory to benefit from this optimization. Data Read Optimization for FWS = 1 Master Clock ARM Request (32-bit) @Byte 0 @4 Flash Access XXX @ 12 @ 16 Bytes 0–15 XXX @ 20 @ 24 @ 28 4–7 8–11 @ 36 Bytes 32–47 Bytes 0–15 Bytes 0–3 @ 32 Bytes 16–31 XXX Buffer (128 bits) Data to ARM @8 Bytes 16–31 12–15 16–19 20–23 24–27 28–31 32–35 21.4.3 Flash Commands The EEFC offers a set of commands to manage programming the Flash memory, locking and unlocking lock regions, consecutive programming, locking and full Flash erasing, etc. The commands are listed in the following table. Table 21-2. Set of Commands Command Value Mnemonic Get Flash descriptor 0x00 GETD Write page 0x01 WP Write page and lock 0x02 WPL Erase page and write page 0x03 EWP Erase page and write page then lock 0x04 EWPL Erase all 0x05 EA Erase pages 0x07 EPA Set lock bit 0x08 SLB Clear lock bit 0x09 CLB Get lock bit 0x0A GLB Set GPNVM bit 0x0B SGPB Clear GPNVM bit 0x0C CGPB SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 381 Table 21-2. Set of Commands (Continued) Command Value Mnemonic Get GPNVM bit 0x0D GGPB Start read unique identifier 0x0E STUI Stop read unique identifier 0x0F SPUI Get CALIB bit 0x10 GCALB Erase sector 0x11 ES Write user signature 0x12 WUS Erase user signature 0x13 EUS Start read user signature 0x14 STUS Stop read user signature 0x15 SPUS In order to execute one of these commands, select the required command using the FCMD field in the Flash Command register (EEFC_FCR). As soon as EEFC_FCR is written, the FRDY flag and the FVALUE field in the Flash Result register (EEFC_FRR) are automatically cleared. Once the current command has completed, the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. (Note that this is true for all commands except for the STUI command. The FRDY flag is not set when the STUI command has completed.) All the commands are protected by the same keyword, which must be written in the eight highest bits of EEFC_FCR. Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the whole memory plane, but the FCMDE flag is set in the Flash Status register (EEFC_FSR). This flag is automatically cleared by a read access to EEFC_FSR. When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the FLOCKE flag is set in EEFC_FSR. This flag is automatically cleared by a read access to EEFC_FSR. 382 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 21-7. Command State Chart Read Status: EEFC_FSR No Check if FRDY flag Set Yes Write FCMD and PAGENB in Flash Command Register Read Status: EEFC_FSR No Check if FRDY flag Set Yes Check if FLOCKE flag Set Yes Locking region violation No Check if FCMDE flag Set Yes Bad keyword violation No Command Successful 21.4.3.1 Get Flash Descriptor Command This command provides the system with information on the Flash organization. The system can take full advantage of this information. For instance, a device could be replaced by one with more Flash capacity, and so the software is able to adapt itself to the new configuration. To get the embedded Flash descriptor, the application writes the GETD command in EEFC_FCR. The first word of the descriptor can be read by the software application in EEFC_FRR as soon as the FRDY flag in EEFC_FSR rises. The next reads of EEFC_FRR provide the following word of the descriptor. If extra read operations to EEFC_FRR are done after the last word of the descriptor has been returned, the EEFC_FRR value is 0 until the next valid command. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 383 Table 21-3. Flash Descriptor Definition Symbol Word Index Description FL_ID 0 Flash interface description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes FL_NB_PLANE 3 Number of planes FL_PLANE[0] 4 Number of bytes in the plane FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is used to prevent write or erase operations in the lock region. FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region 21.4.3.2 Write Commands Several commands are used to program the Flash. Only 0 values can be programmed using Flash technology; 1 is the erased value. In order to program words in a page, the page must first be erased. Commands are available to erase the full memory plane or a given number of pages. With the EWP and EWPL commands, a page erase is done automatically before a page programming. After programming, the page (the entire lock region) can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands. Data to be programmed in the Flash must be written in an internal latch buffer before writing the programming command in EEFC_FCR. Data can be written at their final destination address, as the latch buffer is mapped into the Flash memory address space and wraps around within this Flash address space. Byte and half-word AHB accesses to the latch buffer are not allowed. Only 32-bit word accesses are supported. 32-bit words must be written continuously, in either ascending or descending order. Writing the latch buffer in a random order is not permitted. This prevents mapping a C-code structure to the latch buffer and accessing the data of the structure in any order. It is instead recommended to fill in a C-code structure in SRAM and copy it in the latch buffer in a continuous order. Write operations in the latch buffer are performed with the number of wait states programmed for reading the Flash. The latch buffer is automatically re-initialized, i.e., written with logical 1, after execution of each programming command. The programming sequence is the following: 1. Write the data to be programmed in the latch buffer. 2. Write the programming command in EEFC_FCR. This automatically clears the bit EEFC_FSR.FRDY. 3. When Flash programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the EEFC is activated. Three errors can be detected in EEFC_FSR after a programming sequence: Command Error: A bad keyword has been written in EEFC_FCR. Lock Error: The page to be programmed belongs to a locked region. A command must be run previously to unlock the corresponding region. Flash Error: When programming is completed, the WriteVerify test of the Flash memory has failed. Only one page can be programmed at a time. It is possible to program all the bits of a page (full page programming) or only some of the bits of the page (partial page programming). 384 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Depending on the number of bits to be programmed within the page, the EEFC adapts the write operations required to program the Flash. When a ‘Write Page’ (WP) command is issued, the EEFC starts the programming sequence and all the bits written at 0 in the latch buffer are cleared in the Flash memory array. During programming, i.e., until EEFC_FSR.FDRY rises, access to the Flash is not allowed. Full Page Programming To program a full page, all the bits of the page must be erased before writing the latch buffer and issuing the WP command. The latch buffer must be written in ascending order, starting from the first address of the page. See Figure 21-8 "Full Page Programming". Partial Page Programming To program only part of a page using the WP command, the following constraints must be respected: Data to be programmed must be contained in integer multiples of 64-bit address-aligned words. 64-bit words can be programmed only if all the corresponding bits in the Flash array are erased (at logical value 1). See Figure 21-9 "Partial Page Programming". Optimized Partial Page Programming The EEFC automatically detects the number of 128-bit words to be programmed. If only one 128-bit aligned word is to be programmed in the Flash array, the process is optimized to reduce the time needed for programming. If several 128-bit words are to be programmed, a standard page programming operation is performed. See Figure 21-10 "Optimized Partial Page Programming". Programming Bytes Individual bytes can be programmed using the Partial page programming mode. In this case, an area of 64 bits must be reserved for each byte. Refer to Figure 21-11 "Programming Bytes in the Flash". SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 385 Figure 21-8. Full Page Programming 32 bits wide 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF 0xX1C FF FF FF FF 0xX14 FF FF FF FF 0xX10 FF FF FF FF FF FF 0xX0C 0xX08 FF FF FE 0xX04 FF FF FF FF 0xX04 FE 0xX00 FF FF FF FF 0xX00 CA FE CA FE CA FE CA FE 0xX1C CA FE CA FE 0xX18 CA FE CA FE 0xX14 CA FE CA FE 0xX10 CA FE CA FE 0xX0C CA FE CA FE CA FE CA CA FE CA address space for Page N Before programming: Unerased page in Flash array 0xX18 0xX08 Step 1: Flash array after page erase DE CA DE CA DE CA DE CA 0xX1C DE CA DE CA 0xX18 DE DE CA CA DE DE CA CA 0xX14 0xX0C DE CA DE CA 0xX0C CA 0xX08 DE CA DE CA 0xX08 DE CA 0xX04 DE CA DE CA 0xX04 DE CA 0xX00 DE CA DE CA 0xX00 DE CA DE CA DE CA DE CA 0xX1C DE CA DE CA 0xX18 DE DE CA CA DE DE CA CA 0xX14 DE CA DE CA DE CA DE DE CA DE CA 0xX10 address space for latch buffer Step 2: Writing a page in the latch buffer 0xX10 Step 3: Page in Flash array after issuing WP command and FRDY=1 386 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 address space for Page N Figure 21-9. Partial Page Programming 32 bits wide 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX1C FF FF FF FF FF FF FF FF 0xX14 FF FF FF FF FF FF FF FF 0xX10 FF FF FF FF FF FF FF FF CA CA FE FE CA CA FE FE 0xX0C FF FF FF FF FF FF FF FF 0xX04 FF FF FF FF FF FF FF FF 0xX00 address space for Page N Step 1: Flash array after page erase 0xX18 0xX08 Step 2: Flash array after programming 64-bit at address 0xX08 (write latch buffer + WP) 32 bits wide 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF CA CA FE FE CA CA FE FE FF FF FF FF 0xX1C CA FE CA FE 0xX1C 0xX18 CA FE CA FE 0xX18 FF 0xX14 CA FE CA FE 0xX14 FF FF 0xX10 CA FE CA FE 0xX10 CA CA FE FE 0xX0C CA FE CA FE 0xX0C 0xX08 CA FE CA FE 0xX08 FE FE 0xX04 CA FE CA FE 0xX04 0xX00 CA FE CA FE 0xX00 CA CA Step 3: Flash array after programming Step 4: Flash array after programming a second 64-bit data at address 0xX00 a 128-bit data word at address 0xX10 (write latch buffer + WP) (write latch buffer + WP) SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 387 Figure 21-10. Optimized Partial Page Programming 32 bits wide 4 x 32 bits 4 x 32 bits 32 bits wide FF FF FF FF FF FF 0xX1C 0xX18 FF FF FF 0xX14 FF FF FF FF 0xX14 FF FF 0xX10 FF FF FF FF 0xX10 FF FF FF 0xX0C CA FE FF FF 0xX0C FF FF FF FF 0xX08 FF FF CA FE 0xX08 CA FE CA FE 0xX04 FF FF FF FF 0xX04 CA FE CA FE 0xX00 FF FF FF FF 0xX00 FF FF FF FF FF FF FF FF 0xX1C FF FF FF FF FF FF 0xX18 Case 1: 2 x 32 bits modified, not crossing 128-bit boundary Case 2: 2 x 32 bits modified, not crossing 128-bit boundary User programs WP, Flash Controller sends Write Word User programs WP, Flash Controller sends Write Word => Only 1 word programmed => programming period reduced => Only 1 word programmed => programming period reduced 32 bits wide 4 x 32 bits 4 x 32 bits 32 bits wide FF FF FF FF FF FF 0xX1C 0xX18 FF FF FE 0xX14 FF FF FF FF 0xX14 CA CA FE FE 0xX10 FF FF FF FF 0xX10 0xX0C CA FE CA FE 0xX0C FE CA FE 0xX08 CA FE CA FE 0xX08 FF FF FF FF 0xX04 CA FE CA FE 0xX04 FF FF FF FF 0xX00 CA FE CA FE 0xX00 FF FF FF FF 0xX1C FF FF FF FF CA FE CA CA CA FE FE CA 0xX18 Case 3: 4 x 32 bits modified across 128-bit boundary Case 4: 4 x 32 bits modified, not crossing 128-bit boundary User programs WP, Flash Controller sends WP User programs WP, Flash Controller sends Write Word => Whole page programmed => Only 1 word programmed => programming period reduced 388 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 21-11. Programming Bytes in the Flash 32 bits wide 4 x 32 bits = 1 Flash word 4 x 32 bits = 1 Flash word 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX1C FF FF FF FF FF FF FF FF address space 0xX14 for Page N 0xX10 FF FF FF FF 0xX14 FF FF FF FF 0xX10 FF FF FF FF 0xX0C xx xx xx xx 0xX0C FF FF FF FF 0xX08 xx xx xx 55 0xX08 xx xx xx xx 0xX04 xx xx xx xx 0xX04 xx xx xx AA 0xX00 xx xx xx AA 0xX00 0xX1C 0xX18 0xX18 Step 1: Flash array after programming first byte (0xAA) Step 2: Flash array after programming second byte (0x55) 64-bit used at address 0xX00 (write latch buffer + WP) 64-bit used at address 0xX08 (write latch buffer + WP) Note: The byte location shown here is for example only, it can be any byte location within a 64-bit word. 21.4.3.3 Erase Commands Erase commands are allowed only on unlocked regions. Depending on the Flash memory, several commands can be used to erase the Flash: Erase All Memory (EA): All memory is erased. The processor must not fetch code from the Flash memory. Erase Pages (EPA): 8 or 16 pages are erased in the Flash sector selected. The first page to be erased is specified in the FARG[15:2] field of the EEFC_FCR. The first page number must be a multiple of 8, 16 or 32 depending on the number of pages to erase at the same time. Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory. EEFC_FCR.FARG must be set with a page number that is in the sector to be erased. Note: If one subsector is locked within the first sector, the Erase Sector (ES) command cannot be processed on non-locked subsectors of the first sector. All the lock bits of the first sector must be cleared prior to issuing an ES command on the first sector. After the ES command has been issued, the first sector lock bits must be reverted to the state before clearing them. If the processor is fetching code from the Flash memory while the EPA or ES command is being executed, the processor accesses are stalled until the EPA command is completed. To avoid stalling the processor, the code can be run out of internal SRAM. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 389 The erase sequence is the following: 1. Erase starts as soon as one of the erase commands and the FARG field are written in EEFC_FCR. ̶ For the EPA command, the two lowest bits of the FARG field define the number of pages to be erased (FARG[1:0]): Table 21-4. EEFC_FCR.FARG Field for EPA Command FARG[1:0] 2. Number of pages to be erased with EPA command 0 4 pages (only valid for small 8 KB sectors) 1 8 pages 2 16 pages 3 32 pages (not valid for small 8 KB sectors) When erasing is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Three errors can be detected in EEFC_FSR after an erasing sequence: Command Error: A bad keyword has been written in EEFC_FCR. Lock Error: At least one page to be erased belongs to a locked region. The erase command has been refused, no page has been erased. A command must be run previously to unlock the corresponding region. Flash Error: At the end of the erase period, the EraseVerify test of the Flash memory has failed. 21.4.3.4 Lock Bit Protection Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages. The lock sequence is the following: 1. Execute the ‘Set Lock Bit’ command by writing EEFC_FCR.FCMD with the SLB command and EEFC_FCR.FARG with a page number to be protected. 2. When the locking completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. 3. The result of the SLB command can be checked running a ‘Get Lock Bit’ (GLB) command. Note: The value of the FARG argument passed together with SLB command must not exceed the higher lock bit index available in the product. Two errors can be detected in EEFC_FSR after a programming sequence: Command Error: A bad keyword has been written in EEFC_FCR. Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear lock bits previously set. After the lock bits are cleared, the locked region can be erased or programmed. The unlock sequence is the following: 1. Execute the ‘Clear Lock Bit’ command by writing EEFC_FCR.FCMD with the CLB command and EEFC_FCR.FARG with a page number to be unprotected. 2. Note: When the unlock completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. The value of the FARG argument passed together with CLB command must not exceed the higher lock bit index available in the product. Two errors can be detected in EEFC_FSR after a programming sequence: 390 Command Error: A bad keyword has been written in EEFC_FCR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. The status of lock bits can be returned by the EEFC. The ‘Get Lock Bit’ sequence is the following: 1. Execute the ‘Get Lock Bit’ command by writing EEFC_FCR.FCMD with the GLB command. Field EEFC_FCR.FARG is meaningless. 2. Lock bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. For example, if the third bit of the first word read in EEFC_FRR is set, the third lock region is locked. Two errors can be detected in EEFC_FSR after a programming sequence: Command Error: A bad keyword has been written in EEFC_FCR. Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. Note: 21.4.3.5 Access to the Flash in read is permitted when a ‘Set Lock Bit’, ‘Clear Lock Bit’ or ‘Get Lock Bit’ command is executed. GPNVM Bit GPNVM bits do not interfere with the embedded Flash memory plane. For more details, refer to the section “Memories” of this datasheet. The ‘Set GPNVM Bit’ sequence is the following: 1. Execute the ‘Set GPNVM Bit’ command by writing EEFC_FCR.FCMD with the SGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be set. 2. When the GPNVM bit is set, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. 3. The result of the SGPB command can be checked by running a ‘Get GPNVM Bit’ (GGPB) command. Note: The value of the FARG argument passed together with SGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8. Two errors can be detected in EEFC_FSR after a programming sequence: Command Error: A bad keyword has been written in EEFC_FCR. Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear GPNVM bits previously set. The ‘Clear GPNVM Bit’ sequence is the following: 1. Execute the ‘Clear GPNVM Bit’ command by writing EEFC_FCR.FCMD with the CGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be cleared. 2. Note: When the clear completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. The value of the FARG argument passed together with CGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8. Two errors can be detected in EEFC_FSR after a programming sequence: Command Error: A bad keyword has been written in EEFC_FCR. Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 391 The status of GPNVM bits can be returned by the EEFC. The sequence is the following: 1. Execute the ‘Get GPNVM Bit’ command by writing EEFC_FCR.FCMD with the GGPB command. Field EEFC_FCR.FARG is meaningless. 2. GPNVM bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. For example, if the third bit of the first word read in EEFC_FRR is set, the third GPNVM bit is active. One error can be detected in EEFC_FSR after a programming sequence: Command Error: A bad keyword has been written in EEFC_FCR. Note: 21.4.3.6 Access to the Flash in read is permitted when a ‘Set GPNVM Bit’, ‘Clear GPNVM Bit’ or ‘Get GPNVM Bit’ command is executed. Calibration Bit Calibration bits do not interfere with the embedded Flash memory plane. The calibration bits cannot be modified. The status of calibration bits are returned by the EEFC. The sequence is the following: 1. Execute the ‘Get CALIB Bit’ command by writing EEFC_FCR.FCMD with the GCALB command. Field EEFC_FCR.FARG is meaningless. 2. Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to the first 32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. The 8/16/24 MHz fast RC oscillator is calibrated in production. This calibration can be read through the GCALB command. The following table shows the bit implementation for each frequency. Table 21-5. Calibration Bit Indexes RC Calibration Frequency EEFC_FRR Bits 16 MHz output [28–22] 24 MHz output [38–32] The RC calibration for the 8 MHz is set to ‘1000000’. 21.4.3.7 Security Bit Protection When the security bit is enabled, access to the Flash through the SWD interface or through the Fast Flash Programming interface is forbidden. This ensures the confidentiality of the code programmed in the Flash. The security bit is GPNVM0. Disabling the security bit can only be achieved by asserting the ERASE pin at ‘1’, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted. 21.4.3.8 Unique Identifier Area Each device is programmed with a 2*512-bytes unique identifier area . See Figure 21-1 "Flash Memory Areas". The sequence to read the unique identifier area is the following: 1. Execute the ‘Start Read Unique Identifier’ command by writing EEFC_FCR.FCMD with the STUI command. Field EEFC_FCR.FARG is meaningless. 2. 392 Wait until the bit EEFC_FSR.FRDY falls to read the unique identifier area. The unique identifier field is located in the first 128 bits of the Flash memory mapping. The ‘Start Read Unique Identifier’ command reuses some addresses of the memory plane for code, but the unique identifier area is physically different from the memory plane for code. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 3. To stop reading the unique identifier area, execute the ‘Stop Read Unique Identifier’ command by writing EEFC_FCR.FCMD with the SPUI command. Field EEFC_FCR.FARG is meaningless. 4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note that during the sequence, the software cannot be fetched from the Flash. 21.4.3.9 User Signature Area Each product contains a user signature area of 512-bytes. It can be used for storage. Read, write and erase of this area is allowed. See Figure 21-1 "Flash Memory Areas". The sequence to read the user signature area is the following: 1. Execute the ‘Start Read User Signature’ command by writing EEFC_FCR.FCMD with the STUS command. Field EEFC_FCR.FARG is meaningless. 2. Wait until the bit EEFC_FSR.FRDY falls to read the user signature area. The user signature area is located in the first 512 bytes of the Flash memory mapping. The ‘Start Read User Signature’ command reuses some addresses of the memory plane but the user signature area is physically different from the memory plane 3. To stop reading the user signature area, execute the ‘Stop Read User Signature’ command by writing EEFC_FCR.FCMD with the SPUS command. Field EEFC_FCR.FARG is meaningless. 4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note that during the sequence, the software cannot be fetched from the Flash or from the second plane in case of dual plane. One error can be detected in EEFC_FSR after this sequence: Command Error: A bad keyword has been written in EEFC_FCR. The sequence to write the user signature area is the following: 1. Write the full page, at any page address, within the internal memory area address space. 2. Execute the ‘Write User Signature’ command by writing EEFC_FCR.FCMD with the WUS command. Field EEFC_FCR.FARG is meaningless. 3. When programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence: Command Error: A bad keyword has been written in EEFC_FCR. Flash Error: At the end of the programming, the WriteVerify test of the Flash memory has failed. The sequence to erase the user signature area is the following: 1. Execute the ‘Erase User Signature’ command by writing EEFC_FCR.FCMD with the EUS command. Field EEFC_FCR.FARG is meaningless. 2. When programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence: Command Error: A bad keyword has been written in EEFC_FCR. Flash Error: At the end of the programming, the EraseVerify test of the Flash memory has failed. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 393 21.5 Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0800. Table 21-6. Register Mapping Offset Register Name Access Reset State 0x00 EEFC Flash Mode Register EEFC_FMR Read/Write 0x0400_0000 0x04 EEFC Flash Command Register EEFC_FCR Write-only – 0x08 EEFC Flash Status Register EEFC_FSR Read-only 0x0000_0001 0x0C EEFC Flash Result Register EEFC_FRR Read-only 0x0 0x10–0x14 Reserved – – – 0x18–0xE4 Reserved – – – 394 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 21.5.1 EEFC Flash Mode Register Name: EEFC_FMR Address: 0x400E0A00 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – CLOE – FAM 23 22 21 20 19 18 17 16 – – – – – – – SCOD 15 14 13 12 11 10 9 8 – – – – FWS 7 6 5 4 3 2 1 0 – – – – – – – FRDY • FRDY: Flash Ready Interrupt Enable 0: Flash ready does not generate an interrupt. 1: Flash ready (to accept a new command) generates an interrupt. • FWS: Flash Wait State This field defines the number of wait states for read and write operations: FWS = Number of cycles for Read/Write operations - 1 • SCOD: Sequential Code Optimization Disable 0: The sequential code optimization is enabled. 1: The sequential code optimization is disabled. No Flash read should be done during change of this field. • FAM: Flash Access Mode 0: 128-bit access in Read mode only, to enhance access speed. 1: 64-bit access in Read mode only, to enhance power consumption. No Flash read should be done during change of this field. • CLOE: Code Loop Optimization Enable 0: The opcode loop optimization is disabled. 1: The opcode loop optimization is enabled. No Flash read should be done during change of this field. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 395 21.5.2 EEFC Flash Command Register Name: EEFC_FCR Address: 0x400E0A04 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FKEY 23 22 21 20 FARG 15 14 13 12 FARG 7 6 5 4 FCMD • FCMD: Flash Command Value Name Description 0x00 GETD Get Flash descriptor 0x01 WP Write page 0x02 WPL Write page and lock 0x03 EWP Erase page and write page 0x04 EWPL Erase page and write page then lock 0x05 EA Erase all 0x07 EPA Erase pages 0x08 SLB Set lock bit 0x09 CLB Clear lock bit 0x0A GLB Get lock bit 0x0B SGPB Set GPNVM bit 0x0C CGPB Clear GPNVM bit 0x0D GGPB Get GPNVM bit 0x0E STUI Start read unique identifier 0x0F SPUI Stop read unique identifier 0x10 GCALB Get CALIB bit 0x11 ES Erase sector 0x12 WUS Write user signature 0x13 EUS Erase user signature 0x14 STUS Start read user signature 0x15 SPUS Stop read user signature 396 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • FARG: Flash Command Argument GETD, GLB, GGPB, STUI, SPUI, GCALB, WUS, EUS, STUS, SPUS, EA Commands requiring no argument, including Erase all command FARG is meaningless, must be written with 0 ES Erase sector command FARG must be written with any page number within the sector to be erased FARG[1:0] defines the number of pages to be erased The start page must be written in FARG[15:2]. FARG[1:0] = 0: Four pages to be erased. FARG[15:2] = Page_Number / 4 EPA Erase pages command FARG[1:0] = 1: Eight pages to be erased. FARG[15:3] = Page_Number / 8, FARG[2]=0 FARG[1:0] = 2: Sixteen pages to be erased. FARG[15:4] = Page_Number / 16, FARG[3:2]=0 FARG[1:0] = 3: Thirty-two pages to be erased. FARG[15:5] = Page_Number / 32, FARG[4:2]=0 Refer to Table 21-4 “EEFC_FCR.FARG Field for EPA Command”. WP, WPL, EWP, EWPL Programming commands FARG must be written with the page number to be programmed SLB, CLB Lock bit commands FARG defines the page number to be locked or unlocked SGPB, CGPB GPNVM commands FARG defines the GPNVM number to be programmed • FKEY: Flash Writing Protection Key Value Name 0x5A PASSWD Description The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 397 21.5.3 EEFC Flash Status Register Name: EEFC_FSR Address: 0x400E0A08 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – FLERR FLOCKE FCMDE FRDY • FRDY: Flash Ready Status (cleared when Flash is busy) 0: The EEFC is busy. 1: The EEFC is ready to start a new command. When set, this flag triggers an interrupt if the FRDY flag is set in EEFC_FMR. This flag is automatically cleared when the EEFC is busy. • FCMDE: Flash Command Error Status (cleared on read or by writing EEFC_FCR) 0: No invalid commands and no bad keywords were written in EEFC_FMR. 1: An invalid command and/or a bad keyword was/were written in EEFC_FMR. • FLOCKE: Flash Lock Error Status (cleared on read) 0: No programming/erase of at least one locked region has happened since the last read of EEFC_FSR. 1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR. This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written. • FLERR: Flash Error Status (cleared when a programming operation starts) 0: No Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has passed). 1: A Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed). 398 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 21.5.4 EEFC Flash Result Register Name: EEFC_FRR Address: 0x400E0A0C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FVALUE 23 22 21 20 FVALUE 15 14 13 12 FVALUE 7 6 5 4 FVALUE • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, the next resulting value is accessible at the next register read. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 399 22. Bus Matrix (MATRIX) 22.1 Description The Bus Matrix (MATRIX) implements a multi-layer AHB that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing overall bandwidth. The Bus Matrix interconnects three AHB masters to four AHB slaves. The normal latency to connect a master to a slave is one cycle. The exception is the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface also provides a System I/O Configuration user interface with registers that support application-specific features. 22.2 Embedded Characteristics One Decoder for Each Master Support for Long Bursts of 32, 64 and 128 Beats and Up to the 256-beat Word Burst AHB Limit Enhanced Programmable Mixed Arbitration for Each Slave 400 ̶ Round-robin ̶ Fixed Priority ̶ Latency Quality of Service Programmable Default Master for Each Slave ̶ No Default Master ̶ Last Accessed Default Master ̶ Fixed Default Master Deterministic Maximum Access Latency for Masters Zero or One Cycle Arbitration Latency for the First Access of a Burst Bus Lock Forwarding to Slaves Master Number Forwarding to Slaves Register Write Protection SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 22.3 Master/Slave Management 22.3.1 Matrix Masters The Bus Matrix manages three masters. Each master can perform an access concurrently with others to an available slave. Each master has its own specifically-defined decoder. In order to simplify the addressing, all the masters have the same decoding. Table 22-1. List of Bus Matrix Masters Master No. Name 0 Processor Instruction/Data Bus 1 Processor System Bus 2 Peripheral DMA Controller (PDC) 22.3.2 Matrix Slaves The Bus Matrix manages four slaves. Each slave has its own arbiter, providing a different arbitration per slave Table 22-2. List of Bus Matrix Slaves Slave No. Name 0 Internal SRAM 1 Internal ROM 2 Internal Flash 3 Peripheral Bridge 22.3.3 Master to Slave Access Table 22-3 gives valid paths for master to slave access. The paths shown as “–” are forbidden or not wired, e.g., access from the processor I/D bus to internal SRAM. Table 22-3. Master to Slave Access Masters Slaves 22.4 0 1 2 Processor I/D Bus Processor System Bus PDC 0 Internal SRAM – X X 1 Internal ROM X – X 2 Internal Flash X – X 3 Peripheral Bridge – X X Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. Depending on the product, each memory area may be assigned to several slaves. Thus it is possible to boot at the same address while using different AHB slaves. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 401 22.5 Special Bus Granting Techniques The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters, reducing latency at the first access of a burst or single transfer. The bus granting technique sets a default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: No default master Last access master Fixed default master 22.5.1 No Default Master At the end of the current access, if no other request is pending, the slave is disconnected from all masters. This is suitable when the device is in low-power mode. 22.5.2 Last Access Master At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. 22.5.3 Fixed Default Master At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike the last access master, the fixed master does not change unless the user modifies it by software (field FIXED_DEFMSTR of the related MATRIX_SCFG). To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration registers (MATRIX_SCFGx), one for each slave, used to set a default master for each slave. MATRIX_SCFGx contain the fields DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master) whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master, provided that DEFMSTR_TYPE is set to fixed default master. Refer to the Section 22.9 “Bus Matrix (MATRIX) User Interface”. 22.6 Arbitration The Bus Matrix provides an arbitration technique that reduces latency when conflicting cases occur; for example, when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, so that each slave can be arbitrated differently. The Bus Matrix provides the user with two types of arbitration for each slave: Round-robin arbitration (default) Fixed priority arbitration Each algorithm may be complemented by selecting a default master configuration for each slave. When a re-arbitration must be done, specific conditions apply. See Section 22.6.1 “Arbitration Rules”. 22.6.1 Arbitration Rules Each arbiter has the ability to arbitrate between requests from two or more masters. To avoid burst breaking and to provide the maximum throughput for slave interfaces, arbitration should take place during the following cycles: 402 Idle cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it. Single cycles: When a slave is currently doing a single access. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For a defined burst length, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See Section 22.6.1.1 “Undefined Length Burst Arbitration”. Slot cycle limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. See Section 22.6.1.2 “Slot Cycle Limit Arbitration”. 22.6.1.1 Undefined Length Burst Arbitration In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the following Undefined Length Burst Type (ULBT) possibilities: Unlimited: no predetermined end of burst is generated. This value enables 1 Kbyte burst lengths. 4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer. 8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer. 16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR transfer. This selection is made through the ULBT field of the Master Configuration registers (MATRIX_MCFG). 22.6.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related MATRIX_SCFG and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half-word or word transfer. 22.6.1.3 Round-Robin Arbitration The Bus Matrix arbiters use the round-robin algorithm to dispatch the requests from different masters to the same slave. If two or more masters make a request at the same time, the master with the lowest number is serviced first. The others are then serviced in a round-robin manner. Three round-robin algorithms are implemented: Round-robin arbitration without default master Round-robin arbitration with last access master Round-robin arbitration with fixed default master Round-robin arbitration without default master Round-robin arbitration without default master is the main algorithm used by Bus Matrix arbiters. Using this algorithm, the Bus Matrix dispatches requests from different masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts. Round-robin arbitration with last access master Round-robin arbitration with last access master is a biased round-robin algorithm used by Bus Matrix arbiters to remove one latency cycle for the last master that accessed the slave. At the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs the access. Other nonprivileged masters still get one latency cycle if they attempt to access the same slave. This technique can be used for masters that mainly perform single accesses. Round-robin arbitration with fixed default master SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 403 Round-robin arbitration with fixed default master is an algorithm used by the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master. Every request attempted by this fixed default master will not cause any latency whereas other non-privileged masters will still get one latency cycle. This technique can be used for masters that mainly perform single accesses. 22.6.1.4 Fixed Priority Arbitration The fixed priority algorithm is used by the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If requests from two or more masters are active at the same time, the master with the highest priority number is serviced first. If requests from two or more master with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master may be defined through the Priority registers for slaves (MATRIX_PRAS and MATRIX_PRBS). 22.7 System I/O Configuration The System I/O Configuration register (CCFG_SYSIO) configures I/O lines in system I/O mode (such as JTAG, ERASE, etc.) or as general-purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller has no effect. However, the direction (input or output), pull-up, pull-down and other mode control is still managed by the PIO controller. 22.8 Register Write Protection To prevent any single software error from corrupting MATRIX behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the “Bus Matrix Write Protection Mode Register” (MATRIX_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the “Bus Matrix Write Protection Status Register” (MATRIX_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS flag is reset by writing the MATRIX_WPMR with the appropriate access key WPKEY. The following registers can be write-protected: 404 “Bus Matrix Master Configuration Registers” “Bus Matrix Slave Configuration Registers” “Bus Matrix Priority Registers For Slaves” “System I/O Configuration Register” SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 22.9 Bus Matrix (MATRIX) User Interface Table 22-4. Register Mapping Offset Register Name Access Reset 0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read/Write 0x00000000 0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read/Write 0x00000000 0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read/Writ 0x00000000 Reserved – – – 0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read/Write 0x00010010 0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read/Write 0x00050010 0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read/Write 0x00000010 0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read/Write 0x00000010 Reserved – – – 0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read/Write 0x00000000 0x0084 Reserved – – – 0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read/Write 0x00000000 0x008C Reserved – – – 0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read/Write 0x00000000 0x0094 Reserved – – – 0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read/Write 0x00000000 0x009C Reserved – – – 0x0110 Reserved – – 0x22222224 (1) 0x0114 System I/O Configuration Register CCFG_SYSIO Read/Write 0x0000_0000 Reserved – – – 0x1E4 Write Protection Mode Register MATRIX_WPMR Read/Write 0x0 0x1E8 Write Protection Status Register MATRIX_WPSR Read-only 0x0 Reserved – – – 0x000C–0x003C 0x0050–0x007C 0x0118–0x01E0 0x01EC–0x01FC Note: 1. This default reset value must not be modified. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 405 22.9.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFGx [x = 0..2] Address: 0x400E0200 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 2 1 0 7 6 5 4 3 – – – – – ULBT This register can only be written if the WPEN bit is cleared in the Bus Matrix Write Protection Mode Register. • ULBT: Undefined Length Burst Type Value Name Description 0 UNLIMITED No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 1 SINGLE The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. 2 4_BEAT The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. 3 8_BEAT The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 4 16_BEAT The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 406 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 22.9.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFGx [x = 0..3] Address: 0x400E0240 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 FIXED_DEFMSTR DEFMSTR_TYPE SLOT_CYCLE This register can only be written if the WPEN bit is cleared in the Bus Matrix Write Protection Mode Register. • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place to let another master access this slave. If another master is requesting the slave bus, then the current master burst is broken. If SLOT_CYCLE = 0, the slot cycle limit feature is disabled and bursts always complete unless broken according to the ULBT. This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access. This limit must not be too small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice. In most cases, this feature is not needed and should be disabled for power saving. See Section 22.6.1.2 “Slot Cycle Limit Arbitration” for details. • DEFMSTR_TYPE: Default Master Type Value 0 1 Name NO_DEFAUL T LAST Description At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in having a one cycle latency for the first access of a burst transfer or for a single access. At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. This results in not having the one cycle latency when the last master tries to access the slave again. 2 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master tries to access the slave again. • FIXED_DEFMSTR: Fixed Default Master The number of the default master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 407 22.9.3 Bus Matrix Priority Registers For Slaves Name: MATRIX_PRAS0..MATRIX_PRAS3 Address: 0x400E0280 [0], 0x400E0288 [1], 0x400E0290 [2], 0x400E0298 [3] Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – 7 6 – – M3PR 5 4 M1PR 3 2 – – M2PR 1 0 M0PR This register can only be written if the WPEN bit is cleared in the Bus Matrix Write Protection Mode Register. • MxPR: Master x Priority Fixed priority of master x to access the selected slave. The higher the number, the higher the priority. 408 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 22.9.4 System I/O Configuration Register Name: CCFG_SYSIO Address: 0x400E0314 Access Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – SYSIO12 – – – – 7 6 5 4 3 2 1 0 SYSIO7 SYSIO6 SYSIO5 SYSIO4 – – – – This register can only be written if the WPEN bit is cleared in the Bus Matrix Write Protection Mode Register. • SYSIO4: PB4 or TDI Assignment 0: TDI function selected. 1: PB4 function selected. • SYSIO5: PB5 or TDO/TRACESWO Assignment 0: TDO/TRACESWO function selected. 1: PB5 function selected. • SYSIO6: PB6 or TMS/SWDIO Assignment 0: TMS/SWDIO function selected. 1: PB6 function selected. • SYSIO7: PB7 or TCK/SWCLK Assignment 0: TCK/SWCLK function selected. 1: PB7 function selected. • SYSIO12: PB12 or ERASE Assignment 0: ERASE function selected. 1: PB12 function selected. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 409 22.9.5 Bus Matrix Write Protection Mode Register Name: MATRIX_WPMR Address: 0x400E03E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). See Section 22.8 “Register Write Protection“ for the list of registers that can be write-protected. • WPKEY: Write Protection Key Value Name 0x4D4154 PASSWD 410 Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 22.9.6 Bus Matrix Write Protection Status Register Name: MATRIX_WPSR Address: 0x400E03E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last write of the MATRIX_WPMR. 1: A write protection violation has occurred since the last write of the MATRIX_WPMR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 411 23. Peripheral DMA Controller (PDC) 23.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the target memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user interface of mono-directional channels (receive-only or transmit-only) contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for the current transfer and one set (pointer, counter) for the next transfer. The bidirectional channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used by the current transmit, next transmit, current receive and next receive. Using the PDC decreases processor overhead by reducing its intervention during the transfer. This lowers significantly the number of clock cycles required for a data transfer, improving microcontroller performance. To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself. 23.2 412 Embedded Characteristics Performs Transfers to/from APB Communication Serial Peripherals Supports Half-duplex and Full-duplex Peripherals Automatic Circular Buffer Mode Transfer Bus Error Report SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 23.3 Block Diagram Figure 23-1. Block Diagram FULL DUPLEX PERIPHERAL PDC THR PDC Channel A RHR PDC Channel B Control Status & Control HALF DUPLEX PERIPHERAL Control THR PDC Channel C RHR Control Status & Control RECEIVE or TRANSMIT PERIPHERAL RHR or THR Control PDC Channel D Status & Control SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 413 23.4 Functional Description 23.4.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full- or half-duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each type are programmed differently: the transmit and receive parts of a full-duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half-duplex peripheral can be programmed at a time. 32-bit pointers define the access location in memory for the current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of the current and next transfers. It is possible, at any moment, to read the number of transfers remaining for each channel. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control register. At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in the peripheral Status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 23.4.3 and to the associated peripheral user interface. The peripheral where a PDC transfer is configured must have its peripheral clock enabled. The peripheral clock must be also enabled to access the PDC register set associated to this peripheral. 23.4.2 Memory Pointers Each full-duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels have 32-bit memory pointers that point to a receive area and to a transmit area, respectively, in the target memory. Each half-duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. These pointers point to transmit or receive data depending on the operating mode of the peripheral. Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes. If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the new address. 23.4.3 Transfer Counters Each channel has two 16-bit counters, one for the current transfer and the one for the next transfer. These counters define the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed by the current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks its next transfer counter. If the value of the next counter is zero, the channel stops transferring data and sets the appropriate flag. If the next counter value is greater than zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer, whereas next pointer/next counter get zero/zero as values. When the Circular buffer mode is activated, the register set {next counter, next pointer} is not reset when the next counter value is copied to the current counter, both next and current registers must be written to the same value. At the end of this transfer, the PDC channel sets the appropriate flags in the Peripheral Status register. The following list gives an overview of how status register flags behave depending on the counters’ values: 414 ENDRX flag is set when the PDC Receive Counter Register (PERIPH_RCR) reaches zero. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 RXBUFF flag is set when both PERIPH_RCR and the PDC Receive Next Counter Register (PERIPH_RNCR) reach zero. ENDTX flag is set when the PDC Transmit Counter Register (PERIPH_TCR) reaches zero. TXBUFE flag is set when both PERIPH_TCR and the PDC Transmit Next Counter Register (PERIPH_TNCR) reach zero. These status flags are described in the Transfer Status Register (PERIPH_PTSR). 23.4.4 Data Transfers The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface. When the peripheral receives external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive Holding register (RHR). The read data are stored in an internal buffer and then written to memory. When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and transfers the data to the Transmit Holding register (THR) of its associated peripheral. The same peripheral sends data depending on its mechanism. In case of invalid memory address resulting from a badly programmed PDC transmit or receive pointer, the bus matrix does not perform the requested access and signals a bus error to the PDC. This transfer bus error drives the PERIPH_PTSR.ERR bit high to flag the error in the Transfer Status Register. 23.4.5 PDC Flags and Peripheral Status Register Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC returns flags to the peripheral. All these flags are only visible in the peripheral’s Status register. Depending on whether the peripheral is half- or full-duplex, the flags belong to either one single channel or two different channels. 23.4.5.1 Receive Transfer End The receive transfer end flag is set when PERIPH_RCR reaches zero and the last data has been transferred to memory. This flag is reset by writing a non-zero value to PERIPH_RCR or PERIPH_RNCR. 23.4.5.2 Transmit Transfer End The transmit transfer end flag is set when PERIPH_TCR reaches zero and the last data has been written to the peripheral THR. This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR. 23.4.5.3 Receive Buffer Full The receive buffer full flag is set when PERIPH_RCR reaches zero, with PERIPH_RNCR also set to zero and the last data transferred to memory. This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR. 23.4.5.4 Transmit Buffer Empty The transmit buffer empty flag is set when PERIPH_TCR reaches zero, with PERIPH_TNCR also set to zero and the last data written to peripheral THR. This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 415 23.5 Peripheral DMA Controller (PDC) User Interface Table 23-1. Offset Register Mapping Register Name (1) Access Reset 0x00 Receive Pointer Register PERIPH _RPR Read/Write 0 0x04 Receive Counter Register PERIPH_RCR Read/Write 0 0x08 Transmit Pointer Register PERIPH_TPR Read/Write 0 0x0C Transmit Counter Register PERIPH_TCR Read/Write 0 0x10 Receive Next Pointer Register PERIPH_RNPR Read/Write 0 0x14 Receive Next Counter Register PERIPH_RNCR Read/Write 0 0x18 Transmit Next Pointer Register PERIPH_TNPR Read/Write 0 0x1C Transmit Next Counter Register PERIPH_TNCR Read/Write 0 0x20 Transfer Control Register PERIPH_PTCR Write-only – 0x24 Transfer Status Register PERIPH_PTSR Read-only 0 Note: 416 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user depending on the function and the desired peripheral. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 23.5.1 Receive Pointer Register Name: PERIPH_RPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 417 23.5.2 Receive Counter Register Name: PERIPH_RCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0: Stops peripheral data transfer to the receiver. 1–65535: Starts peripheral data transfer if the corresponding channel is active. 418 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 23.5.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 419 23.5.4 Transmit Counter Register Name: PERIPH_TCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0: Stops peripheral data transfer to the transmitter. 1–65535: Starts peripheral data transfer if the corresponding channel is active. 420 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 23.5.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains the next receive buffer address. When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 421 23.5.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR • RXNCTR: Receive Next Counter RXNCTR contains the next receive buffer size. When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 422 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 23.5.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains the next transmit buffer address. When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 423 23.5.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR • TXNCTR: Transmit Counter Next TXNCTR contains the next transmit buffer size. When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 424 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 23.5.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 ERRCLR 23 – 22 – 21 – 20 – 19 TXCBDIS 18 TXCBEN 17 RXCBDIS 16 RXCBEN 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set. When a half-duplex peripheral is connected to the PDC, enabling the receiver channel requests automatically disables the transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half-duplex peripheral. • RXTDIS: Receiver Transfer Disable 0: No effect. 1: Disables the PDC receiver channel requests. When a half-duplex peripheral is connected to the PDC, disabling the receiver channel requests also disables the transmitter channel requests. • TXTEN: Transmitter Transfer Enable 0: No effect. 1: Enables the PDC transmitter channel requests. When a half-duplex peripheral is connected to the PDC, it enables the transmitter channel requests only if RXTEN is not set. It is forbidden to set both TXTEN and RXTEN for a half-duplex peripheral. • TXTDIS: Transmitter Transfer Disable 0: No effect. 1: Disables the PDC transmitter channel requests. When a half-duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver channel requests. • RXCBEN: Receiver Circular Buffer Enable 0: No effect. 1: Enables the PDC circular buffer for the receiver operation. • RXCBDIS: Receiver Circular Buffer Disable 0: No effect. 1: Disables the PDC circular buffer for the receiver operation. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 425 • TXCBEN: Transmitter Circular Buffer Enable 0: No effect. 1: Enables the PDC circular buffer for the transmitter operation. • TXCBDIS: Transmitter Circular Buffer Disable 0: No effect. 1: Enables the PDC circular buffer for the transmitter operation. • ERRCLR: Transfer Bus Error Clear 0: No effect. 1: Clears the transfer bus error status bit. 426 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 23.5.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 ERR 23 – 22 – 21 – 20 – 19 – 18 TXCBEN 17 – 16 RXCBEN 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0: PDC receiver channel requests are disabled. 1: PDC receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0: PDC transmitter channel requests are disabled. 1: PDC transmitter channel requests are enabled. • RXCBEN: Receiver Circular Buffer Enable 0: PDC Receiver circular buffer mode is disabled. 1: PDC Receiver circular buffer mode is enabled. • TXCBEN: Transmitter Circular Buffer Enable 0: PDC Transmitter circular buffer mode is disabled. 1: PDC Transmitter circular buffer mode is enabled. • ERR: Transfer Bus Error 0: PDC accesses are performed on valid memory address since the last write of ERRCLR bit in PERIPH_PTCR. 1: PDC transmit or receive pointer (or next pointer) is programmed with an invalid memory address since the last write of ERRCLR bit in PERIPH_PTCR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 427 24. Clock Generator 24.1 Description The Clock Generator user interface is embedded within the Power Management Controller and is described in Section 25.17 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 24.2 Embedded Characteristics The Clock Generator is made up of: A low-power 32768 Hz crystal oscillator with Bypass mode A low-power embedded 32 kHz (typical) RC oscillator A 3 to 20 MHz crystal or ceramic resonator-based oscillator, which can be bypassed. A factory-trimmed embedded RC oscillator. Three output frequencies can be selected: 8/16/24 MHz. By default 8 MHz is selected. A 24 to 48 MHz programmable PLL (input from 32 to 1000 KHz), capable of providing the clock MCK to the processor and to the peripherals. It provides the following clocks: 428 SLCK, the slow clock, which is the only permanent clock within the system. MAINCK is the output of the main clock oscillator selection: either the crystal or ceramic resonator-based oscillator or 8/16/24 MHz RC oscillator. PLLACK is the output of the 24 to 48 MHz programmable PLL (PLLA). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 24.3 Block Diagram Figure 24-1. Clock Generator Block Diagram Clock Generator XTALSEL (Supply Controller) Embedded 32 kHz RC Oscillator 0 Slow Clock SLCK XIN32 XOUT32 32768 Hz Crystal Oscillator 1 CKGR_MOR MOSCSEL Embedded 8/16/24 MHz RC Oscillator 0 Main Clock MAINCK XIN XOUT 3–20 MHz Crystal Oscillator 1 PLLA Status PLLA Clock PLLACK Control Power Management Controller SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 429 24.4 Slow Clock The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as VDDIO is supplied, both the 32768 Hz crystal oscillator and the embedded 32 kHz (typical) RC oscillator are powered up, but only the RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The slow clock is generated either by the 32768 Hz crystal oscillator or by the embedded 32 kHz (typical) RC oscillator. The selection of the slow clock source is made via the XTALSEL bit in the Supply Controller Control Register (SUPC_CR). The OSCSEL bit of the Supply Controller Status Register (SUPC_SR) and the OSCSELS bit of the PMC Status Register (PMC_SR) report which oscillator is selected as the slow clock source. PMC_SR.OSCSELS informs when the switch sequence initiated by a new value written in SUPC_CR.XTALSEL is done. 24.4.1 Embedded 32 kHz (typical) RC Oscillator By default, the embedded 32 kHz (typical) RC oscillator is enabled and selected. The user has to take into account the possible drifts of this oscillator. More details are given in the section “DC Characteristics”. This oscillator is disabled by clearing the SUPC_CR.XTALSEL. 24.4.2 32768 Hz Crystal Oscillator The Clock Generator integrates a low-power 32768 Hz crystal oscillator. To use this oscillator, the XIN32 and XOUT32 pins must be connected to a 32768 Hz crystal. Two external capacitors must be wired as shown in Figure 24-2. More details are given in the section “DC Characteristics”. Note that the user is not obliged to use the 32768 Hz crystal oscillator and can use the 32 kHz (typical) RC oscillator instead. Figure 24-2. Typical 32768-Hz Crystal Oscillator Connection XIN32 XOUT32 GND 32768 Hz Crystal The 32768 Hz crystal oscillator provides a more accurate frequency than the 32 kHz (typical) RC oscillator. To select the 32768 Hz crystal oscillator as the source of the slow clock, the bit SUPC_CR.XTALSEL must be set. This results in a sequence which first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the slow clock oscillator, then enables the 32768 Hz crystal oscillator and then disables the 32 kHz (typical) RC oscillator to save power. The switch of the slow clock source is glitch-free. Reverting to the 32 kHz (typical) RC oscillator is only possible by shutting down the VDDIO power supply. If the user does not need the 32768 Hz crystal oscillator, the XIN32 and XOUT32 pins can be left unconnected since by default the XIN32 and XOUT32 system I/O pins are in PIO input mode with pull-up after reset. The user can also set the 32768 Hz crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user must provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the section “Electrical Characteristics”. To enter Bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) must be set prior to setting SUPC_CR.XTALSEL. 430 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 24.5 Main Clock Figure 24-3 shows the main clock block diagram. Figure 24-3. Main Clock Block Diagram CKGR_MOR MOSCRCEN CKGR_MOR MOSCRCF PMC_SR MOSCRCS Fast RC Oscillator CKGR_MOR PMC_SR MOSCSEL MOSCSELS 0 CKGR_MOR MAINCK Main Clock MOSCXTEN 1 3–20 MHz Crystal or Ceramic Resonator Oscillator XIN XOUT CKGR_MOR MOSCXTST PMC_SR 3–20 MHz Oscillator Counter SLCK Slow Clock MOSCXTS CKGR_MOR MOSCRCEN CKGR_MOR CKGR_MCFR MOSCXTEN RCMEAS CKGR_MOR MOSCSEL CKGR_MCFR MAINCK Main Clock Ref. MAINF Main Clock Frequency Counter CKGR_MCFR MAINFRDY The main clock has two sources: A 8/16/24 MHz RC oscillator with a fast start-up time and that is selected by default to start the system A 3 to 20 MHz crystal or ceramic resonator-based oscillator which can be bypassed 24.5.1 Embedded 8/16/24 MHz RC Oscillator After reset, the 8/16/24 MHz RC oscillator is enabled with the 8 MHz frequency selected. This oscillator is selected as the source of MAINCK. MAINCK is the default clock selected to start the system. The 8/16/24 MHz RC oscillator frequencies are calibrated in production except for the lowest frequency which is not calibrated. Refer to the section “DC Characteristics”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 431 The software can disable or enable the 8/16/24 MHz RC oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator Register (CKGR_MOR). The output frequency of the RC oscillator can be selected among 8/16/24 MHz. The selection is done via the CKGR_MOR.MOSCRCF field. When changing the frequency selection, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared and MAINCK is stopped until the oscillator is stabilized. Once the oscillator is stabilized, MAINCK restarts and PMC_SR.MOSCRCS is set. When disabling the main clock by clearing the CKGR_MOR.MOSCRCEN bit, the PMC_SR.MOSCRCS bit is automatically cleared, indicating the main clock is off. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. When main clock (MAINCK) is not used to drive the processor and frequency monitor (SLCK or PLLACK is used instead), it is recommended to disable the 8/16/24 MHz RC oscillator and 3 to 20 MHz crystal oscillator. The CAL8, CAL16 and CAL24 values in the PMC Oscillator Calibration Register (PMC_OCR) are the default values set by Atmel during production. These values are stored in a specific Flash memory area different from the memory plane for code. These values cannot be modified by the user and cannot be erased by a Flash erase command or by the ERASE pin. Values written by the user application in PMC_OCR are reset after each power up or peripheral reset. 24.5.2 8/16/24 MHz RC Oscillator Clock Frequency Adjustment It is possible for the user to adjust the 8/16/24 MHz RC oscillator frequency through PMC_OCR. By default, SEL8/16/24 bits are cleared, so the RC oscillator will be driven with Flash calibration bits which are programmed during chip production. The user can adjust the trimming of the 8/16/24 MHz RC oscillator through this register. This can be used to compensate derating factors such as temperature and voltage, thus providing greater accuracy. In order to calibrate the RC oscillator lower frequency, SEL8 bit must be set to 1 and a frequency value must be configured in the field CAL8. Likewise, SEL16/24 bit must be set to 1 and a trim value must be configured in the field CAL16/24 in order to adjust the other frequencies of the RC oscillator. It is possible to adjust the RC oscillator frequency while operating from this clock. For example, when running on lowest frequency it is possible to change the CAL8 value if PMC_OCR.SEL8 bit is set. At any time, it is possible to restart a measurement of the frequency of the selected clock via the RCMEAS bit in Main Clock Frequency Register (CKGR_MCFR). Thus, when CKGR_MCFR.MAINFRDY reads 1, another read access on CKGR_MCFR provides an image of the frequency on CKGR_MCFR.MAINF field. The software can calculate the error with an expected frequency and correct the CAL8 (or CAL16/CAL24) field accordingly. This may be used to compensate frequency drift due to derating factors such as temperature and/or voltage. 24.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator After reset, the 3 to 20 MHz crystal or ceramic resonator-based oscillator is disabled and is not selected as the source of MAINCK. As the source of MAINCK, the 3 to 20 MHz crystal or ceramic resonator-based oscillator provides a very precise frequency. The software enables or disables this oscillator in order to reduce power consumption via CKGR_MOR.MOSCXTEN. When disabling this oscillator by clearing the CKGR_MOR.MOSCXTEN, PMC_SR.MOSCXTS is automatically cleared, indicating the 3 to 20 MHz crystal oscillator is off. When enabling this oscillator, the user must initiate the start-up time counter. The start-up time depends on the characteristics of the external device connected to this oscillator. 432 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 When CKGR_MOR.MOSCXTEN and CKGR_MOR.MOSCXTST are written to enable this oscillator, the XIN and XOUT pins are automatically switched into Oscillator mode. PMC_SR.MOSCXTS is cleared and the counter starts counting down on the slow clock divided by 8 from the CKGR_MOR.MOSCXTST value. Since the CKGR_MOR.MOSCXTST value is coded with 8 bits, the maximum start-up time is about 62 ms. When the start-up time counter reaches 0, PMC_SR.MOSCXTS is set, indicating that the 3 to 20 MHz crystal oscillator is stabilized. Setting the MOSCXTS bit in the Interrupt Mask Register (PMC_IMR) can trigger an interrupt to the processor. 24.5.4 Main Clock Source Selection The user can select the source of the main clock from either the 8/16/24 MHz RC oscillator, the 3 to 20 MHz crystal oscillator or the ceramic resonator-based oscillator. The advantage of the 8/16/24 MHz RC oscillator is its fast start-up time. By default, this oscillator is selected to start the system and when entering Wait mode. The advantage of the 3 to 20 MHz crystal oscillator or ceramic resonator-based oscillator is its precise frequency. The selection of the oscillator is made by writing CKGR_MOR.MOSCSEL. The switch of the main clock source is glitch-free, so there is no need to ru n out of SLCK, PLLACK in orde r to change the selection. PMC_SR.MOSCSELS indicates when the switch sequence is done. Setting PMC_IMR.MOSCSELS triggers an interrupt to the processor. Enabling the 8/16/24 MHz RC oscillator (MOSCRCEN = 1) and changing its frequency (MOSCCRF) at the same time is not allowed. This oscillator must be enabled first and its frequency changed in a second step. 24.5.5 Bypassing the 3 to 20 MHz Crystal Oscillator Prior to bypassing the 3 to 20 MHz crystal oscillator, the external clock frequency provided on the XIN pin must be stable and within the values specified in the XIN Clock characteristics in the section “Electrical Characteristics”. The sequence is as follows: 1. Ensure that an external clock is connected on XIN. 2. Enable the bypass by writing a 1 to CKGR_MOR.MOSCXTBY. 3. Disable the 3 to 20 MHz crystal oscillator by writing a 0 to bit CKGR_MOR.MOSCXTEN. 24.5.6 Main Clock Frequency Counter The frequency counter is managed by CKGR_MCFR. During the measurement period, the frequency counter increments at the main clock speed. A measurement is started in the following cases: When the RCMEAS bit of CKGR_MCFR is written to 1. When the 8/16/24 MHz RC oscillator is selected as the source of main clock and when this oscillator becomes stable (i.e., when the MOSCRCS bit is set) When the 3 to 20 MHz crystal or ceramic resonator-based oscillator is selected as the source of main clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set) When the main clock source selection is modified The measurement period ends at the 16th falling edge of slow clock, the MAINFRDY bit in CKGR_MCFR is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of clock cycles during 16 periods of slow clock, so that the frequency of the 8/16/24 MHz RC oscillator or 3 to 20 MHz crystal or ceramic resonator-based oscillator can be determined. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 433 24.5.7 Switching Main Clock between the RC Oscillator and the Crystal Oscillator When switching the source of the main clock between the RC oscillator and the crystal oscillator, both oscillators must be enabled. After completion of the switch, the unused oscillator can be disabled. If switching to the crystal oscillator, a check must be carried out to ensure that the oscillator is present and that its frequency is valid. Follow the sequence below: 1. Select the slow clock as MCK by configuring bit CSS = 0 in the Master Clock Register (PMC_MCKR)). 2. Wait for PMC_SR.MCKRDY flag in PMC_SR to rise. 3. Enable the crystal oscillator by setting CKGR_MOR.MOSCXTEN. Configure the CKGR_MOR. MOSCXTST field with the crystal oscillator start-up time as defined in the section “Electrical Characteristics”. 4. Wait for PMC_SR.MOSCXTS flag to rise, indicating the end of a start-up period of the crystal oscillator. 5. Select the crystal oscillator as the source of the main clock by setting CKGR_MOR.MOSCSEL. 6. Read CKGR_MOR.MOSCSEL until its value equals 1. 7. Check the status of PMC_SR.MOSCSELS flag: ̶ If MOSCSELS = 1: There is a crystal oscillator connected. a. Initiate a new frequency measurement by setting CKGR_MCFR.RCMEAS. b. Read CKGR_MCFR.MAINFRDY until its value equals 1. c. Read CKGR_MCFR.MAINF and compute the value of the crystal frequency. d. If the MAINF value is valid, the main clock can be switched to the crystal oscillator. ̶ If MOSCSELS = 0: a. There is no crystal oscillator connected or the crystal oscillator is out of specification. b. 434 Select the RC oscillator as the source of the main clock by clearing CKGR_MOR.MOSCSEL. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 24.6 Divider and PLL Block The device features one PLL block that permits a wide range of frequencies to be selected on either the master clock, the processor clock or the programmable clock outputs. Figure 24-4 shows the block diagram of the PLL block. Figure 24-4. PLL Block Diagram CKGR_PLLAR MULA SLCK PLLA PLLACK CKGR_PLLAR PLLACOUNT PMC_SR SLCK PLLA Counter LOCKA 24.6.1 Phase Lock Loop Programming The PLL (PLLA) allows multiplication of the SLCK clock source. The PLL clock signal has a frequency that depends on the respective source signal frequency and MUL (MULA) and PLLEN (PLLAEN). The factor applied to the source signal frequency is MUL + 1. When MUL is written to 0 or PLLEN = 0, the PLL is disabled and its power consumption is saved. Note that there is a delay of two SLCK clock cycles between the disable command and the real disable of the PLL. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field and PLLAEN higher than 0. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA) bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR) are loaded in the PLL counter. The PLL counter then decrements at the speed of the slow clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of slow clock cycles required to cover the PLL transient time into the PLLCOUNT field. The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2) bit in PMC_MCKR. To avoid programming the PLL with a multiplication factor that is too high, the user can saturate the multiplication factor value sent to the PLL by setting the PLLA_MMAX field in PMC_PMMR. It is prohibited to change the frequency of the 8/16/24 MHz RC oscillator or to change the source of the main clock in CKGR_MOR while the master clock source is the PLL. The user must: 1. Switch on the 8/16/24 MHz RC oscillator by writing a 1 to the CSS field of PMC_MCKR. 2. Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR. 3. Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR. 4. Disable and then enable the PLL. 5. Wait for the LOCK flag in PMC_SR. 6. Switch back to the PLL by writing the appropriate value to the CSS field of PMC_MCKR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 435 25. Power Management Controller (PMC) 25.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M4 processor. The Supply Controller selects either the embedded 32 kHz RC oscillator or the 32768 Hz crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at startup, the chip runs out of the master clock using the 8/16/24 MHz RC oscillator running at 8 MHz. The user can trim the 16 and 24 MHz RC oscillator frequencies by software. 25.2 Embedded Characteristics The PMC provides the following clocks: MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the Enhanced Embedded Flash Controller. Processor Clock (HCLK) , automatically switched off when entering the processor in Sleep Mode Free-running processor Clock (FCLK) The Cortex-M4 SysTick external clock Peripheral Clocks, provided to the embedded peripherals (USART, SPI, TWI, TC, etc.) and independently controllable. Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCK pins The PMC also provides the following features on clocks: 436 A 3 to 20 MHz crystal oscillator clock failure detector A frequency counter on main clock An on-the-fly adjustable 8/16/24 MHz RC oscillator frequency Asynchronous partial wake-up (SleepWalking™) for UART0, UART1, TWI0 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.3 Block Diagram Figure 25-1. General Clock Block Diagram Clock Generator Processor Clock Controller XTALSEL (Supply Controller) Processor clock HCLK int Sleep Mode Embedded 32 kHz RC Oscillator 0 Divider /8 Slow Clock SLCK XOUT32 32768 Hz Crystal Oscillator SLCK 1 CKGR_MOR Prescaler /1,/2,/3,/4,/8, /16,/32,/64 MOSCSEL PLLACK Embedded 8/16/24 MHz RC Oscillator XIN XOUT Master Clock MCK Peripherals Clock Controller (PMC_PCERx) ON/OFF 0 CSS PRES Main Clock MAINCK 3-20 MHz Crystal or Ceramic Resonator Oscillator periph_clk[..] 1 Programmable Clock Controller (PMC_PCKx) SLCK MAINCK PLLA and Divider/2 PLLA Clock PLLACK Prescaler /1,/2,/4,/8, /16,/32,/64 PLLACK MCK CSS PLLADIV2 PMC_MCKR Status Free Running Clock FCLK MAINCK PRES ON/OFF pck[..] (PMC_SCER/SCDR) XIN32 SysTick Master Clock Controller (PMC_MCKR) Control Power Management Controller 25.4 Master Clock Controller The Master Clock Controller provides selection and division of the master clock (MCK). MCK is the source clock of the peripheral clocks. The master clock is selected from one of the clocks provided by the Clock Generator. Selecting the slow clock provides a slow clock signal to the whole device. Selecting the main clock saves power consumption of the PLL. The Master Clock Controller is made up of a clock selector and a prescaler. The master clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR. The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to define a new master clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the master clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 437 Figure 25-2. Master Clock Controller PMC_MCKR CSS PMC_MCKR PRES SLCK MAINCK Master Clock Prescaler MCK PLLACK To the Processor Clock Controller (HCLK) 25.5 Processor Clock Controller The PMC features a Processor Clock Controller (HCLK) that implements the processor Sleep mode. These processor clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup Mode Register (PMC_FSMR). The Processor Clock Controller HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The processor Sleep mode is entered by disabling the processor clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When processor Sleep mode is entered, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 25.6 SysTick Clock The SysTick calibration value is fixed to 6000 which allows the generation of a time base of 1 ms with SysTick clock to the maximum frequency on MCK divided by 8. 25.7 Peripheral Clock Controller The PMC controls the clocks of each embedded peripheral by means of the Peripheral Clock Controller. The user can individually enable and disable the clock on the peripherals. The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0). The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) . When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. To stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Clock Control registers (PMC_PCER0, PMC_PCDR0, and PMC_PCSR0) is the Peripheral Identifier defined at the product level. The bit number corresponds to the interrupt source number assigned to the peripheral. 25.8 Asynchronous Partial Wake-up (SleepWalking) 25.8.1 Description The asynchronous partial wake-up (SleepWalking) wakes up a peripheral in a fully asynchronous way when activity is detected on the communication line. Moreover, under some user configurable conditions, the asynchronous partial wake-up can trigger an exit of the system from Wait mode (full system wake-up). 438 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 The asynchronous partial wake-up function automatically manages the peripheral clock. It improves the overall power consumption of the system by clocking peripherals only when needed. Only the following peripherals can be configured with asynchronous partial wake-up: UART0, UART1, TWI0. The peripheral selected for asynchronous partial wake-up must be first configured so that its clock is enabled by setting the appropriate PIDx bit in PMC_PCERx. When the system is in Wait mode, all clocks of the system (except SLCK) are stopped. When an asynchronous clock request from a peripheral occurs, the PMC partially wakes up the system to feed the clock only to this peripheral. The rest of the system is not fed with the clock, thus optimizing power consumption. Finally, depending on user-configurable conditions, the peripheral either wakes up the whole system if these conditions are met or stops the peripheral clock until the next clock request. If a wake-up request occurs, the Asynchronous Partial Wake-up mode is automatically disabled until the user instructs the PMC to enable asynchronous partial wake-up. This is done by setting PIDx in the PMC SleepWalking Enable Register (PMC_SLPWK_ER). Figure 25-3. SleepWalking During Wait Mode system_clock The system is in wait mode. No clock is fed to the system. peripheral_clock peripheral clock request peripheral wakeup request peripheral sleepwalking status The wakeup request wakes up the system and resets the sleepwalking status of the peripheral When the system is in Active mode, peripherals enabled for asynchronous partial wake-up have their respective clocks stopped until the peripherals request a clock. When a peripheral requests the clock, the PMC provides the clock without CPU intervention. The triggering of the peripheral clock request depends on conditions which can be configured for each peripheral. If these conditions are met, the peripheral asserts a request to the PMC. The PMC disables the Asynchronous Partial Wake-up mode of the peripheral and provides the clock to the peripheral until the user instructs the PMC to re-enable partial wake-up on the peripheral. This is done by setting PIDx in the PMC_SLPWK_ER. If the conditions are not met, the peripheral clears the clock request and PMC stops the peripheral clock until the clock request is re-asserted by the peripheral. Figure 25-4. SleepWalking During Active Mode system_clock peripheral_clock peripheral clock request peripheral wakeup request peripheral sleepwalking status The wakeup request resets the sleepwalking status of the peripheral SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 439 25.8.2 Configuration Procedure Before configuring the asynchronous partial wake-up (SleepWalking) function of a peripheral, check that the PIDx bit in the PMC Peripheral Clock Status Register (PMC_PCSR) is set. This ensures that the peripheral clock is enabled. To enable the asynchronous partial wake-up (SleepWalking) function of a peripheral, follow the steps below: 1. Check that the corresponding PIDx bit in the PMC SleepWalking Activity Status Register (PMC_SLPWK_ASR) is cleared. This ensures that the peripheral has no activity in progress. 2. Enable the asynchronous partial wake-up function of the peripheral by writing a one to the corresponding PIDx bit in the PMC_SLPWK_ER. 3. Check that the corresponding PIDx bit in PMC_SLPWK_ASR is cleared. This ensures that no activity has started during the enable phase. 4. In the PMC_SLPWK_ASR, if the corresponding PIDx bit is set, the asynchronous partial wake-up function must be immediately disabled by writing a one to the PIDx bit in the PMC SleepWalking Disable Register (PMC_SLPWK_DR). Wait for the end of peripheral activity before reinitializing the procedure. If the corresponding PIDx bit is cleared, the peripheral clock is disabled and the system can now be placed in Wait mode. Before entering Wait mode, check that all the PIDx bits in PMC_SLPWK_ASR are cleared. This ensures that none of the peripherals has any activity in progress. Note: 25.9 When asynchronous partial wake-up (SleepWalking) of a peripheral is enabled and the core is running (system not in Wait mode), the peripheral must not be accessed before a wake-up of the peripheral is performed. Free-Running Processor Clock The free-running processor clock (FCLK)used for sampling interrupts and clocking debug blocks ensures that interrupts can be sampled, and sleep events can be traced, while the processor is sleeping. It is connected to master clock (MCK). 25.10 Programmable Clock Output Controller The PMC controls three signals to be output on external pins, PCKx. Each signal can be independently programmed via the Programmable Clock Registers (PMC_PCKx). PCKx can be independently selected between the slow clock (SLCK), the main clock (MAINCK), the PLLA clock (PLLACK),and the master clock (MCK) by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing a 1 to the corresponding PCKx bit of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR. The PCKRDYx status flag in PMC_SR indicates that the programmable clock is actually what has been programmed in the programmable clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is actually performed. 25.11 Fast Startup At exit from Wait mode, the device allows the processor to restart in less than 5 microseconds only if the C-code function that manages the Wait mode entry and exit is linked to and executed from on-chip SRAM. The fast startup time cannot be achieved if the first instruction after an exit is located in the embedded Flash. 440 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 If fast startup is not required, or if the first instruction after a Wait mode exit is located in embedded Flash, see Section 25.12 ”Startup from Embedded Flash”. Prior to instructing the device to enter Wait mode: 1. Select the 8/16/24 MHz RC oscillator as the master clock source (the CSS field in PMC_MCKR must be written to 1). 2. Disable the PLL if enabled. 3. Wait for two SLCK clock cycles. 4. Clear the internal wake-up sources. The system enters Wait mode either by setting the WAITMODE bit in CKGR_MOR, or by executing the WaitForEvent (WFE) instruction of the processor while the LPM bit is at 1 in PMC_FSMR. Immediately after setting the WAITMODE bit or using the WFE instruction, wait for the MCKRDY bit to be set in PMC_SR. A fast startup is enabled upon the detection of a programmed level on one the wake-up input pins WKUPx (up to 16 inputs, see Peripheral Signal Multiplexing on I/O Lines section for exact number) or upon an active alarm from the RTC and RTT. The polarity of each wake-up input is programmable by writing the PMC Fast Startup Polarity Register (PMC_FSPR). The fast startup circuitry, as shown in Figure 25-5, is fully asynchronous and provides a fast startup signal to the PMC. As soon as the fast startup signal is asserted, the embedded 8/16/24 MHz RC oscillator restarts automatically. When entering Wait mode, the embedded Flash can be placed in one of the Low-power modes (Deep-powerdown or Standby modes) depending on the configuration of the FLPM field in the PMC_FSMR. The FLPM field can be programmed at anytime and its value will be applied to the next Wait mode period. The power consumption reduction is optimal when configuring 1 (Deep-power-down mode) in field FLPM. If 0 is programmed (Standby mode), the power consumption is slightly higher than in Deep-power-down mode. When programming 2 in field FLPM, the Wait mode Flash power consumption is equivalent to that of the Active mode when there is no read access on the Flash. Figure 25-5. Fast Startup Circuitry FSTT0 WKUP0 FSTP0 FSTT1 WKUP1 FSTP1 FSTT15 WKUP15 fast_restart FSTP15 RTTAL RTT Alarm RTCAL RTC Alarm SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 441 Each wake-up input pin and alarm can be enabled to generate a fast startup event by setting the corresponding bit in PMC_FSMR. The user interface does not provide any status for fast startup, but the user can easily recover this information by reading the PIO Controller and the status registers of the RTC and RTT. 25.12 Startup from Embedded Flash The inherent start-up time of the embedded Flash cannot provide a fast startup of the system. If system fast start-up time is not required, the first instruction after a Wait mode exit can be located in the embedded Flash. Under these conditions, prior to entering Wait mode, the Flash controller must be programmed to perform access in 0 wait-state. Refer to the section “Enhanced Embedded Flash Controller (EEFC)”. If the 8/16/24 MHz RC oscillator is configured to generate 16 MHz or 24 MHz (MOSCRCF = 1 or 2 in CKGR_MOR), the first instruction after an exit must not be located in the embedded Flash and the fast startup procedure must be used (see Section 25.11 ”Fast Startup”). If this RC oscillator is configured to generate 8 MHz (MOSCRCF = 0 in CKGR_MOR), the instructions managing start-up time can be located in any on-chip memory. The procedure and conditions to enter Wait mode and the circuitry to exit Wait mode are strictly the same as fast startup (see Section 25.11 ”Fast Startup”). 25.13 Main Clock Failure Detector The clock failure detector monitors the 3 to 20 MHz crystal oscillator or ceramic resonator-based oscillator to identify a failure of this oscillator when selected as main clock. The clock failure detector can be enabled or disabled by bit CFDEN in CKGR_MOR. After a VDDCORE reset, the detector is disabled. However, if the oscillator is disabled (MOSCXTEN = 0), the detector is also disabled. A failure is detected by means of a counter incrementing on the main clock and detection logic is triggered by the 32 kHz (typical) RC oscillator which is automatically enabled when CFDEN=1. The counter is cleared when the 32 kHz (typical) RC oscillator clock signal is low and enabled when the signal is high. Thus, the failure detection time is one RC oscillator period. If, during the high level period of the 32 kHz (typical) RC oscillator clock signal, less than eight 3 to 20 MHz crystal oscillator clock periods have been counted, then a failure is reported. If a failure of the main clock is detected, bit CFDEV in PMC_SR indicates a failure event and generates an interrupt if the corresponding interrupt source is enabled. The interrupt remains active until a read occurs in PMC_SR. The user can know the status of the clock failure detection at any time by reading the CFDS bit in PMC_SR. Figure 25-6. Clock Failure Detection (Example) Main Crytal Clock SLCK CDFEV Read PMC_SR CDFS Note: ratio of clock periods is for illustration purposes only If the 3 to 20 MHz crystal oscillator or ceramic resonator-based oscillator is selected as the source clock of MAINCK (MOSCSEL in CKGR_MOR = 1), and if MCK source is PLLACK (CSS = 2), a clock failure detection 442 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 automatically forces MAINCK to be the source clock for MCK. Then, regardless of the PMC configuration, a clock failure detection automatically forces the 8/16/24 MHz RC oscillator to be the source clock for MAINCK. If this oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism. It takes two 32 kHz (typical) RC oscillator clock cycles to detect and switch from the 3 to 20 MHz crystal oscillator, to the 8/16/24 MHz RC oscillator if the source master clock (MCK) is main clock (MAINCK), or three 32 kHz (typical) RC oscillator clock cycles if the source of MCK is PLLACK. The user can know the status of the clock failure detector at any time by reading the FOS bit in PMC_SR. This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear Register (PMC_FOCR). 25.14 Programming Sequence 1. If the 3 to 20 MHz crystal oscillator is not required, the PLL and divider can be directly configured (Step 6.) else this oscillator must be started (Step 2.). 2. Enable the 3 to 20 MHz crystal oscillator by setting the MOSCXTEN field in CKGR_MOR: The user can define a start-up time. This is done by writing a value in the MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the user must wait for MOSCXTS field in PMC_SR to be set. This is done either by polling MOSCXTS in PMC_SR, or by waiting for the interrupt line to be raised if the associated interrupt source (MOSCXTS) has been enabled in PMC_IER. 3. Switch the MAINCK to the 3 to 20 MHz crystal oscillator by setting MOSCSEL in CKGR_MOR. 4. Wait for the MOSCSELS to be set in PMC_SR to ensure the switch is complete. 5. Check the main clock frequency: This main clock frequency can be measured via CKGR_MCFR. Read CKGR_MCFR until the MAINFRDY field is set, after which the user can read the MAINF field in CKGR_MCFR by performing an additional read. This provides the number of main clock cycles that have been counted during a period of 16 slow clock cycles. If MAINF = 0, switch the MAINCK to the 8/16/24 MHz RC Oscillator by clearing MOSCSEL in CKGR_MOR. If MAINF ≠ 0, proceed to Step 6. 6. Set PLLx and Divider (if not required, proceed to Step 7.): In the names PLLx, DIVx, MULx, LOCKx, PLLxCOUNT, and CKGR_PLLxR, ‘x’ represents A. All parameters needed to configure PLLx and the divider are located in CKGR_PLLxR. The DIVx field is used to control the divider itself. This parameter can be programmed between 0 and 127. Divider output is divider input divided by DIVx parameter. By default, DIVx field is cleared which means that the divider and PLLx are turned off. The MULx field is the PLLx multiplier factor. This parameter can be programmed between 0 and 1500. If MULx is cleared, PLLx will be turned off, otherwise the PLLx output frequency is PLLx input frequency multiplied by (MULx + 1). The PLLxCOUNT field specifies the number of slow clock cycles before the LOCKx bit is set in the PMC_SR after CKGR_PLLxR has been written. Once CKGR_PLLxR has been written, the user must wait for the LOCKx bit to be set in the PMC_SR. This can be done either by polling LOCKx in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKx) has been enabled in PMC_IER. All fields in CKGR_PLLxR can be programmed in a single write operation. If at some stage one of the following parameters, MULx or DIVx is modified, the LOCKx bit goes low to indicate that PLLx is not yet ready. When PLLx is locked, LOCKx is set again. The user must wait for the LOCKx bit to be set before using the PLLx output clock. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 443 7. Select the master clock and processor clock The master clock and the processor clock are configurable via PMC_MCKR. The CSS field is used to select the clock source of the master clock and processor clock dividers. By default, the selected clock source is the main clock. The PRES field is used to define the processor clock and master clock prescaler. The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value. Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR. This can be done either by polling MCKRDY in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (MCKRDY) has been enabled in PMC_IER. PMC_MCKR must not be programmed in a single write operation. The programming sequence for PMC_MCKR is as follows: If a new value for CSS field corresponds to PLL clock, ̶ Program the PRES field in PMC_MCKR. ̶ Wait for the MCKRDY bit to be set in PMC_SR. ̶ Program the CSS field in PMC_MCKR. ̶ Wait for the MCKRDY bit to be set in PMC_SR. If a new value for CSS field corresponds to main clock or slow clock, ̶ Program the CSS field in PMC_MCKR. ̶ Wait for the MCKRDY bit to be set in the PMC_SR. ̶ Program the PRES field in PMC_MCKR. ̶ Wait for the MCKRDY bit to be set in PMC_SR. If at some stage, parameters CSS or PRES are modified, the MCKRDY bit goes low to indicate that the master clock and the processor clock are not yet ready. The user must wait for MCKRDY bit to be set again before using the master and processor clocks. Note: IF PLLx clock was selected as the master clock and the user decides to modify it by writing in CKGR_PLLxR, the MCKRDY flag will go low while PLLx is unlocked. Once PLLx is locked again, LOCKx goes high and MCKRDY is set. While PLLx is unlocked, the master clock selection is automatically changed to slow clock for PLLA. For further information, see Section 25.15.2 ”Clock Switching Waveforms”. Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) The master clock is main clock divided by 2. 8. Select the programmable clocks Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Three programmable clocks can be used. PMC_SCSR indicates which programmable clock is enabled. By default all programmable clocks are disabled. PMC_PCKx registers are used to configure programmable clocks. The CSS field is used to select the programmable clock divider source. Several clock options are available: main clock, slow clock, master clock, PLLACK. The slow clock is the default clock source. The PRES field is used to control the programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES value is cleared which means that PCKx is equal to slow clock. 444 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Once PMC_PCKx register has been configured, the corresponding programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done either by polling PCKRDYx in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (PCKRDYx) has been enabled in PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be set. 9. Enable the peripheral clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER0, PMC_PCDR0. 25.15 Clock Switching Details 25.15.1 Master Clock Switching Timings Table 25-1 gives the worst case timings required for the master clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added. Table 25-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.5 x Main Clock 0.5 x Main Clock + 4.5 x SLCK – 3 x PLL Clock + 5 x SLCK 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK To Main Clock SLCK PLL Clock Notes: 1. 2. 3 x PLL Clock + 4 x SLCK + 1 x Main Clock PLL designates the PLLA . PLLCOUNT designates PLLACOUNT . SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 445 25.15.2 Clock Switching Waveforms Figure 25-7. Switch Master Clock from Slow Clock to PLLx Clock Slow Clock PLLx Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 25-8. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR 446 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 25-9. Change PLLx Programming Slow Clock PLLx Clock LOCKx MCKRDY Master Clock Slow Clock Write CKGR_PLLxR Figure 25-10. Programmable Clock Output Programming PLLx Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR PLL Clock is selected PCKx is enabled PCKx is disabled SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 447 25.16 Register Write Protection To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PMC Write Protection Mode Register (PMC_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the PMC Write Protection Status Register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PMC_WPSR. The following registers can be write-protected: 448 PMC System Clock Enable Register PMC System Clock Disable Register PMC Peripheral Clock Enable Register 0 PMC Peripheral Clock Disable Register 0 PMC Clock Generator Main Oscillator Register PMC Clock Generator PLLA Register PMC Master Clock Register PMC Programmable Clock Register PMC Fast Startup Mode Register PMC Fast Startup Polarity Register PMC Oscillator Calibration Register PMC SleepWalking Enable Register 0 PMC SleepWalking Disable Register 0 PLL Maximum Multiplier Value Register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17 Power Management Controller (PMC) User Interface Table 25-2. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only – 0x0004 System Clock Disable Register PMC_SCDR Write-only – 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0001 0x000C Reserved – – 0x0010 Peripheral Clock Enable Register 0 PMC_PCER0 Write-only – 0x0014 Peripheral Clock Disable Register 0 PMC_PCDR0 Write-only – 0x0018 Peripheral Clock Status Register 0 PMC_PCSR0 Read-only 0x0000_0000 0x0020 Main Oscillator Register CKGR_MOR Read/Write 0x0000_0008 0x0024 Main Clock Frequency Register CKGR_MCFR Read/Write 0x0000_0000 0x0028 PLLA Register CKGR_PLLAR Read/Write 0x0000_3F00 0x002C Reserved – – 0x0030 Master Clock Register Read/Write 0x0000_0001 – – 0x0034–0x003C – – PMC_MCKR Reserved – 0x0040 Programmable Clock 0 Register PMC_PCK0 Read/Write 0x0000_0000 0x0044 Programmable Clock 1 Register PMC_PCK1 Read/Write 0x0000_0000 0x0048 Programmable Clock 2 Register PMC_PCK2 Read/Write 0x0000_0000 – – 0x004C– 0x005C Reserved – 0x0060 Interrupt Enable Register PMC_IER Write-only – 0x0064 Interrupt Disable Register PMC_IDR Write-only – 0x0068 Status Register PMC_SR Read-only 0x0003_0008 0x006C Interrupt Mask Register PMC_IMR Read-only 0x0000_0000 0x0070 Fast Startup Mode Register PMC_FSMR Read/Write 0x0000_0000 0x0074 Fast Startup Polarity Register PMC_FSPR Read/Write 0x0000_0000 0x0078 Fault Output Clear Register PMC_FOCR Write-only – – – 0x007C–0x00E0 Reserved – 0x00E4 Write Protection Mode Register PMC_WPMR Read/Write 0x0000_0000 0x00E8 Write Protection Status Register PMC_WPSR Read-only 0x0000_0000 0x00EC–0x00FC Reserved – – – 0x0100–0x0108 Reserved – – – 0x010C Reserved – – – 0x0110 Oscillator Calibration Register PMC_OCR Read/Write 0x0040_4040 0x114 SleepWalking Enable Register 0 PMC_SLPWK_ER0 Write-only – 0x118 SleepWalking Disable Register 0 PMC_SLPWK_DR0 Write-only – SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 449 Table 25-2. Register Mapping (Continued) Offset Register Name Access Reset 0x11C SleepWalking Status Register 0 PMC_SLPWK_SR0 Read-only 0x0000_0000 0x120 SleepWalking Activity Status Register 0 PMC_SLPWK_ASR0 Read-Only – Read/Write 0x07FF_07FF 0x130 PLL Maximum Multiplier Value Register PMC_PMMR Note: If an offset is not listed in the table it must be considered as “reserved”. 450 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0x400E0400 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PCKx: Programmable Clock x Output Enable 0: No effect. 1: Enables the corresponding Programmable Clock output. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 451 25.17.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0x400E0404 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PCKx: Programmable Clock x Output Disable 0: No effect. 1: Disables the corresponding Programmable Clock output. 452 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0x400E0408 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PCKx: Programmable Clock x Output Status 0: The corresponding Programmable Clock output is disabled. 1: The corresponding Programmable Clock output is enabled. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 453 25.17.4 PMC Peripheral Clock Enable Register 0 Name: PMC_PCER0 Address: 0x400E0410 Access: Write-only 31 – 30 – 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PIDx: Peripheral Clock x Enable 0: No effect. 1: Enables the corresponding peripheral clock. Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. 454 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.5 PMC Peripheral Clock Disable Register 0 Name: PMC_PCDR0 Address: 0x400E0414 Access: Write-only 31 – 30 – 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PIDx: Peripheral Clock x Disable 0: No effect. 1: Disables the corresponding peripheral clock. Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 455 25.17.6 PMC Peripheral Clock Status Register 0 Name: PMC_PCSR0 Address: 0x400E0418 Access: Read-only 31 – 30 – 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled. 1: The corresponding peripheral clock is enabled. Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. 456 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.7 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0x400E0420 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 CFDEN 24 MOSCSEL 23 22 21 20 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 WAITMODE 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 5 MOSCRCF 4 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • MOSCXTEN: 3 to 20 MHz Crystal Oscillator Enable A crystal must be connected between XIN and XOUT. 0: The 3 to 20 MHz crystal oscillator is disabled. 1: The 3 to 20 MHz crystal oscillator is enabled. MOSCXTBY must be cleared. When MOSCXTEN is set, the MOSCXTS flag is set once the crystal oscillator start-up time is achieved. • MOSCXTBY: 3 to 20 MHz Crystal Oscillator Bypass 0: No effect. 1: The 3 to 20 MHz crystal oscillator is bypassed. MOSCXTEN must be cleared. An external clock must be connected on XIN. When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set. Clearing MOSCXTEN and MOSCXTBY bits resets the MOSCXTS flag. Note: When the crystal oscillator bypass is disabled (MOSCXTBY = 0), the MOSCXTS flag must be read at 0 in PMC_SR before enabling the crystal oscillator (MOSCXTEN = 1). • WAITMODE: Wait Mode Command (Write-only) 0: No effect. 1: Puts the device in Wait mode. • MOSCRCEN: 8/16/24 MHz RC Oscillator Enable 0: The 8/16/24 MHz RC oscillator is disabled. 1: The 8/16/24 MHz RC oscillator is enabled. When MOSCRCEN is set, the MOSCRCS flag is set once the RC oscillator start-up time is achieved. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 457 • MOSCRCF: 8/16/24 MHz RC Oscillator Frequency Selection At startup, the RC oscillator frequency is 8 MHz. Value Name Description 0 8_MHz The RC oscillator frequency is at 8 MHz (default) 1 16_MHz The RC oscillator frequency is at 16 MHz 2 24_MHz The RC oscillator frequency is at 24 MHz Note: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR. Therefore MOSCRCF and MOSCRCEN cannot be changed at the same time. • MOSCXTST: 3 to 20 MHz Crystal Oscillator Start-up Time Specifies the number of slow clock cycles multiplied by 8 for the crystal oscillator start-up time. • KEY: Write Access Password Value Name 0x37 PASSWD Description Writing any other value in this field aborts the write operation. Always reads as 0. • MOSCSEL: Main Clock Oscillator Selection 0: The 8/16/24 MHz RC oscillator is selected. 1: The 3 to 20 MHz crystal oscillator is selected. • CFDEN: Clock Failure Detector Enable 0: The clock failure detector is disabled. 1: The clock failure detector is enabled. Note: 458 1. The 32 kHz (typical) RC oscillator is automatically enabled when CFDEN=1. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.8 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0x400E0424 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 RCMEAS 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • MAINF: Main Clock Frequency Gives the number of main clock cycles within 16 slow clock periods. To calculate the frequency of the measured clock: fMAINCK = (MAINF × fSLCK) / 16 where frequency is in MHz. • MAINFRDY: Main Clock Frequency Measure Ready 0: MAINF value is not valid or the measured oscillator is disabled or a measure has just been started by means of RCMEAS. 1: The measured oscillator has been enabled previously and MAINF value is available. Note: To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at 1 then another read access must be performed on the register to get a stable value on the MAINF field. • RCMEAS: Restart Main Clock Source Frequency Measure (write-only) 0: No effect. 1: Restarts measuring of the frequency of the main clock source. MAINF will carry the new frequency as soon as a low to high transition occurs on the MAINFRDY flag. The measure is performed on the main frequency (i.e. not limited to RC oscillator only), but if the main clock frequency source is the 3 to 20 MHz crystal oscillator, the restart of measuring is not needed because of the well known stability of crystal oscillators. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 459 25.17.9 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0x400E0428 Access: Read/Write 31 – 30 – 29 ZERO 28 – 27 23 22 21 20 19 26 25 24 18 17 16 10 9 8 2 1 0 MULA MULA 15 – 14 – 13 7 6 5 12 11 PLLACOUNT 4 3 PLLAEN Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PLLAEN: PLLA Control 0: PLLA is disabled 1: PLLA is enabled 2–255: Forbidden • PLLACOUNT: PLLA Counter Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written. • MULA: PLLA Multiplier 0: The PLLA is deactivated (PLLA also disabled if DIVA = 0). 24 up to 1500 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1. Unlisted values are forbidden. • ZERO: Must Be Written to 0 Bit 29 must always be written to 0 when programming the CKGR_PLLAR. 460 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.10PMC Master Clock Register Name: PMC_MCKR Address: 0x400E0430 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 PLLADIV2 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 – 1 0 CSS This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • CSS: Master Clock Source Selection Value Name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLA Clock is selected • PRES: Processor Clock Prescaler Value Name Description 0 CLK_1 Selected clock 1 CLK_2 Selected clock divided by 2 2 CLK_4 Selected clock divided by 4 3 CLK_8 Selected clock divided by 8 4 CLK_16 Selected clock divided by 16 5 CLK_32 Selected clock divided by 32 6 CLK_64 Selected clock divided by 64 7 CLK_3 Selected clock divided by 3 • PLLADIV2: PLLA Divisor by 2 PLLADIV2 PLLA Clock Division 0 PLLA clock frequency is divided by 1. 1 PLLA clock frequency is divided by 2. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 461 25.17.11PMC Programmable Clock Register Name: PMC_PCKx Address: 0x400E0440 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 1 CSS 0 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • CSS: Master Clock Source Selection Value Name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLA Clock is selected 4 MCK Master Clock is selected • PRES: Programmable Clock Prescaler 462 Value Name Description 0 CLK_1 Selected clock 1 CLK_2 Selected clock divided by 2 2 CLK_4 Selected clock divided by 4 3 CLK_8 Selected clock divided by 8 4 CLK_16 Selected clock divided by 16 5 CLK_32 Selected clock divided by 32 6 CLK_64 Selected clock divided by 64 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.12PMC Interrupt Enable Register Name: PMC_IER Address: 0x400E0460 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 CFDEV 17 MOSCRCS 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 – 6 – 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. • MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Enable • LOCKA: PLLA Lock Interrupt Enable • MCKRDY: Master Clock Ready Interrupt Enable • PCKRDYx: Programmable Clock Ready x Interrupt Enable • MOSCSELS: Main Clock Source Oscillator Selection Status Interrupt Enable • MOSCRCS: 8/16/24 MHz RC Oscillator Status Interrupt Enable • CFDEV: Clock Failure Detector Event Interrupt Enable SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 463 25.17.13PMC Interrupt Disable Register Name: PMC_IDR Address: 0x400E0464 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 CFDEV 17 MOSCRCS 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 – 6 – 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. • MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Disable • LOCKA: PLLA Lock Interrupt Disable • MCKRDY: Master Clock Ready Interrupt Disable • PCKRDYx: Programmable Clock Ready x Interrupt Disable • MOSCSELS: Main Clock Source Oscillator Selection Status Interrupt Disable • MOSCRCS: 8/16/24 MHz RC Oscillator Status Interrupt Disable • CFDEV: Clock Failure Detector Event Interrupt Disable 464 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.14PMC Status Register Name: PMC_SR Address: 0x400E0468 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 FOS 19 CFDS 18 CFDEV 17 MOSCRCS 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 OSCSELS 6 – 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS • MOSCXTS: 3 to 20 MHz Crystal Oscillator Status 0: 3 to 20 MHz crystal oscillator is not stabilized. 1: 3 to 20 MHz crystal oscillator is stabilized. • LOCKA: PLLA Lock Status 0: PLLA is not locked 1: PLLA is locked. • MCKRDY: Master Clock Status 0: Master Clock is not ready. 1: Master Clock is ready. • OSCSELS: Slow Clock Oscillator Selection 0: Embedded 32 kHz RC oscillator is selected. 1: 32768 Hz crystal oscillator is selected. • PCKRDYx: Programmable Clock Ready Status 0: Programmable Clock x is not ready. 1: Programmable Clock x is ready. • MOSCSELS: Main Clock Source Oscillator Selection Status 0: Selection is in progress. 1: Selection is done. • MOSCRCS: 8/16/24 MHz RC Oscillator Status 0: 8/16/24 MHz RC oscillator is not stabilized. 1: 8/16/24 MHz RC oscillator is stabilized. • CFDEV: Clock Failure Detector Event 0: No clock failure detection of the 3 to 20 MHz crystal oscillator has occurred since the last read of PMC_SR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 465 1: At least one clock failure detection of the 3 to 20 MHz crystal oscillator has occurred since the last read of PMC_SR. • CFDS: Clock Failure Detector Status 0: A clock failure of the 3 to 20 MHz crystal oscillator is not detected. 1: A clock failure of the 3 to 20 MHz crystal oscillator is detected. • FOS: Clock Failure Detector Fault Output Status 0: The fault output of the clock failure detector is inactive. 1: The fault output of the clock failure detector is active. 466 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.15PMC Interrupt Mask Register Name: PMC_IMR Address: 0x400E046C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 CFDEV 17 MOSCRCS 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 – 6 – 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. • MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Mask • LOCKA: PLLA Lock Interrupt Mask • MCKRDY: Master Clock Ready Interrupt Mask • PCKRDYx: Programmable Clock Ready x Interrupt Mask • MOSCSELS: Main Clock Source Oscillator Selection Status Interrupt Mask • MOSCRCS: 8/16/24 MHz RC Oscillator Status Interrupt Mask • CFDEV: Clock Failure Detector Event Interrupt Mask SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 467 25.17.16PMC Fast Startup Mode Register Name: PMC_FSMR Address: 0x400E0470 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 LPM 19 – 18 17 RTCAL 16 RTTAL 15 FSTT15 14 FSTT14 13 FSTT13 12 FSTT12 11 FSTT11 10 FSTT10 9 FSTT9 8 FSTT8 7 FSTT7 6 FSTT6 5 FSTT5 4 FSTT4 3 FSTT3 2 FSTT2 1 FSTT1 0 FSTT0 FLPM This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • FSTT0–FSTT15: Fast Startup Input Enable 0 to 15 0: The corresponding wake-up input has no effect on the PMC. 1: The corresponding wake-up input enables a fast restart signal to the PMC. • RTTAL: RTT Alarm Enable 0: The RTT alarm has no effect on the PMC. 1: The RTT alarm enables a fast restart signal to the PMC. • RTCAL: RTC Alarm Enable 0: The RTC alarm has no effect on the PMC. 1: The RTC alarm enables a fast restart signal to the PMC. • LPM: Low-power Mode 0: The WaitForInterrupt (WFI) or the WaitForEvent (WFE) instruction of the processor makes the processor enter Sleep mode. 1: The WaitForEvent (WFE) instruction of the processor makes the system to enter Wait mode. • FLPM: Flash Low-power Mode Value 468 Name Description 0 FLASH_STANDBY Flash is in Standby Mode when system enters Wait Mode 1 FLASH_DEEP_POWERDOWN Flash is in Deep-power-down mode when system enters Wait Mode 2 FLASH_IDLE Idle mode SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.17PMC Fast Startup Polarity Register Name: PMC_FSPR Address: 0x400E0474 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 FSTP15 14 FSTP14 13 FSTP13 12 FSTP12 11 FSTP11 10 FSTP10 9 FSTP9 8 FSTP8 7 FSTP7 6 FSTP6 5 FSTP5 4 FSTP4 3 FSTP3 2 FSTP2 1 FSTP1 0 FSTP0 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • FSTPx: Fast Startup Input Polarityx Defines the active polarity of the corresponding wake-up input. If the corresponding wake-up input is enabled and at the FSTP level, it enables a fast restart signal. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 469 25.17.18PMC Fault Output Clear Register Name: PMC_FOCR Address: 0x400E0478 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FOCLR • FOCLR: Fault Output Clear Clears the clock failure detector fault output. 470 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.19PMC Write Protection Mode Register Name: PMC_WPMR Address: 0x400E04E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). See Section 25.16 ”Register Write Protection” for the list of registers that can be write-protected. • WPKEY: Write Protection Key Value 0x504D43 Name Description PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 471 25.17.20PMC Write Protection Status Register Name: PMC_WPSR Address: 0x400E04E8 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PMC_WPSR. 1: A write protection violation has occurred since the last read of the PMC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. 472 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.21PMC Oscillator Calibration Register Name: PMC_OCR Address: 0x400E0510 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 SEL24 22 21 20 19 CAL24 18 17 16 15 SEL16 14 13 12 11 CAL16 10 9 8 7 SEL8 6 5 4 3 CAL8 2 1 0 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • CAL8: RC Oscillator Calibration bits for 8 MHz Calibration bits applied to the RC Oscillator when SEL8 is set. • SEL8: Selection of RC Oscillator Calibration bits for 8 MHz 0: Default value stored in Flash memory. 1: Value written by user in CAL8 field of this register. • CAL16: RC Oscillator Calibration bits for 16 MHz Calibration bits applied to the RC Oscillator when SEL16 is set. • SEL16: Selection of RC Oscillator Calibration bits for 16 MHz 0: Factory-determined value stored in Flash memory. 1: Value written by user in CAL16 field of this register. • CAL24: RC Oscillator Calibration bits for 24 MHz Calibration bits applied to the RC Oscillator when SEL24 is set. • SEL24: Selection of RC Oscillator Calibration bits for 24 MHz 0: Factory-determined value stored in Flash memory. 1: Value written by user in CAL24 field of this register. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 473 25.17.22PMC SleepWalking Enable Register 0 Name: PMC_SLPWK_ER0 Address: 0x400E0514 Access: Write-only 31 – 30 – 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PIDx: Peripheral x SleepWalking Enable 0: No effect. 1: The asynchronous partial wake-up (SleepWalking) function of the corresponding peripheral is enabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PID can be configured with asynchronous partial wake-up: UART0, UART1, TWI0. The clock of the peripheral must be enabled before using its asynchronous partial wake-up (SleepWalking) function (its associated PIDx field in PMC Peripheral Clock Status Register 0 is set to ‘1’). Note: The values for PIDx are defined in section “Peripheral Identifiers”. 474 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.23PMC SleepWalking Disable Register 0 Name: PMC_SLPWK_DR0 Address: 0x400E0518 Access: Write-only 31 – 30 – 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PIDx: Peripheral x SleepWalking Disable 0: No effect. 1: The asynchronous partial wake-up (SleepWalking) function of the corresponding peripheral is disabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PIDs can be configured with asynchronous partial wake-up: UART0, UART1, TWI0. Note: The values for PIDx are defined in the section “Peripheral Identifiers”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 475 25.17.24PMC SleepWalking Status Register 0 Name: PMC_SLPWK_SR0 Address: 0x400E051C Access: Read-only 31 – 30 – 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PIDx: Peripheral x SleepWalking Status 0: The asynchronous partial wake-up (SleepWalking) function of the peripheral is currently disabled or the peripheral enabled for asynchronous partial wake-up (SleepWalking) cleared the PIDx bit upon detection of a wake-up condition. 1: The asynchronous partial wake-up (SleepWalking) function of the peripheral is currently enabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PIDs can be configured with asynchronous partial wake-up: UART0, UART1, TWI0. Note: The values for PIDx are defined in the section “Peripheral Identifiers”. 476 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 25.17.25PMC SleepWalking Activity Status Register 0 Name: PMC_SLPWK_ASR0 Address: 0x400E0520 Access: Read-only 31 – 30 – 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PIDx: Peripheral x Activity Status 0: The peripheral x is not presently active. The asynchronous partial wake-up (SleepWalking) function can be activated. 1: The peripheral x is presently active. The asynchronous partial wake-up (SleepWalking) function must not be activated. Only the following PIDs can be configured with asynchronous partial wake-up: UART0, UART1, TWI0. All other PIDs are always read at 0. Note: The values for PIDx are defined in the section “Peripheral Identifiers”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 477 25.17.26PLL Maximum Multiplier Value Register Name: PMC_PMMR Address: 0x400E0530 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 PLLA_MMAX 8 7 6 5 4 3 2 1 0 PLLA_MMAX This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PLLA_MMAX: PLLA Maximum Allowed Multiplier Value Defines the maximum value of multiplication factor that can be sent to PLLA. Any value of the MULA field (see PMC Clock Generator PLLA Register) above PLLA_MMAX is saturated to PLLA_MMAX. PLLA_MMAX write operation is cancelled in the following cases: • The value of MULA is currently saturated by PLLA_MMAX • The user is trying to write a value of PLLA_MMAX that is smaller than the current value of MULA 478 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 26. Chip Identifier (CHIPID) 26.1 Description Chip Identifier (CHIPID) registers are used to recognize the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two CHIPID registers are embedded: Chip ID Register (CHIPID_CIDR) and Chip ID Extension Register (CHIPID_EXID). Both registers contain a hard-wired value that is read-only. The CHIPID_CIDR register contains the following fields: VERSION: Identifies the revision of the silicon EPROC: Indicates the embedded ARM processor NVPTYP and NVPSIZ: Identify the type of embedded non-volatile memory and the size SRAMSIZ: Indicates the size of the embedded SRAM ARCH: Identifies the set of embedded peripherals EXT: Shows the use of the extension identifier register The CHIPID_EXID register is device-dependent and reads 0 if CHIPID_CIDR.EXT = 0. 26.2 Embedded Characteristics Chip ID Registers ̶ Table 26-1. Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals, Embedded Processor SAM G53 Chip ID Registers Chip Name CHIPID_CIDR CHIPID_EXID SAM G53G19 Rev A 0x247E_0AE0 0x0 SAM G53N19 Rev A 0x247E_0AE8 0x0 SAM G53G19 Rev B 0X247E_0AE1 0x0 SAM G53N19 Rev B 0X247E_0AE9 0x0 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 479 26.3 Chip Identifier (CHIPID) User Interface Table 26-2. Offset 480 Register Mapping Register Name 0x0 Chip ID Register 0x4 Chip ID Extension Register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Access Reset CHIPID_CIDR Read-only – CHIPID_EXID Read-only – 26.3.1 Chip ID Register Name: CHIPID_CIDR Address: 0x400E0740 Access: Read-only 31 EXT 30 23 22 29 NVPTYP 28 21 20 27 26 19 18 ARCH 15 14 13 6 EPROC 24 17 16 9 8 1 0 SRAMSIZ 12 11 NVPSIZ2 7 25 ARCH 10 NVPSIZ 5 4 3 2 VERSION • VERSION: Version of the Device Current version of the device. • EPROC: Embedded Processor Value Name Description 0 SAM x7 Cortex-M7 1 ARM946ES ARM946ES 2 ARM7TDMI ARM7TDMI 3 CM3 Cortex-M3 4 ARM920T ARM920T 5 ARM926EJS ARM926EJS 6 CA5 Cortex-A5 7 CM4 Cortex-M4 • NVPSIZ: Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 – Reserved 5 64K 64 Kbytes 6 – Reserved 7 128K 128 Kbytes 8 160K 160 Kbytes 9 256K 256 Kbytes 10 512K 512 Kbytes SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 481 Value Name Description 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved • NVPSIZ2: Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 – Reserved 5 64K 64 Kbytes 6 – Reserved 7 128K 128 Kbytes 8 – Reserved 9 256K 256 Kbytes 10 512K 512 Kbytes 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved • SRAMSIZ: Internal SRAM Size Value 482 Name Description 0 48K 48 Kbytes 1 192K 192 Kbytes 2 384K 384 Kbytes 3 6K 6 Kbytes 4 24K 24 Kbytes 5 4K 4 Kbytes 6 80K 80 Kbytes 7 160K 160 Kbytes 8 8K 8 Kbytes 9 16K 16 Kbytes 10 32K 32 Kbytes 11 64K 64 Kbytes SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Value Name Description 12 128K 128 Kbytes 13 256K 256 Kbytes 14 96K 96 Kbytes 15 512K 512 Kbytes • ARCH: Architecture Identifier Value Name Description 0x47 SAM G53 SAM G53 0x66 SAM4CxxE SAM4CxE (144-pin version) • NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 2 FLASH Embedded Flash Memory ROM and Embedded Flash Memory 3 ROM_FLASH NVPSIZ is ROM size NVPSIZ2 is Flash size 4 SRAM SRAM emulating ROM • EXT: Extension Flag 0: Chip ID has a single register definition without extension. 1: An extended Chip ID exists. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 483 26.3.2 Chip ID Extension Register Name: CHIPID_EXID Address: 0x400E0744 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension This field is cleared if CHIPID_CIDR.EXT = 0. 484 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27. Parallel Input/Output Controller (PIO) 27.1 Description The Parallel Input/Output Controller (PIO) manages up to 25 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This ensures effective optimization of the pins of the product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. Each I/O line of the PIO Controller features: An input change interrupt enabling level change detection on any I/O line. Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O line. A glitch filter providing rejection of glitches lower than one-half of peripheral clock cycle. A debouncing filter providing rejection of unwanted pulses from key or push button operations. Multi-drive capability similar to an open drain I/O line. Control of the pull-up and pull-down of the I/O line. Input visibility and output control. The PIO Controller also features a synchronous output providing up to 25 bits of data output in a single write operation. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 485 27.2 486 Embedded Characteristics Up to 25 Programmable I/O Lines Fully Programmable through Set/Clear Registers Multiplexing of Four Peripheral Functions per I/O Line For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O) ̶ Input Change Interrupt ̶ Programmable Glitch Filter ̶ Programmable Debouncing Filter ̶ Multi-drive Option Enables Driving in Open Drain ̶ Programmable Pull-Up on Each I/O Line ̶ Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time ̶ Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or HighLevel Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write Register Write Protection Programmable Schmitt Trigger Inputs SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.3 Block Diagram Figure 27-1. Block Diagram PIO Controller Interrupt Controller PMC PIO Interrupt Peripheral Clock Data, Enable Up to x peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Embedded Peripheral x is an integer representing the maximum number of IOs managed by one PIO controller. 27.4 Up to x peripheral IOs PIN x-1 APB Product Dependencies 27.4.1 Pin Multiplexing Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e., not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. 27.4.2 External Interrupt Lines When the WKUPx input pins must be used as external interrupt lines, the PIO Controller must be configured to disable the peripheral control on these IOs, and the corresponding IO lines must be set to Input mode. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 487 27.4.3 Power Management The Power Management Controller controls the peripheral clock in order to save power. Writing any of the registers of the user interface does not require the peripheral clock to be enabled. This means that the configuration of the I/O lines does not require the peripheral clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch filtering. Note that the input change interrupt, the interrupt modes on a programmable event and the read of the pin level require the clock to be validated. After a hardware reset, the peripheral clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. 27.4.4 Interrupt Sources For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the Peripheral Identifiers table to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO Controller requires the Interrupt Controller to be programmed first. The PIO Controller interrupt can be generated only if the peripheral clock is enabled. Table 27-1. 488 Peripheral IDs Instance ID PIOA 11 PIOB 12 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.5 Functional Description The PIO Controller features up to 25 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 27-2. In this description each signal shown represents one of up to 25 possible indexes. Figure 27-2. I/O Line Control Logic PIO_OER[0] VDD PIO_OSR[0] PIO_PUER[0] PIO_ODR[0] PIO_PUSR[0] PIO_PUDR[0] 1 Peripheral A Output Enable 00 01 10 11 Peripheral B Output Enable Peripheral C Output Enable Peripheral D Output Enable 0 0 PIO_PER[0] PIO_ABCDSR1[0] PIO_PDR[0] 00 01 10 11 Peripheral B Output Peripheral C Output Peripheral D Output 1 PIO_PSR[0] PIO_ABCDSR2[0] Peripheral A Output Integrated Pull-Up Resistor PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 0 0 PIO_SODR[0] 1 PIO_ODSR[0] Pad PIO_CODR[0] 1 PIO_PPDER[0] Integrated Pull-Down Resistor PIO_PPDSR[0] PIO_PPDDR[0] GND Peripheral A Input Peripheral B Input Peripheral C Input Peripheral D Input PIO_PDSR[0] PIO_ISR[0] 0 D Peripheral Clock 0 Slow Clock PIO_SCDR Clock Divider div_slck 1 Programmable Glitch or Debouncing Filter Q DFF D Q DFF EVENT DETECTOR (Up to 32 possible inputs) PIO Interrupt 1 Peripheral Clock Resynchronization Stage PIO_IER[0] PIO_IMR[0] PIO_IFER[0] PIO_IDR[0] PIO_IFSR[0] PIO_IFSCER[0] PIO_IFDR[0] PIO_IFSCSR[0] PIO_IFSCDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] 27.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing to the Pull-up Enable Register (PIO_PUER) or Pull-up Disable Register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in the Pull-up Status Register (PIO_PUSR). Reading a one in PIO_PUSR means the pull-up is disabled and reading a zero means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing the Pull-down Enable Register (PIO_PPDER) or the Pull-down Disable Register (PIO_PPDDR), respectively. Writing in these SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 489 registers results in setting or clearing the corresponding bit in the Pull-down Status Register (PIO_PPDSR). Reading a one in PIO_PPDSR means the pull-up is disabled and reading a zero means the pull-down is enabled. Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. In this case, the write of PIO_PUER for the relevant I/O line is discarded. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, depending on the I/O, pull-up or pull-down can be set. 27.5.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable Register (PIO_PER) and the Disable Register (PIO_PDR). The Status Register (PIO_PSR) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the ABCD Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO Controller. If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns a one for the corresponding bit. After reset, the I/O lines are controlled by the PIO Controller, i.e., PIO_PSR resets at one. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset, or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the device. 27.5.3 Peripheral A or B or C or D Selection The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by writing PIO_ABCDSR1 and PIO_ABCDSR2. For each pin: The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral A is selected. The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral B is selected. The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2 means peripheral C is selected. The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2 means peripheral D is selected. Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are always connected to the pin input (see Figure 27-2). Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2 in addition to a write in PIO_PDR. After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. If the software selects a peripheral A, B, C or D which does not exist for a pin, no alternate functions are enabled for this pin and the selection is taken into account. The PIO Controller does not carry out checks to prevent selection of a peripheral which does not exist. 490 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.5.4 Output Control When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 determines whether the pin is driven or not. When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing the Output Enable Register (PIO_OER) and Output Disable Register (PIO_ODR). The results of these write operations are detected in the Output Status Register (PIO_OSR). When a bit in this register is at zero, the corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the PIO Controller. The level driven on an I/O line can be determined by writing in the Set Output Data Register (PIO_SODR) and the Clear Output Data Register (PIO_CODR). These write operations, respectively, set and clear the Output Data Status Register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 27.5.5 Synchronous Data Output Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by using PIO_SODR and PIO_CODR. It requires two successive write operations into two different registers. To overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only bits unmasked by the Output Write Status Register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set by writing to the Output Write Enable Register (PIO_OWER) and cleared by writing to the Output Write Disable Register (PIO_OWDR). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 27.5.6 Multi-Drive Control (Open Drain) Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The multi-drive feature is controlled by the Multi-driver Enable Register (PIO_MDER) and the Multi-driver Disable Register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or assigned to a peripheral function. The Multi-driver Status Register (PIO_MDSR) indicates the pins that are configured to support external drivers. After reset, the multi-drive feature is disabled on all pins, i.e., PIO_MDSR resets at value 0x0. 27.5.7 Output Line Timings Figure 27-3 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 27-3 also shows when the feedback in the Pin Data Status Register (PIO_PDSR) is available. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 491 Figure 27-3. Output Line Timings Peripheral clock Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 27.5.8 Inputs The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 27.5.9 Input Glitch and Debouncing Filters Optional input glitch and debouncing filters are independently programmable on each I/O line. The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock. The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock Disable Register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable Register (PIO_IFSCER). Writing PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status Register (PIO_IFSCSR). The current selection status can be checked by reading the PIO_IFSCSR. If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period. If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable divided slow clock period. For the debouncing filter, the period of the divided slow clock is defined by writing in the DIV field of the Slow Clock Divider Debouncing Register (PIO_SCDR): tdiv_slck = ((DIV + 1) × 2) × tslck When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle (selected clock represents peripheral clock or divided slow clock depending on PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of one selected clock (peripheral clock or divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock cycle and one selected clock cycle, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle. The filters also introduce some latencies, illustrated in Figure 27-4 and Figure 27-5. 492 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 The glitch filters are controlled by the Input Filter Enable Register (PIO_IFER), the Input Filter Disable Register (PIO_IFDR) and the Input Filter Status Register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters require that the peripheral clock is enabled. Figure 27-4. Input Glitch Filter Timing PIO_IFCSR = 0 Peripheral clcok up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles up to 2.5 cycles PIO_PDSR if PIO_IFSR = 1 Figure 27-5. 1 cycle up to 2 cycles Input Debouncing Filter Timing PIO_IFCSR = 1 Divided Slow Clock (div_slck) Pin Level up to 2 cycles tperipheral clock up to 2 cycles tperipheral clock PIO_PDSR if PIO_IFSR = 0 1 cycle tdiv_slck PIO_PDSR if PIO_IFSR = 1 1 cycle tdiv_slck up to 1.5 cycles tdiv_slck up to 1.5 cycles tdiv_slck up to 2 cycles tperipheral clock up to 2 cycles tperipheral clock 27.5.10 Input Edge/Level Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level interrupt is controlled by writing the Interrupt Enable Register (PIO_IER) and the Interrupt Disable Register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and clearing the corresponding bit in the Interrupt Mask Register (PIO_IMR). As input change detection is possible only by comparing two successive samplings of the input of the I/O line, the peripheral clock must be enabled. The Input Change interrupt is available regardless of the configuration of the I/O line, i.e., configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. By default, the interrupt can be generated at any time an edge is detected on the input. Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable Register (PIO_AIMER) and Additional Interrupt Modes Disable Register (PIO_AIMDR). The current state of this selection can be read through the Additional Interrupt Modes Mask Register (PIO_AIMMR). These additional modes are: SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 493 Rising edge detection Falling edge detection Low-level detection High-level detection In order to select an additional interrupt mode: The type of event detection (edge or level) must be selected by writing in the Edge Select Register (PIO_ESR) and Level Select Register (PIO_LSR) which select, respectively, the edge and level detection. The current status of this selection is accessible through the Edge/Level Status Register (PIO_ELSR). The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the Falling Edge/Low-Level Select Register (PIO_FELLSR) and Rising Edge/High-Level Select Register (PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or highor low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible through the Fall/Rise - Low/High Status Register (PIO_FRLHSR). When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status Register (PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The interrupt signals of the 25 channels are ORed-wired together to generate a single interrupt signal to the interrupt controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed. 494 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 27-6. Event Detector on Input Lines (Figure Represents Line 0) Event Detector Rising Edge Detector 1 Falling Edge Detector 0 0 PIO_REHLSR[0] 1 PIO_FRLHSR[0] Resynchronized input on line 0 Event detection on line 0 1 PIO_FELLSR[0] 0 High Level Detector 1 Low Level Detector 0 PIO_LSR[0] PIO_ELSR[0] PIO_AIMER[0] PIO_ESR[0] PIO_AIMMR[0] PIO_AIMDR[0] Edge Detector Example of interrupt generation on following lines: Rising edge on PIO line 0 Falling edge on PIO line 1 Rising edge on PIO line 2 Low-level on PIO line 3 High-level on PIO line 4 High-level on PIO line 5 Falling edge on PIO line 6 Rising edge on PIO line 7 Any edge on the other lines Table 27-2 provides the required configuration for this example. Table 27-2. Configuration for Example Interrupt Generation Configuration Description All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Interrupt Mode Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. Edge or Level Detection The other lines are configured in edge detection by default, if they have not been previously configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32’h0000_00C7 in PIO_ESR. Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR. Falling/Rising Edge or Low/High-Level Detection Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing 32’h0000_00B5 in PIO_REHLSR. The other lines are configured in falling edge or low-level detection by default if they have not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in falling edge/low-level detection by writing 32’h0000_004A in PIO_FELLSR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 495 Figure 27-7. Input Change Interrupt Timings When No Additional Interrupt Modes Peripheral clock Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 27.5.11 Programmable Schmitt Trigger It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the Schmitt trigger is requested when using the QTouch® Library. 27.5.12 I/O Lines Programming Example The programming example shown in Table 27-3 is used to obtain the following configuration: 4-bit output port on I/O lines 0 to 3 (should be written in a single write operation), open-drain, with pull-up resistor Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor, no pull-down resistor Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor I/O lines 24 to 27 assigned to peripheral C with input change interrupt, no pull-up resistor and no pull-down resistor I/O lines 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor Table 27-3. 496 Programming Example Register Value to be Written PIO_PER 0x0000_FFFF PIO_PDR 0xFFFF_0000 PIO_OER 0x0000_00FF PIO_ODR 0xFFFF_FF00 PIO_IFER 0x0000_0F00 PIO_IFDR 0xFFFF_F0FF PIO_SODR 0x0000_0000 PIO_CODR 0x0FFF_FFFF PIO_IER 0x0F00_0F00 PIO_IDR 0xF0FF_F0FF SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 27-3. Programming Example (Continued) PIO_MDER 0x0000_000F PIO_MDDR 0xFFFF_FFF0 PIO_PUDR 0xFFF0_00F0 PIO_PUER 0x000F_FF0F PIO_PPDDR 0xFF0F_FFFF PIO_PPDER 0x00F0_0000 PIO_ABCDSR1 0xF0F0_0000 PIO_ABCDSR2 0xFF00_0000 PIO_OWER 0x0000_000F PIO_OWDR 0x0FFF_ FFF0 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 497 27.5.13 Register Write Protection To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PIO Write Protection Mode Register (PIO_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the PIO Write Protection Status Register (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PIO_WPSR. The following registers can be write-protected: 498 PIO Enable Register PIO Disable Register PIO Output Enable Register PIO Output Disable Register PIO Input Filter Enable Register PIO Input Filter Disable Register PIO Multi-driver Enable Register PIO Multi-driver Disable Register PIO Pull-Up Disable Register PIO Pull-Up Enable Register PIO Peripheral ABCD Select Register 1 PIO Peripheral ABCD Select Register 2 PIO Output Write Enable Register PIO Output Write Disable Register PIO Pad Pull-Down Disable Register PIO Pad Pull-Down Enable Register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32-bit wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns one systematically. Table 27-4. Register Mapping Offset Register Name Access Reset 0x0000 PIO Enable Register PIO_PER Write-only – 0x0004 PIO Disable Register PIO_PDR Write-only – Read-only (1) – – 0x0008 PIO Status Register PIO_PSR 0x000C Reserved – 0x0010 Output Enable Register PIO_OER Write-only – 0x0014 Output Disable Register PIO_ODR Write-only – 0x0018 Output Status Register PIO_OSR Read-only 0x00000000 0x001C Reserved – – – 0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only – 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only – 0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x00000000 0x002C Reserved – – – 0x0030 Set Output Data Register PIO_SODR Write-only – 0x0034 Clear Output Data Register PIO_CODR Write-only 0x0038 Output Data Status Register PIO_ODSR Read-only or(2) Read/Write – 0x003C Pin Data Status Register PIO_PDSR Read-only (3) 0x0040 Interrupt Enable Register PIO_IER Write-only – 0x0044 Interrupt Disable Register PIO_IDR Write-only – 0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000 (4) 0x004C Interrupt Status Register PIO_ISR Read-only 0x00000000 0x0050 Multi-driver Enable Register PIO_MDER Write-only – 0x0054 Multi-driver Disable Register PIO_MDDR Write-only – 0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000 0x005C Reserved – – – 0x0060 Pull-up Disable Register PIO_PUDR Write-only – 0x0064 Pull-up Enable Register PIO_PUER Write-only – 0x0068 Pad Pull-up Status Register PIO_PUSR Read-only (1) 0x006C Reserved – – – SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 499 Table 27-4. Register Mapping (Continued) Offset Register Name Access Reset 0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read/Write 0x00000000 0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read/Write 0x00000000 0x0078–0x007C Reserved – – – 0x0080 Input Filter Slow Clock Disable Register PIO_IFSCDR Write-only – 0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only – 0x0088 Input Filter Slow Clock Status Register PIO_IFSCSR Read-only 0x00000000 0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read/Write 0x00000000 0x0090 Pad Pull-down Disable Register PIO_PPDDR Write-only – 0x0094 Pad Pull-down Enable Register PIO_PPDER Write-only – Read-only (1) – – 0x0098 Pad Pull-down Status Register PIO_PPDSR 0x009C Reserved – 0x00A0 Output Write Enable PIO_OWER Write-only – 0x00A4 Output Write Disable PIO_OWDR Write-only – 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 0x00AC Reserved – – – 0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write-only – 0x00B4 Additional Interrupt Modes Disable Register PIO_AIMDR Write-only – 0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x00000000 0x00BC Reserved – – – 0x00C0 Edge Select Register PIO_ESR Write-only – 0x00C4 Level Select Register PIO_LSR Write-only – 0x00C8 Edge/Level Status Register PIO_ELSR Read-only 0x00000000 0x00CC Reserved – – – 0x00D0 Falling Edge/Low-Level Select Register PIO_FELLSR Write-only – 0x00D4 Rising Edge/High-Level Select Register PIO_REHLSR Write-only – 0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-only 0x00000000 0x00DC Reserved – – – 0x00E0 Reserved – – – 0x00E4 Write Protection Mode Register PIO_WPMR Read/Write 0x00000000 0x00E8 Write Protection Status Register PIO_WPSR Read-only 0x00000000 0x00EC–0x00FC Reserved – – – 0x0100 Schmitt Trigger Register PIO_SCHMITT Read/Write 0x00000000 0x0104–0x010C Reserved – – – 0x0110 Reserved – – – 0x0114–0x011C Reserved – – – 0x0120–0x014C Reserved Notes: 1. Reset value depends on the product implementation. 500 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 – – – 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. If an offset is not listed in the table it must be considered as reserved. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 501 27.6.1 PIO Enable Register Name: PIO_PER Address: 0x400E0E00 (PIOA), 0x400E1000 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: PIO Enable 0: No effect. 1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 502 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.2 PIO Disable Register Name: PIO_PDR Address: 0x400E0E04 (PIOA), 0x400E1004 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: PIO Disable 0: No effect. 1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 503 27.6.3 PIO Status Register Name: PIO_PSR Address: 0x400E0E08 (PIOA), 0x400E1008 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active). 1: PIO is active on the corresponding I/O line (peripheral is inactive). 504 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.4 PIO Output Enable Register Name: PIO_OER Address: 0x400E0E10 (PIOA), 0x400E1010 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Output Enable 0: No effect. 1: Enables the output on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 505 27.6.5 PIO Output Disable Register Name: PIO_ODR Address: 0x400E0E14 (PIOA), 0x400E1014 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Output Disable 0: No effect. 1: Disables the output on the I/O line. 506 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.6 PIO Output Status Register Name: PIO_OSR Address: 0x400E0E18 (PIOA), 0x400E1018 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 507 27.6.7 PIO Input Filter Enable Register Name: PIO_IFER Address: 0x400E0E20 (PIOA), 0x400E1020 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Input Filter Enable 0: No effect. 1: Enables the input glitch filter on the I/O line. 508 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.8 PIO Input Filter Disable Register Name: PIO_IFDR Address: 0x400E0E24 (PIOA), 0x400E1024 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Input Filter Disable 0: No effect. 1: Disables the input glitch filter on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 509 27.6.9 PIO Input Filter Status Register Name: PIO_IFSR Address: 0x400E0E28 (PIOA), 0x400E1028 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Filter Status 0: The input glitch filter is disabled on the I/O line. 1: The input glitch filter is enabled on the I/O line. 510 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.10 PIO Set Output Data Register Name: PIO_SODR Address: 0x400E0E30 (PIOA), 0x400E1030 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 511 27.6.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0x400E0E34 (PIOA), 0x400E1034 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Clear Output Data 0: No effect. 1: Clears the data to be driven on the I/O line. 512 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.12 PIO Output Data Status Register Name: PIO_ODSR Address: 0x400E0E38 (PIOA), 0x400E1038 (PIOB) Access: Read-only or Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Data Status 0: The data to be driven on the I/O line is 0. 1: The data to be driven on the I/O line is 1. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 513 27.6.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0x400E0E3C (PIOA), 0x400E103C (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1. 514 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.14 PIO Interrupt Enable Register Name: PIO_IER Address: 0x400E0E40 (PIOA), 0x400E1040 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Change Interrupt Enable 0: No effect. 1: Enables the input change interrupt on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 515 27.6.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0x400E0E44 (PIOA), 0x400E1044 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Change Interrupt Disable 0: No effect. 1: Disables the input change interrupt on the I/O line. 516 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.16 PIO Interrupt Mask Register Name: PIO_IMR Address: 0x400E0E48 (PIOA), 0x400E1048 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Change Interrupt Mask 0: Input change interrupt is disabled on the I/O line. 1: Input change interrupt is enabled on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 517 27.6.17 PIO Interrupt Status Register Name: PIO_ISR Address: 0x400E0E4C (PIOA), 0x400E104C (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Input Change Interrupt Status 0: No input change has been detected on the I/O line since PIO_ISR was last read or since reset. 1: At least one input change has been detected on the I/O line since PIO_ISR was last read or since reset. 518 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.18 PIO Multi-driver Enable Register Name: PIO_MDER Address: 0x400E0E50 (PIOA), 0x400E1050 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0-P31: Multi-drive Enable 0: No effect. 1: Enables multi-drive on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 519 27.6.19 PIO Multi-driver Disable Register Name: PIO_MDDR Address: 0x400E0E54 (PIOA), 0x400E1054 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Multi-drive Disable 0: No effect. 1: Disables multi-drive on the I/O line. 520 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.20 PIO Multi-driver Status Register Name: PIO_MDSR Address: 0x400E0E58 (PIOA), 0x400E1058 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Multi-drive Status 0: The multi-drive is disabled on the I/O line. The pin is driven at high- and low-level. 1: The multi-drive is enabled on the I/O line. The pin is driven at low-level only. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 521 27.6.21 PIO Pull-Up Disable Register Name: PIO_PUDR Address: 0x400E0E60 (PIOA), 0x400E1060 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Pull-Up Disable 0: No effect. 1: Disables the pull-up resistor on the I/O line. 522 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.22 PIO Pull-Up Enable Register Name: PIO_PUER Address: 0x400E0E64 (PIOA), 0x400E1064 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Pull-Up Enable 0: No effect. 1: Enables the pull-up resistor on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 523 27.6.23 PIO Pull-Up Status Register Name: PIO_PUSR Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Pull-Up Status 0: Pull-up resistor is enabled on the I/O line. 1: Pull-up resistor is disabled on the I/O line. 524 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Peripheral Select If the same bit is set to 0 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral B function. If the same bit is set to 1 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral C function. 1: Assigns the I/O line to the Peripheral D function. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 525 27.6.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Address: 0x400E0E70 (PIOA), 0x400E1070 (PIOB) Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Peripheral Select If the same bit is set to 0 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral C function. If the same bit is set to 1 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral B function. 1: Assigns the I/O line to the Peripheral D function. 526 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Address: 0x400E0E80 (PIOA), 0x400E1080 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Peripheral Clock Glitch Filtering Select 0: No effect. 1: The glitch filter is able to filter glitches with a duration < tperipheral clock/2. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 527 27.6.27 PIO Input Filter Slow Clock Enable Register Name: PIO_IFSCER Address: 0x400E0E84 (PIOA), 0x400E1084 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Slow Clock Debouncing Filtering Select 0: No effect. 1: The debouncing filter is able to filter pulses with a duration < tdiv_slck/2. 528 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.28 PIO Input Filter Slow Clock Status Register Name: PIO_IFSCSR Address: 0x400E0E88 (PIOA), 0x400E1088 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Glitch or Debouncing Filter Selection Status 0: The glitch filter is able to filter glitches with a duration < tperipheral clock/2. 1: The debouncing filter is able to filter pulses with a duration < tdiv_slck/2. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 529 27.6.29 PIO Slow Clock Divider Debouncing Register Name: PIO_SCDR Address: 0x400E0E8C (PIOA), 0x400E108C (PIOB) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 2 1 0 – – 7 6 DIV 5 4 3 DIV • DIV: Slow Clock Divider Selection for Debouncing tdiv_slck = ((DIV + 1) × 2) × tslck 530 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.30 PIO Pad Pull-Down Disable Register Name: PIO_PPDDR Address: 0x400E0E90 (PIOA), 0x400E1090 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Pull-Down Disable 0: No effect. 1: Disables the pull-down resistor on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 531 27.6.31 PIO Pad Pull-Down Enable Register Name: PIO_PPDER Address: 0x400E0E94 (PIOA), 0x400E1094 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Pull-Down Enable 0: No effect. 1: Enables the pull-down resistor on the I/O line. 532 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.32 PIO Pad Pull-Down Status Register Name: PIO_PPDSR Address: 0x400E0E98 (PIOA), 0x400E1098 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Pull-Down Status 0: Pull-down resistor is enabled on the I/O line. 1: Pull-down resistor is disabled on the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 533 27.6.33 PIO Output Write Enable Register Name: PIO_OWER Address: 0x400E0EA0 (PIOA), 0x400E10A0 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Output Write Enable 0: No effect. 1: Enables writing PIO_ODSR for the I/O line. 534 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.34 PIO Output Write Disable Register Name: PIO_OWDR Address: 0x400E0EA4 (PIOA), 0x400E10A4 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. • P0–P31: Output Write Disable 0: No effect. 1: Disables writing PIO_ODSR for the I/O line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 535 27.6.35 PIO Output Write Status Register Name: PIO_OWSR Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Output Write Status 0: Writing PIO_ODSR does not affect the I/O line. 1: Writing PIO_ODSR affects the I/O line. 536 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.36 PIO Additional Interrupt Modes Enable Register Name: PIO_AIMER Address: 0x400E0EB0 (PIOA), 0x400E10B0 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Additional Interrupt Modes Enable 0: No effect. 1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 537 27.6.37 PIO Additional Interrupt Modes Disable Register Name: PIO_AIMDR Address: 0x400E0EB4 (PIOA), 0x400E10B4 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Additional Interrupt Modes Disable 0: No effect. 1: The interrupt mode is set to the default interrupt mode (both-edge detection). 538 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.38 PIO Additional Interrupt Modes Mask Register Name: PIO_AIMMR Address: 0x400E0EB8 (PIOA), 0x400E10B8 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: IO Line Index Selects the IO event type triggering an interrupt. 0: The interrupt source is a both-edge detection event. 1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 539 27.6.39 PIO Edge Select Register Name: PIO_ESR Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Edge Interrupt Selection 0: No effect. 1: The interrupt source is an edge-detection event. 540 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.40 PIO Level Select Register Name: PIO_LSR Address: 0x400E0EC4 (PIOA), 0x400E10C4 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Level Interrupt Selection 0: No effect. 1: The interrupt source is a level-detection event. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 541 27.6.41 PIO Edge/Level Status Register Name: PIO_ELSR Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Edge/Level Interrupt Source Selection 0: The interrupt source is an edge-detection event. 1: The interrupt source is a level-detection event. 542 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.42 PIO Falling Edge/Low-Level Select Register Name: PIO_FELLSR Address: 0x400E0ED0 (PIOA), 0x400E10D0 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Falling Edge/Low-Level Interrupt Selection 0: No effect. 1: The interrupt source is set to a falling edge detection or low-level detection event, depending on PIO_ELSR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 543 27.6.43 PIO Rising Edge/High-Level Select Register Name: PIO_REHLSR Address: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Rising Edge/High-Level Interrupt Selection 0: No effect. 1: The interrupt source is set to a rising edge detection or high-level detection event, depending on PIO_ELSR. 544 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.44 PIO Fall/Rise - Low/High Status Register Name: PIO_FRLHSR Address: 0x400E0ED8 (PIOA), 0x400E10D8 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0–P31: Edge/Level Interrupt Source Selection 0: The interrupt source is a falling edge detection (if PIO_ELSR = 0) or low-level detection event (if PIO_ELSR = 1). 1: The interrupt source is a rising edge detection (if PIO_ELSR = 0) or high-level detection event (if PIO_ELSR = 1). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 545 27.6.45 PIO Write Protection Mode Register Name: PIO_WPMR Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII). See Section 27.5.13 “Register Write Protection” for the list of registers that can be protected. • WPKEY: Write Protection Key Value Name 0x50494F PASSWD 546 Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 27.6.46 PIO Write Protection Status Register Name: PIO_WPSR Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PIO_WPSR. 1: A write protection violation has occurred since the last read of the PIO_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 547 27.6.47 PIO Schmitt Trigger Register Name: PIO_SCHMITT Address: 0x400E0F00 (PIOA), 0x400E1100 (PIOB) Access: Read/Write 31 30 29 28 27 26 25 24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 23 22 21 20 19 18 17 16 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 15 14 13 12 11 10 9 8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8 7 6 5 4 3 2 1 0 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0 • SCHMITTx [x=0..31]: Schmitt Trigger Control 0: Schmitt trigger is enabled. 1: Schmitt trigger is disabled. 548 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 28. Serial Peripheral Interface (SPI) 28.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a Shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (multiple master protocol, contrary to single master protocol where one CPU is always the master while all of the others are always slaves). One master can simultaneously shift data into multiple slaves. However, only one slave can drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: 28.2 Master Out Slave In (MOSI)—This data line supplies the output data from the master shifted into the input(s) of the slave(s). Master In Slave Out (MISO)—This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. Serial Clock (SPCK)—This control line is driven by the master and regulates the flow of the data bits. The master can transmit data at a variety of baud rates; there is one SPCK pulse for each bit that is transmitted. Slave Select (NSS)—This control line allows slaves to be turned on and off by hardware. Embedded Characteristics Master or Slave Serial Peripheral Bus Interface 8-bit to 16-bit programmable data length per chip select ̶ Programmable phase and polarity per chip select ̶ Programmable transfer delay between consecutive transfers and delay before SPI clock per chip select ̶ ̶ ̶ Programmable delay between chip selects Selectable mode fault detection Master Mode can drive SPCK up to Peripheral Clock Master Mode Bit Rate can be Independent of the Processor/Peripheral Clock Slave mode operates on SPCK, asynchronously with core and bus clock Two chip selects with external decoder support allow communication with up to 3 peripherals Communication with Serial External Devices Supported ̶ ̶ Serial memories, such as DataFlash and 3-wire EEPROMs ̶ Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and sensors External coprocessors Connection to PDC Channel Capabilities, Optimizing Data Transfers ̶ One channel for the receiver ̶ One channel for the transmitter Register Write Protection SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 549 28.3 Block Diagram Figure 28-1. Block Diagram AHB Matrix PDC Peripheral bridge Trigger events Bus clock PMC 28.4 Peripheral clock SPI Application Block Diagram Figure 28-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS NPCS1 Slave 0 SPCK MISO Slave 1 MOSI NSS 550 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 28.5 Signal Description Table 28-1. Signal Description Type 28.6 Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1 Peripheral Chip Select Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input Product Dependencies 28.6.1 I/O Lines The pins used for interfacing the compliant external devices can be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. Table 28-2. I/O Lines Instance Signal I/O Line Peripheral SPI MISO PA12 A SPI MOSI PA13 A SPI NPCS0 PA11 A SPI NPCS1 PA5 B SPI NPCS1 PB2 B SPI SPCK PA14 A 28.6.2 Power Management The SPI can be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. 28.6.3 Interrupt The SPI interface has an interrupt line connected to the interrupt controller. Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI. Table 28-3. Peripheral IDs Instance ID SPI 21 28.6.4 Peripheral DMA Controller (PDC) The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full description of the PDC, refer to the relevant section. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 551 28.7 Functional Description 28.7.1 Modes of Operation The SPI operates in Master mode or in Slave mode. The SPI operates in Master mode by writing a 1 to the MSTR bit in the SPI Mode Register (SPI_MR): ̶ Pins NPCS0 to NPCS1 are all configured as outputs ̶ The SPCK pin is driven ̶ The MISO line is wired on the receiver input ̶ The MOSI line is driven as an output by the transmitter. The SPI operates in Slave mode if the MSTR bit in the SPI_MR is written to 0: ̶ The MISO line is driven by the transmitter output ̶ The MOSI line is wired on the receiver input ̶ The SPCK pin is driven by the transmitter to synchronize the receiver. ̶ The NPCS0 pin becomes an input, and is used as a slave select signal (NSS) ̶ Pin NPCS1 is not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operation. The baud rate generator is activated only in Master mode. 28.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the SPI Chip Select register (SPI_CSR). The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Consequently, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are connected and require different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 28-4 shows the four modes and corresponding parameter settings. Table 28-4. SPI Bus Protocol Modes SPI Mode CPOL NCPHA Shift SPCK Edge Capture SPCK Edge SPCK Inactive Level 0 0 1 Falling Rising Low 1 0 0 Rising Falling Low 2 1 1 Rising Falling High 3 1 0 Falling Rising High Figure 28-3 and Figure 28-4 show examples of data transfers. 552 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 28-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined. Figure 28-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 5 8 7 6 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) * Not defined. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 553 28.7.3 Master Mode Operations When configured in Master mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register (SPI_TDR) and the Receive Data Register (SPI_RDR), and a single shift register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer starts when the processor writes to the SPI_TDR. The written data is immediately transferred in the Shift register and the transfer on the SPI bus starts. While the data in the Shift register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift register. Data cannot be loaded in the SPI_RDR without transmitting data. If there is no data to transmit, dummy data can be used (SPI_TDR filled with ones). When the SPI_MR.WDRBT bit is set, new data cannot be transmitted if the SPI_RDR has not been read. If Receiving mode is not required, for example when communicating with a slave receiver only (such as an LCD), the receive status flags in the SPI Status register (SPI_SR) can be discarded. Before writing the SPI_TDR, the PCS field in the SPI_MR must be set in order to select a slave. If new data is written in the SPI_TDR during the transfer, it is kept in the SPI_TDR until the current transfer is completed. Then, the received data is transferred from the Shift register to the SPI_RDR, the data in the SPI_TDR is loaded in the Shift register and a new transfer starts. As soon as the SPI_TDR is written, the Transmit Data Register Empty (TDRE) flag in the SPI_SR is cleared. When the data written in the SPI_TDR is loaded into the Shift register, the TDRE flag in the SPI_SR is set. The TDRE bit is used to trigger the Transmit PDC channel. See Figure 28-5. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of this delay. The peripheral clock can be switched off at this time. Note: Figure 28-5. When the SPI is enabled, the TDRE and TXEMPTY flags are set. TDRE and TXEMPTY flag behavior Write SPI_CR.SPIEN =1 TDRE Write SPI_TDR Write SPI_TDR automatic set TDR loaded in shifter Write SPI_TDR automatic set TDR loaded in shifter automatic set TDR loaded in shifter TXEMPTY Transfer Transfer DLYBCT Transfer DLYBCT DLYBCT The transfer of received data from the Shift register to the SPI_RDR is indicated by the Receive Data Register Full (RDRF) bit in the SPI_SR. When the received data is read, the RDRF bit is cleared. If the SPI_RDR has not been read before new data is received, the Overrun Error (OVRES) bit in the SPI_SR is set. As long as this flag is set, data is loaded in the SPI_RDR. The user has to read the SPI_SR to clear the OVRES bit. Figure 28-6 shows a block diagram of the SPI when operating in Master mode. Figure 28-7 shows a flow chart describing how transfers are handled. 554 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 28.7.3.1 Master Mode Block Diagram Figure 28-6. Master Mode Block Diagram SPI_CSRx SCBR Baud Rate Generator Peripheral clock SPCK SPI Clock SPI_CSRx BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSRx SPI_RDR CSAAT PCS PS NPCSx PCSDEC SPI_MR PCS 0 Current Peripheral SPI_TDR NPCS0 PCS 1 MSTR MODF NPCS0 MODFDIS SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 555 28.7.3.2 Master Mode Flow Diagram Figure 28-7. Master Mode Flow Diagram SPI Enable TDRE/TXEMPTY are set TDRE ? (SW check) 0 1 Write SPI_TDR ? - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - ‘x <= y’ must be interpreted as ‘x is loaded with y’ where x,y represent either register fields or SPI pins - HW = hardware, SW = software no yes TDRE/TXEMPTY are cleared CSAAT ? (HW check) 1 PS ? (HW check) 0 1 PS ? (HW check) 1 0 Fixed peripheral Variable peripheral NPCS <= SPI_TDR(PCS) Fixed peripheral 0 Variable peripheral SPI_TDR(PCS) = NPCS ? (HW check) yes SPI_MR(PCS) = NPCS ? (HW check) no NPCS <= SPI_MR(PCS) no NPCS deasserted NPCS deasserted Delay DLYBCS Delay DLYBCS NPCS <= SPI_TDR(PCS) NPCS <= SPI_MR(PCS), SPI_TDR(PCS) Delay DLYBS Shifter <= SPI_TDR(TD) TDRE is set Data Transfer (SPI bus driven) From this step, SPI_TDR can be rewritten for the next transfer SPI_RDR(RD) <= Shifter RDRF is set if read is required Read SPI_RDR(RD) Delay DLYBCT TDRE ? (HW check) 1 TXEMPTY is set 1 CSAAT ? (HW check) 0 NPCS deasserted Delay DLYBCS 556 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 0 (i.e. a new write to SPI_TDR occured while data transfer or delay DLYBCT) Figure 28-8 shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags within the SPI_SR during an 8-bit data transfer in Fixed mode without the PDC involved. Figure 28-8. Status Register Flags Behavior 1 2 3 4 6 5 7 8 SPCK NPCS0 MOSI (from master) MSB 6 5 4 3 2 1 LSB TDRE RDR read Write in SPI_TDR RDRF MISO (from slave) MSB 6 5 4 3 2 1 LSB TXEMPTY shift register empty Figure 28-9 shows the behavior of Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags within the SPI_SR during an 8-bit data transfer in Fixed mode with the PDC involved. The PDC is programmed to transfer and receive three units of data. The next pointer and counter are not used. The RDRF and TDRE are not shown because these flags are managed by the PDC when using the PDC. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 557 Figure 28-9. PDC Status Register Flags Behavior 1 3 2 SPCK NPCS0 MOSI MSB (from master) MISO MSB (from slave) 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB TDRE (not required if PDC is used) PDC loads first byte PDC loads 2nd byte (double buffer effect) PDC loads last byte ENDTX ENDRX TXBUFE RXBUFF TXEMPTY 28.7.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the peripheral clock by a value between 1 and 255. If the SCBR field in the SPI_CSR is programmed to 1, the operating baud rate is peripheral clock (see the electrical characteristics section for the SPCK maximum frequency). Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it to a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 28.7.3.4 Transfer Delays Figure 28-10 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: Delay between the chip selects—programmable only once for all chip selects by writing the DLYBCS field in the SPI_MR. The SPI slave device deactivation delay is managed through DLYBCS. If there is only one SPI slave device connected to the master, the DLYBCS field does not need to be configured. If several slave devices are connected to a master, DLYBCS must be configured depending on the highest deactivation delay. Refer to the SPI slave device electrical characteristics. Delay before SPCK—independently programmable for each chip select by writing the DLYBS field. The SPI slave device activation delay is managed through DLYBS. Refer to the SPI slave device electrical characteristics to define DLYBS. Delay between consecutive transfers—independently programmable for each chip select by writing the DLYBCT field. The time required by the SPI slave device to process received data is managed through DLYBCT. This time depends on the SPI slave system activity. These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. 558 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 28-10. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS 28.7.3.5 DLYBS DLYBCT DLYBCT Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS1 signals. By default, all NPCS signals are high before and after each transfer. Fixed Peripheral Select Mode: SPI exchanges data with only one peripheral. Fixed Peripheral Select mode is enabled by writing the PS bit to zero in the SPI_MR. In this case, the current peripheral is defined by the PCS field in the SPI_MR and the PCS field in the SPI_TDR has no effect. Variable Peripheral Select Mode: Data can be exchanged with more than one peripheral without having to reprogram the NPCS field in the SPI_MR. Variable Peripheral Select mode is enabled by setting the PS bit to 1 in the SPI_MR. The PCS field in the SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR has the following format: [xxxxxxx(7-bit) + LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals the chip select to assert, as defined in Section 28.8.4 “SPI Transmit Data Register” and LASTXFER bit at 0 or 1 depending on the CSAAT bit. Note: 1. Optional CSAAT, LASTXFER and CSNAAT bits are discussed in Section 28.7.3.9 “Peripheral Deselection with PDC”. If LASTXFER is used, the command must be issued after writing the last character. Instead of LASTXFER, the user can use the SPIDIS command. After the end of the PDC transfer, it is necessary to wait for the TXEMPTY flag and then write SPIDIS into the SPI Control Register (SPI_CR). This does not change the configuration register values). The NPCS is disabled after the last character transfer. Then, another PDC transfer can be started if the SPIEN has previously been written in the SPI_CR. 28.7.3.6 SPI Peripheral DMA Controller (PDC) In both Fixed and Variable Peripheral Select modes, the Peripheral DMA Controller (PDC) can be used to reduce processor overhead. The fixed peripheral selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, if the peripheral selection is modified, the SPI_MR must be reprogrammed. The variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming the SPI_MR. Data written in the SPI_TDR is 32 bits wide and defines the real data to be transmitted and the destination peripheral. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs. However, the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers (SPI_CSRx). This is not the SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 559 optimal means in terms of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. Transfer Size Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer size it has to point to. The PDC performs the following transfer, depending on the mode and number of bits per data. 28.7.3.7 Fixed mode: ̶ 8-bit data: 1-Byte transfer, PDC pointer address = address + 1 byte, PDC counter = counter - 1 ̶ 9-bit to 16-bit data: 2-Byte transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s, PDC pointer address = address + 2 bytes, PDC counter = counter - 1 Variable mode: ̶ In Variable mode, PDC pointer address = address +4 bytes and PDC counter = counter - 1 for 8 to 16bit transfer size. ̶ When using the PDC, the TDRE and RDRF flags are handled by the PDC. The user’s application does not have to check these bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF), TX Buffer Empty (TXBUFE) are significant. For further details about the Peripheral DMA Controller and user interface, refer to the PDC section. Peripheral Chip Select Decoding The user can program the SPI to operate with up to 3 slave peripherals by decoding the two chip select lines, NPCS0 to NPCS1 with an external decoder/demultiplexer (refer to Figure 28-11). This can be enabled by writing a 1 to the PCSDEC bit in the SPI_MR. When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field on the NPCS lines of either SPI_MR or SPI_TDR (depending on PS). As the SPI sets a default value of 0x3 on the chip select lines (i.e., all chip select lines at 1) when not processing any transfer, only 3 peripherals can be decoded. The SPI has two Chip Select registers. As a result, when external decoding is activated, each NPCS chip select defines the characteristics of up to two peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 1, corresponding to the PCS values 0x0 to 0x1. Consequently, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 1 and 2. Figure 28-11 shows this type of implementation. If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This is not required for all other chip select lines since mode fault detection is only on NPCS0. 560 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 28-11. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI Slave 0 Slave 1 Slave 2 NSS NSS NSS SPI Master NPCS0 NPCS1 External 1-of-n Decoder/Demultiplexer 28.7.3.8 Peripheral Deselection without PDC During a transfer of more than one unit of data on a Chip Select without the PDC, the SPI_TDR is loaded by the processor, the TDRE flag rises as soon as the content of the SPI_TDR is transferred into the internal Shift register. When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep the chip select active (low). A null DLYBCT value (delay between consecutive transfers) in the SPI_CSR, gives even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, if the chip select line must remain active (low) during a full set of transfers, communication errors can occur. To facilitate interfacing with such devices, the Chip Select registers [CSR0...CSR1] can be programmed with the Chip Select Active After Transfer (CSAAT) bit to 1. This allows the chip select lines to remain in their current state (low = active) until a transfer to another chip select is required. Even if the SPI_TDR is not reloaded, the chip select remains active. To de-assert the chip select line at the end of the transfer, the Last Transfer (LASTXFER) bit in SPI_CR must be set after writing the last data to transmit into SPI_TDR. 28.7.3.9 Peripheral Deselection with PDC PDC provides faster reloads of the SPI_TDR compared to software. However, depending on the system activity, it is not guaranteed that the SPI_TDR is written with the next data before the end of the current transfer. Consequently, data can be lost by the de-assertion of the NPCS line for SPI slave peripherals requiring the chip select line to remain active between two transfers. The only way to guarantee a safe transfer in this case is the use of the CSAAT and LASTXFER bits. When the CSAAT bit is configured to 0, the NPCS does not rise in all cases between two transfers on the same peripheral. During a transfer on a Chip Select, the TDRE flag rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is detected, the SPI_TDR can be reloaded. If this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. This can lead to difficulties to interface with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the SPI_CSR can be programmed with the Chip Select Not Active After Transfer SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 561 (CSNAAT) bit to 1. This allows the chip select lines to be de-asserted systematically during a time “DLYBCS” (the value of the CSNAAT bit is processed only if the CSAAT bit is configured to 0 for the same chip select). Figure 28-12 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits. Figure 28-12. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..n] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..n] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..n] DLYBCT DLYBCT A B A B DLYBCS DLYBCS PCS = B PCS = B Write SPI_TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE NPCS[0..n] A A A A DLYBCS PCS = A PCS = A Write SPI_TDR 28.7.3.10 Mode Fault Detection The SPI has the capability to operate in multi-master environment. Consequently, the NPCS0/NSS line must be monitored. If one of the masters on the SPI bus is currently transmitting, the NPCS0/NSS line is low and the SPI must not transmit any data. A mode fault is detected when the SPI is programmed in Master mode and a low level is driven by an external master on the NPCS0/NSS signal. In multi-master environment, NPCS0, MOSI, MISO and 562 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 SPCK pins must be configured in open drain (through the PIO controller). When a mode fault is detected, the SPI_SR.MODF bit is set until SPI_SR is read and the SPI is automatically disabled until it is re-enabled by writing a 1 to the SPI_CR.SPIEN bit. By default, the mode fault detection is enabled. The user can disable it by setting the SPI_MR.MODFDIS bit. 28.7.4 SPI Slave Mode When operating in Slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits until NSS goes active before receiving the serial clock from an external master. When NSS falls, the clock is validated and the data is loaded in the SPI_RDR depending on the BITS field configured in the SPI_CSR0. These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits in the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select registers have no effect when the SPI is programmed in Slave mode. The bits are shifted out on the MISO line and sampled on the MOSI line. Note: For more information on the BITS field, see also the note below the SPI_CSRx register bitmap (Section 28.8.9 “SPI Chip Select Register”). When all bits are processed, the received data is transferred in the SPI_RDR and the RDRF bit rises. If the SPI_RDR has not been read before new data is received, the Overrun Error Status (OVRES) bit in the SPI_SR is set. As long as this flag is set, data is loaded in the SPI_RDR. The user must read SPI_SR to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift register. If no data has been written in the SPI_TDR, the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift register resets to 0. When a first data is written in the SPI_TDR, it is transferred immediately in the Shift register and the TDRE flag rises. If new data is written, it remains in the SPI_TDR until a transfer occurs, i.e., NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in the SPI_TDR is transferred in the Shift register and the TDRE flag rises. This enables frequent updates of critical variables with single transfers. Then, new data is loaded in the Shift register from the SPI_TDR. If no character is ready to be transmitted, i.e., no character has been written in the SPI_TDR since the last load from the SPI_TDR to the Shift register, the SPI_TDR is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in the SPI_SR. Figure 28-13 shows a block diagram of the SPI when operating in Slave mode. Figure 28-13. Slave Mode Functional Block Diagram SPCK NSS SPI Clock SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RDRF OVRES RD MSB Shift Register MISO SPI_TDR TD TDRE SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 563 28.7.5 Register Write Protection To prevent any single software error from corrupting SPI behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the SPI Write Protection Status Register (SPI_WPSR) is set and the WPVSRC field indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading SPI_WPSR. The following registers can be write-protected: 564 SPI Mode Register SPI Chip Select Register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 28.8 Serial Peripheral Interface (SPI) User Interface Table 28-5. Register Mapping Offset Register Name Access Reset 0x00 Control Register SPI_CR Write-only – 0x04 Mode Register SPI_MR Read/Write 0x0 0x08 Receive Data Register SPI_RDR Read-only 0x0 0x0C Transmit Data Register SPI_TDR Write-only – 0x10 Status Register SPI_SR Read-only 0x000000F0 0x14 Interrupt Enable Register SPI_IER Write-only – 0x18 Interrupt Disable Register SPI_IDR Write-only – 0x1C Interrupt Mask Register SPI_IMR Read-only 0x0 Reserved – – – 0x30 Chip Select Register 0 SPI_CSR0 Read/Write 0x0 0x34 Chip Select Register 1 SPI_CSR1 Read/Write 0x0 0x38–0x3C Reserved – – – 0x40-0x48 Reserved – – – 0x4C–0xE0 Reserved – – – 0xE4 Write Protection Mode Register SPI_WPMR Read/Write 0x0 0xE8 Write Protection Status Register SPI_WPSR Read-only 0x0 0xEC–0xF8 Reserved – – – 0xFC Reserved – – – Reserved for PDC Registers – – – 0x20–0x2C 0x100–0x124 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 565 28.8.1 SPI Control Register Name: SPI_CR Address: 0x40008000 Access: Write-only 31 30 29 28 27 26 25 24 FIFODIS FIFOEN – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – RXFCLR TXFCLR 15 14 13 12 11 10 9 8 – – – REQCLR – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0: No effect. 1: Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0: No effect. 1: Disables the SPI. All pins are set in Input mode after completion of the transmission in progress, if any. If a transfer is in progress when SPIDIS is set, the SPI completes the transmission of the shifter register and does not start any new transfer, even if the SPI_THR is loaded. Note: If both SPIEN and SPIDIS are equal to one when the SPI_CR is written, the SPI is disabled. • SWRST: SPI Software Reset 0: No effect. 1: Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in Slave mode after software reset. PDC channels are not affected by software reset. • REQCLR: Request to Clear the Comparison Trigger 0: No effect. 1: Restarts the comparison trigger to enable SPI_RDR loading. • TXFCLR: Transmit FIFO Clear 0: No effect. 1: Clears the Transmit FIFO, Transmit FIFO will become empty. • RXFCLR: Receive FIFO Clear 0: No effect. 1: Clears the Receive FIFO, Receive FIFO will become empty. 566 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • LASTXFER: Last Transfer 0: No effect. 1: The current NPCS is de-asserted after the character written in TD has been transferred. When SPI_CSRx.CSAAT is set, the communication with the current serial peripheral can be closed by raising the corresponding NPCS line as soon as TD transfer is completed. Refer to Section 28.7.3.5 “Peripheral Selection” for more details. • FIFOEN: FIFO Enable 0: No effect. 1: Enables the Transmit and Receive FIFOs • FIFODIS: FIFO Disable 0: No effect. 1: Disables the Transmit and Receive FIFOs SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 567 28.8.2 SPI Mode Register Name: SPI_MR Address: 0x40008004 Access: Read/Write 31 30 29 28 27 26 25 17 24 DLYBCS 23 22 21 20 19 18 – – – – – – 16 15 14 13 12 11 10 9 8 – – – - – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register. • MSTR: Master/Slave Mode 0: SPI is in Slave mode 1: SPI is in Master mode • PS: Peripheral Select 0: Fixed Peripheral Select 1: Variable Peripheral Select • PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The two NPCS chip select lines are connected to a 2-bit to 4-bit decoder. When PCSDEC = 1, up to 3 Chip Select signals can be generated with the two NPCS lines using an external 2-bit to 4-bit decoder. The Chip Select registers define the characteristics of the 3 chip selects, with the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 1. SPI_CSR1 defines peripheral chip select signal 2. • MODFDIS: Mode Fault Detection 0: Mode fault detection enabled 1: Mode fault detection disabled • WDRBT: Wait Data Read Before Transfer 0: No Effect. In Master mode, a transfer can be initiated regardless of the SPI_RDR state. 1: In Master mode, a transfer can start only if the SPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. • LLB: Local Loopback Enable 0: Local loopback path disabled. 1: Local loopback path enabled. 568 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 LLB controls the local loopback on the data shift register for testing in Master mode only (MISO is internally connected on MOSI). • PCS: Peripheral Chip Select This field is only used if fixed peripheral select is active (PS = 0). If SPI_MR.PCSDEC = 0: PCS = x0 NPCS[1:0] = 10 PCS = 01 NPCS[1:0] = 01 PCS = 11 forbidden (no peripheral is selected) (x = don’t care) If SPI_MR.PCSDEC = 1: NPCS[1:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay between the inactivation and the activation of NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is lower than 6, six peripheral clock periods are inserted by default. Otherwise, the following equation determines the delay: : DLYBCS Delay Between Chip Selects = --------------------------------f peripheral clock SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 569 28.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0x40008008 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register in a right-justified format. Unused bits are read as zero. • PCS: Peripheral Chip Select In Master mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits are read as zero. Note: When using Variable Peripheral Select mode (PS = 1 in SPI_MR), it is mandatory to set the SPI_MR.WDRBT bit to 1 if the PCS field must be processed in SPI_RDR. 570 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 28.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0x4000800C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. • PCS: Peripheral Chip Select This field is only used if variable peripheral select is active (PS = 1). If SPI_MR.PCSDEC = 0: PCS = x0 NPCS[1:0] = 10 PCS = 01 NPCS[1:0] = 01 PCS = 11 forbidden (no peripheral is selected) (x = don’t care) If SPI_MR.PCSDEC = 1: NPCS[1:0] output signals = PCS. • LASTXFER: Last Transfer 0: No effect 1: The current NPCS is de-asserted after the transfer of the character written in TD. When SPI_CSRx.CSAAT is set, the communication with the current serial peripheral can be closed by raising the corresponding NPCS line as soon as TD transfer is completed. This field is only used if variable peripheral select is active (SPI_MR.PS = 1). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 571 28.8.5 SPI Status Register Name: SPI_SR Address: 0x40008010 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – SPIENS 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full (cleared by reading SPI_RDR) 0: No data has been received since the last read of SPI_RDR. 1: Data has been received and the received data has been transferred from the shift register to SPI_RDR since the last read of SPI_RDR. • TDRE: Transmit Data Register Empty (cleared by writing SPI_TDR) 0: Data has been written to SPI_TDR and not yet transferred to the shift register. 1: The last data written in the SPI_TDR has been transferred to the shift register. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to 1. • MODF: Mode Fault Error (cleared on read) 0: No mode fault has been detected since the last read of SPI_SR. 1: A mode fault occurred since the last read of SPI_SR. • OVRES: Overrun Error Status (cleared on read) 0: No overrun has been detected since the last read of SPI_SR. 1: An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the shift register since the last read of the SPI_RDR. • ENDRX: End of RX Buffer (cleared by writing SPI_RCR or SPI_RNCR) 0: The Receive Counter register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1: The Receive Counter register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). • ENDTX: End of TX Buffer (cleared by writing SPI_TCR or SPI_TNCR) 0: The Transmit Counter register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1: The Transmit Counter register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). • RXBUFF: RX Buffer Full (cleared by writing SPI_RCR or SPI_RNCR) 0: SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1: Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0. 572 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • TXBUFE: TX Buffer Empty (cleared by writing SPI_TCR or SPI_TNCR) 0: SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1: Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising (cleared on read) 0: No rising edge detected on NSS pin since the last read of SPI_SR. 1: A rising edge occurred on NSS pin since the last read of SPI_SR. • TXEMPTY: Transmission Registers Empty (cleared by writing SPI_TDR) 0: As soon as data is written in SPI_TDR. 1: SPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set after the end of this delay. • UNDES: Underrun Error Status (Slave mode only) (cleared on read) 0: No underrun has been detected since the last read of SPI_SR. 1: A transfer starts whereas no data has been loaded in SPI_TDR. • SPIENS: SPI Enable Status 0: SPI is disabled. 1: SPI is enabled. Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are PDC registers. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 573 28.8.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0x40008014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. • RDRF: Receive Data Register Full Interrupt Enable • TDRE: SPI Transmit Data Register Empty Interrupt Enable • MODF: Mode Fault Error Interrupt Enable • OVRES: Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable • NSSR: NSS Rising Interrupt Enable • TXEMPTY: Transmission Registers Empty Enable • UNDES: Underrun Error Interrupt Enable 574 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 28.8.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0x40008018 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. • RDRF: Receive Data Register Full Interrupt Disable • TDRE: SPI Transmit Data Register Empty Interrupt Disable • MODF: Mode Fault Error Interrupt Disable • OVRES: Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable • NSSR: NSS Rising Interrupt Disable • TXEMPTY: Transmission Registers Empty Disable • UNDES: Underrun Error Interrupt Disable SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 575 28.8.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0x4000801C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. • RDRF: Receive Data Register Full Interrupt Mask • TDRE: SPI Transmit Data Register Empty Interrupt Mask • MODF: Mode Fault Error Interrupt Mask • OVRES: Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask • NSSR: NSS Rising Interrupt Mask • TXEMPTY: Transmission Registers Empty Mask • UNDES: Underrun Error Interrupt Mask 576 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 28.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..1] Address: 0x40008030 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT CSNAAT NCPHA CPOL This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register. Note: SPI_CSRx registers must be written even if the user wants to use the default reset values. The BITS field is not updated with the translated value unless the register is written. • CPOL: Clock Polarity 0: The inactive state value of SPCK is logic level zero. 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. • NCPHA: Clock Phase 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains inactive after the end of transfer for a minimal duration of: DLYBCS --------------------------------(If field DLYBCS is lower than 6, a minimum of six periods is introduced.) f peripheral clock • CSAAT: Chip Select Active After Transfer 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. • BITS: Bits Per Transfer (See the note below the register bitmap.) SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 577 The BITS field determines the number of data bits transferred. Reserved values should not be used. Value Name Description 0 8_BIT 8 bits for transfer 1 9_BIT 9 bits for transfer 2 10_BIT 10 bits for transfer 3 11_BIT 11 bits for transfer 4 12_BIT 12 bits for transfer 5 13_BIT 13 bits for transfer 6 14_BIT 14 bits for transfer 7 15_BIT 15 bits for transfer 8 16_BIT 16 bits for transfer 9 – Reserved 10 – Reserved 11 – Reserved 12 – Reserved 13 – Reserved 14 – Reserved 15 – Reserved • SCBR: Serial Clock Bit Rate In Master mode, the SPI Interface uses a modulus counter to derive the SPCK bit rate from the peripheral clock. The bit rate is selected by writing a value from1 to 255 in the SCBR field. The following equation determines the SPCK bit rate: SCBR = fperipheral clock / SPCK Bit Rate Programming the SCBR field to 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. If BRSRCCLK = 1 in SPI_MR, SCBR must be programmed with a value greater than 1. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. Note: If one of the SCBR fields in SPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are used to process transfers. If they are not used to transfer data, they can be set at any value. • DLYBS: Delay Before SPCK This field defines the delay from NPCS falling edge (activation) to the first valid SPCK transition. When DLYBS = 0, the delay is half the SPCK clock period. Otherwise, the following equation determines the delay: DLYBS = Delay Before SPCK × fperipheral clock • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT = 0, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: DLYBCT = Delay Between Consecutive Transfers × fperipheral clock / 32 578 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 28.8.10 SPI Write Protection Mode Register Name: SPI_WPMR Address: 0x400080E4 Access: Read/Write. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x535049 (“SPI” in ASCII) 1: Enables the write protection if WPKEY corresponds to 0x535049 (“SPI” in ASCII) See Section 28.7.5 “Register Write Protection” for the list of registers that can be write-protected. • WPKEY: Write Protection Key Value 0x535049 Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 579 28.8.11 SPI Write Protection Status Register Name: SPI_WPSR Address: 0x400080E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of SPI_WPSR. 1: A write protection violation has occurred since the last read of SPI_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. 580 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29. Two-wire Interface (TWIHS) 29.1 Description The Atmel Two-wire Interface (TWIHS) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s in Fast mode and up to 3.4 Mbit/s in High-speed slave mode only, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C-compatible devices, such as a Real-Time Clock (RTC), Dot Matrix/Graphic LCD Controller and temperature sensor. The TWIHS is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Table 29-1 lists the compatibility level of the Atmel Two-wire Interface in Master mode and a full I2C compatible device. Atmel TWI Compatibility with I2C Standard Table 29-1. I2C Standard Atmel TWI Standard Mode Speed (100 kHz) Supported Fast Mode Speed (400 kHz) Supported High-speed Mode (Slave only, 3.4 MHz) Supported (1) 7- or 10-bit Slave Addressing (2) START Byte Not Supported Repeated Start (Sr) Condition Supported ACK and NACK Management Supported Input Filtering Supported Slope Control Not Supported Clock Stretching Supported Multi Master Capability Supported Notes: 29.2 Supported 1. 2. 10-bit support in Master mode only START + b000000001 + Ack + Sr Embedded Characteristics 1 TWIHS Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices(1) One, Two or Three Bytes for Slave Address Sequential Read/Write Operations Master and Multi-master Operation (Standard and Fast Mode Only) Slave Mode Operation (Standard, Fast and High-Speed Mode) Bit Rate: Up to 400 kbit/s in Fast Mode and 3.4 Mbit/s in High-Speed Mode (Slave Only) General Call Supported in Slave Mode SleepWalking (Asynchronous and Partial Wake-up) SMBus Quick Command Supported in Master Mode Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers Register Write Protection ̶ Note: 1. One Channel for the Receiver, One Channel for the Transmitter See Table 29-1 for details on compatibility with I²C Standard. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 581 29.3 List of Abbreviations Table 29-2. Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write 29.4 Block Diagram Figure 29-1. Block Diagram APB Bridge TWCK PIO PMC Peripheral Clock TWD Two-wire Interface TWIHS Interrupt Interrupt Controller 29.4.1 I/O Lines Description Table 29-3. I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 582 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.5 Product Dependencies 29.5.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWIHS, the user must program the PIO Controller to dedicate TWD and TWCK as peripheral lines. When High-speed Slave mode is enabled, the analog pad filter must be enabled. The user must not program TWD and TWCK as open-drain. This is already done by the hardware. Table 29-4. I/O Lines Instance Signal I/O Line Peripheral TWI0 TWCK0 PA4 A TWI0 TWD0 PA3 A 29.5.2 Power Management Enable the peripheral clock. The TWIHS may be clocked through the Power Management Controller (PMC), thus the user must first configure the PMC to enable the TWIHS clock. 29.5.3 Interrupt Sources The TWIHS has an interrupt line connected to the Interrupt Controller. In order to handle inter-rupts, the Interrupt Controller must be programmed before configuring the TWIHS. Table 29-5. Peripheral IDs Instance ID TWI0 19 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 583 29.6 Functional Description 29.6.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited. See Figure 29-3. Each transfer begins with a START condition and terminates with a STOP condition. See Figure 29-2. A high-to-low transition on the TWD line while TWCK is high defines the START condition. A low-to-high transition on the TWD line while TWCK is high defines the STOP condition. Figure 29-2. START and STOP Conditions TWD TWCK Start Figure 29-3. Stop Transfer Format TWD TWCK Start Address R/W Ack Data Ack 29.6.2 Modes of Operation The TWIHS has different modes of operation: Master Transmitter mode (Standard and Fast modes only) Master Receiver mode (Standard and Fast modes only) Multi-master Transmitter mode (Standard and Fast modes only) Multi-master Receiver mode (Standard and Fast modes only) Slave Transmitter mode (Standard, Fast and High-speed modes) Slave Receiver mode (Standard, Fast and High-speed modes) These modes are described in the following sections. 584 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Data Ack Stop 29.6.3 Master Mode 29.6.3.1 Definition The master is the device that starts a transfer, generates a clock and stops it. This operating mode is not available if High-speed mode is selected. 29.6.3.2 Programming Master Mode The following registers must be programmed before entering Master mode: 1. TWIHS_MMR.DADR (+ IADRSZ + IADR if a 10-bit device is addressed): The device address is used to access slave devices in Read or Write mode. 2. TWIHS_CWGR.CKDIV + CHDIV + CLDIV: Clock Waveform register 3. TWIHS_CR.SVDIS: Disables the Slave mode 4. TWIHS_CR.MSEN: Enables the Master mode Note: 29.6.3.3 If the TWIHS is already in Master mode, the device address (DADR) can be configured without disabling the Master mode. Master Transmitter Mode This operating mode is not available if High-speed mode is selected. After the master initiates a START condition when writing into the Transmit Holding register (TWIHS_THR), it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWIHS_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWIHS_MMR). The TWIHS transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. If the slave does not acknowledge the byte, then the Not Acknowledge flag (NACK) is set in the TWIHS Status Register (TWIHS_SR) of the master and a STOP condition is sent. The NACK flag must be cleared by reading TWIHS_SR before the next write into TWIHS_THR. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable register (TWIHS_IER). If the slave acknowledges the byte, the data written in the TWIHS_THR is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the TWIHS_THR. TXRDY is used as Transmit Ready for the PDC transmit channel. While no new data is written in the TWIHS_THR, the serial clock line is tied low. When new data is written in the TWIHS_THR, the SCL is released and the data is sent. Setting the STOP bit in TWIHS_CR generates a STOP condition. After a master write transfer, the serial clock line is stretched (tied low) as long as no new data is written in the TWIHS_THR or until a STOP command is performed. To clear the TXRDY flag, first set the bit TWIHS_CR.MSDIS, then set the bit TWIHS_CR.MSEN. See Figure 29-4, Figure 29-5, and Figure 29-6. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 585 Figure 29-4. Master Write with One Data Byte STOP Command sent (write in TWIHS_CR) S TWD DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 29-5. Master Write with Multiple Data Bytes STOP command performed (by writing in the TWIHS_CR) S TWD DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Figure 29-6. Write THR (Data n+2) Last data sent Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWIHS_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) 586 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Write THR (Data n+2) Last data sent A P 29.6.3.4 Master Receiver Mode Master Receiver mode is not available if High-speed mode is selected. The read sequence begins by setting the START bit. After the START condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWIHS_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the TWIHS_SR if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data (see Figure 29-7). When the RXRDY bit is set in the TWIHS_SR, a character has been received in the Receive Holding register (TWIHS_RHR). The RXRDY bit is reset when reading the TWIHS_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 29-7. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-to-last data received (same condition applies for START bit to generate a REPEATED START). See Figure 29-8. For internal address usage, see Section 29.6.3.5 ”Internal Address”. If TWIHS_RHR is full (RXRDY high) and the master is receiving data, the serial clock line is tied low before receiving the last bit of the data and until the TWIHS_RHR is read. Once the TWIHS_RHR is read, the master stops stretching the serial clock line and ends the data reception. See Figure 29-9. Warning: When receiving multiple bytes in Master Read mode, if the next-to-last access is not read (the RXRDY flag remains high), the last access is not completed until TWIHS_RHR is read. The last access stops on the nextto-last bit (clock stretching). When the TWIHS_RHR is read, there is only half a bit period to send the STOP (or START) command, else another read access might occur (spurious access). A possible workaround is to set the STOP (or START) bit before reading the TWIHS_RHR on the next-to-last access (within IT handler). Figure 29-7. Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 587 Figure 29-8. TWD Master Read with Multiple Data Bytes S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read Figure 29-9. Master Read Clock Stretching with Multiple Data Bytes STOP command performed (by writing in the TWIHS_CR) Clock Streching TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP RXRDY Read RHR (Data n) Read RHR (Data n+1) Read RHR (Data n+2) RXRDY is used as receive ready for the PDC receive channel. 29.6.3.5 Internal Address The TWIHS can perform transfers with 7-bit slave address devices and with 10-bit slave address devices. 7-bit Slave Addressing When addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, e.g. within a memory page location in a serial memory. When performing read operations with an internal address, the TWIHS performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second START condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 2911. See Figure 29-10 and Figure 29-12 for the master write operation with internal address. The three internal address bytes are configurable through TWIHS_MMR. If the slave device supports only a 7-bit address, i.e., no internal address, IADRSZ must be set to 0. 588 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 29-6 shows the abbreviations used in Figure 29-10 and Figure 29-11. Table 29-6. Abbreviations Abbreviation Definition S Start Sr Repeated Start P Stop W Write R Read A Acknowledge NA Not Acknowledge DADR Device Address IADR Internal Address Figure 29-10. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address TWD S DADR P One byte internal address TWD S DADR P Figure 29-11. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA N P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A Sr W A IADR(7:0) A Sr R A DADR R A DATA N P One byte internal address TWD S DADR DADR DATA N P 10-bit Slave Addressing For a slave address higher than seven bits, configure the address size (IADRSZ) and set the other slave address bits in the Internal Address register (TWIHS_IADR). The two remaining internal address bytes, IADR[15:8] and IADR[23:16], can be used the same way as in 7-bit slave addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) 3. Program TWIHS_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 29-12 shows a byte write to a memory device. This demonstrates the use of internal addresses to access the device. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 589 Figure 29-12. Internal Address Usage S T A R T W R I T E Device Address FIRST WORD ADDRESS SECOND WORD ADDRESS S T O P DATA 0 M S B 29.6.3.6 LR A S / C BW K M S B A C K LA SC BK A C K Repeated Start In addition to Internal Address mode, REPEATED START (Sr) can be generated manually by writing the START bit at the end of a transfer instead of the STOP bit. In such case, the parameters of the next transfer (direction, SADR, etc.) need to be set before writing the START bit at the end of the previous transfer. See Section 29.6.3.10 ”Read/Write Flowcharts” for detailed flowcharts. Note that generating a REPEATED START after a single data read is not supported. 29.6.3.7 Bus Clear Command The TWIHS can perform a Bus Clear command: 1. Configure the Master mode (DADR, CKDIV, etc). 2. 29.6.3.8 Start the transfer by setting the CLEAR bit in the TWIHS_CR. Using the Peripheral DMA Controller (PDC) in Master Mode The use of the PDC significantly reduces the CPU load. To ensure correct implementation, follow the programming sequences below: Data Transmit with the PDC in Master Mode The PDC transfer size must be defined with the buffer size minus 1. The remaining character must be managed without PDC to ensure that the exact number of bytes are transmitted regardless of system bus latency conditions during the end of the buffer transfer period. 1. Initialize the transmit PDC (memory pointers, transfer size - 1). 2. Configure the Master mode (DADR, CKDIV, MREAD = 0, etc.). 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC ENDTX flag either by using the polling method or ENDTX interrupt. 5. Disable the PDC by setting the PDC TXTDIS bit. 6. Wait for the TXRDY flag in TWIHS_SR. 7. Set the STOP bit in TWIHS_CR. 8. Write the last character in TWIHS_THR. 9. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWIHS_SR. Data Receive with the PDC in Master Mode The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed without PDC to ensure that the exact number of bytes are received regardless of system bus latency conditions during the end of the buffer transfer period. 1. Initialize the receive PDC (memory pointers, transfer size - 2). 590 2. Configure the Master mode (DADR, CKDIV, MREAD = 1, etc.). 3. Set the PDC RXTEN bit. 4. (Master Only) Write the START bit in the TWIHS_CR to start the transfer. 5. Wait for the PDC ENDRX flag either by using polling method or ENDRX interrupt. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 6. Disable the PDC by setting the PDC RXTDIS bit. 7. Wait for the RXRDY flag in TWIHS_SR. 8. Set the STOP bit in TWIHS_CR to end the transfer. 9. Read the penultimate character in TWIHS_RHR. 10. Wait for the RXRDY flag in TWIHS_SR. 11. Read the last character in TWIHS_RHR. 12. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWIHS_SR. 29.6.3.9 SMBus Quick Command (Master Mode Only) The TWIHS can perform a quick command: 1. Configure the Master mode (DADR, CKDIV, etc). 2. Write the MREAD bit in the TWIHS_MMR at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWIHS_CR. Figure 29-13. SMBus Quick Command TWD S DADR R/W A P TXCOMP TXRDY Write QUICK command in TWIHS_CR 29.6.3.10 Read/Write Flowcharts The flowcharts give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that TWIHS_IER be configured first. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 591 Figure 29-14. TWIHS Write Operation with Single Data Byte without Internal Address BEGIN Set TWIHS clock (CLDIV, CHDIV, CKDIV) in TWIHS_CWGR (Needed only once) Set the Control register: - Master enable TWIHS_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWIHS_THR = Data to send Write STOP Command TWIHS_CR = STOP Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished 592 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 29-15. TWIHS Write Operation with Single Data Byte and Internal Address BEGIN Set TWIHS clock (CLDIV, CHDIV, CKDIV) in TWIHS_CWGR (Needed only once) Set the Control register: - Master enable TWIHS_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWIHS_IADR = address Load transmit register TWIHS_THR = Data to send Write STOP command TWIHS_CR = STOP Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 593 Figure 29-16. TWIHS Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWIHS clock (CLDIV, CHDIV, CKDIV) in TWIHS_CWGR (Needed only once) Set the Control register: - Master enable TWIHS_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWIHS_IADR = address Yes Load Transmit register TWIHS_THR = Data to send Read Status register TWIHS_THR = data to send No TXRDY = 1? Yes Data to send? Yes No Write STOP Command TWIHS_CR = STOP Read Status register No TXCOMP = 1? Yes END 594 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 29-17. TWIHS Write Operation with Multiple Data Bytes and Read Operation with Multiple Data Bytes (Sr) BEGIN Set TWIHS clock (CLDIV, CHDIV, CKDIV) in TWIHS_CWGR (Needed only once) Set the Control register: - Master enable TWIHS_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWIHS_IADR = address Yes Load Transmit register TWIHS_THR = Data to send Read Status register TWIHS_THR = data to send No TXRDY = 1? Yes Data to send ? Yes No Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - TWIHS_IADR = address (if Internal address size = 0) - Transfer direction bit Read ==> bit MREAD = 1 Set the next transfer parameters and send the repeated start command Start the transfer TWIHS_CR = START Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWIHS_RHR) No Last data to read but one? Yes Stop the transfer TWIHS_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWIHS_RHR) Read status register TXCOMP = 1? No Yes END SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 595 Figure 29-18. TWIHS Read Operation with Single Data Byte without Internal Address BEGIN Set TWIHS clock (CLDIV, CHDIV, CKDIV) in TWIHS_CWGR (Needed only once) Set the Control register: - Master enable TWIHS_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWIHS_CR = START | STOP Read status register RXRDY = 1? No Yes Read Receive Holding Register Read Status register No TXCOMP = 1? Yes END 596 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 29-19. TWIHS Read Operation with Single Data Byte and Internal Address BEGIN Set TWIHS clock (CLDIV, CHDIV, CKDIV) in TWIHS_CWGR (Needed only once) Set the Control register: - Master enable TWIHS_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWIHS_IADR = address Start the transfer TWIHS_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 597 Figure 29-20. TWIHS Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWIHS clock (CLDIV, CHDIV, CKDIV) in TWIHS_CWGR (Needed only once) Set the Control register: - Master enable TWIHS_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 No Internal address size = 0? Set the internal address TWIHS_IADR = address Yes Start the transfer TWIHS_CR = START Read Status register RXRDY = 1? No Yes Read Receive Holding register (TWIHS_RHR) No Last data to read but one? Yes Stop the transfer TWIHS_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWIHS_RHR) Read status register TXCOMP = 1? Yes END 598 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 No 29.6.4 Multi-master Mode 29.6.4.1 Definition In Multi-master mode, more than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master that has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 29-22. 29.6.4.2 Different Multi-master Modes Two Multi-master modes may be distinguished: 1. The TWIHS is considered as a master only and is never addressed. 2. Note: The TWIHS may be either a master or a slave and may be addressed. Arbitration in supported in both Multi-master modes. TWIHS as Master Only In this mode, the TWIHS is considered as a master only (MSEN is always at one) and must be driven like a master with the ARBLST (Arbitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the user must reinitiate the data transfer. If starting a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWIHS automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 29-21). Note: The state of the bus (busy or free) is not indicated in the user interface. TWIHS as Master or Slave The automatic reversal from master to slave is not supported in case of a lost arbitration. Then, in the case where TWIHS may be either a master or a slave, the user must manage the pseudo Multi-master mode described in the steps below: 1. Program the TWIHS in Slave mode (SADR + MSDIS + SVEN) and perform a slave access (if TWIHS is addressed). 2. If the TWIHS has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program the Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, the TWIHS scans the bus in order to detect if it is busy or free. When the bus is considered free, the TWIHS initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWIHS in Slave mode in case the master that won the arbitration needs to access the TWIHS. 7. If the TWIHS has to be set in Slave mode, wait until the TXCOMP flag is at 1 and then program the Slave mode. Note: If the arbitration is lost and the TWIHS is addressed, the TWIHS does not acknowledge, even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then the master must repeat SADR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 599 Figure 29-21. User Sends Data While the Bus is Busy TWCK START sent by the TWIHS STOP sent by the master DATA sent by a master TWD DATA sent by the TWIHS Bus is busy Bus is free Transfer is kept TWIHS DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 29-22. Arbitration Cases TWCK TWD TWCK Data from a Master Data from TWIHS TWD S 1 0 0 1 1 S 1 0 S 1 0 0 1 P Arbitration is lost TWIHS stops sending data Data from the master 1 1 P Arbitration is lost S 1 0 1 S 1 0 0 1 1 S 1 0 0 1 1 The master stops sending data Data from the TWIHS ARBLST Bus is busy Transfer is kept TWIHS DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is free Transfer is stopped Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 29-23 gives an example of read and write operations in Multi-master mode. 600 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 29-23. Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? Yes GACC = 1 ? No No No SVREAD = 1 ? Yes No EOSACC = 1 ? TXRDY= 1 ? Yes Yes No Write in TWIHS_THR TXCOMP = 1 ? No RXRDY= 1 ? Yes No No Yes Read TWIHS_RHR Need to perform a master access ? GENERAL CALL TREATMENT Yes Decoding of the programming sequence No Prog seq OK ? Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register Yes No ARBLST = 1 ? Yes Yes No MREAD = 1 ? RXRDY= 0 ? TXRDY= 0 ? No No Read TWIHS_RHR Yes Yes Data to read? Data to send ? Yes Write in TWIHS_THR No No Stop Transfer TWIHS_CR = STOP Read Status Register Yes TXCOMP = 0 ? No SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 601 29.6.5 Slave Mode 29.6.5.1 Definition Slave mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 29.6.5.2 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. TWIHS_SMR.SADR: The slave device address is used in order to be accessed by master devices in Read or Write mode. 2. (Optional) TWIHS_SMR.MASK can be set to mask some SADR address bits and thus allow multiple address matching. 3. TWIHS_CR.MSDIS: Disables the Master mode. 4. TWIHS_CR.SVEN: Enables the Slave mode. As the device receives the clock, values written in TWIHS_CWGR are ignored. 29.6.5.3 Receiving Data After a START or REPEATED START condition is detected, and if the address sent by the master matches the slave address programmed in the SADR (Slave Address) field, the SVACC (Slave Access) flag is set and SVREAD (Slave Read) indicates the direction of the transfer. SVACC remains high until a STOP condition or a REPEATED START is detected. When such a condition is detected, the EOSACC (End Of Slave Access) flag is set. Read Sequence In the case of a read sequence (SVREAD is high), the TWIHS transfers data written in the TWIHS_THR until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWIHS_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the internal shifter is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. Note that a STOP or a REPEATED START always follows a NACK. To clear the TXRDY flag, first set the bit TWIHS_CR.SVDIS, then set the bit TWIHS_CR.SVEN. See Figure 29-24. Write Sequence In the case of a write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWIHS_RHR. RXRDY is reset when reading the TWIHS_RHR. The TWIHS continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence, the TXCOMP flag is set and SVACC is reset. See Figure 29-25. Clock Stretching Sequence If TWIHS_THR or TWIHS_RHR is not written/read in time, the TWIHS performs a clock stretching. Clock stretching information is given by the SCLWS (Clock Wait State) bit. See Figure 29-27 and Figure 29-28. 602 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Note: Clock stretching can be disabled by configuring the SCLWSDIS bit in the TWIHS_SMR. In that case, the UNRE and OVRE flags indicate an underrun (when TWIHS_THR is not filled on time) or an overrun (when TWIHS_RHR is not read on time). General Call In the case where a GENERAL CALL is performed, the GACC (General Call Access) flag is set. After GACC is set, the user must interpret the meaning of the GENERAL CALL and decode the new address programming sequence. See Figure 29-26. 29.6.5.4 Data Transfer Read Operation The Read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, the TWIHS continues sending data loaded in the TWIHS_THR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 29-24 describes the read operation. Figure 29-24. Read Access Ordered by a Master SADR matches, TWIHS answers with an ACK ACK/NACK from the Master SADR does not match, TWIHS answers with a NACK TWD S ADR R NA DATA NA P/S/Sr SADR R A DATA A A DATA NA S/Sr TXRDY NACK Read RHR Write THR SVACC SVREAD SVREAD has to be taken into account only while SVACC is active EOSACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWIHS_THR to the internal shifter and set when this data has been acknowledged or non acknowledged. Write Operation The Write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, the TWIHS stores the received data in the TWIHS_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 29-25 describes the write operation. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 603 Figure 29-25. Write Access Ordered by a Master SADR does not match, TWIHS answers with a NACK TWD S ADR W NA DATA NA SADR matches, TWIHS answers with an ACK P/S/Sr SADR W A DATA Read RHR A A DATA NA S/Sr RXRDY SVACC SVREAD has to be taken into account only while SVACC is active SVREAD EOSACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the internal shifter to the TWIHS_RHR and reset when this data is read. General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of general call, decode the commands that follow. In case of a WRITE command, decode the programming sequence and program a new SADR if the programming sequence matches. Figure 29-26 describes the general call access. Figure 29-26. Master Performs a General Call 0000000 + W TXD S GENERAL CALL RESET command = 00000110X WRITE command = 00000100X A Reset or write DADD A DATA1 A DATA2 A New SADR A P New SADR Programming sequence GACC Reset after read SVACC Note: This method allows the user to create a personal programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. Clock Stretching In both Read and Write modes, it may occur that TWIHS_THR/TWIHS_RHR buffer is not filled/emptied before the transmission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Note: Clock stretching can be disabled by setting the SCLWSDIS bit in the TWIHS_SMR. In that case the UNRE and OVRE flags indicate an underrun (when TWIHS_THR is not filled on time) or an overrun (when TWIHS_RHR is not read on time). Clock Stretching in Read Mode The clock is tied low if the internal shifter is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the internal shifter is loaded. Figure 29-27 describes the clock stretching in Read mode. 604 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 29-27. Clock Stretching in Read Mode TWIHS_THR S R SADR DATA1 1 DATA0 A A DATA0 DATA2 A DATA1 XXXXXXX DATA2 NA S 2 TWCK CLOCK is tied low by the TWIHS as long as THR is empty Write THR SCLWS TXRDY SVACC SVREAD As soon as a START is detected TXCOMP Ack or Nack from the master TWIHS_THR is transmitted to the internal shifter Notes: 1 The data is memorized in TWIHS_THR until a new value is written 2 The clock is stretched after the ACK, the state of TWD is undefined during clock stretching 1. TXRDY is reset when data has been written in the TWIHS_THR to the internal shifter and set when this data has been acknowledged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock stretching mechanism is started. Clock Stretching in Write Mode The clock is tied low if the internal shifter and the TWIHS_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWIHS_RHR is read. Figure 29-28 describes the clock stretching in Write mode. Figure 29-28. Clock Stretching in Write Mode TWCK CLOCK is tied low by the TWIHS as long as RHR is full TWD S SADR W A DATA0 TWIHS_RHR A DATA1 A DATA2 DATA0 is not read in the RHR DATA1 NA S ADR DATA2 SCLWS SCL is stretched after the acknowledge of DATA1 RXRDY Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD TXCOMP Notes: As soon as a START is detected 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the clock stretching mechanism is started and automatically reset when the mechanism is finished. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 605 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 29-29 describes the REPEATED START and the reversal from Read mode to Write mode. Figure 29-29. Repeated Start and Reversal from Read Mode to Write Mode TWIHS_THR TWD DATA0 S SADR R A DATA0 DATA1 A DATA1 NA Sr SADR W A DATA2 TWIHS_RHR A DATA3 DATA2 A P DATA3 SVACC SVREAD TXRDY RXRDY EOSACC Cleared after read As soon as a START is detected TXCOMP Note: 1. TXCOMP is only set at the end of the transmission. This is because after the REPEATED START, SADR is detected again. Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command. Figure 29-30 describes the REPEATED START and the reversal from Write mode to Read mode. Figure 29-30. Repeated Start and Reversal from Write Mode to Read Mode DATA2 TWIHS_THR TWD S SADR W A DATA0 A TWIHS_RHR DATA1 DATA0 A Sr SADR R A DATA3 DATA2 A DATA3 NA P DATA1 SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP Notes: 29.6.5.5 Read TWIHS_RHR Cleared after read As soon as a START is detected 1. In this case, if TWIHS_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission. This is because after the REPEATED START, SADR is detected again. Using the Peripheral DMA Controller (PDC) in Slave Mode The use of the PDC significantly reduces the CPU load. Data Transmit with the PDC in Slave Mode The following procedure shows an example to transmit data with PDC. 606 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 1. Initialize the transmit PDC (memory pointers, transfer size, etc.). 2. Start the transfer by setting the PDC TXTEN bit. 3. Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt. 4. Disable the PDC by setting the PDC TXTDIS bit. 5. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWIHS_SR. Data Receive with the PDC in Slave Mode The following procedure shows an example to transmit data with PDC where the number of characters to receive is known. 1. Initialize the receive PDC (memory pointers, transfer size, etc.). 2. Set the PDC RXTEN bit. 3. Wait for the PDC ENDRX flag either by using polling method or ENDRX interrupt. 4. Disable the PDC by setting the PDC RXTDIS bit. 5. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWIHS_SR. 29.6.5.6 High-Speed Slave Mode High-speed mode is enabled when a one is written to the HSEN bit in the TWIHS_CR. Furthermore, the analog pad filter must be enabled, a one must be written to the PADFEN bit in the TWIHS_FILTR and the FILT bit must be cleared. TWIHS High-speed mode operation is similar to TWIHS operation with the following exceptions: 1. A master code is received first at normal speed before entering High-speed mode period. 2. When TWIHS High-speed mode is active, clock stretching is only allowed after acknowledge (ACK), notacknowledge (NACK), START (S) or REPEATED START (Sr) (as consequence OVF may happen). TWIHS High-speed mode allows transfers of up to 3.4 Mbit/s. The TWIHS slave in High-speed mode requires that slave clock stretching is disabled (SCLWSDIS bit at ‘1’). The peripheral clock must run at a minimum of 11 MHz. Note: Note: When slave clock stretching is disabled, the TWIHS_RHR must always be read before receiving the next data (MASTER write frame). It is strongly recommended to use either the polling method on the RXRDY flag in TWIHS_SR, or the PDC. If the receive is managed by an interrupt, the TWIHS interrupt priority must be set to the right level and its latency minimized to avoid receive overrun. When slave clock stretching is disabled, the TWIHS_THR must be filled with the first data to send before the beginning of the frame (MASTER read frame). It is strongly recommended to use either the polling method on the TXRDY flag in TWIHS_SR, or the PDC. If the transmit is managed by an interrupt, the TWIHS interrupt priority must be set to the right level and its latency minimized to avoid transmit underrun. Read/Write Operation A TWIHS high-speed frame always begins with the following sequence: 1. START condition (S) 2. Master Code (0000 1XXX) 3. Not-acknowledge (NACK) When the TWIHS is programmed in Slave mode and TWIHS High-speed mode is activated, master code matching is activated and internal timings are set to match the TWIHS High-speed mode requirements. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 607 Figure 29-31. High-Speed Mode Read/Write F/S Mode S MASTER CODE HS Mode NA Sr SADR R/W A F/S Mode DATA F/S Mode S MASTER CODE A/NA P F/S Mode HS Mode NA Sr SADR R/W A DATA A/NA Sr SADR P Usage TWIHS High-speed mode usage is the same as the standard TWIHS (See Section 29.6.3.10 ”Read/Write Flowcharts”). 29.6.5.7 Asynchronous Partial Wake-up (SleepWalking) The TWIHS includes an asynchronous start condition detector. It is capable of waking the device up from a Sleep mode upon an address match (and optionally an additional data match), including Sleep modes where the TWIHS peripheral clock is stopped. After detecting the START condition on the bus, the TWIHS stretches TWCK until the TWIHS peripheral clock has started. The time required for starting the TWIHS depends on which Sleep mode the device is in. After the TWIHS peripheral clock has started, the TWIHS releases its TWCK stretching and receives one byte of data (slave address) on the bus. At this time, only a limited part of the device, including the TWIHS module, receives a clock, thus saving power. If the address phase causes a TWIHS address match (and, optionally, if the first data byte causes data match as well), the entire device is waked and normal TWIHS address matching actions are performed. Normal TWIHS transfer then follows. If the TWIHS is not addressed (or if the optional data match fails), the TWIHS peripheral clock is automatically stopped and the device returns to its original Sleep mode. The TWIHS has the capability to match on more than one address. The SADR1EN, SADR2EN and SADR3EN bits in TWIHS_SMR enable address matching on additional addresses which can be configured through SADR1, SADR2 and SADR3 fields in the TWIHS_SWMR. The SleepWalking matching process can be extended to the first received data byte if DATAMEN bit in TWIHS_SMR is set and, in this case, a complete matching includes address matching and first received data matching. The field DATAM in TWIHS_SWMR configures the data to match on the first received byte. When the system is in Active mode and the TWIHS enters Asynchronous Partial Wake-up mode, the flag SVACC must be programmed as the unique source of the TWIHS interrupt and the data match comparison must be disabled. When the system exits Wait mode as the result of a matching condition, the SVACC flag is used to determine if the TWIHS is the source of exit. 608 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 29-32. Address Match Only (Data Matching Disabled) Address Matching Area Clock Stretching SADR S PClk R/W A DATA A/NA DATA A/NA P PClk Startup PClk_request SystemWakeUp_req Figure 29-33. No Address Match (Data Matching Disabled) Address Matching Area Clock Stretching S PClk SADR R/W NA P PClk Startup PClk_request SystemWakeUp_req SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 609 Figure 29-34. Address Match and Data Match (Data Matching Enabled) Address Matching + Data Matching Area Clock Stretching SADR S PClk W A DATA A DATA A/NA P NA DATA NA P PClk Startup PClk_request SystemWakeUp_req Figure 29-35. Address Match and No Data Match (Data Matching Enabled) Address Matching + Data Matching Area Clock Stretching S PClk SADR W A DATA PClk Startup PClk_request SystemWakeUp_req 29.6.5.8 Slave Read Write Flowcharts The flowchart shown in Figure 29-36 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that TWIHS_IER be configured first. 610 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 29-36. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? GACC = 1 ? No No No EOSACC = 1 ? SVREAD = 1 ? TXRDY= 1 ? No No Write in TWIHS_THR No TXCOMP = 1 ? RXRDY= 1 ? No END Read TWIHS_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR 29.6.6 TWIHS Comparison Function on Received Character The comparison function differs if asynchronous partial wake-up (SleepWalking) is enabled or not. If asynchronous partial wake-up is disabled (see the section “Power Management Controller (PMC)”), the TWIHS can extend the address matching on up to three slave addresses. The SADR1EN, SADR2EN and SADR3EN bits in TWIHS_SMR enable address matching on additional addresses which can be configured through SADR1, SADR2 and SADR3 fields in the TWIHS_SWMR. The DATAMEN bit in the TWIHS_SMR has no effect. The SVACC bit is set when there is a comparison match with the received slave address. 29.6.7 Register Write Protection To prevent any single software error from corrupting TWIHS behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the TWIHS Write Protection Mode Register (TWIHS_WPMR). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 611 If a write access to a write-protected register is detected, the WPVS bit in the TWIHS Write Protection Status Register (TWIHS_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the TWIHS_WPSR. The following register(s) can be write-protected: 612 TWIHS Slave Mode Register TWIHS Clock Waveform Generator Register TWIHS SleepWalking Matching Register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7 Two-wire Interface High Speed (TWIHS) User Interface Table 29-7. Register Mapping Offset Register Name Access Reset 0x00 Control Register TWIHS_CR Write-only – 0x04 Master Mode Register TWIHS_MMR Read/Write 0x00000000 0x08 Slave Mode Register TWIHS_SMR Read/Write 0x00000000 0x0C Internal Address Register TWIHS_IADR Read/Write 0x00000000 0x10 Clock Waveform Generator Register TWIHS_CWGR Read/Write 0x00000000 0x14–0x1C Reserved – – – 0x20 Status Register TWIHS_SR Read-only 0x0300F009 0x24 Interrupt Enable Register TWIHS_IER Write-only – 0x28 Interrupt Disable Register TWIHS_IDR Write-only – 0x2C Interrupt Mask Register TWIHS_IMR Read-only 0x00000000 0x30 Receive Holding Register TWIHS_RHR Read-only 0x00000000 0x34 Transmit Holding Register TWIHS_THR Write-only 0x00000000 0x38 Reserved – – – 0x3C Reserved – – – 0x40 Reserved – – – 0x44 Filter Register TWIHS_FILTR Read/Write 0x00000000 0x48 Reserved – – – 0x4C SleepWalking Matching Register TWIHS_SWMR Read/Write 0x00000000 0x50–0xCC Reserved – – – 0xD0 Reserved – – – 0xD4–0xE0 Reserved – – – 0xE4 Write Protection Mode Register TWIHS_WPMR Read/Write 0x00000000 Write Protection Status Register TWIHS_WPSR Read-only 0x00000000 Reserved – – – Reserved for PDC registers – – – 0xE8 0xEC–0xFC (1) 0x100–0x128 Note: 1. All unlisted offset values are considered as “reserved”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 613 29.7.1 TWIHS Control Register Name: TWIHS_CR Address: 0x40018000 Access: Write-only 31 – 30 – 29 FIFODIS 28 FIFOEN 27 – 26 LOCKCLR 25 – 24 THRCLR 23 – 22 – 21 – 20 – 19 – 18 – 17 ACMDIS 16 ACMEN 15 CLEAR 14 – 13 – 12 – 11 – 10 – 9 HSDIS 8 HSEN 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the TWIHS Master Mode Register (TWIHS_MMR). This action is necessary when the TWIHS peripheral needs to read data from a slave. When configured in Master mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWIHS_THR). • STOP: Send a STOP Condition 0: No effect. 1: STOP condition is sent just after completing the current byte transmission in Master Read mode. – In single data byte master read, both START and STOP must be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In Master Read mode, if a NACK bit is received, the STOP is automatically performed. – In master data write operation, a STOP condition will be sent after the transmission of the current data is finished. • MSEN: TWIHS Master Mode Enabled 0: No effect. 1: Enables the Master mode (MSDIS must be written to 0). Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. • MSDIS: TWIHS Master Mode Disabled 0: No effect. 1: The Master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. 614 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • SVEN: TWIHS Slave Mode Enabled 0: No effect. 1: Enables the Slave mode (SVDIS must be written to 0). Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWIHS Slave Mode Disabled 0: No effect. 1: The Slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBus Quick Command 0: No effect. 1: If Master mode is enabled, a SMBus Quick Command is sent. • SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset. • HSEN: TWIHS High-Speed Mode Enabled 0: No effect. 1: High-speed mode enabled. • HSDIS: TWIHS High-Speed Mode Disabled 0: No effect. 1: High-speed mode disabled. • CLEAR: Bus CLEAR Command 0: No effect. 1: If Master mode is enabled, sends a bus clear command. • ACMEN: Alternative Command Mode Enable 0: No effect. 1: Alternative Command mode enabled. • ACMDIS: Alternative Command Mode Disable 0: No effect. 1: Alternative Command mode disabled. • THRCLR: Transmit Holding Register Clear 0: No effect. 1: Clears the Transmit Holding Register and set TXRDY, TXCOMP flags. • LOCKCLR: Lock Clear 0: No effect. 1: Clears the TWIHS FSM lock. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 615 • FIFOEN: FIFO Enable 0: No effect. 1: Enables the Transmit and Receive FIFOs • FIFODIS: FIFO Disable 0: No effect. 1: Disables the Transmit and Receive FIFOs 616 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7.2 TWIHS Master Mode Register Name: TWIHS_MMR Address: 0x40018004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 DADR 18 17 16 15 – 14 – 13 – 12 MREAD 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 – 8 IADRSZ 0 – • IADRSZ: Internal Device Address Size Value Name Description 0 NONE No internal device address 1 1_BYTE One-byte internal device address 2 2_BYTE Two-byte internal device address 3 3_BYTE Three-byte internal device address • MREAD: Master Read Direction 0: Master write direction. 1: Master read direction. • DADR: Device Address The device address is used to access slave devices in Read or Write mode. These bits are only used in Master mode. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 617 29.7.3 TWIHS Slave Mode Register Name: TWIHS_SMR Address: 0x40018008 Access: Read/Write 31 DATAMEN 30 SADR3EN 29 SADR2EN 28 SADR1EN 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 13 12 11 MASK 10 9 8 7 – 6 SCLWSDIS 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register. • SCLWSDIS: Clock Wait State Disable 0: No effect. 1: Clock stretching disabled in Slave mode, OVRE and UNRE indicate an overrun/underrun. • MASK: Slave Address Mask A mask can be applied on the slave device address in Slave mode in order to allow multiple address answer. For each bit of the MASK field set to 1, the corresponding SADR bit is masked. If the MASK field value is 0, no mask is applied to the SADR field. • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in Read or Write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. • SADR1EN: Slave Address 1 Enable 0: Slave address 1 matching is disabled. 1: Slave address 1 matching is enabled. • SADR2EN: Slave Address 2 Enable 0: Slave address 2 matching is disabled. 1: Slave address 2 matching is enabled. • SADR3EN: Slave Address 3 Enable 0: Slave address 3 matching is disabled. 1: Slave address 3 matching is enabled. • DATAMEN: Data Matching Enable 0: Data matching on first received data is disabled. 1: Data matching on first received data is enabled. 618 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7.4 TWIHS Internal Address Register Name: TWIHS_IADR Address: 0x4001800C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 619 29.7.5 TWIHS Clock Waveform Generator Register Name: TWIHS_CWGR Address: 0x40018010 Access: Read/Write 31 – 30 – 29 – 28 27 26 HOLD 25 24 23 – 22 – 21 – 20 – 19 – 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register. TWIHS_CWGR is used in Master mode only. • CLDIV: Clock Low Divider The SCL low period is defined as follows: tlow = ((CLDIV × 2CKDIV) + 3) × tperipheral clock • CHDIV: Clock High Divider The SCL high period is defined as follows: thigh = ((CHDIV × 2CKDIV) + 3) × tperipheral clock • CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. • HOLD: TWD Hold Time Versus TWCK Falling If High-speed mode is selected TWD is internally modified on the TWCK falling edge to meet the I2C specified maximum hold time, else if High-speed mode is not configured TWD is kept unchanged after TWCK falling edge for a period of (HOLD + 3) × tperipheral clock. 620 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7.6 TWIHS Status Register Name: TWIHS_SR Address: 0x40018020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 SDA 24 SCL 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 UNRE 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (cleared by writing TWIHS_THR) TXCOMP used in Master mode: 0: During the length of the current frame. 1: When both holding register and internal shifter are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 29-6 and in Figure 29-8. TXCOMP used in Slave mode: 0: As soon as a START is detected. 1: After a STOP or a REPEATED START + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 29-27, Figure 29-28, Figure 29-29 and Figure 29-30. • RXRDY: Receive Holding Register Ready (cleared by reading TWIHS_RHR) 0: No character has been received since the last TWIHS_RHR read operation. 1: A byte has been received in the TWIHS_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 29-7, Figure 29-8 and Figure 29-9. RXRDY behavior in Slave mode can be seen in Figure 29-25, Figure 29-28, Figure 29-29 and Figure 29-30. • TXRDY: Transmit Holding Register Ready (cleared by writing TWIHS_THR) TXRDY used in Master mode: 0: The transmit holding register has not been transferred into the internal shifter. Set to 0 when writing into TWIHS_THR. 1: As soon as a data byte is transferred from TWIHS_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enables TWIHS). TXRDY behavior in Master mode can be seen in Figure 29-4, Figure 29-5 and Figure 29-6. TXRDY used in Slave mode: 0: As soon as data is written in the TWIHS_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1: Indicates that the TWIHS_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission is stopped. Thus when TRDY = NACK = 1, the user must not fill TWIHS_THR to avoid losing it. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 621 TXRDY behavior in Slave mode can be seen in Figure 29-24, Figure 29-27, Figure 29-29 and Figure 29-30. • SVREAD: Slave Read This bit is used in Slave mode only. When SVACC is low (no slave access has been detected) SVREAD is irrelevant. 0: Indicates that a write access is performed by a master. 1: Indicates that a read access is performed by a master. SVREAD behavior can be seen in Figure 29-24, Figure 29-25, Figure 29-29 and Figure 29-30. • SVACC: Slave Access This bit is used in Slave mode only. 0: TWIHS is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1: Indicates that the address decoding sequence has matched (A master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 29-24, Figure 29-25, Figure 29-29 and Figure 29-30. • GACC: General Call Access (cleared on read) This bit is used in Slave mode only. 0: No general call has been detected. 1: A general call has been detected. After the detection of general call, if need be, the user may acknowledge this access and decode the following bytes and respond according to the value of the bytes. GACC behavior can be seen in Figure 29-26. • OVRE: Overrun Error (cleared on read) This bit is used only if clock stretching is disabled. 0: TWIHS_RHR has not been loaded while RXRDY was set. 1: TWIHS_RHR has been loaded while RXRDY was set. Reset by read in TWIHS_SR when TXCOMP is set. • UNRE: Underrun Error (cleared on read) This bit is used only if clock stretching is disabled. 0: TWIHS_THR has been filled on time. 1: TWIHS_THR has not been filled on time. • NACK: Not Acknowledged (cleared on read) NACK used in Master mode: 0: Each data byte has been correctly received by the far-end side TWIHS slave component. 1: A data or address byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. NACK used in Slave Read mode: 0: Each data byte has been correctly received by the master. 1: In Read mode, a data byte has not been acknowledged by the master. When NACK is set, the user must not fill TWIHS_THR even if TXRDY is set, because it means that the master stops the data transfer or re-initiate it. Note: in Slave Write mode, all data are acknowledged by the TWIHS. 622 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • ARBLST: Arbitration Lost (cleared on read) This bit is used in Master mode only. 0: Arbitration won. 1: Arbitration lost. Another master of the TWIHS bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State This bit is used in Slave mode only. 0: The clock is not stretched. 1: The clock is stretched. TWIHS_THR / TWIHS_RHR buffer is not filled / emptied before the transmission / reception of a new character. SCLWS behavior can be seen in Figure 29-27 and Figure 29-28. • EOSACC: End Of Slave Access (cleared on read) This bit is used in Slave mode only. 0: A slave access is being performing. 1: The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 29-29 and Figure 29-30. • ENDRX: End of RX Buffer (cleared by writing TWIHS_RCR or TWIHS_RNCR) 0: The Receive Counter Register has not reached 0 since the last write in TWIHS_RCR or TWIHS_RNCR. 1: The Receive Counter Register has reached 0 since the last write in TWIHS_RCR or TWIHS_RNCR. • ENDTX: End of TX Buffer (cleared by writing TWIHS_TCR or TWIHS_TNCR) 0: The Transmit Counter Register has not reached 0 since the last write in TWIHS_TCR or TWIHS_TNCR. 1: The Transmit Counter Register has reached 0 since the last write in TWIHS_TCR or TWIHS_TNCR. • RXBUFF: RX Buffer Full (cleared by writing TWIHS_RCR or TWIHS_RNCR) 0: TWIHS_RCR or TWIHS_RNCR have a value other than 0. 1: Both TWIHS_RCR and TWIHS_RNCR have a value of 0. • TXBUFE: TX Buffer Empty (cleared by writing TWIHS_TCR or TWIHS_TNCR) 0: TWIHS_TCR or TWIHS_TNCR have a value other than 0. 1: Both TWIHS_TCR and TWIHS_TNCR have a value of 0. • SCL: SCL Line Value 0: SCL line sampled value is ‘0’. 1: SCL line sampled value is ‘1.’ • SDA: SDA Line Value 0: SDA line sampled value is ‘0’. 1: SDA line sampled value is ‘1’. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 623 29.7.7 TWIHS Filter Register Name: TWIHS_FILTR Address: 0x40018044 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 THRES 8 7 – 6 – 5 – 4 – 3 – 2 PADFCFG 1 PADFEN 0 FILT • FILT: RX Digital Filter 0: No filtering applied on TWIHS inputs. 1: TWIHS input filtering is active (only in Standard and Fast modes) Note: TWIHS digital input filtering follows a majority decision based on three samples from SDA/SCL lines at peripheral clock frequency. • PADFEN: PAD Filter Enable 0: PAD analog filter is disabled. 1: PAD analog filter is enabled. (The analog filter must be enabled if High-speed mode is enabled.) • PADFCFG: PAD Filter Config See the electrical characteristics section for filter configuration details. • THRES: Digital Filter Threshold 0: No filtering applied on TWIHS inputs. 1–7: Maximum pulse width of spikes to be suppressed by the input filter, defined in peripheral clock cycles. 624 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7.8 TWIHS Interrupt Enable Register Name: TWIHS_IER Address: 0x40018024 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 UNRE 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. • TXCOMP: Transmission Completed Interrupt Enable • RXRDY: Receive Holding Register Ready Interrupt Enable • TXRDY: Transmit Holding Register Ready Interrupt Enable • SVACC: Slave Access Interrupt Enable • GACC: General Call Access Interrupt Enable • OVRE: Overrun Error Interrupt Enable • UNRE: Underrun Error Interrupt Enable • NACK: Not Acknowledge Interrupt Enable • ARBLST: Arbitration Lost Interrupt Enable • SCL_WS: Clock Wait State Interrupt Enable • EOSACC: End Of Slave Access Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 625 29.7.9 TWIHS Interrupt Disable Register Name: TWIHS_IDR Address: 0x40018028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 UNRE 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. • TXCOMP: Transmission Completed Interrupt Disable • RXRDY: Receive Holding Register Ready Interrupt Disable • TXRDY: Transmit Holding Register Ready Interrupt Disable • SVACC: Slave Access Interrupt Disable • GACC: General Call Access Interrupt Disable • OVRE: Overrun Error Interrupt Disable • UNRE: Underrun Error Interrupt Disable • NACK: Not Acknowledge Interrupt Disable • ARBLST: Arbitration Lost Interrupt Disable • SCL_WS: Clock Wait State Interrupt Disable • EOSACC: End Of Slave Access Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable 626 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7.10 TWIHS Interrupt Mask Register Name: TWIHS_IMR Address: 0x4001802C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 UNRE 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. • TXCOMP: Transmission Completed Interrupt Mask • RXRDY: Receive Holding Register Ready Interrupt Mask • TXRDY: Transmit Holding Register Ready Interrupt Mask • SVACC: Slave Access Interrupt Mask • GACC: General Call Access Interrupt Mask • OVRE: Overrun Error Interrupt Mask • UNRE: Underrun Error Interrupt Mask • NACK: Not Acknowledge Interrupt Mask • ARBLST: Arbitration Lost Interrupt Mask • SCL_WS: Clock Wait State Interrupt Mask • EOSACC: End Of Slave Access Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 627 29.7.11 TWIHS Receive Holding Register Name: TWIHS_RHR Address: 0x40018030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Master or Slave Receive Holding Data 628 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7.12 TWIHS SleepWalking Matching Register Name: TWIHS_SWMR Address: 0x4001804C Access: Read/Write 31 30 29 28 27 26 25 24 DATAM 23 – 22 21 20 19 SADR3 18 17 16 15 – 14 13 12 11 SADR2 10 9 8 7 – 6 5 4 3 SADR1 2 1 0 This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register. • SADR1: Slave Address 1 Slave address 1. The TWIHS module matches on this additional address if SADR1EN bit is enabled. • SADR2: Slave Address 2 Slave address 2. The TWIHS module matches on this additional address if SADR2EN bit is enabled. • SADR3: Slave Address 3 Slave address 3. The TWIHS module matches on this additional address if SADR3EN bit is enabled. • DATAM: Data Match The TWIHS module extends the SleepWalking matching process to the first received data, comparing it with DATAM if DATAMEN bit is enabled. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 629 29.7.13 TWIHS Transmit Holding Register Name: TWIHS_THR Address: 0x40018034 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Master or Slave Transmit Holding Data 630 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7.14 TWIHS FIFO Level Register Name: TWIHS_FLR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – RXFL TXFL • TXFL: Transmit FIFO Level 0: There is no data in the Transmit FIFO 1––: Indicates the number of DATA in the Transmit FIFO • RXFL: Receive FIFO Level 0: There is no unread data in the Receive FIFO 1––: Indicates the number of unread DATA in the Receive FIFO SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 631 29.7.15 TWIHS Write Protection Mode Register Name: TWIHS_WPMR Address: 0x400180E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x545749 (“TWI” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x545749 (“TWI” in ASCII). See Section 29.6.7 ”Register Write Protection” for the list of registers that can be write-protected. • WPKEY: Write Protection Key Value 0x545749 632 Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 29.7.16 TWIHS Write Protection Status Register Name: TWIHS_WPSR Address: 0x400180E8 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 23 22 21 20 WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the TWIHS_WPSR. 1: A write protection violation has occurred since the last read of the TWIHS_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 633 30. Two-wire Interface (TWI) 30.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as a Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and temperature sensor. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Table 30-1 lists the compatibility level of the Atmel Two-wire Interface in Master mode and a full I2C compatible device. Atmel TWI Compatibility with I2C Standard Table 30-1. I2C Standard Atmel TWI Standard Mode Speed (100 kHz) Supported Fast Mode Speed (400 kHz) Supported 7- or 10-bit Slave Addressing Supported (1) START byte Not Supported Repeated Start (Sr) Condition Supported ACK and NACK Management Supported Slope Control and Input Filtering (Fast mode) Not Supported Clock Stretching/Synchronization Supported Multi Master Capability Supported Note: 30.2 1. Embedded Characteristics Compatible with Atmel Two-wire Interface Serial Memory and I2C Compatible Devices(1) One, Two or Three Bytes for Slave Address Sequential Read/Write Operations Master, Multi-master and Slave Mode Operation Bit Rate: Up to 400 Kbit/s General Call Supported in Slave Mode Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers ̶ Note: 634 START + b000000001 + Ack + Sr One Channel for the Receiver, One Channel for the Transmitter Register Write Protection 1. See Table 30-1 for details on compatibility with I²C Standard. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 30.3 List of Abbreviations Table 30-2. 30.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 30-1. Block Diagram Bus clock Peripheral Bridge TWCK PIO PMC Peripheral clock TWD Two-wire Interface TWI Interrupt 30.5 Interrupt Controller I/O Lines Description Table 30-3. I/O Lines Description Name Description Type TWD Two-wire Serial Data (drives external serial data line – SDA) Input/Output TWCK Two-wire Serial Clock (drives external serial clock line – SCL) Input/Output SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 635 30.6 Product Dependencies 30.6.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the user must program the PIO Controller to dedicate TWD and TWCK as peripheral lines. The user must not program TWD and TWCK as open-drain. This is already done by the hardware. Table 30-4. I/O Lines Instance Signal I/O Line Peripheral TWI1 TWCK1 PB9 A TWI1 TWCK1 PB11 A TWI1 TWD1 PB8 A TWI1 TWD1 PB10 A TWI2 TWCK2 PB1 B TWI2 TWCK2 PB11 B TWI2 TWD2 PB0 B TWI2 TWD2 PB10 B 30.6.2 Power Management The TWI may be clocked through the Power Management Controller (PMC), thus the user must first configure the PMC to enable the TWI clock. 30.6.3 Interrupt Sources The TWI has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt Controller must be programmed before configuring the TWI. Table 30-5. 30.7 Peripheral IDs Instance ID TWI1 20 TWI2 22 Functional Description 30.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 30-3). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 30-2). 636 A high-to-low transition on the TWD line while TWCK is high defines the START condition. A low-to-high transition on the TWD line while TWCK is high defines the STOP condition. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 30-2. START and STOP Conditions TWD TWCK Start Figure 30-3. Stop Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 30.7.2 Modes of Operation The TWI has different modes of operations: Master transmitter mode Master receiver mode Multi-master transmitter mode Multi-master receiver mode Slave transmitter mode Slave receiver mode These modes are described in the following sections. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 637 30.7.3 Master Mode 30.7.3.1 Definition The master is the device that starts a transfer, generates a clock and stops it. 30.7.3.2 Programming Master Mode The following fields must be programmed before entering Master mode: 1. TWI_MMR.DADR (+ IADRSZ + IADR if a 10-bit device is addressed): The device address is used to access slave devices in Read or Write mode. 2. TWI_CWGR.CKDIV + CHDIV + CLDIV: Clock waveform. 3. TWI_CR.SVDIS: Disables the Slave mode 4. TWI_CR.MSEN: Enables the Master mode Note: 30.7.3.3 If the TWI is already in Master mode, the device address (DADR) can be configured without disabling the Master mode. Master Transmitter Mode After the master initiates a START condition when writing into the Transmit Holding register (TWI_THR), it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction—0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. If the slave does not acknowledge the byte, then the Not Acknowledge flag (NACK) is set in the TWI Status Register (TWI_SR) of the master and a STOP condition is sent. The NACK flag must be cleared by reading the TWI Status Register (TWI_SR) before the next write into the TWI Transmit Holding Register (TWI_THR). As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR. TXRDY is used as Transmit Ready for the PDC transmit channel. When no more data is written into the TWI_THR, the master generates a STOP condition to end the transfer. A TXCOMP bit value of one in the TWI_SR indicates that the transfer has completed. See Figure 30-4, Figure 30-5, and Figure 30-6. To clear the TXRDY flag, first set the bit TWI_CR.MSDIS, then set the bit TWI_CR.MSEN. Figure 30-4. Master Write with One Data Byte TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) 638 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 STOP sent automaticaly (ACK received and TXRDY = 1) Figure 30-5. Master Write with Multiple Data Byte S TWD DADR W A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Figure 30-6. TWD S Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) Master Write with One Byte Internal Address and Multiple Data Bytes DADR W A IADR(7:0) A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) 30.7.3.4 Write THR (Data n+1) Write THR (Data n+x) STOP sent automaticaly Last data sent (ACK received and TXRDY = 1) Master Receiver Mode The read sequence begins by setting the START bit. After the START condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction—1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the TWI_SR if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data. See . When the RXRDY bit is set in the TWI_SR, a character has been received in the Receive Holding Register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. RXRDY is used as Receive Ready for the PDC receive channel. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See . When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-to-last data received. See . For internal address usage, see Section 30.7.3.5. If the Receive Holding Register (TWI_RHR) is full (RXRDY high) and the master is receiving data, the serial clock line is tied low before receiving the last bit of the data and until the TWI_RHR is read. Once the TWI_RHR is read, the master stops stretching the serial clock line and ends the data reception. See Figure 30-9. Warning: When receiving multiple bytes in Master read mode, if the next-to-last access is not read (the RXRDY flag remains high), the last access is not completed until TWI_RHR is read. The last access stops on the next-tolast bit. When the TWI_RHR is read, the STOP bit command must be sent within a period of half a bit only, otherwise another read access might occur (spurious access). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 639 A possible workaround is to set the STOP bit before reading the TWI_RHR on the next-to-last access (within the interrupt handler). Figure 30-7. Master Read with One Data Byte TWD S DADR R A DATA NA P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 30-8. TWD Master Read with Multiple Data Bytes S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) NA P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read Figure 30-9. Master Read Wait State with Multiple Data Bytes STOP command performed (by writing in the TWI_CR) Clock Wait State TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP RXRDY Read RHR (Data n) 30.7.3.5 Read RHR (Data n+1) Read RHR (Data n+2) Internal Address The TWI can perform transfers with 7-bit slave address devices and 10-bit slave address devices. 7-bit Slave Addressing 640 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 When addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, e.g. within a memory page location in a serial memory. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master receiver mode. Note that the second START condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 30-11. See Figure 30-10 and Figure 30-12 for master write operation with internal address. The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e., no internal address, IADRSZ must be set to 0. Table 30-6 shows the abbreviations used in Figure 30-10 and Figure 30-11. Table 30-6. Abbreviations Abbreviation Definition S Start Sr Repeated Start P Stop W Write R Read A Acknowledge NA Not Acknowledge DADR Device Address IADR Internal Address Figure 30-10. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address TWD S DADR P One byte internal address TWD S DADR P Figure 30-11. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA NA P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A Sr W A IADR(7:0) A Sr R A DADR R A DATA NA P One byte internal address TWD S DADR DADR DATA NA P 10-bit Slave Addressing SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 641 For a slave address higher than seven bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the Internal Address register (TWI_IADR). The two remaining internal address bytes, IADR[15:8] and IADR[23:16] can be used the same way as in 7-bit slave addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) 3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 30-12 below shows a byte write to a memory device. This demonstrates the use of internal addresses to access the device. Figure 30-12. Internal Address Usage S T A R T Device Address W R I T E FIRST WORD ADDRESS SECOND WORD ADDRESS S T O P DATA 0 M S B 30.7.3.6 LR A S / C BW K M S B A C K LA SC BK A C K Using the Peripheral DMA Controller (PDC) The use of the PDC significantly reduces the CPU load. To ensure correct implementation, proceed as follows. Data Transmit with the PDC 1. Initialize the transmit PDC (memory pointers, transfer size - 1). 2. Configure the master (DADR, CKDIV, MREAD = 0, etc.) 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt. 5. Disable the PDC by setting the PDC TXTDIS bit. 6. Wait for the TXRDY flag in TWI_SR. 7. Set the STOP bit in TWI_CR. 8. Write the last character in TWI_THR. 9. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR. Data Receive with the PDC The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed without PDC to ensure that the exact number of bytes are received regardless of system bus latency conditions encountered during the end of buffer transfer period. In Slave mode, the number of characters to receive must be known in order to configure the PDC. 1. Initialize the receive PDC (memory pointers, transfer size - 2). 642 2. Configure the master (DADR, CKDIV, MREAD = 1, etc.) 3. Set the PDC RXTEN bit. 4. (Master Only) Write the START bit in the TWI_CR to start the transfer. 5. Wait for the PDC ENDRX Flag either by using polling method or ENDRX interrupt. 6. Disable the PDC by setting the PDC RXTDIS bit. 7. Wait for the RXRDY flag in TWI_SR. 8. Set the STOP bit in TWI_CR. 9. Read the penultimate character in TWI_RHR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 10. Wait for the RXRDY flag in TWI_SR. 11. Read the last character in TWI_RHR. 12. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR. 30.7.3.7 Read/Write Flowcharts The flowcharts in the following figures provide examples of read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the Interrupt Enable Register (TWI_IER) be configured first. Figure 30-13. TWI Write Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 643 Figure 30-14. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished 644 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 30-15. TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Read Status register TWI_THR = data to send No TXRDY = 1? Yes Data to send? Yes No Read Status register No TXCOMP = 1? Yes END SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 645 Figure 30-16. TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? No Yes Read Receive Holding Register Read Status register No TXCOMP = 1? Yes END 646 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 30-17. TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 647 Figure 30-18. TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register RXRDY = 1? No Yes Read Receive Holding register (TWI_RHR) No Last data to read but one? Yes Stop the transfer TWI_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) Read status register TXCOMP = 1? Yes END 648 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 No 30.7.4 Multi-master Mode 30.7.4.1 Definition In Multi-master mode, more than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as a master lose arbitration, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master may put its data on the bus by performing arbitration. Arbitration is illustrated in Figure 30-20. 30.7.4.2 Two Multi-master Modes Two Multi-master modes may be distinguished: 1. TWI is considered as a master only and will never be addressed. 2. Note: TWI may be either a master or a slave and may be addressed. Arbitration is supported in both Multi-master modes. TWI as Master Only In this mode, TWI is considered as a Master only (MSEN is always one) and must be driven like a Master with the ARBLST (Arbitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the user must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 30-19). Note: The state of the bus (busy or free) is not shown in the user interface. TWI as Master or Slave The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the user must manage the pseudo Multi-master mode described in the steps below. 1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform a slave access (if TWI is addressed). 2. If the TWI has to be set in Master mode, wait until the TXCOMP flag is at 1. 3. Program the Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, the TWI scans the bus in order to detect if it is busy or free. When the bus is considered free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in case the Master that won the arbitration is required to access the TWI. 7. If the TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. Note: If the arbitration is lost and the TWI is addressed, the TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then the Master must repeat SADR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 649 Figure 30-19. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 30-20. Arbitration Cases TWCK TWD TWCK Data from a Master S 1 0 0 1 1 Data from TWI S 1 0 TWD S 1 0 0 1 P Arbitration is lost TWI stops sending data Data from the master 1 1 P Arbitration is lost S 1 0 1 S 1 0 0 1 1 S 1 0 0 1 1 The master stops sending data Data from the TWI ARBLST Bus is busy Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is free Transfer is stopped Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 30-21 gives an example of read and write operations in Multi-master mode. 650 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 30-21. Multi-master Flowchart START Program the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? Yes GACC = 1 ? No No SVREAD = 1 ? No No EOSACC = 1 ? TXRDY= 1 ? Yes Yes Yes No Write in TWI_THR TXCOMP = 1 ? RXRDY= 1 ? Yes No No No Yes Read TWI_RHR Need to perform a master access ? GENERAL CALL TREATMENT Yes Decoding of the programming sequence Prog seq OK ? No Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register Yes No ARBLST = 1 ? Yes Yes No MREAD = 1 ? RXRDY= 0 ? TXRDY= 0 ? No Read TWI_RHR Yes Yes No Data to read? Data to send ? No Yes Write in TWI_THR No Stop transfer Read Status Register Yes TXCOMP = 0 ? No 30.7.5 Slave Mode 30.7.5.1 Definition Slave mode is defined as a mode where the device receives the clock and the address from another device called the master. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 651 In this mode, the device never initiates and never completes the transmission (START, REPEATED START and STOP conditions are always provided by the master). 30.7.5.2 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. TWI_SMR.SADR: The slave device address is used in order to be accessed by master devices in Read or Write mode. 2. TWI_CR.MSDIS: Disables the Master mode. 3. TWI_CR.SVEN: Enables the Slave mode. As the device receives the clock, values written in TWI_CWGR are ignored. 30.7.5.3 Receiving Data After a START or REPEATED START condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave Address) field, SVACC (Slave Access) flag is set and SVREAD (Slave Read) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, the EOSACC (End Of Slave Access) flag is set. Read Sequence In the case of a read sequence (SVREAD is high), TWI transfers data written in TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START and an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in TWI_THR, the TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the internal shifter is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. Note that a STOP or a REPEATED START always follows a NACK. To clear the TXRDY flag, first set the bit TWI_CR.SVDIS, then set the bit TWI_CR.SVEN. See Figure 30-22. Write Sequence In the case of a write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 30-23. Clock Synchronization Sequence If TWI_RHR is not read in time, the TWI performs a clock synchronization. Clock synchronization information is given by the bit SCLWS (Clock Wait State). See Figure 30-26. Clock Stretching Sequence If TWI_THR is not written in time, the TWI performs a clock stretching. Clock stretching information is given by the bit SCLWS (Clock Wait State). See Figure 30-25. 652 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 General Call In the case where a GENERAL CALL is performed, the GACC (General Call Access) flag is set. After GACC is set, the user must interpret the meaning of the GENERAL CALL and decode the new address programming sequence. See Figure 30-24. 30.7.5.4 Data Transfer Read Operation The Read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 30-22 describes the write operation. Figure 30-22. Read Access Ordered by a Master SADR matches, TWI answers with an ACK SADR does not match, TWI answers with a NACK TWD S ADR R NA DATA NA P/S/Sr SADR R A DATA A ACK/NACK from the Master A DATA NA S/Sr TXRDY NACK Read RHR Write THR SVACC SVREAD SVREAD has to be taken into account only while SVACC is active EOSACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the internal shifter and set when this data has been acknowledged or non acknowledged. Write Operation The Write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 30-23 describes the write operation. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 653 Figure 30-23. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK TWD S ADR W NA DATA NA SADR matches, TWI answers with an ACK P/S/Sr SADR W A DATA Read RHR A A DATA NA S/Sr RXRDY SVACC SVREAD has to be taken into account only while SVACC is active SVREAD EOSACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the internal shifter to the TWI_RHR and reset when this data is read. General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of GENERAL CALL, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 30-24 describes the GENERAL CALL access. Figure 30-24. Master Performs a General Call 0000000 + W TXD S GENERAL CALL RESET command = 00000110X WRITE command = 00000100X A Reset or write DADD A DATA1 A DATA2 A New SADR A P New SADR Programming sequence GACC Reset after read SVACC Note: 654 This method allows the user to create a personal programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Clock Synchronization/Stretching In both Read and Write modes, it may occur that TWI_THR/TWI_RHR buffer is not filled /emptied before transmission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching/synchronization mechanism is implemented. Clock Stretching in Read Mode The clock is tied low during the acknowledge phase if the internal shifter is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the internal shifter is loaded. Figure 30-25 describes clock stretching in Read mode. Figure 30-25. Clock Stretching in Read Mode TWI_THR S SADR R DATA1 1 DATA0 A DATA0 A DATA1 DATA2 A XXXXXXX DATA2 NA S 2 TWCK Write THR CLOCK is tied low by the TWI as long as THR is empty SCLWS TXRDY SVACC SVREAD As soon as a START is detected TXCOMP Ack or Nack from the master TWI_THR is transmitted to the shift register Notes: 1 The data is memorized in TWI_THR until a new value is written 2 The clock is stretched after the ACK, the state of TWD is undefined during clock stretching 1. TXRDY is reset when data has been written in the TWI_THR to the internal shifter and set when this data has been acknowledged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock stretching mechanism is started. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 655 Clock Synchronization in Write Mode The clock is tied low outside of the acknowledge phase if the internal shifter and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 30-26 describes the clock synchronization in Write mode. Figure 30-26. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full TWD S SADR W A DATA0 A TWI_RHR DATA1 A DATA0 is not read in the RHR DATA2 DATA1 NA S ADR DATA2 SCLWS TWCK is stretched on the last bit of DATA1 RXRDY Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD TXCOMP Notes: 656 As soon as a START is detected 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Reversal After a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 30-27 describes the repeated start + reversal from Read to Write mode. Figure 30-27. Repeated Start + Reversal from Read to Write Mode TWI_THR TWD DATA0 S SADR R A DATA0 DATA1 A DATA1 NA Sr SADR W A DATA2 TWI_RHR A DATA3 DATA2 A P DATA3 SVACC SVREAD TXRDY RXRDY EOSACC Cleared after read As soon as a START is detected TXCOMP Note: 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command. Figure 30-28 describes the repeated start + reversal from Write to Read mode. Figure 30-28. Repeated Start + Reversal from Write to Read Mode DATA2 TWI_THR TWD S SADR W A DATA0 TWI_RHR A DATA1 DATA0 A Sr SADR R A DATA3 DATA2 A DATA3 NA P DATA1 SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP Notes: 30.7.5.5 Read TWI_RHR Cleared after read As soon as a START is detected 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. Using the Peripheral DMA Controller (PDC) in Slave Mode The use of the PDC significantly reduces the CPU load. Data Transmit with the PDC in Slave Mode The following procedure shows an example of data transmission with PDC. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 657 1. Initialize the transmit PDC (memory pointers, transfer size). 2. Start the transfer by setting the PDC TXTEN bit. 3. Wait for the PDC ENDTX flag by using either the polling method or the ENDTX interrupt. 4. Disable the PDC by setting the PDC TXTDIS bit. 5. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR. Data Receive with the PDC in Slave Mode The following procedure shows an example of data transmission with PDC where the number of characters to be received is known. 1. Initialize the receive PDC (memory pointers, transfer size). 30.7.5.6 2. Set the PDC RXTEN bit. 3. Wait for the PDC ENDRX flag by using either the polling method or the ENDRX interrupt. 4. Disable the PDC by setting the PDC RXTDIS bit. 5. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR. Read Write Flowcharts The flowchart shown in Figure 30-29 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the Interrupt Enable Register (TWI_IER) be configured first. 658 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 30-29. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? GACC = 1 ? No No EOSACC = 1 ? No SVREAD = 1 ? TXRDY= 1 ? No No Write in TWI_THR No TXCOMP = 1 ? RXRDY= 1 ? No END Read TWI_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR 30.7.6 Register Write Protection To prevent any single software error from corrupting TWI behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the TWI Write Protection Mode Register (TWI_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the TWI Write Protection Status Register (TWI_WPSR) is set and the WPVSRC field shows the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the TWI_WPSR. The following registers can be write-protected: TWI Slave Mode Register TWI Clock Waveform Generator Register SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 659 30.8 Two-wire Interface (TWI) User Interface Table 30-7. Register Mapping Offset Register Name Access Reset 0x00 Control Register TWI_CR Write-only – 0x04 Master Mode Register TWI_MMR Read/Write 0x00000000 0x08 Slave Mode Register TWI_SMR Read/Write 0x00000000 0x0C Internal Address Register TWI_IADR Read/Write 0x00000000 0x10 Clock Waveform Generator Register TWI_CWGR Read/Write 0x00000000 0x14–0x1C Reserved – – – 0x20 Status Register TWI_SR Read-only 0x0000F009 0x24 Interrupt Enable Register TWI_IER Write-only – 0x28 Interrupt Disable Register TWI_IDR Write-only – 0x2C Interrupt Mask Register TWI_IMR Read-only 0x00000000 0x30 Receive Holding Register TWI_RHR Read-only 0x00000000 0x34 Transmit Holding Register TWI_THR Write-only – 0x38–0xE0 Reserved – – – 0xE4 Write Protection Mode Register TWI_WPMR Read/Write 0x00000000 0xE8 Write Protection Status Register TWI_WPSR Read-only 0x00000000 0xEC–0xFC Reserved – – – 0x100–0x128 Reserved for PDC registers – – – Note: All unlisted offset values are considered as “reserved”. 660 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 30.8.1 TWI Control Register Name: TWI_CR Address: 0x4001C000 (1), 0x40040000 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the TWI Master Mode Register (TWI_MMR). This action is necessary for the TWI to read data from a slave. When configured in Master mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR). • STOP: Send a STOP Condition 0: No effect. 1: STOP condition is sent just after completing the current byte transmission in Master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In Master read mode, if a NACK bit is received, the STOP is automatically performed. – In multiple data write operation, when both THR and internal shifter are empty, a STOP condition is sent automatically. • MSEN: TWI Master Mode Enabled 0: No effect. 1: Enables the Master mode (MSDIS must be written to 0). Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. • MSDIS: TWI Master Mode Disabled 0: No effect. 1: The Master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 661 • SVEN: TWI Slave Mode Enabled 0: No effect. 1: Enables the Slave mode (SVDIS must be written to 0) Note: Switching from master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0: No effect. 1: The Slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset. 662 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 30.8.2 TWI Master Mode Register Name: TWI_MMR Address: 0x4001C004 (1), 0x40040004 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 DADR 18 17 16 15 – 14 – 13 – 12 MREAD 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 – 8 IADRSZ 0 – • IADRSZ: Internal Device Address Size Value Name Description 0 NONE No internal device address 1 1_BYTE One-byte internal device address 2 2_BYTE Two-byte internal device address 3 3_BYTE Three-byte internal device address • MREAD: Master Read Direction 0: Master write direction. 1: Master read direction. • DADR: Device Address The device address is used to access slave devices in Read or Write mode. These bits are only used in Master mode. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 663 30.8.3 TWI Slave Mode Register Name: TWI_SMR Address: 0x4001C008 (1), 0x40040008 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the TWI Write Protection Mode Register. • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in Read or Write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. 664 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 30.8.4 TWI Internal Address Register Name: TWI_IADR Address: 0x4001C00C (1), 0x4004000C (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 665 30.8.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0x4001C010 (1), 0x40040010 (2) Access: Read/Write 31 – 30 – 29 – 28 27 26 HOLD 25 24 23 – 22 – 21 – 20 – 19 – 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV This register can only be written if the WPEN bit is cleared in the TWI Write Protection Mode Register. TWI_CWGR is only used in Master mode. • CLDIV: Clock Low Divider The TWCK low period is defined as follows: tlow = ((CLDIV × 2CKDIV) + 4 × tperipheral clock • CHDIV: Clock High Divider The TWCK high period is defined as follows: thigh = ((CHDIV × 2CKDIV) + 4 × tperipheral clock • CKDIV: Clock Divider The CKDIV field is used to increase both TWCK high and low periods. • HOLD: TWD Hold Time versus TWCK falling TWD is kept unchanged after TWCK falling edge for a period of (HOLD + 3) × tperipheral clock. 666 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 30.8.6 TWI Status Register Name: TWI_SR Address: 0x4001C020 (1), 0x40040020 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (cleared by writing TWI_THR) TXCOMP used in Master mode: 0: During the length of the current frame. 1: When both holding register and internal shifter are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 30-8. TXCOMP used in Slave mode: 0: As soon as a START is detected. 1: After a STOP or a REPEATED START + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 30-25, Figure 30-26, Figure 30-27 and Figure 30-28. • RXRDY: Receive Holding Register Ready (cleared by reading TWI_RHR) 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 30-8. RXRDY behavior in Slave mode can be seen in Figure 30-23, Figure 30-26, Figure 30-27 and Figure 30-28. • TXRDY: Transmit Holding Register Ready (cleared by writing TWI_THR) TXRDY used in Master mode: 0: The transmit holding register has not been transferred into internal shifter. Set to 0 when writing into TWI_THR. 1: As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 30.7.3.3. TXRDY used in Slave mode: 0: As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1: It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 667 TXRDY behavior in Slave mode can be seen in Figure 30-22, Figure 30-25, Figure 30-27 and Figure 30-28. • SVREAD: Slave Read This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0: Indicates that a write access is performed by a Master. 1: Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 30-22, Figure 30-23, Figure 30-27 and Figure 30-28. • SVACC: Slave Access This bit is only used in Slave mode. 0: TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1: Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 30-22, Figure 30-23, Figure 30-27 and Figure 30-28. • GACC: General Call Access (cleared on read) This bit is only used in Slave mode. 0: No General Call has been detected. 1: A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. GACC behavior can be seen in Figure 30-24. • OVRE: Overrun Error (cleared on read) This bit is only used in Master mode. 0: TWI_RHR has not been loaded while RXRDY was set 1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. • NACK: Not Acknowledged (cleared on read) NACK used in Master mode: 0: Each data byte has been correctly received by the far-end side TWI slave component. 1: A data byte or an address byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. NACK used in Slave Read mode: 0: Each data byte has been correctly received by the Master. 1: In Read mode, a data byte has not been acknowledged by the Master. When NACK is set, the programmer must not fill TWI_THR even if TXRDY is set, because that means that the Master will stop the data transfer or reinitiate it. Note that in Slave write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (cleared on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. 668 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • SCLWS: Clock Wait State This bit is only used in Slave mode. 0: The clock is not stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before transmission / reception of a new character. SCLWS behavior can be seen in Figure 30-25 and Figure 30-26. • EOSACC: End Of Slave Access (cleared on read) This bit is only used in Slave mode. 0: A slave access is being performed. 1: The Slave access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 30-27 and Figure 30-28. • ENDRX: End of RX buffer (cleared by writing TWI_RCR or TWI_RNCR) 0: The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR. 1: The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR. • ENDTX: End of TX buffer (cleared by writing TWI_TCR or TWI_TNCR) 0: The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR. 1: The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR. • RXBUFF: RX Buffer Full (cleared by writing TWI_RCR or TWI_RNCR) 0: TWI_RCR or TWI_RNCR have a value other than 0. 1: Both TWI_RCR and TWI_RNCR have a value of 0. • TXBUFE: TX Buffer Empty (cleared by writing TWI_TCR or TWI_TNCR) 0: TWI_TCR or TWI_TNCR have a value other than 0. 1: Both TWI_TCR and TWI_TNCR have a value of 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 669 30.8.7 TWI Interrupt Enable Register Name: TWI_IER Address: 0x4001C024 (1), 0x40040024 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. • TXCOMP: Transmission Completed Interrupt Enable • RXRDY: Receive Holding Register Ready Interrupt Enable • TXRDY: Transmit Holding Register Ready Interrupt Enable • SVACC: Slave Access Interrupt Enable • GACC: General Call Access Interrupt Enable • OVRE: Overrun Error Interrupt Enable • NACK: Not Acknowledge Interrupt Enable • ARBLST: Arbitration Lost Interrupt Enable • SCL_WS: Clock Wait State Interrupt Enable • EOSACC: End Of Slave Access Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable 670 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 30.8.8 TWI Interrupt Disable Register Name: TWI_IDR Address: 0x4001C028 (1), 0x40040028 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. • TXCOMP: Transmission Completed Interrupt Disable • RXRDY: Receive Holding Register Ready Interrupt Disable • TXRDY: Transmit Holding Register Ready Interrupt Disable • SVACC: Slave Access Interrupt Disable • GACC: General Call Access Interrupt Disable • OVRE: Overrun Error Interrupt Disable • NACK: Not Acknowledge Interrupt Disable • ARBLST: Arbitration Lost Interrupt Disable • SCL_WS: Clock Wait State Interrupt Disable • EOSACC: End Of Slave Access Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 671 30.8.9 TWI Interrupt Mask Register Name: TWI_IMR Address: 0x4001C02C (1), 0x4004002C (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. • TXCOMP: Transmission Completed Interrupt Mask • RXRDY: Receive Holding Register Ready Interrupt Mask • TXRDY: Transmit Holding Register Ready Interrupt Mask • SVACC: Slave Access Interrupt Mask • GACC: General Call Access Interrupt Mask • OVRE: Overrun Error Interrupt Mask • NACK: Not Acknowledge Interrupt Mask • ARBLST: Arbitration Lost Interrupt Mask • SCL_WS: Clock Wait State Interrupt Mask • EOSACC: End Of Slave Access Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask 672 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 30.8.10 TWI Receive Holding Register Name: TWI_RHR Address: 0x4001C030 (1), 0x40040030 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Master or Slave Receive Holding Data SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 673 30.8.11 TWI Transmit Holding Register Name: TWI_THR Address: 0x4001C034 (1), 0x40040034 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Master or Slave Transmit Holding Data 674 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 30.8.12 TWI Write Protection Mode Register Name: TWI_WPMR Address: 0x4001C0E4 (1), 0x400400E4 (2) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x545749 (“TWI” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x545749 (“TWI” in ASCII). See Section 30.7.6 “Register Write Protection” for the list of registers that can be write-protected. • WPKEY: Write Protection Key Value 0x545749 Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 675 30.8.13 TWI Write Protection Status Register Name: TWI_WPSR Address: 0x4001C0E8 (1), 0x400400E8 (2) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 23 22 21 20 WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the TWI_WPSR. 1: A write protection violation has occurred since the last read of the TWI_WPSR. If this violation is an unauthorized attempt to write a protected register, the violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC shows the register address offset at which a write access has been attempted. 676 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 31. Inter-IC Sound Controller (I2SC) 31.1 Description The Inter-IC Sound Controller (I2SC) provides a 5-wire, bidirectional, synchronous, digital audio link to external audio devices: I2SDI, I2SDO, I2SWS, I2SCK, and I2SMCK pins. The I2SC is compliant with the Inter-IC Sound (I2S) bus specification. The I2SC consists of a receiver, a transmitter and a common clock generator that can be enabled separately to provide Master, Slave or Controller modes with receiver and/or transmitter active. Peripheral DMA Controller (PDC) channels, separate for the receiver and for the transmitter, allow a continuous high bit rate data transfer without processor intervention to the following: Audio CODECs in Master, Slave, or Controller mode Stereo DAC or ADC through a dedicated I2S serial interface The I2SC can use either a single PDC channel for both audio channels or one PDC channel per audio channel. The 8- and 16-bit compact stereo format reduces the required PDC bandwidth by transferring the left and right samples within the same data word. In Master mode, the I2SC can produce a 16 fs to 1024 fs master clock that provides an over-sampling clock to an external audio codec or digital signal processor (DSP). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 677 31.2 Embedded Characteristics Compliant with Inter-IC Sound (I2S) Bus Specification Master, Slave, and Controller Modes ̶ Slave: Data Received/Transmitted ̶ Master: Data Received/Transmitted And Clocks Generated ̶ Controller: Clocks Generated Individual Enable and Disable of Receiver, Transmitter and Clocks Configurable Clock Generator Common to Receiver and Transmitter ̶ ̶ Suitable for a Wide Range of Sample Frequencies (fs), Including 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz 678 16 fs to 1024 fs Master Clock Generated for External Oversampling Data Converters Support for Multiple Data Formats ̶ 32-, 24-, 20-, 18-, 16-, and 8-bit Mono or Stereo Format ̶ 16- and 8-bit Compact Stereo Format, with Left and Right Samples Packed in the Same Word to Reduce Data Transfers PDC Interfaces the Receiver and Transmitter to Reduce Processor Overhead ̶ One PDC Channel for Both Audio Channels, or ̶ One PDC Channel Per Audio Channel Smart Holding Registers Management to Avoid Audio Channels Mix After Overrun or Underrun SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 31.3 Block Diagram Figure 31-1. I2SC Block Diagram I2SC Power Manager PIO Peripheral Clock I2SMCK Bus Interface I2SCK Clocks I2SWS Peripheral Bus Bridge Peripheral DMA Controller Interrupt Controller 31.4 I2SDI Transmitter I2SDO I/O Lines Description Table 31-1. Pin Name 31.5 Receiver Events I/O Lines Description Pin Description Type I2SMCK Master Clock Output I2SCK Serial Clock Input/Output 2 I2SWS I S Word Select Input/Output I2SDI Serial Data Input Input I2SDO Serial Data Output Output Product Dependencies To use the I2SC, other parts of the system must be configured correctly, as described below. 31.5.1 I/O Lines The I2SC pins may be multiplexed with I/O Controller lines. The user must first program the PIO Controller to assign the required I2SC pins to their peripheral function. If the I2SC I/O lines are not used by the application, they SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 679 can be used for other purposes by the PIO Controller. The user must enable the I2SC inputs and outputs that are used. Table 31-2. I/O Lines Instance Signal I/O Line Peripheral I2SC0 I2SC0_CK PA0 A I2SC0 I2SC0_DI0 PA2 B I2SC0 I2SC0_DO0 PA3 B I2SC0 I2SC0_DO0 PA17 A I2SC0 I2SC0_MCK PA4 B I2SC0 I2SC0_MCK PA18 A I2SC0 I2SC0_WS PA1 A I2SC1 I2SC1_CK PA19 B I2SC1 I2SC1_DI0 PA22 B I2SC1 I2SC1_DO0 PA23 A I2SC1 I2SC1_MCK PA24 A I2SC1 I2SC1_WS PA20 B 31.5.2 Power Management If the CPU enters a Sleep mode that disables clocks used by the I2SC, the I2SC stops functioning and resumes operation after the system wakes up from Sleep mode. 31.5.3 Clocks The clock for the I2SC bus interface is generated by the Power Management Controller (PMC). I2SC must be disabled before disabling the clock to avoid freezing the I2SC in an undefined state. 31.5.4 Peripheral DMA Controller The I2SC interfaces to the Peripheral DMA Controller (PDC). Using the I2SC DMA functionality requires the PDC to be programmed first. 31.5.5 Interrupt Sources The I2SC interrupt line is connected to the Interrupt Controller. Using the I2SC interrupt requires the Interrupt Table 31-3. Peripheral IDs Instance ID I2SC0 16 I2SC1 17 Controller to be programmed first. 680 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 31.6 Functional Description 31.6.1 Initialization The I2SC features a receiver, a transmitter and a clock generator for Master and Controller modes. Receiver and transmitter share the same serial clock and word select. Before enabling the I2SC, the selected configuration must be written to the I2SC Mode Register (I2SC_MR). If the I2SC_MR.IMCKMODE bit is set, the I2SC_MR.IMCKFS field must be configured as described in Section 31.6.5 ”Serial Clock and Word Select Generation”. Once the I2SC_MR has been written, the I2SC clock generator, receiver, and transmitter can be enabled by writing a one to the CKEN, RXEN, and TXEN bits in the Control Register (I2SC_CR). The clock generator can be enabled alone in Controller mode to output clocks to the I2SMCK, I2SCK, and I2SWS pins. The clock generator must also be enabled if the receiver or the transmitter is enabled. The clock generator, receiver, and transmitter can be disabled independently by writing a one to I2SC_CR.CXDIS, I2SC_CR.RXDIS and/or I2SC_CR.TXDIS, respectively. Once requested to stop, they stop only when the transmission of the pending frame transmission is completed. 31.6.2 Basic Operation The receiver can be operated by reading the Receiver Holding Register (I2SC_RHR), whenever the Receive Ready (RXRDY) bit in the Status Register (I2SC_SR) is set. Successive values read from RHR correspond to the samples from the left and right audio channels for the successive frames. The transmitter can be operated by writing to the Transmitter Holding Register (I2SC_THR), whenever the Transmit Ready (TXRDY) bit in the I2SC_SR is set. Successive values written to THR correspond to the samples from the left and right audio channels for the successive frames. The RXRDY and TXRDY bits can be polled by reading the I2SC_SR. The I2SC processor load can be reduced by enabling interrupt-driven operation. The RXRDY and/or TXRDY interrupt requests can be enabled by writing a one to the corresponding bit in the Interrupt Enable Register (I2SC_IER). The interrupt service routine associated to the I2SC interrupt request is executed whenever the Receive Ready or the Transmit Ready status bit is set. 31.6.3 Master, Controller and Slave Modes In Master and Controller modes, the I2SC provides the master clock, the serial clock and the word select. I2SMCK, I2SCK, and I2SWS pins are outputs. In Controller mode, the I2SC receiver and transmitter are disabled. Only the clocks are enabled and used by an external receiver and/or transmitter. In Slave mode, the I2SC receives the serial clock and the word select from an external master. I2SCK and I2SWS pins are inputs. The mode is selected by writing the MODE field in the I2SC_MR. Since the MODE field changes the direction of the I2SWS and I2SSCK pins, the I2SC_MR must only be written when the I2SC is stopped in order to avoid unwanted glitches on the I2SWS and I2SCK pins. 31.6.4 I2S Reception and Transmission Sequence As specified in the I2S protocol, data bits are left-justified in the word select time slot, with the MSB transmitted first, starting one clock period after the transition on the word select line. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 681 Figure 31-2. I2S Reception and Transmission Sequence Serial clock I2SCK Word Select I2SWS Data I2SDI/I2SDO MSB LSB MSB Left Channel Right Channel Data bits are sent on the falling edge of the serial clock and sampled on the rising edge of the serial clock. the word select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel. The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the I2SC_MR.DATALENGTH field. If the time slot allows for more data bits than written in the I2SC_MR.DATALENGTH field, zeroes are appended to the transmitted data word or extra received bits are discarded. 31.6.5 Serial Clock and Word Select Generation The generation of clocks in the I2SC is described in Figure 31-3 ”I2SC Clock Generation”. In Slave mode, the serial clock and word select clock are driven by an external master. I2SCK and I2SWS pins are inputs. In Master mode, the user can configure the master clock, serial clock, and word select clock through the I2SC_MR. I2SMCK, I2SCK, and I2SWS pins are outputs and MCK is used to derive the I2SC clocks. Audio codecs connected to the I2SC pins may require a master clock (I2SMCK) signal with a frequency multiple of the audio sample frequency (f s ), such as 256f s . When the I2SC is in Master mode, writing a one to I2SC_MR.IMCKMODE outputs MCK as master clock to the I2SMCK pin, and divides MCK to create the internal bit clock, output on the I2SCK pin. The clock division factor is defined by writing to I2SC_MR.IMCKFS and I2SC_MR.DATALENGTH, as described in the I2SC_MR.IMCKFS field description. The master clock (I2SMCK) frequency is [16 × (IMCKFS + 1)] / (IMCKDIV + 1) times the sample frequency (fs), i.e., I2SWS frequency. Example: if the sampling rate is 44.1 kHz with an I2S master clock (I2SMCK) ratio of 256, the core frequency must be an integer multiple of 11.2896 MHz. Assuming an integer multiple of 4, the IMCKDIV field must be configured to 4; the field IMCKFS must then be set to 63. The serial clock (I2SCK) frequency is 2 × Slot Length times the sample frequency (fs), where Slot Length is defined in Table 31-4. Table 31-4. Slot Length I2SC_MR.DATALENGTH Word Length Slot Length 0 32 bits 32 1 24 bits 2 20 bits 3 18 bits 4 16 bits 5 16 bits compact stereo 32 if I2SC_MR.IWS = 0 24 if I2SC_MR.IWS = 1 16 682 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Table 31-4. Slot Length (Continued) I2SC_MR.DATALENGTH Word Length 6 8 bits 7 8 bits compact stereo Slot Length 8 Warning: I2SC_MR.IMCKMODE must only be written to one if the master clock frequency is strictly higher than the serial clock. If a master clock output is not required, the MCK clock is used as I2SCK by clearing I2SC_MR.IMCKMODE. Alternatively, if the frequency of the MCK clock used is a multiple of the required I2SCK frequency, the I2SMCK to I2SCK divider can be used with the ratio defined by writing the I2SC_MR.IMCKFS field. The I2SWS pin is used as word select as described in Section 31.6.4 ”I2S Reception and Transmission Sequence”. Figure 31-3. I2SC Clock Generation I2SC_CR.CKEN/CKDIS I2SC_MR.IMCKMODE I2SC_MR.IMCKDIV Peripheral Clock Clock Divider Clock Enable Clock Divider I2SC_MR.IMCKMODE 0 1 I2SMCK I2SC_MR.IMCKFS I2SC_MR.DATALENGTH I2SCK master 0 I2SCK_in slave 1 Clock Enable I2SC_CR.CKEN/CKDIS I2SC_MR.MODE I2SCK_in internal bit clock Clock Divider I2SC_MR.DATALENGTH I2SWS 0 I2SWS_in 1 I2SWS_in internal word clock slave 31.6.6 Mono When the Transmit Mono bit (TXMONO) in I2SC_MR is set, data written to the left channel is duplicated to the right output channel. When the Receive Mono bit (RXMONO) in I2SC_MR is set, data received from the left channel is duplicated to the right channel. 31.6.7 Holding Registers The I2SC user interface includes a Receive Holding Register (I2SC_RHR) and a Transmit Holding Register (I2SC_THR). These registers are used to access audio samples for both audio channels. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 683 When a new data word is available in I2SC_RHR, the Receive Ready bit (RXRDY) in I2SC_SR is set. Reading I2SC_RHR clears this bit. A receive overrun condition occurs if a new data word becomes available before the previous data word has been read from I2SC_RHR. In this case, the Receive Overrun bit in I2SC_SR and bit i of the RXORCH field in I2SC_SR are set, where i is the current receive channel number. When I2SC_THR is empty, the Transmit Ready bit (TXRDY) in I2SC_SR is set. Writing to I2SC_THR clears this bit. A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to I2SC_THR. In this case, the Transmit Underrun (TXUR) bit and bit i of the TXORCH field in I2SC_SR are set, where i is the current transmit channel number. If the TXSAME bit in I2SC_MR is zero, then a zero data word is transmitted in case of underrun. If I2SC_MR.TXSAME is one, then the previous data word for the current transmit channel number is transmitted. Data words are right-justified in I2SC_RHR and I2SC_THR. For the 16-bit compact stereo data format, the left sample uses bits 15:0 and the right sample uses bits 31:16 of the same data word. For the 8-bit compact stereo data format, the left sample uses bits 7:0 and the right sample uses bits 15:8 of the same data word. 31.6.8 Peripheral DMA Controller Operation All receiver audio channels can be assigned to a single PDC channel or individual audio channels can be assigned to one PDC channel per audio channel. The same channel assignment choice applies to the transmitter audio channels. Channel assignment is selected by writing to the I2SC_MR.RXDMA and I2SC_MR.TXDMA bits. If a single PDC channel is selected, all data samples use I2SC receiver or transmitter PDC channel 0. The PDC reads from the I2SC_RHR and writes to the I2SC_THR for both audio channels successively. The PDC transfers may use 32-bit word, 16-bit halfword, or 8-bit byte depending on the value of the I2SC_MR.DATALENGTH field. 31.6.9 Loop-back Mode For debug purposes, the I2SC can be configured to loop back the transmitter to the Receiver. Writing a one to the I2SC_MR.LOOP bit internally connects I2SDO to I2SDI, so that the transmitted data is also received. Writing a zero to I2SC_MR.LOOP restores the normal behavior with independent Receiver and Transmitter. As for other changes to the Receiver or Transmitter configuration, the I2SC Receiver and Transmitter must be disabled before writing to I2SC_MR to update I2SC_MR.LOOP. 31.6.10 Interrupts An I2SC interrupt request can be triggered whenever one or several of the following bits are set in I2SC_SR: Receive Ready (RXRDY), Receive Overrun (RXOR), Transmit Ready (TXRDY) or Transmit Underrun (TXUR). The interrupt request is generated if the corresponding bit in the Interrupt Mask Register (I2SC_IMR) is set. Bits in I2SC_IMR are set by writing a one to the corresponding bit in I2SC_IER and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (I2SC_IDR). The interrupt request remains active until the corresponding bit in I2SC_SR is cleared by writing a one to the corresponding bit in the Status Clear Register (I2SC_SCR). For debug purposes, interrupt requests can be simulated by writing a one to the corresponding bit in the Status Set Register (I2SC_SSR). 684 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 31-4. Interrupt Block Diagram Set I2SC_IER Clear I2SC_IMR I2SC_IDR Transmitter TXRDY TXUR Interrupt Logic I2SC interrupt line Receiver RXRDY RXOR 31.7 I2SC Application Examples The I2SC supports several serial communication modes used in audio or high-speed serial links. Examples of standard applications are shown in the following figures. All serial link applications supported by the I2SC are not listed here. Figure 31-5. Slave Transmitter I2SC Application Example I2SC Serial Clock I2SCK Stereo Audio DAC Word Select I2SWS Serial Data Out I2SDO I2SDI Serial Clock Word Select Serial Data Out MSB LSB MSB SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 685 Figure 31-6. Dual Microphone Application Block Diagram I2S Microphone for Left Channel I2SC I2SMCK Serial Clock I2SCK Word Select I2SWS SCK WS L/R Tied to 1 I2SDO Serial Data In I2SDI SD I2S Microphone for Right Channel SCK WS L/R Tied to 0 SD Serial Clock Left Channel Word Select Right Channel Dend Dstart Serial Data In Figure 31-7. Codec Application Block Diagram I2SC Master Clock I2SMCK Serial Clock I2SCK Word Select I2SWS Serial Data Out I2SDO Serial Data In I2SDI MCLK I2S Audio Codec BCLK LRCLK/WCLK DAC_SDATA/DIN ADC_SDATA/DOUT Serial Clock Word Select Left Time Slot Dstart Serial Data Out Serial Data In 686 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Right Time Slot Dend 31.8 Inter-IC Sound Controller (I2SC) User Interface Table 31-5. Register Mapping Offset Register Name Access Reset 0x00 Control Register I2SC_CR Write-only – 0x04 Mode Register I2SC_MR Read/Write 0x00000000 0x08 Status Register I2SC_SR Read-only 0x00000000 0x0C Status Clear Register I2SC_SCR Write-only – 0x10 Status Set Register I2SC_SSR Write-only – 0x14 Interrupt Enable Register I2SC_IER Write-only – 0x18 Interrupt Disable Register I2SC_IDR Write-only – 0x1C Interrupt Mask Register I2SC_IMR Read-only 0x00000000 0x20 Receiver Holding Register I2SC_RHR Read-only 0x00000000 0x24 Transmitter Holding Register I2SC_THR Write-only – 0x28–0xFC Reserved – – – 0x100–0x124 Reserved for PDC registers for left side – – – 0x128–0x1FC Reserved – – – 0x200–0x224 Reserved for PDC registers for right side – – – SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 687 31.8.1 Inter-IC Sound Controller Control Register Name: I2SC_CR Address: 0x40000000 (0), 0x40004000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 TXDIS 4 TXEN 3 CKDIS 2 CKEN 1 RXDIS 0 RXEN • RXEN: Receiver Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit enables the I2SC receiver, if RXDIS is not one. Bit I2SC_SR.RXEN is set when the receiver is activated. • RXDIS: Receiver Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit disables the I2SC receiver. Bit I2SC_SR.RXEN is cleared when the receiver is stopped. • CKEN: Clocks Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit enables the I2SC clocks generation, if CKDIS is not one. • CKDIS: Clocks Disable 0: Writing a zero to this bit has no effect. 1: Writing a zone to this bit disables the I2SC clock generation. • TXEN: Transmitter Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit enables the I2SC transmitter, if TXDIS is not one. Bit I2SC_SR.TXEN is set when the Transmitter is started. • TXDIS: Transmitter Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit disables the I2SC transmitter. Bit I2SC_SR.TXEN is cleared when the Transmitter is stopped. • SWRST: Software Reset 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit resets all the registers in the I2SC. The I2SC is disabled after the reset. 688 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 31.8.2 Inter-IC Sound Controller Mode Register Name: I2SC_MR Address: 0x40000004 (0), 0x40004004 (1) Access: Read/Write 31 IWS 30 IMCKMODE 29 23 – 22 – 21 15 – 14 TXSAME 13 TXDMA 12 TXMONO 6 5 – 4 7 FORMAT 28 27 26 25 24 18 17 16 11 – 10 RXLOOP 9 RXDMA 8 RXMONO 3 DATALENGTH 2 1 – 0 MODE IMCKFS 20 19 IMCKDIV The I2SC_MR must only be written when the I2SC is stopped in order to avoid unexpected behavior on the I2SWS, I2SCK and I2SDO outputs. The proper sequence is to write to I2SC_MR, then write to I2SC_CR to enable the I2SC or to disable the I2SC before writing a new value to I2SC_MR. • MODE: Inter-IC Sound Controller Mode Value Name Description 0 SLAVE I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization. 1 MASTER Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set. • DATALENGTH: Data Word Length Value Name Description 0 32_BITS Data length is set to 32 bits 1 24_BITS Data length is set to 24 bits 2 20_BITS Data length is set to 20 bits 3 18_BITS Data length is set to 18 bits 4 16_BITS Data length is set to 16 bits 5 16_BITS_COMPAC T Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. 6 8_BITS Data length is set to 8 bits 7 8_BITS_COMPACT Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. • FORMAT: Data Format Value Name Description 0 I2S I2S format, stereo with I2SWS low for left channel, and MSB of sample starting one I2SCK period after I2SWS edge 1 LJ Left-justified format, stereo with I2SWS high for left channel, and MSB of sample starting on I2SWS edge 2 – Reserved 3 – Reserved SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 689 • RXDMA: Single or Multiple PDC Channels for Receiver 0: Receiver uses one PDC channel for both audio channels. 1: Receiver uses one PDC channel per audio channel. • RXMONO: Receive Mono 0: Stereo 1: Mono, with left audio samples duplicated to right audio channel by the I2SC. • RXLOOP: Loop-back Test Mode 0: Normal mode 1: I2SDO output of I2SC is internally connected to I2SDI input. • TXMONO: Transmit Mono 0: Stereo 1: Mono, with left audio samples duplicated to right audio channel by the I2SC. • TXDMA: Single or Multiple PDC Channels for Transmitter 0: Transmitter uses one PDC channel for both audio channels. 1: Transmitter uses one PDC channel per audio channel. • TXSAME: Transmit Data when Underrun 0: Zero sample transmitted when underrun. 1: Previous sample transmitted when underrun • IMCKDIV: Peripheral Clock to I2SC Master Clock Ratio I2SMCK Master clock output frequency is Peripheral Clock divided by (IMCKDIV + 1). Please refer to the IMCKFS field description. Note: This field is write-only. Always read as 0. • IMCKFS: Master Clock to fs Ratio Master clock frequency is [16 × (IMCKFS + 1)] / (IMCKDIV + 1) times the sample rate, i.e., I2SWS frequency. Value Name Description 0 M2SF16 Sample frequency ratio set to 16 1 M2SF32 Sample frequency ratio set to 32 2 M2SF48 Sample frequency ratio set to 48 3 M2SF64 Sample frequency ratio set to 64 5 M2SF96 Sample frequency ratio set to 96 7 M2SF128 Sample frequency ratio set to 128 11 M2SF192 Sample frequency ratio set to 192 15 M2SF256 Sample frequency ratio set to 256 23 M2SF384 Sample frequency ratio set to 384 31 M2SF512 Sample frequency ratio set to 512 47 M2SF768 Sample frequency ratio set to 768 63 M2SF1024 Sample frequency ratio set to 1024 690 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 • IMCKMODE: Master Clock Mode 0: No master clock generated (Peripheral Clock drives I2SCK output). 1: Master clock generated (internally generated clock is used as I2SMCK output). Warning: If I2SMCK frequency is the same as I2SCK, IMCKMODE must be cleared. Refer to Section 31.6.5 ”Serial Clock and Word Select Generation” and Table 31-4 “Slot Length”. • IWS: I2SWS Slot Width 0: I2SWS slot is 32 bits wide for DATALENGTH = 18/20/24 bits. 1: I2SWS slot is 24 bits wide for DATALENGTH = 18/20/24 bits. Refer to Table 31-4 “Slot Length”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 691 31.8.3 Inter-IC Sound Controller Status Register Name: I2SC_SR Address: 0x40000008 (0), 0x40004008 (1) Access: Read-only 31 TXBUFE 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 20 19 RXBUFF 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 ENDTX 6 TXUR 5 TXRDY 4 TXEN 3 ENDRX 2 RXOR 1 RXRDY TXURCH 8 RXORCH 0 RXEN • RXEN: Receiver Enabled 0: This bit is cleared when the receiver is disabled, following a RXDIS or SWRST request in I2SC_CR. 1: This bit is set when the receiver is enabled, following a RXEN request in I2SC_CR. • RXRDY: Receive Ready 0: This bit is cleared when I2SC_RHR is read. 1: This bit is set when received data is present in I2SC_RHR. • RXOR: Receive Overrun 0: This bit is cleared when the corresponding bit in I2SC_SCR is written to one. 1: This bit is set when an overrun error occurs on I2SC_RHR or when the corresponding bit in I2SC_SSR is written to one. • ENDRX: End of Receiver Transfer 0: This bit is set when PDC has completed the receive transfer. 1: This bit is cleared when a new receive transfer is programmed into the PDC. • TXEN: Transmitter Enabled 0: This bit is cleared when the transmitter is disabled, following a I2SC_CR.TXDIS or I2SC_CR.SWRST request. 1: This bit is set when the transmitter is enabled, following a I2SC_CR.TXEN request. • TXRDY: Transmit Ready 0: This bit is cleared when data is written to I2SC_THR. 1: This bit is set when I2SC_THR is empty and can be written with new data to be transmitted. • TXUR: Transmit Underrun 0: This bit is cleared when the corresponding bit in I2SC_SCR is written to one. 1: This bit is set when an underrun error occurs on I2SC_THR or when the corresponding bit in I2SC_SSR is written to one. • ENDTX: End of Transmitter Transfer 0: This bit is set when the PDC has completed the transmit transfer. 692 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 1: This bit is cleared when a new transmit transfer is programmed into the PDC. • RXORCH: Receive Overrun Channel This field is cleared when I2SC_SCR.RXOR is written to one. Bit i of this field is set when a receive overrun error occurred in channel i (i = 0 for first channel of the frame). • RXBUFF: Receive Buffer Full 0: This bit is set when received data is present in I2SC_RHR. 1: This bit is cleared when I2SC_RHR is read and no more received data is present. • TXURCH: Transmit Underrun Channel 0: This field is cleared when I2SC_SCR.TXUR is written to one. 1: Bit i of this field is set when a transmit underrun error occurred in channel i (i = 0 for first channel of the frame). • TXBUFE: Transmit Buffer Empty 0: This bit is set when I2SC_THR is empty and can be written with new data to be transmitted. 1: This bit is cleared when data is written to I2SC_THR and is being transmitted. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 693 31.8.4 Inter-IC Sound Controller Status Clear Register Name: I2SC_SCR Address: 0x4000000C (0), 0x4000400C (1) Access: Write-only 31 – 30 – 29 – 23 – 22 – 21 15 – 14 – 7 – 6 TXUR 28 – 27 – 26 – 25 – 24 – 20 19 – 18 – 17 – 16 – 13 – 12 – 11 – 10 – 9 5 – 4 – 3 – 2 RXOR 1 – TXURCH 8 RXORCH 0 – • RXOR: Receive Overrun Status Clear Writing a zero to this bit has no effect. Writing a one to this bit clears the status bit. • TXUR: Transmit Underrun Status Clear Writing a zero to this bit has no effect. Writing a one to this bit clears the status bit. • RXORCH: Receive Overrun Per Channel Status Clear Writing a zero has no effect. Writing a one to any bit in this field clears the corresponding bit in the I2SC_SR and the corresponding interrupt request. • TXURCH: Transmit Underrun Per Channel Status Clear Writing a zero has no effect. Writing a one to any bit in this field clears the corresponding bit in the I2SC_SR and the corresponding interrupt request. 694 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 31.8.5 Inter-IC Sound Controller Status Set Register Name: I2SC_SSR Address: 0x40000010 (0), 0x40004010 (1) Access: Write-only 31 – 30 – 29 – 23 – 22 – 21 15 – 14 – 7 – 6 TXUR 28 – 27 – 26 – 25 – 24 – 20 19 – 18 – 17 – 16 – 13 – 12 – 11 – 10 – 9 5 – 4 – 3 – 2 RXOR 1 – TXURCH 8 RXORCH 0 – • RXOR: Receive Overrun Status Set Writing a zero to this bit has no effect. Writing a one to this bit sets the status bit. • TXUR: Transmit Underrun Status Set Writing a zero to this bit has no effect. Writing a one to this bit sets the status bit. • RXORCH: Receive Overrun Per Channel Status Set Writing a zero has no effect. Writing a one to any bit in this field sets the corresponding bit in I2SC_SR and the corresponding interrupt request. • TXURCH: Transmit Underrun Per Channel Status Set Writing a zero has no effect. Writing a one to any bit in this field sets the corresponding bit in I2SC_SR and the corresponding interrupt request. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 695 31.8.6 Inter-IC Sound Controller Interrupt Enable Register Name: I2SC_IER Address: 0x40000014 (0), 0x40004014 (1) Access: Write-only 31 TXEMPTY 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXFULL 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ENDTX 6 TXUR 5 TXRDY 4 – 3 ENDRX 2 RXOR 1 RXRDY 0 – • RXRDY: Receiver Ready Interrupt Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit sets the corresponding bit in I2SC_IMR. • RXOR: Receiver Overrun Interrupt Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit sets the corresponding bit in I2SC_IMR. • ENDRX: End of Reception Interrupt Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit sets the corresponding bit in the I2SC_IMR. • TXRDY: Transmit Ready Interrupt Enable 0: Writing a zero to this bit as no effect. 1: Writing a one to this bit sets the corresponding bit in I2SC_IMR. • TXUR: Transmit Underflow Interrupt Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit sets the corresponding bit in I2SC_IMR. • ENDTX: End of Transmission Interrupt Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit sets the corresponding bit in I2SC_IMR. • RXFULL: Receive Buffer Full Interrupt Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit sets the corresponding bit in I2SC_IMR. • TXEMPTY: Transmit Buffer Empty Interrupt Enable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit sets the corresponding bit in I2SC_IMR. 696 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 31.8.7 Inter-IC Sound Controller Interrupt Disable Register Name: I2SC_IDR Address: 0x40000018 (0), 0x40004018 (1) Access: Write-only 31 TXEMPTY 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXFULL 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ENDTX 6 TXUR 5 TXRDY 4 – 3 ENDRX 2 RXOR 1 RXRDY 0 – • RXRDY: Receiver Ready Interrupt Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit clears the corresponding bit in I2SC_IMR. • RXOR: Receiver Overrun Interrupt Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit clears the corresponding bit in I2SC_IMR. • ENDRX: End of Reception Interrupt Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit clears the corresponding bit in I2SC_IMR. • TXRDY: Transmit Ready Interrupt Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit clears the corresponding bit in I2SC_IMR. • TXUR: Transmit Underflow Interrupt Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit clears the corresponding bit in I2SC_IMR. • ENDTX: End of Transmission Interrupt Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit clears the corresponding bit in I2SC_IMR. • RXFULL: Receive Buffer Full Interrupt Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit clears the corresponding bit in I2SC_IMR. • TXEMPTY: Transmit Buffer Empty Interrupt Disable 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit clears the corresponding bit in I2SC_IMR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 697 31.8.8 Inter-IC Sound Controller Interrupt Mask Register Name: I2SC_IMR Address: 0x4000001C (0), 0x4000401C (1) Access: Write-only 31 TXEMPTY 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXFULL 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ENDTX 6 TXUR 5 TXRDY 4 – 3 ENDRX 2 RXOR 1 RXRDY 0 – • RXRDY: Receiver Ready Interrupt Disable 0: The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to one. 1: The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to one. • RXOR: Receiver Overrun Interrupt Disable 0: The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to one. 1: The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to one. • ENDRX: End of Reception Interrupt Disable 0: The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to one. 1: The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to one. • TXRDY: Transmit Ready Interrupt Disable 0: The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to one. 1: The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to one. • TXUR: Transmit Underflow Interrupt Disable 0: The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to one. 1: The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to one. • ENDTX: End of Transmission Interrupt Disable 0: The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to one. 1: The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to one. • RXFULL: Receive Buffer Full Interrupt Disable 0: The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to one. 1: The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to one. • TXEMPTY: Transmit Buffer Empty Interrupt Disable 0: The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to one. 1: The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to one. 698 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 31.8.9 Inter-IC Sound Controller Receiver Holding Register Name: I2SC_RHR Address: 0x40000020 (0), 0x40004020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RHR 23 22 21 20 RHR 15 14 13 12 RHR 7 6 5 4 RHR • RHR: Receiver Holding Register This field is set by hardware to the last received data word. If I2SC_MR.DATALENGTH specifies fewer than 32 bits, data is right justified in the RHR field. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 699 31.8.10 Inter-IC Sound Controller Transmitter Holding Register Name: I2SC_THR Address: 0x40000024 (0), 0x40004024 (1) Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 THR 23 22 21 20 THR 15 14 13 12 THR 7 6 5 4 THR • THR: Transmitter Holding Register Next data word to be transmitted after the current word if TXRDY is not set. If I2SC_MR.DATALENGTH specifies fewer than 32 bits, data is right-justified in the THR field. 700 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 32. Pulse Density Modulation Interface Controller (PDMIC) 32.1 Description The Pulse Density Modulation Interface Controller (PDMIC) is a PDM interface controller and decoder that supports both mono/stereo PDM format. It integrates a clock generator driving the PDM microphones and embeds filters which decimate the incoming bitstream to obtain most common audio rates. 32.2 32.3 Embedded Characteristics Multiplexed PDM Input Support 16-bit Resolution PDC Support Up to 4 Conversions Stored in the Converted Data Register (PDMIC_CDR) Register Write Protection Block Diagram Figure 32-1. PDMIC Block Diagram PMC Peripheral Clock PDM Interface Controller PDMIC Interrupt Control Logic Interrupt Controller System Bus PDC Peripheral Bridge Digital Filter User Interface APB PDMIC_DAT PDMIC_CLK PDM Data Sampling Data, to second PDM Interface Controller Clock, from second PDM Interface Controller Configuration, from second PDM Interface Controller SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 701 32.4 Signal Description Table 32-1. 702 PDMIC Pin Description Pin Name Description Type PDMIC_CLK Pulse Density Modulation Bitstream Sampling Clock Output PDMIC_DAT Pulse Density Modulation Multiplexed Data Input SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 32.5 Product Dependencies 32.5.1 I/O Lines The pins used for interfacing the PDMIC are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to PDMIC pins. Table 32-2. I/O Lines Instance Signal I/O Line Peripheral PDMIC0 PDMIC0_CLK PA10 B PDMIC0 PDMIC0_DAT PA9 B 32.5.2 Power Management The PDMIC is not continuously clocked. The user must first enable the PDMIC peripheral clock in the Power Management Controller (PMC) before using the controller. 32.5.3 Interrupt Sources The PDMIC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the PDMIC Table 32-3. Peripheral IDs Instance ID PDMIC0 13 PDMIC1 18 interrupt requires the Interrupt Controller to be programmed first. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 703 32.6 Functional Description 32.6.1 PDM Interface 32.6.1.1 Description The PDM clock (PDMIC_CLK) is used to sample the PDM bitstream. The PDMIC_CLK frequency range is between peripheral clock/2 and peripheral clock/256. The field PRESCAL in the Mode Register (PDMIC_MR) must be programmed in order to provide a PDMIC_CLK frequency compliant with the microphone parameters. 32.6.1.2 Start-up Sequence To start processing the bitstream coming from the PDM interface, follow the steps below: 1. Clear all bits in the Control Register (PDMIC_CR) or compute a soft reset using the SWRST bit of PDMIC_CR. 2. Configure the PRESCAL field in PDMIC_MR according to the microphone specifications. 3. Enable the PDM mode and start the conversions using the ENPDM bit in PDMIC_CR. 32.6.1.3 Restrictions The external PDM data sampling module is shared with two PDMIC modules. When two PDM microphones are connected on the PDMIC_DAT line, both PDMICs must be enabled and the steps below must be followed: 1. Clear all bits in PDMIC_CR or compute a soft reset using the SWRST bit of PDMIC_CR in both PDMIC modules. 2. Configure the PMC to provide the same clock to both PDMIC modules (clock frequencies should be the same). 3. Configure the PRESCAL field in PDMIC_MR according to the microphone specifications (the PRESCAL value should be the same in both PDMIC). 4. Enable the PDM mode and start the conversions using the ENPDM bit in PDMIC_CR in the PDMIC0. 5. Enable the PDM mode and start the conversions using the ENPDM bit in PDMIC_CR in the PDMIC1. To stop the conversions, follow the steps below: 1. Disable the PDM mode or compute a software reset in the PDMIC1. 2. Disable the PDM mode or compute a software reset in the PDMIC0. The bitstream sampled on the rising edge of the PDMIC_CLK is routed to the PDMIC0 and the bitstream sampled on the falling edge of the PDMIC_CLK is routed to the PDMIC1. 32.6.2 Digital Signal Processing (Digital Filter) 32.6.2.1 Description The PDMIC includes a DSP section containing a decimation filter, a droop compensation filter, a sixth-order low pass filter, a first-order high pass filter and an offset and gain compensation stage. A block diagram of the DSP section is represented in Figure 32-2 “DSP Block Diagram”. Data processed by the filtering section are two’s complement signals defined on 24 bits. The filtering of the decimation stage is performed by a fourth-order sinc-based filter whose zeros are placed in order to minimize aliasing effects of the decimation. The decimation ratio of this filter is either 32 or 64. The droop induced by this filter can be compensated by the droop compensation stage. The sixth-order low pass filter is used to decimate the sinc filter output by a ratio of 2. An optional first-order high pass filter is implemented in order to eliminate the DC component of the incoming signal. 704 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 The overall decimation ratio of this DSP section is either 64 or 128. This fits an audio sampling rate of 48 kHz with a PDM microphone sampling frequency of either 3.072 or 6.144 MHz. The frequency response of the filters optimizes the gain flatness between 0 and 20 kHz (when the droop compensation filter is implemented and the high pass filter is bypassed) and highly reduces the aliasing effects of the decimation. Figure 32-2. DSP Block Diagram hpf_byp sincc_byp PDC 16 or 32 bits data0 3 24 24 32 + 2 Droop Compensation High Pass Filter Low Pass Filter signed right shift 0 1 0 1 16 LSBs ... 0 1 1 data Decimation offset * 28 32.6.2.2 32 1 signed right shift 32/64 SINC Filter Decimation ... 0 { 1 scale gain shift Decimation Filter The sigma-delta architecture of the PDM microphone implies a filtering and a decimation of the bitstream at the output of the microphone bitstream. The decimation filter decimates the bitstream by either 32 or 64. To perform this operation, a fourth-order sinc filter with an Over-Sampling Ratio (OSR) of 32 or 64 is implemented with the following transfer function: OSR – 1 1 –i H ( z ) = -------------4- z OSR i=0 4 The DC gain of this filter is unity and does not depend on its OSR. However, as it generates a fourth-order zero at Fs/OSR frequency multiples (Fs being the sampling frequency of the microphone), the frequency response of the decimation filter depends on the OSR parameter. See Section 32.6.2.3 “Droop Compensation” for frequency plots. Its non-flat frequency response can be compensated over the 0 to 20 kHz band by using the droop compensation filter when the decimated frequency is set to 48 kHz. See Section 32.6.2.3 “Droop Compensation”. If the decimated sampling rate is modified, the frequency response of this filter is scaled proportionally to the new frequency. In Figure 32-3 and Figure 32-4, Fs is the sampling rate of the PDM microphone. Figure 32-3. Spectral mask of an OSR = 32, Fs = 6.144 MHz, Fourth-Order Sinc Filter: Overall Response (continuous line) and 0 to 20 kHz Bandwidth Response (dashed line) frequency (kHz), base band, output sampling rate = 48 kHz 0 2.5 5 7.5 10 12.5 15 17.5 20 0 -24 -0.14 -48 -0.28 -72 -0.42 -96 -0.56 -120 0 Fs/16 2*Fs/16 3*Fs/16 4*Fs/16 5*Fs/16 frequency (Hz), overall mask 6*Fs/16 7*Fs/16 gain (dB), base band gain (dB), overall mask 0 -0.7 8*Fs/16 The zeros of this filter are located at multiples of Fs/32 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 705 Figure 32-4. Spectral Mask of an OSR = 64, Fs = 3.072 MHz, Fourth-order Sinc Filter: Overall Response (continuous line) and 0 to 20 kHz Bandwidth Response (dashed line) frequency (kHz), base band, output sampling rate = 48 kHz 2.5 5 7.5 10 12.5 15 17.5 20 0 -24 -0.6 -48 -1.2 -72 -1.8 -96 -2.4 -120 0 Fs/16 2*Fs/16 3*Fs/16 4*Fs/16 5*Fs/16 frequency (Hz), overall mask 6*Fs/16 7*Fs/16 gain (dB), base band gain (dB), overall mask 0 0 -3 8*Fs/16 The zeros of this filter are located at multiples of Fs/64. 32.6.2.3 Droop Compensation The droop effect introduced by the sinc filter can be compensated in the 0 to 20 kHz by the droop compensation filter (see Figure 32-5). This is a second-order IIR filter which is applied on the signal output by the sinc. The default coefficients of the droop compensation filter are computed to optimize the droop of the sinc filter with the decimated frequency equal to 48 kHz. This filter compensates the droop of the sinc filter regardless of the OSR value. If the decimated sampling rate is modified, the frequency response of this filter is scaled proportionally to the new frequency. This filter can be bypassed by setting the SINBYP bit in the PDMIC DSP Configuration Register 0 (PDMIC_DSPR0). Figure 32-5. Droop Compensation Filter Overall Frequency Response droop compensation overall response 2 sinc filter response sinc filter+droop compensation response 0 gain (dB) -2 -4 -6 -8 -10 706 0 1 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 2 3 4 5 6 frequency (Hz) 7 8 9 10 4 x 10 Figure 32-6. Droop Compensation Filter 0 to 20 kHz Band Flatness -4 2 droop compensation flatness in 0-20kHz band x 10 gain (dB) 1 0 -1 -2 0.2 0.4 0.6 0.8 1 1.2 frequency (Hz) 1.4 1.6 1.8 2 4 x 10 Low Pass Filter The PDMIC includes a sixth-order IIR filter that performs a low pass transfer function and decimates by 2 the output of the sinc filter. The coefficients are computed for a decimated sampling rate of 48 kHz and optimize the 0 to 20 kHz band flatness while rejecting the aliasing of the PDM microphone by at least 60 dB in the 28 to 48 kHz band. If the decimated sampling rate is modified, the frequency response of this filter is scaled proportionally to the new frequency. Figure 32-7 and Figure 32-8 are drawn for an output sampling frequency of 48 kHz. Figure 32-7. Low Pass Filter Spectral Mask Low pass filter spectral mask 0 -20 -40 gain (dB) 32.6.2.4 0 -60 -80 -100 -120 0 0.5 1 1.5 2 2.5 3 frequency (Hz) 3.5 4 4.5 5 4 x 10 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 707 Figure 32-8. Low Pass Filter Ripple in the 0 to 20 kHz Band Low pass filter 0-20kHz ripple 0.05 0.04 0.03 0.02 gain (dB) 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 32.6.2.5 0 0.2 0.4 0.6 0.8 1 1.2 frequency (Hz) 1.4 1.6 1.8 2 4 x 10 High Pass Filter The PDMIC includes an optional first-order IIR filter performing a high pass transfer function after the low pass filter and before the decimation. The coefficients are computed for a decimated sampling rate of 48 kHz to obtain a -3dB cutoff frequency at 15 Hz. If the decimated sampling rate is modified, the frequency response of this filter is scaled proportionally to the new frequency. This filter can be bypassed by setting the HPFBYP bit in PDMIC_DSPR0 (see “PDMIC DSP Configuration Register 0” on page 719). Figure 32-9 is drawn for an output sampling frequency of 48 kHz. Figure 32-9. High Pass Filter Spectral Mask in the 0 to 100 Hz Band High pass filter spectral mask 0 -5 gain (dB) -10 -15 -20 -25 -30 32.6.2.6 0 10 20 30 40 50 60 frequency (Hz) 70 80 90 100 Gain and Offset Compensation An offset, a gain, a scaling factor and a shift can be applied to a converted PDM microphone value using the following operation: 8 ( data 0 + offset × 2 ) × dgain data = -----------------------------------------------------------------------scale + shift + 8 2 where: 708 data0 is a signed integer defined on 24 bits. It is the output of the filtering channel. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 offset is a signed integer defined on 16 bits (see PDMIC DSP Configuration Register 1). It is multiplied by 28 to have the same weight as data0. dgain is an unsigned integer defined on 15 bits (see PDMIC DSP Configuration Register 1). Only the 32 MSBs of the multiplication operation are used for scaling and shifting operations. scale is an unsigned integer defined on 4 bits (see PDMIC DSP Configuration Register 0). It shifts the multiplication operation result by scale bits to the right. Maximum allowed value is 15. shift is an unsigned integer defined on 4 bits (see PDMIC DSP Configuration Register 0). It shifts the multiplication operation result by shift bits to the right. Maximum allowed value is 15. If the data transfer is configured in 32-bit mode (see PDMIC DSP Configuration Register 0), the 2shift division is not performed and the 32-bit result of the remaining operation is sent. If the data transfer is configured in 16-bit mode, the 2shift division is performed. The result is then saturated to be within ±(215-1) and the 16 LSBs of this saturation operation are sent to the controller as the result of the PDM microphone conversion. Default parameters are defined to output a 16-bit result whatever the data transfer configuration may be. 32.6.3 Conversion Results When a conversion is completed, the resulting 16-bit digital value is stored in the PDMIC Converted Data Register (PDMIC_CDR). The DRDY bit in the Interrupt Status Register (PDMIC_ISR) is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, DRDY can trigger an interrupt. Reading PDMIC_CDR clears the DRDY flag. Figure 32-10. DRDY Flag Behavior Write the PDMIC_CR with ENPDM = 1 Read the PDMIC_CDR Read the PDMIC_CDR DRDY (PDMIC_SR) If PDMIC_CDR is not read before further incoming data is converted, the Overrun Error (OVRE) flag is set in PDMIC_ISR. Likewise, new data converted when DRDY is high sets the OVRE bit (Overrun Error) in PDMIC_ISR. In case of overrun, the newly converted data is lost. The OVRE flag is automatically cleared when PDMIC_ISR is read. 32.6.4 Buffer Structure The PDC read channel is triggered each time new data is stored in PDMIC_CDR. The same structure of data is repeatedly stored in PDMIC_CDR each time a trigger event occurs. Depending on the user mode of operation as defined in PDMIC_MR, the structure differs. Each data transfer to PDC buffer, carried on a half-word (16-bit), consists of the last converted data, right-aligned. 32.6.5 Register Write Protection To prevent any single software error from corrupting PDMIC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PDMIC Write Protection Mode Register (PDMIC_WPMR). SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 709 If a write access to a write-protected register is detected, the WPVS flag in the PDMIC Write Protection Status Register (PDMIC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PDMIC_WPSR. The following registers can be write-protected: 710 PDMIC Mode Register PDMIC DSP Configuration Register 0 PDMIC DSP Configuration Register 1 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 32.7 Pulse Density Modulation Interface Controller (PDMIC) User Interface Table 32-4. Register Mapping Offset(1) Register Name Access Reset 0x00 Control Register PDMIC_CR Read/Write 0x00000000 0x04 Mode Register PDMIC_MR Read/Write 0x00F00000 Reserved – – – 0x14 Converted Data Register PDMIC_CDR Read-only 0x00000000 0x18 Interrupt Enable Register PDMIC_IER Write-only – 0x1C Interrupt Disable Register PDMIC_IDR Write-only – 0x20 Interrupt Mask Register PDMIC_IMR Read-only 0x00000000 0x24 Interrupt Status Register PDMIC_ISR Read-only 0x00000000 Reserved – – – 0x58 DSP Configuration Register 0 PDMIC_DSPR0 Read/Write 0x00000000 0x5C DSP Configuration Register 1 PDMIC_DSPR1 Read/Write 0x00000001 Reserved – – – 0xE4 Write Protection Mode Register PDMIC_WPMR Read/Write 0x00000000 0xE8 Write Protection Status Register PDMIC_WPSR Read-only 0x00000000 Reserved – – – Reserved for PDC Registers – – – 0x08–0x10 0x28–0x54 0x60–0xE0 0xEC–0xFC 0x100–0x124 Notes: 1. If an offset is not listed in the table it must be considered as “reserved”. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 711 32.7.1 PDMIC Control Register Name: PDMIC_CR Address: 0x4002C000 (0), 0x40030000 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ENPDM 3 – 2 – 1 – 0 SWRST • SWRST: Software Reset 0: No effect. 1: Resets the PDMIC, simulating a hardware reset. Warning: The read value of this bit is always 0. • ENPDM: Enable PDM 0: Disables the PDM and stops the conversions. 1: Enables the PDM and starts the conversions. 712 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 32.7.2 PDMIC Mode Register Name: PDMIC_MR Address: 0x4002C004 (0), 0x40030004 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 13 12 11 PRESCAL 10 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the PDMIC Write Protection Mode Register. • PRESCAL: Prescaler Rate Selection PRESCAL determines the frequency of the PDM bitstream sampling clock (PDMIC_CLK): f peripheral clock PRESCAL = -------------------------------------- – 1 2 × f PDMIC_CLK where fperipheral clock is the system clock frequency in Hz. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 713 32.7.3 PDMIC Converted Data Register Name: PDMIC_CDR Address: 0x4002C014 (0), 0x40030014 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until it is read. 714 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 32.7.4 PDMIC Interrupt Enable Register Name: PDMIC_IER Address: 0x4002C018 (0), 0x40030018 (1) Access: Write-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 – 25 OVRE 24 DRDY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. • DRDY: Data Ready Interrupt Enable • OVRE: Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 715 32.7.5 PDMIC Interrupt Disable Register Name: PDMIC_IDR Address: 0x4002C01C (0), 0x4003001C (1) Access: Write-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 – 25 OVRE 24 DRDY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. • DRDY: Data Ready Interrupt Disable • OVRE: General Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable 716 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 32.7.6 PDMIC Interrupt Mask Register Name: PDMIC_IMR Address: 0x4002C020 (0), 0x40030020 (1) Access: Read-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 – 25 OVRE 24 DRDY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. • DRDY: Data Ready Interrupt Mask • OVRE: General Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 717 32.7.7 PDMIC Interrupt Status Register Name: PDMIC_ISR Address: 0x4002C024 (0), 0x40030024 (1) Access: Read-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 – 25 OVRE 24 DRDY 23 22 21 20 19 18 17 16 FIFOCNT 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • FIFOCNT: FIFO Count Number of conversions available in the FIFO (not a source of interrupt). • DRDY: Data Ready (cleared by reading PDMIC_CDR) 0: No data has been converted since the last read of PDMIC_CDR. 1: At least one data has been converted and is available in PDMIC_CDR. • OVRE: Overrun Error (cleared on read) 0: No overrun error has occurred since the last read of PDMIC_ISR. 1: At least one overrun error has occurred since the last read of PDMIC_ISR. • ENDRX: End of RX Buffer (cleared by writing PDMIC_RCR or PDMIC_RNCR) 0: The Receive Counter register has not reached 0 since the last write in PDMIC_RCR or PDMIC_RNCR. 1: The Receive Counter register has reached 0 since the last write in PDMIC_RCR or PDMIC_RNCR. Note: PDMIC_RCR and PDMIC_RNCR are located in the Peripheral DMA Controller (PDC). • RXBUFF: RX Buffer Full (cleared by writing PDMIC_RCR or PDMIC_RNCR) 0: PDMIC_RCR or PDMIC_RNCR has a value other than 0. 1: Both PDMIC_RCR and PDMIC_RNCR have a value of 0. Note: PDMIC_RCR and PDMIC_RNCR are located in the Peripheral DMA Controller (PDC). 718 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 32.7.8 PDMIC DSP Configuration Register 0 Name: PDMIC_DSPR0 Address: 0x4002C058 (0), 0x40030058 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 HPFBYP 0 – SHIFT 7 – 6 SCALE 5 OSR 4 3 SIZE 2 SINBYP This register can only be written if the WPEN bit is cleared in the PDMIC Write Protection Mode Register. • HPFBYP: High-Pass Filter Bypass 0: High-pass filter enabled. 1: Bypasses the high-pass filter. • SINBYP: SINCC Filter Bypass 0: Droop compensation filter enabled. 1: Bypasses the droop compensation filter. • SIZE: Data Size 0: Converted data size is 16 bits. 1: Converted data size is 32 bits. • OSR: Oversampling Ratio Value Name Description 0 128 Oversampling ratio is 128 1 64 Oversampling ratio is 64 Note: Values not listed are reserved. • SCALE: Data Scale Shifts the multiplication operation result by SCALE bits to the right. • SHIFT: Data Shift Shifts the scaled result by SHIFT bits to the right. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 719 32.7.9 PDMIC DSP Configuration Register 1 Name: PDMIC_DSPR1 Address: 0x4002C05C (0), 0x4003005C (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 DGAIN 10 9 8 3 2 1 0 OFFSET 23 22 21 20 OFFSET 15 – 14 13 12 7 6 5 4 DGAIN This register can only be written if the WPEN bit is cleared in the PDMIC Write Protection Mode Register. • DGAIN: Gain Correction Gain correction to apply to the final result. • OFFSET: Offset Correction Offset correction to apply to the final result. DGAIN and OFFSET values can be determined using the formula in Section 32.6.2.6 “Gain and Offset Compensation”. 720 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 32.7.10 PDMIC Write Protection Mode Register Name: PDMIC_WPMR Address: 0x4002C0E4 (0), 0x400300E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x414443 (“ADC” in ASCII). See Section 32.6.5 “Register Write Protection” for the list of registers that can be write-protected. • WPKEY: Write Protection Key Value Name 0x414443 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 721 32.7.11 PDMIC Write Protection Status Register Name: PDMIC_WPSR Address: 0x4002C0E8 (0), 0x400300E8 (1) Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PDMIC_WPSR. 1: A write protection violation has occurred since the last read of the PDMIC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. 722 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 33. Universal Synchronous Asynchronous Receiver Transmitter (USART) 33.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: Remote loopback, Local loopback and Automatic echo. The USART supports specific operating modes providing interfaces on RS485, and SPI buses and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 33.2 Embedded Characteristics Programmable Baud Rate Generator 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications ̶ 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode ̶ Parity Generation and Error Detection ̶ Framing Error Detection, Overrun Error Detection ̶ Digital Filter on Receive Line ̶ MSB- or LSB-first ̶ Optional Break Generation and Detection ̶ By 8 or by 16 Oversampling Receiver Frequency ̶ Optional Hardware Handshaking RTS-CTS ̶ Receiver Time-out and Transmitter Timeguard ̶ Optional Multidrop Mode with Address Generation and Detection RS485 with Driver Control Signal SPI Mode ̶ Master or Slave ̶ Serial Clock Programmable Phase and Polarity ̶ SPI Serial Clock (SCK) Frequency up to fperipheral clock/6 Test Modes Supports Connection of: ̶ ̶ Remote Loopback, Local Loopback, Automatic Echo Two Peripheral DMA Controller Channels (PDC) Offers Buffer Transfer without Processor Intervention Register Write Protection SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 723 33.3 Block Diagram Figure 33-1. Figure 33-2. USART Block Diagram Interrupt Controller USART Interrupt PIO Controller USART RXD Receiver Channel RTS (Peripheral) DMA Controller TXD Channel Transmitter CTS Bus clock SCK Baud Rate Generator Bridge APB User Interface Peripheral clock PMC 33.4 Peripheral clock/DIV I/O Lines Description Table 33-1. I/O Line Description Name Description Type Active Level SCK Serial Clock I/O — I/O — Input — Input Low Output Low Transmit Serial Data TXD or Master Out Slave In (MOSI) in SPI master mode or Master In Slave Out (MISO) in SPI slave mode Receive Serial Data RXD or Master In Slave Out (MISO) in SPI master mode or Master Out Slave In (MOSI) in SPI slave mode CTS RTS 724 Clear to Send or Slave Select (NSS) in SPI slave mode Request to Send or Slave Select (NSS) in SPI master mode SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 33.5 Product Dependencies 33.5.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. Table 33-2. I/O Lines Instance Signal I/O Line Peripheral USART CTS PA16 A USART RTS PA15 A USART RXD PA5 A USART SCK PA15 B USART TXD PA6 A 33.5.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. 33.5.3 Interrupt Sources The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART Table 33-3. Peripheral IDs Instance ID USART 14 interrupt requires the Interrupt Controller to be programmed first. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 725 33.6 Functional Description 33.6.1 Baud Rate Generator The baud rate generator provides the bit period clock, also named the baud rate clock, to both the receiver and the transmitter. The baud rate generator clock source is selected by configuring the USCLKS field in the USART Mode Register (US_MR) to one of the following: The peripheral clock A division of the peripheral clock, where the divider is product-dependent, but generally set to 8 The external clock, available on the SCK pin The baud rate generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator register (US_BRGR). If a 0 is written to CD, the baud rate generator does not generate any clock. If a 1 is written to CD, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a peripheral clock period. The frequency of the signal provided on SCK must be at least 3 times lower than the frequency provided on the peripheral clock in USART mode (field USART_MODE differs from 0xE or 0xF), or 6 times lower in SPI mode (field USART_MODE equals 0xE or 0xF). Figure 33-3. Baud Rate Generator USCLKS Peripheral clock Peripheral clock/DIV Reserved SCK (CLKO = 0) CD SCK (CLKO = 1) CD 0 1 2 Selected Clock 16-bit Counter FIDI >1 3 1 Selected Clock 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC USCLKS = 3 33.6.1.1 Sampling Clock Baud Rate in Asynchronous Mode If the USART is programmed to operate in Asynchronous mode, the selected clock is first divided by CD, which is field programmed in the US_BRGR. The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on how the OVER bit in the US_MR is programmed. If OVER is set, the receiver sampling is eight times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The baud rate is calculated as per the following formula: Selected Clock Baud Rate = ----------------------------------------------( 8 ( 2 – OVER )CD ) This gives a maximum baud rate of peripheral clock divided by 8, assuming that the peripheral clock is the highest possible clock and that the OVER bit is set. 726 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Baud Rate Calculation Example Table 33-4 shows calculations of CD to obtain a baud rate at 38,400 bit/s for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 33-4. Baud Rate Example (OVER = 0) Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 3,686,400 38,400 6.00 6 38,400.00 0.00% 4,915,200 38,400 8.00 8 38,400.00 0.00% 5,000,000 38,400 8.14 8 39,062.50 1.70% 7,372,800 38,400 12.00 12 38,400.00 0.00% 8,000,000 38,400 13.02 13 38,461.54 0.16% 12,000,000 38,400 19.53 20 37,500.00 2.40% 12,288,000 38,400 20.00 20 38,400.00 0.00% 14,318,180 38,400 23.30 23 38,908.10 1.31% 14,745,600 38,400 24.00 24 38,400.00 0.00% 18,432,000 38,400 30.00 30 38,400.00 0.00% 24,000,000 38,400 39.06 39 38,461.54 0.16% 24,576,000 38,400 40.00 40 38,400.00 0.00% 25,000,000 38,400 40.69 40 38,109.76 0.76% 32,000,000 38,400 52.08 52 38,461.54 0.16% 32,768,000 38,400 53.33 53 38,641.51 0.63% 33,000,000 38,400 53.71 54 38,194.44 0.54% 40,000,000 38,400 65.10 65 38,461.54 0.16% 50,000,000 38,400 81.38 81 38,580.25 0.47% In this example, the baud rate is calculated with the following formula: Baud Rate = Selected Clock ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. Expected Baud Rate Error = 1 – ------------------------------------------------- Actual Baud Rate 33.6.1.2 Fractional Baud Rate in Asynchronous Mode The baud rate generator is subject to the following limitation: the output frequency changes only by integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain baud rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the US_BRGR. If FP is not 0, the SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 727 fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional baud rate is calculated using the following formula: Selected Clock Baud Rate = ------------------------------------------------------------------ 8 ( 2 – OVER ) CD + FP ------- 8 The modified architecture is presented in the following Figure 33-4. Figure 33-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV Reserved 1 2 Selected Clock 16-bit Counter 3 SCK (CLKO = 0) SCK (CLKO = 1) CD 0 Glitch-free Logic FIDI >1 1 0 SYNC OVER Selected Clock 0 0 Sampling Divider 0 Baud Rate Clock 1 1 SYNC USCLKS = 3 33.6.1.3 Sampling Clock Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in Synchronous mode, the selected clock is simply divided by the field CD in the US_BRGR. Selected Clock Baud Rate = -----------------------------------CD In Synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the system clock. In Synchronous mode master (USCLKS = 0 or 1, CLKO set to 1), the receive part limits the SCK maximum frequency toSelected Clock/3 in USART mode, or Selected Clock/6 in SPI mode. When either the external clock SCK or the internal clock divided (peripheral clock/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. When the peripheral clock is selected, the baud rate generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 33.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the US_CR. However, the transmitter registers can be programmed before being enabled. The receiver and the transmitter can be enabled together or independently. 728 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the US_CR. The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in the US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding register (US_THR). If a timeguard is programmed, it is handled normally. 33.6.3 Synchronous and Asynchronous Modes 33.6.3.1 Transmitter Operations The transmitter performs the same in both Synchronous and Asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in US_MR. Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in the US_MR configures which data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in the US_MR. The 1.5 stop bit is supported in Asynchronous mode only. Figure 33-5. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding register (US_THR). The transmitter reports two status bits in the Channel Status register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 729 Figure 33-6. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 33.6.3.2 Asynchronous Receiver If the USART is programmed in Asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the baud rate clock, depending on the OVER bit in the US_MR. The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16 (OVER = 0), a start is detected at the eighth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration corresponding to 16 oversampling clock cycles. If the oversampling is 8 (OVER = 1), a start bit is detected at the fourth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration corresponding to 8 oversampling clock cycles. The number of data bits, first bit sent and Parity mode are selected by the same fields and bits as the transmitter, i.e., respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 33-7 and Figure 33-8 illustrate start detection and character reception when USART operates in Asynchronous mode. Figure 33-7. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 2 3 4 Start Detection RXD Sampling 1 730 2 3 4 5 6 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 7 0 1 Start Rejection 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Figure 33-8. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 33.6.3.3 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Synchronous Receiver In Synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high-speed transfer capability. Configuration fields and bits are the same as in Asynchronous mode. Figure 33-9 illustrates a character reception in Synchronous mode. Figure 33-9. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 33.6.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the RXRDY bit in US_CSR rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in the US_CR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 731 Figure 33-10. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 33.6.3.5 Parity The USART supports five Parity modes that are selected by writing to the PAR field in the US_MR. The PAR field also enables the Multidrop mode, see Section 33.6.3.6 ”Multidrop Mode”. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 33-5 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits set to 1 in the character value, the parity bit is set to 1 when the parity is odd, or configured to 0 when the parity is even. Table 33-5. Parity Bit Examples Character Hexadecimal Binary Parity Bit Parity Mode A 0x41 0100 0001 1 Odd A 0x41 0100 0001 0 Even A 0x41 0100 0001 1 Mark A 0x41 0100 0001 0 Space A 0x41 0100 0001 None None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the US_CSR. The PARE bit can be cleared by writing a 1 to the RSTSTA bit the US_CR. Figure 33-11 illustrates the parity bit status setting and clearing. 732 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 33-11. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE Parity Error Detect Time Flags Report Time RXRDY 33.6.3.6 Multidrop Mode If the value 0x6 or 0x07 is written to the PAR field in the US_MR, the USART runs in Multidrop mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in Multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when a 1 is written to the SENTA bit in the US_CR. To handle parity error, the PARE bit is cleared when a 1 is written to the RSTSTA bit in the US_CR. The transmitter sends an address byte (parity bit set) when SENDA is written to in the US_CR. In this case, the next byte written to the US_THR is transmitted as an address. Any character written in the US_THR without having written the command SENDA is transmitted normally with the parity at 0. 33.6.3.7 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard register (US_TTGR). When this field is written to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 33-12, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 733 Figure 33-12. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 33-6 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. Table 33-6. 33.6.3.8 Maximum Timeguard Length Depending on Baud Rate Baud Rate (bit/s) Bit Time (µs) Timeguard (ms) 1,200 833 212.50 9,600 104 26.56 14,400 69.4 17.71 19,200 52.1 13.28 28,800 34.7 8.85 38,400 26 6.63 56,000 17.9 4.55 57,600 17.4 4.43 115,200 8.7 2.21 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the US_CSR rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out register (US_RTOR). If the TO field is written to 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in the US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in US_CSR rises. Then, the user can either: 734 Stop the counter clock until a new character is received. This is performed by writing a 1 to the STTTO (Start Time-out) bit in the US_CR. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. Obtain an interrupt while no character is received. This is performed by writing a 1 to the RETTO (Reload and Start Time-out) bit in the US_CR. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 33-13 shows the block diagram of the Receiver Time-out feature. Figure 33-13. Receiver Time-out Block Diagram TO Baud Rate Clock 1 D Clock Q 16-bit Time-out Counter 16-bit Value = STTTO Character Received RETTO Load Clear TIMEOUT 0 Table 33-7 gives the maximum time-out period for some standard baud rates. Table 33-7. 33.6.3.9 Maximum Time-out Period Baud Rate (bit/s) Bit Time (µs) Time-out (ms) 600 1,667 109,225 1,200 833 54,613 2,400 417 27,306 4,800 208 13,653 9,600 104 6,827 14,400 69 4,551 19,200 52 3,413 28,800 35 2,276 38,400 26 1,704 56,000 18 1,170 57,600 17 1,138 200,000 5 328 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of US_CSR. The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing a 1 to the RSTSTA bit in the US_CR. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 735 Figure 33-14. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 33.6.3.10 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing a 1 to the STTBRK bit in the US_CR. This can be performed at any time, either while the transmitter is empty (no character in either the Shift register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing a 1 to the STPBRK bit in the US_CR. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e., the STTBRK and STPBRK commands are processed only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 33-15 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. 736 SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 Figure 33-15. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 33.6.3.11 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing a 1 to the RSTSTA bit in the US_CR. An end of receive break is detected by a high level for at least 2/16 of a bit period in Asynchronous operating mode or one sample at high level in Synchronous operating mode. The end of break detection also asserts the RXBRK bit. 33.6.3.12 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 33-16. Figure 33-16. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in US_MR to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard Synchronous or Asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 33-17 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled or if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer in the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. SAM G53G / SAM G53N [DATASHEET] Atmel-11240F-ATARM-SAM-G53G-SAM-G53N-Datasheet_24-Jul-15 737 Figure 33-17. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write US_CR RTS RXBUFF Figure 33-18 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processed, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 33-18. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 33.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode.