Features • Fast Read Access Time – 150 ns • Automatic Page Write Operation • • • • • • • • • • – Internal Address and Data Latches for 64 Bytes – Internal Control Timer Fast Write Cycle Times – Page Write Cycle Time: 3 ms or 10 ms Maximum – 1 to 64-byte Page Write Operation Low Power Dissipation – 50 mA Active Current – 200 µA CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 104 or 105 Cycles – Data Retention: 10 Years Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Full Military and Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option 256K (32K x 8) Paged Parallel EEPROM AT28C256 1. Description The AT28C256 is a high-performance electrically erasable and programmable readonly memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 200 µA. The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s AT28C256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 0006M–PEEPR–12/09 2. Pin Configurations Pin Name Function A0 - A14 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect 28-lead PGA Top View A7 A12 A14 DC VCC WE A13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE I/O7 I/O6 Note: PLCC package pins 1 and 17 are Don’t Connect. 2.4 28-lead Cerdip/PDIP/Flatpack/SOIC – Top View A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 2 4 3 2 1 32 31 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32-pad LCC, 28-lead PLCC Top View 14 15 16 17 18 19 20 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 2.2 2.3 28-lead TSOP Top View I/O1 I/O2 GND DC I/O3 I/O4 I/O5 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 AT28C256 0006M–PEEPR–12/09 AT28C256 3. Block Diagram 4. Device Operation 4.1 Read The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. 4.2 Byte Write A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. 4.3 Page Write The page write operation of the AT28C256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 4.4 DATA Polling The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. 3 0006M–PEEPR–12/09 4.5 Toggle Bit In addition to DATA Polling the AT28C256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. 4.6 Data Protection If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.6.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28C256 in the following ways: (a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay – once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. 4.6.2 Software Data Protection A software controlled data protection feature has been implemented on the AT28C256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to “Software Data Protection” algorithm). After writing the 3-byte command sequence and after tWC the entire AT28C256 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C256. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C256 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. 4.7 Device Identification An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. 4.8 Optional Chip Erase Mode The entire device can be erased using a 6-byte software code. Please see “Software Chip Erase” application note for details. 4 AT28C256 0006M–PEEPR–12/09 AT28C256 5. DC and AC Operating Range AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35 Ind. -40°C - 85°C Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% Mode CE OE WE I/O Read VIL VIL VIH DOUT Operating Temperature (Case) VCC Power Supply 6. Operating Modes (2) Write VIL VIH VIL DIN Standby/Write Inhibit VIH X(1) X High Z Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X High Z VIL High Z Chip Erase Notes: 1. X can be VIL or VIH. VIL VH (3) 2. Refer to AC programming waveforms. 3. VH = 12.0V ± 0.5V. 7. Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C *NOTICE: Storage Temperature..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V 8. DC Characteristics Symbol Parameter Condition Max Units ILI Input Load Current VIN = 0V to VCC + 1V Min 10 µA ILO Output Leakage Current VI/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V Ind. 200 µA Mil. 300 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage VOL Output Low Voltage IOL = 2.1 mA VOH Output High Voltage IOH = -400 µA 2.0 V 0.45 2.4 V V 5 0006M–PEEPR–12/09 9. AC Read Characteristics AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35 Min Min Min Min Symbol Parameter tACC Address to Output Delay 150 200 tCE(1) CE to Output Delay 150 200 tOE(2) OE to Output Delay 0 70 0 80 0 100 CE or OE to Output Float 0 50 0 55 0 60 Output Hold from OE, CE or Address, whichever occurred first 0 tDF (3)(4) tOH Max 0 Max 0 Max Max Units 250 350 ns 250 350 ns 0 100 ns 0 70 ns 0 ns 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 6 AT28C256 0006M–PEEPR–12/09 AT28C256 11. Input Test Waveforms and Measurement Level tR, tF < 5 ns 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: Conditions 1. This parameter is characterized and is not 100% tested. 7 0006M–PEEPR–12/09 14. AC Write Characteristics Symbol Parameter tAS, tOES Address, OE Setup Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 100 ns tDS Data Setup Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns tDV Time to Data Valid Note: Min Max Units NR(1) 1. NR = No Restriction 15. AC Write Waveforms 15.1 WE Controlled 15.2 CE Controlled 8 AT28C256 0006M–PEEPR–12/09 AT28C256 16. Page Mode Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time (option available) AT28C256 10 ms AT28C256F 3 ms tAS Address Setup Time 0 ns tAH Address Hold Time 50 ns tDS Data Setup Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 150 50 µs ns 17. Page Mode Write Waveforms(1)(2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 18. Chip Erase Waveforms tS = tH = 5 µsec (min.) tW = 10 msec (min.) VH = 12.0V ± 0.5V 9 0006M–PEEPR–12/09 19. Software Data Protection Enable Algorithm(1) Notes: 20. Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA 80 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(4) LOAD DATA AA TO ADDRESS 5555 LOAD LAST BYTE TO LAST ADDRESS LOAD DATA 55 TO ADDRESS 2AAA ENTER DATA PROTECT STATE 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE(3) LOAD DATA XX TO ANY ADDRESS(4) 4. 1 to 64 bytes of data are loaded. LOAD LAST BYTE TO LAST ADDRESS 21. Software Protected Write Cycle Waveforms(1)(2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. 10 AT28C256 0006M–PEEPR–12/09 AT28C256 22. Data Polling Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time OE to Output Delay tOE Typ Max Units 0 ns 0 ns (2) Write Recovery Time tWR Notes: Min ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See“AC Read Characteristics” on page 6. 23. Data Polling Waveforms 24. Toggle Bit Characteristics(1) Symbol Parameter tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) tOEHP OE High Pulse tWR Notes: Write Recovery Time Min Typ Max Units ns 150 ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 6. 25. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 11 0006M–PEEPR–12/09 26. Normalized ICC Graphs 12 AT28C256 0006M–PEEPR–12/09 AT28C256 27. Ordering Information 27.1 27.1Military Dual Marked Package 27.1.1 AT28C256 tACC (ns) Active Standby Ordering Code Package 150 50 0.3 AT28C256-15DM/883 5962-88525 14 XX(1) 5962-88525 06 XX 28D6 AT28C256-15FM/883 5962-88525 14 ZX(1) 5962-88525 06 ZX 28F AT28C256-15LM/883 5962-88525 14 YX(1) 5962-88525 06 YX 32L AT28C256-15UM/883 5962-88525 14 UX(1) 5962-88525 06 UX 28U AT28C256-20DM/883 5962-88525 12 XX(1) 5962-88525 04 XX 28D6 AT28C256-20FM/883 5962-88525 12 ZX(1) 5962-88525 04 ZX 28F AT28C256-20LM/883 5962-88525 12 YX(1) 5962-88525 04 YX 32L AT28C256-20UM/883 5962-88525 12 UX(1) 5962-88525 04 UX 28U AT28C256-25DM/883 5962-88525 11 XX(1) 5962-88525 03 XX 28D6 AT28C256-25FM/883 5962-88525 11 ZX(1) 5962-88525 03 ZX 28F AT28C256-25LM/883 5962-88525 11 YX(1) 5962-88525 03 YX 32L AT28C256-25UM/883 5962-88525 11 UX(1) 5962-88525 03 UX 28U 200 250 Note: ICC (mA) 50 50 0.3 0.3 Operation Range Military/883C Class B, Fully Compliant (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) 1. Where two DESC numbers apply to the Atmel ordering code apply SL815 to receive parts with the noted DESC number dual marked along with Atmel part number. 13 0006M–PEEPR–12/09 27.1.2 AT28C256E tACC (ns) Active Standby Ordering Code Package 150 50 0.3 AT28C256E-15DM/883 5962-88525 16 XX(1) 5962-88525 08 XX 28D6 AT28C256E-15FM/883 5962-88525 16 ZX(1) 5962-88525 08 ZX 28F AT28C256E-15LM/883 5962-88525 16 YX(1) 5962-88525 08 YX 32L AT28C256E-15UM/883 5962-88525 16 UX(1) 5962-88525 08 UX 28U AT28C256E-20DM/883 28D6 AT28C256E-20FM/883 28F AT28C256E-20LM/883 32L AT28C256E-20UM/883 28U AT28C256E-25DM/883 5962-88525 13 XX(1) 5962-88525 05 XX 28D6 5962-88525 05 XX 5962-88525 13 ZX(1) 5962-88525 05 ZX 28F AT28C256E-25LM/883 5962-88525 13 YX(1) 5962-88525 05 YX 32L AT28C256E-25UM/883 5962-88525 13 UX(1) 5962-88525 05 UX 28U 200 250 Note: 14 ICC (mA) 50 50 0.3 0.3 Operation Range Military/883C Class B, Fully Compliant (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) 1. Where two DESC numbers apply to the Atmel ordering code apply SL815 to receive parts with the noted DESC number dual marked along with Atmel part number. AT28C256 0006M–PEEPR–12/09 AT28C256 27.1.3 AT28C256F ICC (mA) tACC (ns) Active Standby Ordering Code Package 150 50 0.3 AT28C256F-15DM/883 5962-88525 15 XX(3) 5962-88525 07 XX 28D6 AT28C256F-15FM/883 5962-88525 15 ZX(3) 5962-88525 07 ZX 28F AT28C256F-15LM/883 5962-88525 15 YX(3) 5962-88525 07 YX 32L AT28C256F-15UM/883 5962-88525 15 UX(3) 5962-88525 07 UX 28U Notes: Operation Range Military/883C Class B, Fully Compliant (-55°C to 125°C) 1. Electrical specifications for these speeds are defined by Standard Microcircuit Drawing 5962-88525. 2. SMD specifies Software Data Protection feature for device type, although Atmel product supplied to every device type in the SMD is 100% tested for this feature. 3. Where two DESC numbers apply to the Atmel ordering code apply SL815 to receive parts with the noted DESC number dual marked along with Atmel part number. Package Type 28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) 28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack) 32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC) 28U 28-pin, Ceramic Pin Grid Array (PGA) W Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 15 0006M–PEEPR–12/09 27.2 Industrial Green Package Option (Pb/Halide-free) 27.2.1 AT28C256 tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range 150 50 0.2 AT28C256-15JU AT28C256-15PU AT28C256-15SU AT28C256-15TU 32J 28P6 28S 28T Industrial (-40°C to 85°C) 27.2.2 AT28C256E tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range 150 50 0.2 AT28C256E-15JU AT28C256E-15SU AT28C256E-15TU 32J 28S 28T Industrial (-40°C to 85°C) 27.2.3 AT28C256F tACC ICC (mA) (ns) Active Standby Ordering Code Package Operation Range 150 50 0.2 AT28C256F-15JU AT28C256F-15SU AT28C256F-15TU 32J 28S 28T Industrial (-40°C to 85°C) Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 28. Die Products Reference Section: Contact Atmel sales for die sales options. 16 AT28C256 0006M–PEEPR–12/09 AT28C256 29. Packaging Information 29.1 28D6 – Cerdip Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-10 Config A (Glass Sealed) 37.85(1.490) 36.58(1.440) PIN 1 15.49(0.610) 12.95(0.510) 33.02(1.300) REF 5.72(0.225) MAX 0.127(0.005)MIN SEATING PLANE 5.08(0.200) 3.18(0.125) 2.54(0.100)BSC 1.65(0.065) 1.14(0.045) 1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014) 15.70(0.620) 15.00(0.590) 0.46(0.018) 0.20(0.008) 0º~ 15º REF 17.80(0.700) MAX 10/23/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28D6, 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) DRAWING NO. 28D6 REV. B 17 0006M–PEEPR–12/09 29.2 28F – Flatpack Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 F-12 Config B PIN #1 ID 9.40(0.370) 6.35(0.250) 0.56(0.022) 0.38(0.015) 1.27(0.050) BSC 18.49(0.728) 18.08(0.712) 1.14(0.045) MAX 10.57(0.416) 9.75(0.384) 0.23(0.009) 0.10(0.004) 3.02(0.119) 2.29(0.090) 1.96(0.077) 1.09(0.043) 7.26(0.286) 6.96(0.274) 1.14(0.045) 0.660(0.026) 10/21/03 R 18 2325 Orchard Parkway San Jose, CA 95131 TITLE 28F, 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (FlatPack) DRAWING NO. REV. 28F B AT28C256 0006M–PEEPR–12/09 AT28C256 29.3 32J – PLCC 1.14(0.045) X 45 PIN NO. 1 IDENTIFIER 1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075) E1 E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45 MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) D2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 32J B 19 0006M–PEEPR–12/09 29.4 32L – LCC Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12 11.63(0.458) 11.23(0.442) 2.54(0.100) 2.16(0.085) 14.22(0.560) 13.72(0.540) 1.91(0.075) 1.40(0.055) PIN 1 2.41(0.095) 1.91(0.075) 1.40(0.055) 1.14(0.045) INDEX CORNER 0.635(0.025) X 45˚ 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 10.16(0.400) BSC 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45˚ 7.62(0.300) BSC 2.16(0.085) 1.65(0.065) 10/21/03 R 20 2325 Orchard Parkway San Jose, CA 95131 TITLE 32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) DRAWING NO. REV. 32L B AT28C256 0006M–PEEPR–12/09 AT28C256 29.5 28P6 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 4.826 A1 0.381 – – D 36.703 – 37.338 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 e NOTE Note 2 Note 2 2.540 TYP 09/28/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P6 REV. B 21 0006M–PEEPR–12/09 29.6 28S – SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 0.51(0.020) 0.33(0.013) 7.60(0.2992) 10.65(0.419) 7.40(0.2914) 10.00(0.394) PIN 1 1.27(0.50) BSC TOP VIEW 18.10(0.7125) 17.70(0.6969) 2.65(0.1043) 2.35(0.0926) 0.30(0.0118) 0.10(0.0040) SIDE VIEWS 0.32(0.0125) 0.23(0.0091) 0º ~ 8º 1.27(0.050) 0.40(0.016) 8/4/03 R 22 2325 Orchard Parkway San Jose, CA 95131 TITLE 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) JEDEC Standard MS-013 DRAWING NO. REV. 28S B AT28C256 0006M–PEEPR–12/09 AT28C256 29.7 28T – TSOP PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. MIN MAX NOM A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 NOTE D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.55 BASIC 12/06/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. REV. 28T C 23 0006M–PEEPR–12/09 29.8 28U – PGA Dimensions in Millimeters and (Inches). Controlling dimension: Inches. 7.26(0.286) 6.50(0.256) 13.74(0.540) 13.36(0.526) 2.57(0.101) 2.06(0.081) 15.24(0.600) 14.88(0.586) 1.40(0.055) 1.14(0.045) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 2.54(0.100) TYP 16.71(0.658) 16.31(0.642) 12.70(0.500) TYP 2.54(0.100) TYP 10.41(0.410) 9.91(0.390) 10/21/03 R 24 2325 Orchard Parkway San Jose, CA 95131 TITLE 28U, 28-pin, Ceramic Pin Grid Array (PGA) DRAWING NO. REV. 28U B AT28C256 0006M–PEEPR–12/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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