P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell Single 5V ± 10% Power Supply High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Low Power Operation – 715 mW Active –10 (Commercial) – 550 mW Active –25 (Commercial) – 110 mW Standby (TTL Input) – 55 mW Standby (CMOS Input) Standard Pinout (JEDEC Approved) – 18 Pin 300 mil DIP – 18 Pin CERPACK – 18 Pin LCC (290 x 430 mils) – 18 Pin LCC (295 x 335 mils) DESCRIPTION CMOS is utilized to reduce power consumption in both active and standby modes. In addition to very high performance, this device features latch-up protection and single-event-upset protection. The P4C147 is a 4,096-bit ultra high speed static RAM organized as 4K x 1. The CMOS memory requires no clocks or refreshing, and have equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V ± 10% tolerance power supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. The P4C147 is available in 18 pin 300 mil DIP packages, an 18-pin CERPACK package, and 2 different LCC packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P1, D1, C9), CERPACK (F1) SIMILAR LCC (L7, L7-1) Document # SRAM103 REV A 1 Revised October 2005 P4C147 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND – 0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) – 0.5 to VCC +0.5 V TA Operating Temperature – 55 to +125 °C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit TBIAS Temperature Under Bias – 55 to +125 °C TSTG Storage Temperature – 65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol Parameter Conditions Typ. Unit Grade(2) Ambient Temp Gnd VCC Commercial 0°C to 70°C 0V 5.0V ± 10% CIN Input Capacitance VIN = 0V 5 pF -55°C to +125°C 0V 5.0V ± 10% COUT Output Capacitance VOUT= 0V 7 pF Military DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage (2) Symbol Parameter VOH Output High Voltage (TTL Load) IOH = –4 mA, VCC = Min. VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min VIH Input High Voltage VIL Input Low Voltage ILI Input Leakage Current VCC = Max., VIN = GND to VCC ILO Output Leakage Current ISB ISB1 P4C147 Test Conditions Max. Min. Unit V 2.4 0.4 V 2.2 VCC =+0.5 V –0.5(3) 0.8 V Mil. Comm’l –10 –5 +10 +5 µA VCC = Max., CE = VIH, VOUT = GND to VCC Mil. Comm’l +10 +5 µA Standby Power Supply Current (TTL Input Levels) CE ≥ VIH, VCC = Max., f=Max., Output Open Mil. Comm’l –10 –5 __ __ 30 23 mA Standby Power Supply Current (CMOS Input Levels) CE ≥ VHC, VCC = Max., f= 0, Output Open VIN ≤ 0.2V or VIN ≥ VCC -0.2V Mil. Comm’l __ __ 15 10 mA POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range -10 -12 -15 -20 -25 -35 ICC Dynamic Operating Current Commercial Military 130 N/A 130 N/A 120 145 115 135 100 125 N/A 120 Document # SRAM103 REV A Unit mA mA Page 2 of 10 P4C147 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -12 -10 -20 -15 -25 -35 Min Max Min Max Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time tAA Address Access Time 10 12 15 20 25 35 ns tAC Chip Enable Access Time 10 12 15 20 25 35 ns tOH Output Hold from Address Change 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 10 12 15 4 5 0 0 10 20 6 0 12 10 8 0 15 35 25 14 0 0 20 ns 25 ns ns 35 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5) TIMING WAVEFORM OF READ CYCLE NO. 2 (6) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. Document # SRAM103 REV A 4. This parameter is sampled and not 100% tested. 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 3 of 10 P4C147 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -10 -25 -12 -15 -20 -35 Unit Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 10 12 15 20 25 35 ns tCW Chip Enable Time to End of Write 8 10 12 15 20 25 ns tAW Address Valid to End of Write 8 10 12 15 20 25 ns tAS Address Set-up Time 0 0 0 0 0 0 ns tWP Write Pulse Width 8 10 12 14 15 18 ns tAH 0 0 0 0 0 0 ns tDW Address Hold Time from End of Write Data Valid to End of Write 5 6 7 9 12 15 ns tDH Data Hold Time 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 6 5 0 0 7 0 9 0 15 12 0 0 ns ns WE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE high, the output remains in a high impedance state. Document # SRAM103 REV A 11. Write Cycle Time is measured from the last valid address to the first transition address. Page 4 of 10 P4C147 AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Mode CE WE Output Power Standby Input Rise and Fall Times 3ns Standby H X High Z Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L High Z Active Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C147, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor Document # SRAM103 REV A is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 5 of 10 P4C147 ORDERING INFORMATION SELECTION GUIDE The P4C147 is available in the following temperature, speed and package options. Temperature Range Commercial Temperature Package Plastic DIP CERDIP Military Temperature Military Processed* Speed (ns) 10 12 15 20 25 35 -10PC -12PC -15PC -20PC -25PC N/A N/A N/A -15DM -20DM -25DM -35DM Side Brazed DIP N/A N/A -15CM -20CM -25CM -35CM LCC (290 x 430 mil) N/A N/A -15LM -20LM -25LM -35LM LCC (295 x 335 mil) N/A N/A -15LSM -20LSM -25LSM -35LSM CERPACK N/A N/A -15FM -20FM -25FM -35FM CERDIP N/A N/A -15DMB -20DMB -25DMB -35DMB Side Brazed DIP N/A N/A -15CMB -20CMB -25CMB -35CMB LCC (290 x 430 mil) N/A N/A -15LMB -20LMB -25LMB -35LMB LCC (295 x 335 mil) N/A N/A -15LSMB -20LSMB -25LSMB -35LSMB CERPACK N/A N/A -15FMB -20FMB -25FMB -35FMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM103 REV A Page 6 of 10 P4C147 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 α C9 SIDE BRAZED DUAL IN-LINE PACKAGE 18 (300 Mil) Min Max 0.200 0.014 0.026 0.030 0.065 0.008 0.018 0.960 0.220 0.320 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - D1 CERDIP DUAL IN-LINE PACKAGE 18 (300 Mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 0.960 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0° 15° Document # SRAM103 REV A Page 7 of 10 P4C147 Pkg # # Pins Symbol A b c D E e k L Q S S1 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE F1 CERPACK CERAMIC FLAT PACKAGES 18 Min Max 0.045 0.092 0.015 0.022 0.004 0.009 0.540 0.245 0.370 0.050 BSC 0.005 0.018 0.250 0.370 0.026 0.045 0.085 0.005 - L7 RECTANGULAR LEADLESS CHIP CARRIER 18 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.280 0.305 .150 BSC .075 BSC 0.305 0.417 0.440 0.200 BSC 0.100 BSC 0.440 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.075 0.090 0.075 0.148 4 5 Document # SRAM103 REV A Page 8 of 10 P4C147 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α L7-1 RECTANGULAR LEADLESS CHIP CARRIER 18 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.280 0.305 .150 BSC .075 BSC 0.305 0.345 0.365 0.200 BSC 0.100 BSC 0.365 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.125 4 5 P1 PLASTIC DUAL IN-LINE PACKAGE 18 Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 0.880 0.920 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° Document # SRAM103 REV A Page 9 of 10 P4C147 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM103 P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid Document # SRAM103 REV A DESCRIPTION OF CHANGE Page 10 of 10