REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 REV STATUS 18 19 20 21 22 23 24 25 26 26 27 1 2 3 4 5 6 7 8 REV OF SHEETS SHEET PMIC N/A PREPARED BY 9 10 11 12 13 Phu H. Nguyen STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil CHECKED BY Phu H. Nguyen APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE Thomas M. Hess DRAWING APPROVAL DATE 02-04-04 AMSC N/A REVISION LEVEL MICROCIRCUIT, DIGITAL, ASIC, SINGLE POINT TO POINT IEEE 1355 HIGH SPEED CONTROLLER, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 1 OF 5962-02A02 27 5962-E093-02 14 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - Federal stock class designator \ RHA designator (see 1.2.1) 01 Q X X Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) 02A02 / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function T7906E IEEE1355 high speed controller 01 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Descriptive designator See Figure 1 Terminals Package style 100 Square Quad Flat Package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 2 1.3 Absolute maximum ratings 1/ 2/ Supply voltage range (VDD)................................................................ Input voltage range (VIN).................................................................... Input current (IIN) Signal pin .................................................................................. Power pin .................................................................................. Output short circuit current 4/ VOUT = VDD................................................................................. VOUT = VSS ................................................................................. Lead temperature (soldering, 10 sec) ............................................... Storage temperature.......................................................................... Maximum junction temperature (TJ) .................................................. -0.5 V to 7.0 V -0.5 V to VDD + 0.5 V 3/ -10 mA to 10 mA -50 mA to 50 mA 160 mA -130 mA 300°C 5/ -65°C to 150°C 175°C 1.4 Recommended operating conditions. Supply voltage range......................................................................... 4.5 V to 5.5 V Case operating temperature (TC) ...................................................... -55°C to 125°C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _________ 1/ 2/ 3/ 4/ 5/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages referenced to ground unless otherwise specified VDD + 0.5 V shall not exceed 7.0 V The maximum output current of any single output in a shorted condition for a maximum duration of 1 second. Duration 10 s max at a distance not less than 1.6 mm. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 3 2.2 Non Government Publications. The following document(s) form a part of this document to the extent specified herin. Unless otherwise specified, the issues of the documents(s) which are DOD adopted are those listed in the DODISS cited in the solicitation INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1355 - IEEE Standard for Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction. IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture. (Applications for copies should be addressed to the Institute of Electrical and Electronic Engineers, 445 Hoes Lane, Piscataway, NJ 08854-4150 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram(s). The block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be specified in figure 4. 3.2.5 JTAG timing waveforms. The JTAG timing waveforms shall be as specified on figure 5. 3.2.6 Boundary Scan Instruction Codes. The boundary scan instruction codes shall be maintained and available from the device manufacturer upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 4 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 123 (see MIL-PRF-38535, appendix A). 3.11 IEEE 1149.1 compliance. All device types shall be compliant with IEEE 1149.1. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 5 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55°C ≤ TC ≤ +125°C VDD = 5.0 V ± 10 % unless otherwise specified Group A subgroups Limits Unit Min Max -0.2 IOH = -300 µA 1, 2, 3 -1.2 IIL VIN = GND, VDD = 5.5 V 1, 2, 3 -10 µA Low level input current, pull-up 2/ IILPU VIN = GND, VDD = 5.5 V 1, 2, 3 -250 µA Low level input current, ILLPD VIN = GND, VDD = 5.5 V 1, 2, 3 -10 µA IIH VIN = VDD = 5.5 V 1, 2, 3 10 µA IIHPU VIN = VDD = 5.5 V 1, 2, 3 10 µA IIHPD VIN = VDD = 5.5 V 1, 2, 3 450 µA IOZL Outputs disabled, VOUT = GND 1, 2, 3 IOZHPD Outputs disabled, VOUT = VDD 1, 2, 3 IOZLPU Outputs disabled, VOUT =GND 1, 2, 3 Output leakage high current 2 IOZH Outputs disabled, VOUT = VDD 1, 2, 3 10 µA Low level input voltage 1/ VIL Functional verification 1, 2, 3 0.8 V High level input voltage 1/ VIH Functional verification 1, 2, 3 VOL VDD = 4.5 V, 1, 2, 3 Input clamp voltage to GND 1/ VIC Low level input current 2/ V pull-down 2/ High level input current 2/ High level input current, pull-up High level input current, 2/ pull-down 2/ Output leakage low current 2/ Output leakage high current µA -10 µA 450 pull-down output 2/ Output leakage low current µA -250 pull-up output 2/ Low level output voltage 2/ 4/ 2.2 V 0.4 V IOL = + 3, + 6, + 12 mA High level output voltage 2/ 4/ VOH VDD = 4.5 V, 1, 2, 3 3.9 V IOH = - 3, - 6, - 12 mA Supply current at reset 3/ ICCRST VCC=5.5V 1, 2, 3 15 mA Supply current in idle 3/ ICCIDLE VCC=5.5V 1, 2, 3 50 mA ICCOP VCC=5.5V 1, 2, 3 80 mA Supply current at reset 2/ Input capacitance 3/ CI VDD = 0 V 4 15 pF Output capacitance 3/ CIO VDD = 0 V 4 15 pF See notes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test CLK period Symbol 3/ Conditions -55°C ≤ TC ≤ +125°C VDD = 5.0 V ± 10 % unless otherwise specified Group A subgroups Limits Min Unit Max tCLK Nominal 5Mhz : 200ns 9,10,11 CLK width high 3/ tCLKH See figure 4 9,10,11 80 120 ns CLK width low 3/ tCLKL See figure 4 9,10,11 80 120 ns RESET setup before CLK high 3/ tRSTS See figure 4 9,10,11 10 ns RESET low pulse width 3/ tRSTW See figure 4 9,10,11 2*tCLK ns Output disable after CLK high 3/ tOUTD See figure 4 9,10,11 HSEL active low pulse width 3/ tHSL See figure 4 9,10,11 150 ns HSEL inactive high pulse width 3/ tHSH See figure 4 9,10,11 60 ns HWRnRD setup before HSEL active low 3/ tHWnRS See figure 4 9,10,11 5 ns HDATnADR setup before HSEL active low 3/ tHWnRH See figure 4 9,10,11 5 ns HWRnRD hold after HSEL inactive high 3/ tHWnRH See figure 4 9,10,11 0 ns HDATnADR hold after HSEL inactive high 3/ tHDnAH See figure 4 9,10,11 0 ns HDATA valid after HSEL active low and HWRnRD high 3/ tHDWV See figure 4 9,10,11 HDATA hold after HSEL inactive high 3/ tHDWH See figure 4 9,10,11 0 ns HSEL active low pulse width 3/ tHSL See figure 4 9,10,11 150 ns HSEL inactive high pulse width 3/ tHSH See figure 4 9,10,11 60 ns HWRnRD setup before HSEL active low 3/ tHWnRS See figure 4 9,10,11 5 ns HDATnADR setup before HSEL active low 3/ tHWnRL See figure 4 9,10,11 5 ns HWRnRD hold after HSEL inactive high 3/ tHWnRH See figure 4 9,10,11 0 ns HDATnADR hold after HSEL inactive high 3/ tHDnAH See figure 4 9,10,11 0 ns tHDE See figure 4 9,10,11 4 HDATA enable after HSEL low and HWRnRD low 3/ active ns 38 ns 25 ns 18 ns See notes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55°C ≤ TC ≤ +125°C VDD = 5.0 V ± 10 % unless otherwise specified Group A subgroups Limits Min Unit Max HDATA valid after HSEL active low and HWRnRD low 3/ tHDV See figure 4 9,10,11 125 ns HDATA hold after HSEL inactive high 3/ tHDH See figure 4 9,10,11 4 18 ns HSEL active low pulse width 3/ tHSL See figure 4 9,10,11 150 RAM I/F write access time 3/ tRWA See figure 4 9,10,11 120 CSO -3, WR active low pulse width 3/ tRWL See figure 4 9,10,11 40+(ws*40) 5/ 42+(ws*40) 5/ ns Address ADDR0-15 valid before CSO , WR active low 3/ tRWAS See figure 4 9,10,11 38 42 ns Address ADDR0-15 hold after CSO -3, WR inactive high 3/ tRWAH See figure 4 9,10,11 38 42 ns DATA0-15 enable after CSO -3, WR active low 3/ tRWDE See figure 4 9,10,11 0 6 ns DATA0-15 valid before CSO -3, WR inactive high 3/ tRWDV See figure 4 9,10,11 32 DATA0-15 hold after CSO -3, WR inactive high 3/ tRWDH See figure 4 9,10,11 20 26 ns CSO -3, WR , RD and ADDR valid active low pulse width 3/ tRRL See figure 4 9,10,11 40+(ws*40) 5/ 42+(ws*40) 5/ ns CSO -3, WR , RD and ADDR valid inactive high pulse width 3/ tRRH See figure 4 9,10,11 38 40 ns ADDRESS change 3/ 6/ tRRA See figure 4 9,10,11 40+(ws*40) 5/ 42+(ws*40) 5/ ns DATA0-15 setup before CSO -3, RD high or new address on ADDR0-15 valid 3/ tRDS See figure 4 9,10,11 14 DATA hold after CSO -3, RD high or new address on ADDR0-15 3/ tRDH See figure 4 9,10,11 0 40 ns CSO -3, WR , RD , ADDR0-15 and DATA0-15 disable after BUS _ REQ active low 3/ tRBRS See figure 4 9,10,11 40 160 ns CSO -3, WR , RD , ADDR0-15 and DATA0-15 enable after BUS_REQ inactive high 3/ tRBRA See figure 4 9,10,11 20 65 ns ns 120+(ws*40) ns ns ns See notes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55°C ≤ TC ≤ +125°C VDD = 5.0 V ± 10 % unless otherwise specified Group A subgroups Limits Min Unit Max tRETH See figure 4 9,10,11 47 ns tRETL See figure 4 9,10,11 47 ns tRETC See figure 4 9,10,11 120 7/ ns tRETR See figure 4 9,10,11 160 7/ ns tRETS See figure 4 9,10,11 0 tRETD See figure 4 9,10,11 START_RCV high active pulse width 3/ tRERH See figure 4 9,10,11 47 ns START_RCV low inactive pulse width 3/ tRERL See figure 4 9,10,11 47 ns first write access ( CSO -3/ WR low active) after START_RCV high 3/ tRERC See figure 4 9,10,11 120 ns RCV_RDY (receive ready) high inactive after the last write to memory 3/ tRERR See figure 4 9,10,11 160 time between the rising edge of RCV_RDY and the next start (rising edge from START_RCV) 3/ tRERS See figure 4 9,10,11 0 RCV_RDY hold after START_RCV high 3/ tRERD See figure 4 9,10,11 WR active low pulse width 3/ tFWL See figure 4 9,10,11 WR inactive high pulse width 3/ tFWH See figure 4 9,10,11 START_TRM high active pulse width 3/ START_TRM low inactive pulse width 3/ first read access ( CSO -3/ RD low active) after START_TRM high 3/ TRM_RDY (transmit ready) high active after the last read from memory 3/ time between the rising edge of ns TRM_RDY and the next start (rising edge from START_TRM) 3/ TRM_RDY hold after START_TRM 170 ns high 3/ 170 ns ns 170 ns 40+(ws*40) 5/ 42+(ws*40) 5/ ns 38 40 ns See notes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55°C ≤ TC ≤ +125°C VDD = 5.0 V ± 10 % unless otherwise specified Group A subgroups Limits Min Unit Max tFWACK See figure 4 9,10,11 120 ns tFFS See figure 4 9,10,11 8 ns RCVEOP1, RCVEOP2 high after last write and WR high 3/ tFWEOP See figure 4 9,10,11 40 RCV_EOP_ACK active high pulse width 3/ tFWEOPA See figure 4 9,10,11 49 RCVEOP1, RCVEOP2 low after RCV_EOP_ACK high 3/ tFWEOPH See figure 4 9,10,11 DATA0-7 enable after WR low 3/ ` tFWDE See figure 4 9,10,11 0 DATA0-7 valid before WR high 3/ tFWDV See figure 4 9,10,11 32 ns DATA0-7 hold after WR high 3/ tFWDH See figure 4 9,10,11 2 ns tFRL See figure 4 9,10,11 See figure 4 9,10,11 38 tFES See figure 4 9,10,11 8 TRM_EOP_ACKnowledge active high after TRMEOP1, TRMEOP2 high AND FIFO_EMPTY active low 3/ tFREOPA See figure 4 9,10,11 160 TRMEOP1, TRMEOP2 hold after TRM_EOP_ACK high 3/ tFREOPH See figure 4 9,10,11 0 TRM_EOP_ACK hold after TRMEOP1, TRMEOP2 low 3/ tFRACKH See figure 4 9,10,11 122 DATA0-7 setup before RD inactive high 3/ tFRDV See figure 4 9,10,11 9 ns DATA0-7 hold after RD inactive high 3/ tFRDH See figure 4 9,10,11 0 ns ADC _ CS low pulse width 3/ tADCCS See figure 4 9,10,11 ADC_RDY high pulse width 3/ tADCRDY See figure 4 9,10,11 WR active low after RCV_EOP_ACK high 3/ FIFO _ FULL setup before high 3/ WR RD active low pulse width 3/ RD inactive high pulse width 3/ FIFO _ EMPTY setup before RD high 3/ tFRH 7/ ns ns 128 ns 6 ns 40+(ws*40) 42+(ws*40) 5/ 5/ 40+(ws*40) 5/ 40 ns ns ns 7/ ns ns 128 ns 42+(ws*40) 5/ 45 ns ns See notes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 10 TABLE I. Electrical performance characteristics - Continued. Test Conditions -55°C ≤ TC ≤ +125°C Symbol VDD = 5.0 V ± 10 % unless otherwise specified Group A subgroups Limits Min Unit Max ADC_RDY high to ADC_ R / C high 3/ tADCR See figure 4 9,10,11 ADC_ R / C setup before ADC _ CS low 3/ tADCS See figure 4 9,10,11 ADC_TRIG high pulse width 3/ tADCTRIG See figure 4 9,10,11 45 ns ADC_TRIG high to ADC _ CS low 3/ tADCTCS See figure 4 9,10,11 200+(ws*40) 5/ ns DATA 0-15 setup to ADC _ CS high 3/ tADCDS See figure 4 9,10,11 19 ns DATA 0-15 hold after ADC _ CS high 3/ tADCDH See figure 4 9,10,11 0 ns DAC_ADDR 0-2 and DATA 0-15 setup before DAC _ WR low 3/ tDACS See figure 4 9,10,11 40+(ws*40) 5/ 42+(ws*40) 5/ ns DAC _ WR low pulse width 3/ tDACWR See figure 4 9,10,11 40+(ws*40) 5/ 42+(ws*40) 5/ ns DATA 0-15 hold after DAC _ WR high 3/ tDACH See figure 4 9,10,11 38 42 ns TMRx_CLK period 3/ tTCLK See figure 4 9,10,11 80 TMRx_CLK width high 3/ tTCLKH See figure 4 9,10,11 35 45 ns TMRx_CLK width low 3/ tTCLKL See figure 4 9,10,11 35 45 ns TMRx_EXP low / high after TMRx_CLK high 3/ tTEXP See figure 4 9,10,11 9 24 ns EXT_IREQx low pulse width 3/ tEXINT See figure 4 9,10,11 10 ns Bit Period 3/ tLBITP See figure 4 9,10,11 4 ns LDOx, LSOx output skew 3/ 8/ tLOUTS See figure 4 9,10,11 Data/Strobe edge separation 3/ tLDSI See figure 4 9,10,11 1 ns TCK period 3/ tTCK See figure 5 9,10,11 100 ns TCK width high 3/ tTCKH See figure 5 9,10,11 40 ns TCK width low 3/ tTCKL See figure 5 9,10,11 40 ns TMS, TDI setup before TCK high 3/ tTIS See figure 5 9,10,11 8 ns TMS, TDI hold after TCK high 3/ tTIH See figure 5 9,10,11 8 ns TDO delay after TCK low 3/ tTDO See figure 5 9,10,11 200 40+(ws*40) 5/ ns 42+(ws*40) 5/ ns ns 0.5 ns 17 ns See notes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 11 TABLE I. Electrical performance characteristics - Continued. Test Conditions -55°C ≤ TC ≤ +125°C Symbol VDD = 5.0 V ± 10 % unless otherwise specified Group A subgroups Limits Min Unit Max SMCS Inputs setup before TCK high 3/ tSYSS See figure 5 4 8 ns SMCS Inputs hold after TCK high 3/ tSYSM See figure 5 4 8 ns SMCS Outputs delay after TCK low 3/ tSYSO See figure 5 4 27 ns TDO disable after TRST active low 3/ tTDOZ See figure 5 4 5 ns TRST pulse width 3/ tTRST See figure 5 4 1/ 2/ 3/ 4/ 5/ 6/ 7/ 8/ 2 * tTCK ns Forcing conditions of the functional test, assure that these limits are met, but they will not be individually recorded. Read & record measurements in accordance with MIL-PRF-38535. Tested at initial design and after major process changes, otherwise guaranteed. IOL and IOH are based on buffer size. ws = wait state number. Wait state is defined in one register (called RAM_WS_REG) located at address OX42. Internal clock runs at 25MHz, ticlk = 40 ns. Data bandwidth over the IEEE-1355 link. Simultaneous read from the memory with wait states. Output skew includes jitter. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 12 Case X Milimeters Symbol A Inches Min Max Min Max 2.21 2.67 .087 .105 c 0.15 0.20 .006 .008 D/E 31.80 32.80 1.252 1.291 D1/E1 18.80 19.30 .740 .760 e 0.635 BSC .025 BSC b 0.254 REF .010 REF A1 1.83 A2 L 2.24 .072 0.203 REF 6.50 N1/N2 .088 .008 REF 6.75 .256 25 .266 25 Figure1. Case outline. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 13 Pin Number Name Pin Number Name Pin Number Name 1 VCC 35 IOB16 69 GPIO2 2 GND 36 IOB17 70 GPIO3 3 GND 37 IOB18 71 GPIO4 4 VCC 38 IOB19 72 GPIO5 5 LD0 39 IOB20 73 GPIO6 6 LS0 40 IOB21 74 GPIO7 7 LDI 41 IOB22 75 TMR1_CLK 8 LSI 42 IOB23 76 TMR2_CLK 9 GND 43 IOB24 77 RxD1 10 TCK 44 IOB25 78 TMR1_EXP 11 TMS 45 IOB26 79 TMR2_EXP 12 TDI 46 IOB27 80 TxD1 13 TRST 47 DATA0 81 HDATA0 14 TD0 48 DATA1 82 HDATA1 15 GND 49 DATA2 83 HDATA2 16 VCC 50 DATA3 84 HDATA3 17 IOB0 51 DATA4 85 HDATA4 18 IOB1 52 DATA5 86 HDATA5 19 IOB2 53 DATA6 87 HDATA6 20 IOB3 54 DATA7 88 VCC 21 IOB4 55 DATA8 89 GND 22 IOB5 56 VCC 90 HDATA7 23 IOB6 57 GND 91 HDATNADR 24 IOB7 58 DATA9 92 HSEL 25 IOB8 59 DATA10 93 HWRNRD 26 IOB9 60 DATA11 94 HINTR 27 VCC 61 VCC 95 RESET 28 GND 62 GND 96 CLK 29 IOB10 63 DATA12 97 GND 30 IOB11 64 DATA13 98 GND 31 IOB12 65 DATA14 99 VCC 32 IOB13 66 DATA15 100 PLLOUT 33 IOB14 67 GPIO0 34 IOB15 68 GPIO1 Figure 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 14 Figure 3. Block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 15 Figure 4. Timing waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 16 Figure 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 17 Figure 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 18 Figure 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 19 Figure 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 20 Figure 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 21 Figure 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 22 Figure 5. JTAG timing waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 23 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) TA = +125°C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 24 TABLE II. Electrical test requirements. Test requirements Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical parameters (see 4.4) Group D end-point electrical parameters (see 4.4) Group E end-point electrical parameters (see 4.4) Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class M 1,7,9 Subgroups (in accordance with MIL-PRF-38535, table III) Device class Q 1,7,9 Device class V 1,7,9 1,2,3,7,8,9,10,11 1/ 1,2,3,7,8,9,10, 11 1/ 1,2,3,7,8,9,10, 11 2/ 3/ 1,2,3,4,7,8,9,10,11 1/ 1,2,3,4,7,8,9, 10,11 1/ 1,2,3,4,7,8,9,10, 11 2/ 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. 3/ Delta limits are as specified in table IIB herein and shall be required where specified in table I. TABLE IIB. Delta limits Parameter 1/ Symbol Test Method Test Conditions Unit ± 0.1 µA Low Level input current 2/ IIL High level input current 2/ IIH ± 0.1 µA Output leakage low current 2/ IOZL ± 0.1 µA Output leakage high current 2/ IOZH ± 0.1 µA Low level output voltage VOL ± 100 mV High level output voltage VOH ± 100 mV 1/ 2/ As per Table I Change limits The parameters shall be recorded before and after the required burn-in and life test to determine the delta limits. Only for inputs and I/O without pull up or pull down. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C, D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. b. TA = +125°C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 25 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-I-38535. a. End-point electrical parameters shall be as specified in table II herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone (614) 692-0547. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 26 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.5.1 Table III. Pin descriptions. TDI-TEST DATA INPUT. Provides serial data for the boundary scan logic. TDO-TEST DATA OUTPUT. Serial scan output of the scan path. TCK-TEST CLOCK. Provides an asynchronous clock for JTAG boundary scan. TMS-TEST MODE SELECT. Used to control the test state machine. This input should be left unconnected or tied to ground during normal operation. TRST-TEST RESET. Resets the test state machine. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02A02 A REVISION LEVEL SHEET 27 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 02-04-04 Approved sources of supply for SMD 5962-02A02 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard Vendor Vendor microcircuit drawing CAGE similar PIN 1/ number PIN 2/ 5962-02A0201QXC F7400 T7906EKTMQ 5962-02A0201VXC F7400 T7906EKTSV 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number F7400 Vendor name and address Atmel Nantes SA BP 70602 44306 Nantes Cedex 3 France The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.