SAM B11 SOC Ultra Low Power BLE 4.1 SoC - Datasheet

SAMB11 QFN SOC
Ultra-low Power BLE 4.1 SoC
DATASHEET
Description
The SAMB11 is an ultra-low power Bluetooth® SMART (BLE 4.1) System on a Chip
with Integrated MCU, Transceiver, Modem, MAC, PA, TR Switch, and Power
Management Unit (PMU). It is a standalone Cortex®-M0 applications processor with
embedded Flash memory and BLE connectivity.
The qualified Bluetooth Smart protocol stack is stored in dedicated ROM, the
firmware includes L2CAP service layer protocols, Security Manager, Attribute
protocol (ATT), Generic Attribute Profile (GATT) and the Generic Access Profile
(GAP). Additionally, application profiles such as Proximity, Thermometer, Heart Rate,
Blood Pressure, and many others are supported and included in the protocol stack.
Features
 Complies with Bluetooth V4.1, ETSI EN 300 328 and EN 300 440 Class 2, FCC
CFR47 Part 15 and ARIB STD-T66
 2.4GHz transceiver and Modem
– -95dBm/-93dBm programmable receiver sensitivity
– -20 to +3.5dBm programmable TX output power
– Integrated T/R switch
– Single wire antenna connection
 ARM® Cortex®-M0 32-bit processor
– Single wire Debug (SWD) interface
– 4-channel DMA controller
– Brown out detector and Power On Reset
– Watchdog Timer
 Memory
– 128kB embedded RAM (96kB available for application)
– 128kB embedded ROM
– 256kB Flash
 Hardware Security Accelerators
– AES-128
– SHA-256
 Peripherals
– 23 digital and three wakeup GPIOs with 96kΩ internal pull-up resistors, and four
Mixed Signal GPIOs
– 2x SPI Master/Slave
– 2x I2C Master/Slave and 1x I2C Slave
– 2x UART
– Three-axis quadrature decoder
– 4x Pulse Width Modulation (PWM), three General Purpose Timers, and one
Wakeup Timer
– 4-channel 11-bit ADC
Atmel-42426C-SAM-B11-Ultra-Low-Power-BLE-4.1-SoC-Datasheet_02/2016
 Clock
– Integrated 26MHz RC oscillator
– 26MHz crystal oscillator
– Integrated 2MHz sleep RC oscillator
– 32.768kHz RTC crystal oscillator
 Ultra-low Power
– 1.1µA sleep current (8K RAM retention and RTC running)
– 3.0mA peak TX current (0dBm, 3.6V)
– 4.0mA peak RX current (3.6V, -93dBm sensitivity)
 Integrated Power management
– 2.3 to 4.3V battery voltage range (limited by Flash memory)
– Fully integrated Buck DC/DC converter
 Bluetooth SIG Certification –
– The ATSAMB11 uses the ATBTLC1000 as its Bluetooth controller and is certified
under the ATBTLC1000.
 QD ID Controller (see declaration D028678)
 QD ID Host (see declaration D028679)
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Ultra Low Power BLE 4.1 SoC [Datasheet]
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Ta bl e of Conte nts
1
Ordering Information ................................................................................................... 5
2
Package Information ................................................................................................... 5
3
Block Diagram ............................................................................................................. 6
4
Pinout Information....................................................................................................... 7
5
Package drawing ....................................................................................................... 10
6
Power Management ................................................................................................... 11
6.1
6.2
6.3
6.4
6.5
7
Clocking ..................................................................................................................... 18
7.1
7.2
7.3
7.4
8
Overview ........................................................................................................................................ 18
26MHz Crystal Oscillator (XO) ....................................................................................................... 19
32.768kHz RTC Crystal Oscillator (RTC XO) ................................................................................ 20
7.3.1 General Information ..................................................................................................... 20
7.3.2 RTC XO Design and Interface Specification ................................................................ 23
7.3.3 RTC Characterization with Gm Code Variation at Supply 1.2V and Temp. = 25°C ..... 23
7.3.4 RTC Characterization with Supply Variation and Temp. = 25°C .................................. 24
2MHz and 26MHz Integrated RC Oscillator ................................................................................... 25
CPU and Memory Subsystem ................................................................................... 27
8.1
8.2
8.3
8.4
9
Power Architecture ........................................................................................................................ 11
DC/DC Converter ........................................................................................................................... 12
Power Consumption....................................................................................................................... 13
6.3.1 Description of Device States ........................................................................................ 13
6.3.2 Controlling the Device States ....................................................................................... 14
6.3.3 Current Consumption in Various Device States ........................................................... 14
Power-up Sequence ...................................................................................................................... 15
Power On Reset (POR) and Brown Out Detector (BOD) ............................................................... 16
ARM Subsystem ............................................................................................................................ 27
8.1.1 Features....................................................................................................................... 27
8.1.2 Module Descriptions .................................................................................................... 28
Memory Subsystem ....................................................................................................................... 29
8.2.1 Shared Instruction and Data Memory .......................................................................... 29
8.2.2 ROM ............................................................................................................................ 30
8.2.3 BLE Retention Memory ................................................................................................ 30
Non-volatile Memory ...................................................................................................................... 30
Flash Memory ................................................................................................................................ 30
Bluetooth Low Energy (BLE) Subsystem ................................................................ 31
9.1
9.2
9.3
BLE Core ....................................................................................................................................... 31
9.1.1 Features....................................................................................................................... 31
BLE Radio...................................................................................................................................... 31
9.2.1 Receiver Performance ................................................................................................. 31
9.2.2 Transmitter Performance ............................................................................................. 32
Atmel Bluetooth SmartConnect Stack ............................................................................................ 33
10 External Interfaces .................................................................................................... 34
10.1 Overview ........................................................................................................................................ 34
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10.2 I2C Master/Slave Interface ............................................................................................................. 36
10.2.1 Description ................................................................................................................... 36
10.2.2 I2C Interface Timing ..................................................................................................... 37
10.3 SPI Master/Slave Interface ............................................................................................................ 38
10.3.1 Description ................................................................................................................... 38
10.3.2 SPI Interface Modes .................................................................................................... 39
10.3.3 SPI Slave Timing ......................................................................................................... 40
10.3.4 SPI Master Timing ....................................................................................................... 41
10.4 UART Interface .............................................................................................................................. 41
10.5 GPIOs ............................................................................................................................................ 42
10.6 Analog to Digital Converter (ADC) ................................................................................................. 42
10.6.1 Overview ...................................................................................................................... 42
10.6.2 Timing .......................................................................................................................... 43
10.6.3 Performance ................................................................................................................ 44
10.7 Software Programmable Timer and Pulse Width Modulator .......................................................... 47
10.8 Clock Output .................................................................................................................................. 47
10.8.1 Variable Frequency Clock Output Using Fractional Divider ......................................... 47
10.8.2 Fixed Frequency Clock Output .................................................................................... 47
10.9 Three-axis Quadrature Decoder .................................................................................................... 48
11 Reference Design ...................................................................................................... 49
12 Bill of Material (BOM) ................................................................................................ 50
13 Electrical Characteristics .......................................................................................... 51
13.1 Absolute Maximum Ratings ........................................................................................................... 51
13.2 Recommended Operating Conditions ............................................................................................ 51
13.3 DC Characteristics ......................................................................................................................... 52
14 Errata .......................................................................................................................... 53
15 Document Revision History ...................................................................................... 54
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SAMB11
Ultra Low Power BLE 4.1 SoC [Datasheet]
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Ordering Information
Ordering Code
2
Package
Description
ATSAMB11G18A-MU-T
6x6mm QFN 48
SAMB11Tape & Reel
ATSAMB11G18A-MU-Y
6x6mm QFN 48
SAMB11 Tray
Package Information
Table 2-1.
SAMB11 6x6 QFN 48 Package Information
Parameter
Value
Package Size
6x6
QFN Pad Count
48
Total Thickness
0.85
QFN Pad Pitch
0.4
Pad Width
0.2
Exposed Pad size
4.2x4.2
Units
mm
Tolerance
±0.1 mm
+0.15/-0.05mm
mm
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3
Block Diagram
Figure 3-1.
6
SAMB11 Block Diagram
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Ultra Low Power BLE 4.1 SoC [Datasheet]
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Pinout Information
SAMB11 is offered in an exposed pad 48-pin QFN package. This package has an exposed paddle that must be
connected to the system board ground. The QFN package pin assignment is shown in Figure 4-1. The color
shading is used to indicate the pin type as follows:

Red – analog

Green – digital I/O (switchable power domain)

Blue – digital I/O (always-on power domain)

Yellow – digital I/O power

Purple – PMU

Shaded green/red – configurable mixed-signal GPIO (digital/analog)
The SAMB11 pins are described in Table 4-1.
Figure 4-1.
SAMB11 Pin Assignment
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Table 4-1.
Pin #
8
SAMB11 Pin Description with Default Peripheral Mapping
Pin Name
Pin Type
Description / Default Function
1
VDD_VCO
Analog/RF
RF Supply 1.2V
2
VDD_RF
Analog/RF
RF Supply 1.2V
3
RFIO
Analog/RF
RX input and TX output
4
VDD_AMS
Analog/RF
AMS Supply 1.2V
5
LP_GPIO_0
Digital I/O
SWD Clock
6
LP_GPIO_1
Digital I/O
SWD I/O
7
LP_GPIO_2
Digital I/O
UART1 RXD
8
LP_GPIO_3
Digital I/O
UART1 TXD
9
LP_GPIO_4
Digital I/O
UART1 CTS
10
LP_GPIO_22
Digital I/O
GPIO
11
LP_GPIO_23
Digital I/O
GPIO
12
LP_GPIO_5
Digital I/O
UART1 RTS
13
LP_GPIO_6
Digital I/O
UART2 RXD
14
LP_GPIO_7
Digital I/O
UART2 TXD
15
LP_GPIO_8
Digital I/O
I2C0 SDA (high-drive pad, see Table 13-3)
16
LP_GPIO_9
Digital I/O
I2C0 SCL (high-drive pad, see Table 13-3)
17
LP_GPIO_10
Digital I/O
SPI0 SCK
18
LP_GPIO_11
Digital I/O
SPI0 MOSI
19
LP_GPIO_12
Digital I/O
SPI0 SSN
20
LP_GPIO_13
Digital I/O
SPI0 MISO
21
VSW
PMU
DC/DC Converter Switching Node
22
VBATT_BUCK
PMU
DC/DC Converter Supply and General Battery Connection
23
VDDC_PD4
PMU
DC/DC Converter 1.2V output and feedback node
24
GPIO_MS1
Mixed Signal I/O
Configurable to be a GPIO Mixed Signal only (ADC interface)
25
GPIO_MS2
Mixed Signal I/O
Configurable to be a GPIO Mixed Signal only (ADC interface)
26
CHIP_EN
PMU
Master Enable for chip
27
GPIO_MS3
Mixed Signal I/O
Configurable to be a GPIO Mixed Signal only (ADC interface)
28
GPIO_MS4
Mixed Signal I/O
Configurable to be a GPIO Mixed Signal only (ADC interface)
29
LP_LDO_OUT_1P2
PMU
Low Power LDO output (connect to 1µF decoupling cap)
30
RTC_CLK_P
PMU
RTC terminal + / 32.768kHz XTAL +
31
RTC_CLK_N
PMU
RTC terminal - / 32.768kHz XTAL +
32
AO_TEST_MODE
Digital Input
Test Mode Selection (SCAN ATE) /GND for normal operation
33
AO_GPIO_0
Digital I/O
Always On External Wakeup
34
AO_GPIO_1
Digital I/O
Always On External Wakeup
35
AO_GPIO_2
Digital I/O
Always On External Wakeup
36
LP_GPIO_14
Digital I/O
UART2 CTS
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Ultra Low Power BLE 4.1 SoC [Datasheet]
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Pin #
Pin Name
Pin Type
Description / Default Function
37
LP_GPIO_15
Digital I/O
UART2 RTS
38
LP_GPIO_16
Digital I/O
GPIO
39
VDDIO
I/O Power
I/O Supply, can be less than or equal to VBATT_BUCK
40
LP_GPIO_17
Digital I/O
GPIO
41
LP_GPIO_18
Digital I/O
GPIO
42
LP_GPIO_19
Digital I/O
GPIO
43
LP_GPIO_20
Digital I/O
GPIO
44
XO_P
Analog/RF
XO Crystal +
45
XO_N
Analog/RF
XO Crystal -
46
TPP
Analog/RF
Test MUX + output
47
TPN
Analog/RF
Test MUX – output
48
VDD_SXDIG
Analog/RF
RF Supply 1.2V
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5
Package drawing
The SAMB11 QFN package is RoHS/green compliant.
Figure 5-1.
10
SAMB11 6x6 QFN 48 Package Outline Drawing
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Ultra Low Power BLE 4.1 SoC [Datasheet]
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6
Power Management
6.1
Power Architecture
SAMB11 uses an innovative power architecture to eliminate the need for external regulators and reduce the
number of off-chip components. The integrated power management block includes a DC/DC buck converter and
separate Low Drop out (LDO) regulators for different power domains. The DCDC buck converter converts battery
voltage to a lower internal voltage for the different circuit blocks and does this with high efficiency. The DCDC
requires three external components for proper operation (two inductors L 4.7µH and 9.1nH, and one capacitor C
4.7µF).
The stacked Flash has a supply pin that is internally connected to the VDDIO pin.
Figure 6-1.
SAMB11 Power Architecture
RF/AMS
VDD_VCO
LDO2
1.0V
~
SX
VDD_AMS,
VDD_RF,
VDD_SXDIG
RF/AMS Core
VDDIO
Digital
RF/AMS Core Voltage
Pads
Digital Core
eFuse
dcdc_ena
PMU
2.5V
Digital Core Voltage
Sleep
Osc
EFuse
LDO
LP LDO
ena
Dig Core
LDO
ena
CHIP_EN
VDDC_PD4
ena
DC/DC Converter
VBATT_BUCK
Vin
Vout
VSW
Off-Chip
LC
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6.2
DC/DC Converter
The DC/DC Converter is intended to supply current to the BLE digital core and the RF transceiver core. The
DC/DC consists of a power switch, 26MHz RC oscillator, controller, external inductor, and external capacitor. The
DCDC is utilizing pulse skipping discontinuous mode as its control scheme. The DC/DC specifications are shown in
the following tables and charts.
Table 6-1.
DC/DC Converter Specifications (performance is guaranteed for 4.7µF L and 4.7µF C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
IREG
0
10
30
mA
Dependent on external component values and
DC/DC settings with acceptable efficiency
(1)
CEXT
4.7 10%
4.7
20
µF
External capacitance range
External inductor range
LEXT
2.2 10%
4.7
4.7
+10%
µH
External inductance range
Battery voltage
VBAT
2.35
3
4.3
Output current capability
External capacitor range
Note
Functionality and stability given
V
Output voltage range
VREG
Current consumption
IDD
1.05
1.2
125
Startup time
tstartup
50
Voltage ripple
ΔVREG
5
10
η
85
VOS
0
Line Regulation
ΔVREG
10
Load regulation
ΔVREG
5
Efficiency
Overshoot at startup
Note:
1.47
25mV step size
µA
DC/DC quiescent current
600
µs
Dependent on external component values and
DC/DC settings
30
mV
Dependent on external component values and
DC/DC settings
%
Measured at 3V VBATT, at load of 10mA
No overshoot, no output pre-charge
mV
From 2.35 - 4.3V
From 0 - 10mA
External Cap: Sum of all caps connected to the DC/DC output node.
Table 6-2.
DC/DC Converter Allowable Onboard Inductor and Capacitor Values (VBATT=3V)
Vripple [mV]
Inductor [µH]
RX sensitivity (1) [dBm]
Efficiency [%]
C=2.2µF
C=4.7µF
C=10µF
2.2
83
N/A
<5
<5
~1.5dB degrade
4.7
85
9
5
<5
~0.7dB degrade
Degradation relative to design powered by external LDO and DC/DC disabled.
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Ultra Low Power BLE 4.1 SoC [Datasheet]
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Figure 6-2.
DC/DC Converter Efficiency
Efficiency vs. Battery Voltage
95.0
Efficeincy (%)
90.0
85.0
80.0
75.0
70.0
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.3
14
15
Battery Voltage (V)
Efficiency vs. Load Current
86.0
85.0
Efficeincy (%)
84.0
83.0
82.0
81.0
80.0
79.0
78.0
77.0
3
4
5
6
7
8
9
10
11
12
13
Load Current (mA)
6.3
Power Consumption
6.3.1
Description of Device States
SAMB11 has multiple device states, depending on the state of the ARM processor and BLE subsystem.
Note:
The ARM is required to be powered ON if the BLE subsystem is active.

BLE_On_Transmit – Device is actively transmitting a BLE signal (Application may or may not be active)

BLE_On_Receive – Device is actively receiving a BLE signal (Application may or may not be active)

MCU_Only – Device has ARM processor powered on and BLE subsystem powered down

Ultra_Low_Power – BLE is powered down and Application is powered down (with or without RAM retention)

Power_Down – Device core supply off
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6.3.2
Controlling the Device States
The following pins are used to switch between the main device states:

CHIP_EN – Used to enable PMU

VDDIO – I/O supply voltage from external supply
In Power_Down state, VDDIO is on and CHIP_EN is low (at GND level). To switch between Power_Down state
and MCU_Only state CHIP_EN has to change between low and high (VDDIO voltage level). Once the device is
MCU_Only state, all other state transitions are controlled entirely by software. When VDDIO is off and CHIP_EN is
low, the chip is powered off with no leakage.
When no power is supplied to the device (the DC/DC Converter output and VDDIO are both off and at ground
potential), a voltage cannot be applied to the SAMB11 pins because each pin contains an ESD diode from the pin
to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin.
If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be on,
so the Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not apply
a voltage that is more than one diode-drop below ground to any pin.
6.3.3
Current Consumption in Various Device States
Table 6-3.
SAMB11 Device Current Consumption at VBATT=3.6V
CHIP_EN
VDDIO
IVBAT (typical) (3)
IVDDIO (typical) (3)
Power_Down
Off
On
<50nA
<50nA
Ultra_Low_Power Standby
On
On
900nA
50nA
Ultra_Low_Power with 8KB retention, BLE
timer, no RTC (1)
On
On
1.1µA
0.2µA
Ultra_Low_Power with 8KB retention, BLE
timer, with RTC (2)
On
On
1.25µA
0.1uA
MCU_Only, idle (waiting for interrupt)
On
On
0.85mA
0.2µA
BLE_On_Receive@-95dBm
On
On
4.2mA
0.2µA
BLE_On_Transmit, 0dBm output power
On
On
3.0mA
0.2µA
BLE_On_Transmit, 3.5dBm output power
On
On
4.0mA
0.2µA
Device State
Notes:
Note:
14
1.
2.
Remark
Sleep clock derived from internal 32kHz RC oscillator.
Sleep clock derived from external 32.768kHz crystal specified for C L=7pF, using the default on-chip capacitance
only, without using external capacitance.
3. Expected values for production silicon.
Average advertising current for connectable beacon with full payload (37-byte packet) is targeted to be 9.7µA. The
average advertising current is based on automatic advertising from the ROM with RTC 32kHz, BLE sleep timers, and
8KB memory retention. IDRAM1 and IDRAM2 are OFF. External Peripherals and debug clocks are turned OFF. VBAT
is set to 3.6V. This advertising current will be enabled on a future SDK release. For current SDK based advertising
current, see errata Chapter 14.
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Ultra Low Power BLE 4.1 SoC [Datasheet]
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Figure 6-3.
6.4
SAMB11 Average Advertising Current
Power-up Sequence
The power-up sequence for SAMB11 is shown in Figure 6-4. The timing parameters are provided in Table 6-4.
Figure 6-4.
SAMB11 Power-up Sequence
VBATT
t BIO
VDDIO
t IOCE
CHIP_EN
t SCS
32kHz
RC Osc
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Table 6-4.
Parameter
SAMB11 Power-up Sequence Timing
Min.
tBIO
0
tIOCE
0
tSCS
10
Max.
Units
Description
VBATT rise to VDDIO rise
VBATT and VDDIO can rise simultaneously or
can be tied together.
VDDIO rise to CHIP_EN rise
CHIP_EN must not rise before VDDIO.
CHIP_EN must be driven high or low, not left
floating.
ms
6.5
µs
Notes
CHIP_EN rise to 31.25kHz
(2MHz/64) oscillator stabilizing
Power On Reset (POR) and Brown Out Detector (BOD)
The SAMB11 has a POR circuit for proper system power bring up and a brown out detector to reset the system’s
operation when a drop in battery voltage is detected.

POR is a power on reset circuit that outputs a HI logic value when the VBATT_BUCK is below a voltage
threshold. The POR output becomes a LO logic value when the VBATT_BUCK is above a voltage threshold.

BOD is a brown out detector that outputs a HI logic value when the bandgap reference (BGR) voltage falls
below a programmable voltage threshold. When the bandgap voltage reference voltage level is restored
above a voltage threshold, the BOD output becomes a LO logic value.

The counter creates a pulse that is HI for 256*(64*T_2MHz) ~8.2ms
The system block diagram and timing are illustrated in Figure 6-5 and Figure 6-6.
Figure 6-5.
16
SAMB11 POR and BOD Block Diagram
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Ultra Low Power BLE 4.1 SoC [Datasheet]
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Figure 6-6.
SAMB11 POR and BOD Timing Sequence
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7
Clocking
7.1
Overview
Figure 7-1.
SAMB11 Clock Architecture
26 MHz
26 MHz
XO
×2
52 MHz
BLE Clock
26 MHz
26 MHz
26 MHz
RC Osc
ARM
Clock
Control
ARM Clock
Low
Power
Clock
Control
Low Power
Clock
2 MHz
2 MHz
RC Osc
2 MHz
÷64
32.768 kHz
RTC XO
31.25 kHz
32.768 kHz
Figure 7-1 provides an overview of the clock tree and clock management blocks.
The BLE Clock is used to drive the BLE subsystem. The ARM clock is used to drive the Cortex-M0 MCU and its
interfaces (UART, SPI, and I2C), the nominal MCU clock speed is 26MHz. The Low Power Clock is used to drive all
the low power applications like BLE sleep timer, always-on power sequencer, always-on timer, and others.
The 26MHz Crystal Oscillator (XO) must be used for the BLE operations or in the event a very accurate clock is
required for the ARM subsystem operations.
The 26MHz integrated RC Oscillator is used for most general purpose operations on the MCU and its peripherals.
In cases when the BLE subsystem is not used, the RC oscillator can be used for lower power consumption. The
frequency variation of this RC oscillator is up to ±50% over process, voltage, and temperature.
The 2MHz integrated RC Oscillator can be used as the Low Power Clock for applications that require fast wakeup
of the ARM or for generating a ~31.25 kHz clock for slower wakeup but lowest power in sleep mode. This 2MHz
oscillator can also be used as the ARM Clock for low-power applications where the MCU needs to remain on but
run at a reduced clock speed. The frequency variation of this RC oscillator is up to ±50% over process, voltage,
and temperature.
The 32.768kHz RTC Crystal Oscillator (RTC XO) is recommended to be used for BLE operations (although
optional) as it will reduce power consumption by providing the best timing for wakeup precision, allowing circuits to
be in low power sleep mode for as long as possible until they need to wake up and connect during the BLE
connection event. The ~31.25kHz clock derived from the 2MHz integrated RC Oscillator can be used instead of
RTC XO but it has low accuracy over process, voltage and temperature variations (up to ±50%) and thus needs to
be frequently calibrated to within ±500ppm if the RC oscillator is used for BLE timing during a connection event.
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Because this clock is less accurate than RTC XO, it will require waking up earlier to prepare for a connection event
and this will increase the average power consumption. Calibration of the RC Oscillator is described in the
application note.
7.2
26MHz Crystal Oscillator (XO)
Table 7-1.
SAMB11 26MHz Crystal Oscillator Parameters
Parameter
Crystal Resonant Frequency
Min.
Typ.
Max.
Units
N/A
26
N/A
MHz
50
150
Ω
Crystal Equivalent Series Resistance
Stability - Initial Offset (1)
-50
50
ppm
Stability - Temperature and Aging
-40
40
ppm
Initial offset must be calibrated to maintain ±25ppm in all operating conditions. This calibration is performed during
final production testing and calibration offset values are stored in eFuse. More details are provided in the
calibration application note.
The block diagram in Figure 7-2(a) shows how the internal Crystal Oscillator (XO) is connected to the external
crystal.
The XO has up to 10pF internal capacitance on each terminal XO_P and XO_N (programmable in steps of
1.25pF). To bypass the crystal oscillator, an external Signal capable of driving 10pF can be applied to the XO_P
terminal as shown in Figure 7-2(b).
The needed external bypass capacitors depend on the chosen crystal characteristics. Refer to the datasheet of the
preferred crystal and take into account the on chip capacitance.
When bypassing XO_P from an external clock, XO_N is required to be floating.
Figure 7-2.
SAMB11 Connections to XO
(a) Crystal oscillator is used
(b) Crystal oscillator is bypassed
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Table 7-2.
SAMB11 26MHz XTAL C_onchip Programming
xo_cap[3:0]
40020808[17]
40020848[17]
40020814[7,6,15]
Cl,on-chip [pF]
0
0
0
000
1.00
1
0
0
001
2.25
2
0
0
010
3.50
3
0
0
011
4.75
4
0
0
100
6.00
5
0
0
101
7.25
6
0
0
110
8.50
7
0
0
111
9.75
8
1
1
000
6.00
9
1
1
001
7.25
10
1
1
010
8.50
11
1
1
011
9.75
12
1
1
100
11.00
13
1
1
101
12.25
14
1
1
110
13.50
15
1
1
111
14.75
Table 7-3 specifies the electrical and performance requirements for the external clock .
Table 7-3.
SAMB11 Bypass Clock Specification
Parameter
Min.
Max.
Unit
Comments
Oscillation frequency
26
26
MHz
Voltage swing
0.75
1.2
Vpp
Stability – Temperature and Aging
-50
+50
ppm
BLE Spec has +-50ppm Frequency accuracy requirement.
Phase Noise
-130
dBc/Hz
At 10kHz offset
Jitter (RMS)
<1psec
7.3
32.768kHz RTC Crystal Oscillator (RTC XO)
7.3.1
General Information
Must be able to drive 5pF load @ desired frequency
Based on integrated phase noise spectrum from
1kHz to 1MHz
SAMB11 has a 32.768kHz RTC oscillator that is preferably used for BLE activities involving connection events. To
be compliant with the BLE specifications for connection events, the frequency accuracy of this clock has to be
within ±500ppm. Because of the high accuracy of the 32.768kHz crystal oscillator clock, the power consumption
can be minimized by leaving radio circuits in low-power sleep mode for as long as possible until they need to wake
up for the next connection timed event.
The block diagram in Figure 7-3(a) shows how the internal low frequency Crystal Oscillator (XO) is connected to
the external crystal.
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The RTC XO has a programmable internal capacitance with a maximum of 15pF on each terminal, RTC_CLK_P
and RTC_CLK_N. When bypassing the crystal oscillator with an external signal, one can program down the internal
capacitance to its minimum value (~1pF) for easier driving capability. The driving signal can be applied to the
RTC_CLK_P terminal as shown in Figure 7-3(b).
The needed external bypass capacitors depend on the chosen crystal characteristics. Refer to the datasheet of the
preferred crystal and take into account the on chip capacitance.
When bypassing RTC_CLK_P from an external clock, RTC_CLK_N is required to be floating.
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Figure 7-3.
SAMB11 Connections to RTC XO
(a) Crystal oscillator is used
Table 7-4.
22
(b) Crystal oscillator is bypassed
32.768kHz XTAL C_onchip Programming
Register: pierce_cap_ctrl[3:0]
Cl_onchip [pF]
0000
0.0
0001
1.0
0010
2.0
0011
3.0
0100
4.0
0101
5.0
0110
6.0
0111
7.0
1000
8.0
1001
9.0
1010
10.0
1011
11.0
1100
12.0
1101
13.0
1110
14.0
1111
15.0
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7.3.2
RTC XO Design and Interface Specification
The RTC consists of two main blocks: The Programmable Gm stage and tuning capacitors. The programmable Gm
stage is used to maintain a phase shift of 360°C with the motional arm and keep total negative resistance to sustain
oscillation. Tuning capacitors are used to adjust the XO center frequency and control the XO precision for different
crystal models. The output of the XO is driven to the digital domain via a digital buffer stage with supply voltage of
1.2V.
Table 7-5.
RTC XO Interface
Pin Name
Function
Register Default
Digital Control Pins
Pierce_res_ctrl
Control feedback resistance value:
0 = 20MΩ Feedback resistance
1 = 30MΩ Feedback resistance
0X4000F404<15>=’1’
Pierce_cap_ctrl<3:0>
Control the internal tuning capacitors with step of 700fF:
0000=700fF
1111=11.2pF
Refer to crystal datasheet to check for optimum tuning cap value
0X4000F404<23:20>=”1000”
Pierce_gm_ctrl<3:0>
Controls the Gm stage gain for different crystal mode:
0011= for crystal with shunt cap of 1.2pF
1000= for crystal with shunt cap >3pF
0X4000F404<19:16>=”1000”
Supply Pins
VDD_XO
RTC Characterization with Gm Code Variation at Supply 1.2V and Temp. = 25°C
This section shows the RTC total drawn current and the XO accuracy versus different tuning capacitors and
different GM codes, at supply voltage of 1.2V and temp. = 25°C.
Figure 7-4.
RTC Drawn Current vs. Tuning Caps at 25°C
600
500
Current in nA
7.3.3
1.2V
gm code=1
400
gm code=2
300
gm code=4
200
gm code=8
100
gm code=12
gm code=16
0
0
5
10
Tuning Caps in pF
15
20
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Figure 7-5.
RTC Oscillation Frequency Deviation vs. Tuning Caps at 25°C
450
400
ppm
350
300
gm code=1
250
gm code=2
200
gm code=4
150
gm code=8
100
gm code=12
50
gm code=16
0
0
2
4
6
8
10
12
14
16
18
Tuning Caps
7.3.4
RTC Characterization with Supply Variation and Temp. = 25°C
Figure 7-6.
RTC Drawn Current vs. Supply Variation
1400
1200
Current in nA
1000
gm code=0 & Tuning
Cap=8pF
800
gm code=0 & Tuning
Cap=0pF
600
400
gm code=16 &
Tuning Cap=16pF
200
gm code=16 &
Tuning Cap =0pF
0
0.9
1
1.1
1.2
Supply voltage
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1.3
1.4
1.5
Figure 7-7.
RTC Frequency Deviation vs. Supply Voltage
400
350
ppm
300
250
gm code=0 & Tuning
Cap=8pF
200
gm code=0 & Tuning
Cap=0pF
150
gm code=16 & Tuning
Cap=16pF
100
gm code=16 & Tuning Cap=0
50
0
0.9
1
1.1
1.2
1.3
1.4
1.5
Supply Voltage
7.4
2MHz and 26MHz Integrated RC Oscillator
The 2MHz integrated RC Oscillator circuit without calibration has a frequency variation of 50% over process,
temperature, and voltage variation. The ~31.25kHz clock is derived from the 2MHz clock by dividing by 64 and
provides for lowest sleep power mode with a real-time clock running. As described above, calibration over process,
temperature, and voltage is required to maintain the accuracy of this clock.
Figure 7-8.
32kHz RC Oscillator PPM Variation vs. Calibration Time at Room Temperature
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Figure 7-9.
32kHz RC Oscillator Frequency Variation over Temperature
The 26MHz integrated RC Oscillator circuit has a frequency variation of 50% over process, temperature, and
voltage variation.
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8
CPU and Memory Subsystem
8.1
ARM Subsystem
SAMB11 has an ARM Cortex-M0 32-bit processor. It is responsible for controlling the BLE Subsystem and handling
all application features.
The Cortex-M0 Microcontroller consists of a full 32-bit processor capable of addressing 4GB of memory. It has a
RISC-like load/store instruction set and internal 3-stage Pipeline Von Neumann architecture.
The Cortex-M0 processor provides a single system-level interface using AMBA technology to provide high speed,
low latency memory accesses.
The Cortex-M0 processor implements a complete hardware debug solution, with four hardware breakpoint and two
watch point options. This provides high system visibility of the processor, memory, and peripherals through a 2-pin
Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices.
Figure 8-1.
SAMB11 ARM Cortex-M0 Subsystem
PD1
Timer
DualTimer
AHB
Slave
AHB
Master
Watch Dog
Timer x2
SPI x2
Ahb_to_sram
BLE
Retention
Ahb_to_rom
ROM
Ahb_to_sram
IDRAM1
Ahb_to_sram
IDRAM2
GPIO Ctrl x3
System Level AHB Slave
System Regs
Security Cores
I2C x2
Nested Vector
IRQ Ctrl
Control Registers
EFUSE Registers
LP Clock Calibration
ARM APB
DMA Controller
UART x2
System Level
AHB Master
SPI Flash Ctrl
LP
CORTEX
M0
AON Sleep Timer
AON Power
Sequencer
8.1.1
Features
The processor features and benefits are:

Tight integration with the system peripherals to reduce area and development costs

Thumb instruction set combines high code density with 32-bit performance

Integrated sleep modes using a Wakeup Interrupt Controller for low power consumption

Deterministic, high-performance interrupt handling via Nested Vector Interrupt Controller for time-critical
applications

Serial Wire Debug reduces the number of pins required for debugging

DMA engine for Peripheral-to-Memory, Memory-to-Memory and Memory-to-Peripheral operation
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8.1.2
Module Descriptions
8.1.2.1 Timer
The 32 bit timer block allows the CPU to generate a time tick at a programmed interval. This feature can be used
for a wide variety of functions such as counting, interrupt generation, and time tracking.
8.1.2.2 Dual Timer
The APB dual-input timer module is an APB slave module consisting of two programmable 32-bit down-counters
that can generate interrupts when they expire. The timer can be used in a Free-running, Periodic, or One-shot
mode.
8.1.2.3 Watchdog
The two watchdog blocks allow the CPU to be interrupted if it has not interacted with the watchdog timer before it
expires. In addition, this interrupt will be an output of the core so that it can be used to reset the CPU in the event
that a direct interrupt to the CPU is not useful. This will allow the CPU to get back to a known state in the event a
program is no longer executing as expected. The watchdog module applies a reset to a system in the event of a
software failure, providing a way to recover from software crashes.
8.1.2.4 Wake up Timer
This timer is a 32-bit count-down timer that operates on the 32kHz sleep clock. It can be used as a general
purpose timer for the ARM or as a wakeup source for the chip. It has the ability to be a onetime programmable
timer, as it will generate an interrupt/wakeup on expiration and stop operation. It also has the ability to be
programmed in an auto reload fashion where it will generate an interrupt/wakeup and then proceed to start another
count down sequence.
8.1.2.5 SPI Controller
See Section 10.3.
8.1.2.6 I2C Controller
See Section 10.2.
8.1.2.7 SPI-Flash Controller
The AHB SPI-Flash Controller is used to access an internal stacked Flash memory to access various
instruction/data code needed for storing application code, code patches, and OTA images. Supports several SPI
modes including 0, 1, 2, and 3.
8.1.2.8 UART
See Section 10.4.
8.1.2.9 DMA Controller
Direct Memory Access (DMA) allows certain hardware subsystems to access main system memory independently
of the Cortex-M0 Processor.
The DMA features and benefits are:
28

Supports any address alignment

Supports any buffer size alignment

Peripheral flow control, including peripheral block transfer

The following modes are supported:
–
Peripheral to peripheral transfer
–
Memory to memory
–
Memory to peripheral
–
Peripheral to memory
–
Register to memory
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
Interrupts for both TX done and RX done in memory and peripheral mode

Scheduled transfers

Endianness byte swapping

Watchdog timer

Four channel operation

32-bit Data width

AHB MUX (on read and write buses)

Command lists support

Usage of tokens
8.1.2.10 Nested Vector Interrupt Controller
External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority
of each interrupt. The NVIC and the Cortex-M0 processor core are closely coupled, providing low latency interrupt
processing and efficient processing of late arriving interrupts.
All NVIC registers are accessible via word transfers and are little-endian. Any attempt to read or write a half-word
or byte individually is unpredictable.
The NVIC allows the CPU to be able to individually enable, disable each interrupt source and hold each interrupt
until it has been serviced and cleared by the CPU.
Table 8-1.
NVIC Register Summary
Name
Description
ISER
Interrupt Set-Enable Register
ICER
Interrupt Clear-Enable Register
ISPR
Interrupt Set-Pending Register
ICPR
Interrupt Clear-Pending Register
IPR0-IPR7
Interrupt Priority Registers
For a description of each register, see the Cortex-M0 documentation from ARM.
8.1.2.11 GPIO Controller
The AHB GPIO is a general-purpose I/O interface unit allowing the CPU to independently control all input or output
signals on SAMB11. These can be used for a wide variety of functions pertaining to the application.
The AHB GPIO provides a 16-bit I/O interface with the following features:
8.2

Programmable interrupt generation capability

Programmable masking support

Thread safe operation by providing separate set and clear addresses for control registers

Inputs are sampled using a double flip-flop to avoid meta-stability issues
Memory Subsystem
The Cortex-M0 core uses a 128kB instruction/boot ROM along with a 128kB shared instruction and data RAM.
8.2.1
Shared Instruction and Data Memory
The Instruction and Data Memory (IDRAM1 and IDRAM2) contains instructions and data used by the ARM. The
size of IDRAM1 and IDRAM2 is 128kB that can be used for BLE subsystem as well as for the user application.
IDRAM1 contains the three 32kB and IDRAM2 contains two 16kB memories that are accessible to the ARM and
used for instruction/data storage.
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8.2.2
ROM
The ROM is used to store the boot code and BLE firmware, stack and selected user profiles. ROM contains the
128kB memory that is accessible to the ARM.
8.2.3
BLE Retention Memory
The BLE functionality requires 8kB (or more depending on the application) state, instruction and data to be
retained in memory when the processor either goes into Sleep Mode or Power Off Mode. The RAM is separated
into specific power domains to allow tradeoff in power consumption with retention memory size.
8.3
Non-volatile Memory
SAMB11 has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This nonvolatile one-time-programmable memory can be used to store customer-specific parameters, such as BLE address,
XO calibration information, TX power, crystal frequency offset, etc., as well as other software-specific configuration
parameters. The eFuse is partitioned into six 128-bit banks. The bitmap of the first bank is shown in Figure 8-2.
The purpose of the first 80 bits in bank 0 is fixed, and the remaining bits are general-purpose software dependent
bits, or reserved for future use. Since each bank and each bit can be programmed independently, this allows for
several updates of the device parameters following the initial programming, e.g. updating BLE address (this can be
done by invalidating the last programmed bank and programming a new bank). Refer to SAMB11 Programming
Guide for the eFuse programming instructions.
Figure 8-2.
SAMB11 eFuse Bit Map
128 Bits
Bank 0
Bank 1
Application
Specific
Configuration
Bank 2
Bank 3
Bank 4
Bank 5
F
BT ADDR
8
8.4
48
XO
Calibration
3
Reserved
3
HW
Config
1
BT ADDR
Used
Reserved
1
Tx Power
Calibration
HW Config
Flash Memory
SAMB11 has 256kB of Flash memory, stacked on top of the MCU+BLE System on Chip. It is accessed through the
SPI Flash controller and uses the 26MHz clock.
Flash memory features are:

256-bytes per programmable page

Uniform 4kB Sectors, 32kB & 64kB Blocks

Sector Erase (4K-byte)

Block Erase (32K or 64K-byte)

Page program up to 256 bytes <1ms

More than 100,000 erase/write cycles and more than 20-year data retention

2.3V to 3.6V supply range

1mA active current, <1μA Power-down
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9
Bluetooth Low Energy (BLE) Subsystem
The BLE subsystem implements all the critical real-time functions required for full compliance with Specification of
the Bluetooth System, v4.1, Bluetooth SIG.
It consists of a Bluetooth 4.1 baseband controller (core), radio transceiver and the Atmel Bluetooth Smart Stack,
the BLE Software Platform.
9.1
BLE Core
The baseband controller consists of modem and Medium Access Controller (MAC) and it encodes and decodes
HCI packets, constructs baseband data packages, schedules frames, manages and monitors connection status,
slot usage, data flow, routing, segmentation, and buffer control.
The core performs Link Control Layer management supporting the main BLE states, including advertising and
connection.
9.1.1
9.2
Features

Broadcaster, Central, Observer, and Peripheral

Simultaneous Master and Slave operation, connect up to eight slaves

Frequency Hopping

Advertising/Data/Control packet types

Encryption (AES-128, SHA-256)

Bit stream processing (CRC, whitening)

Operating clock 52MHz
BLE Radio
The radio consists of a fully integrated transceiver, including Low Noise Amplifier, Receive (RX) down converter,
and analog baseband processing as well as Phase Locked Loop (PLL), Transmit (TX) Power Amplifier, and
Transmit/Receive switch. At the RF front end, no external RF components on the PCB are required other than the
antenna and a matching component.
The RX sensitivity and TX output power of the radio together with the 4.1 PHY core provide a 100dB RF link
budget for superior range and link reliability.
9.2.1
Receiver Performance
Table 9-1.
SAMB11 BLE Receiver Performance
Parameter
Frequency
Minimum
Typical
2,402
Sensitivity (maximum RX gain setting)
-96
Sensitivity with on-chip DC/DC
-95
Maximum receive signal level
+5
CCI
ACI (N±1)
Maximum
Unit
2,480
MHz
dBm
12.5
0
N+2 Blocker (Image)
-22
N-2 Blocker
-38
N+3 Blocker (Adj. Image)
-35
dB
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Parameter
Minimum
Typical
N-3 Blocker
-43
N±4 or greater
-45
Intermod (N+3, N+6)
-32
OOB (2GHz<f<2.399GHz)
-15
OOB (f<2GHz)
-10
Maximum
dB
dBm
4.0 (1)
RX peak current draw
Unit
mA
At -93dBm sensitivity setting. Add 0.2mA at 3.3V for best sensitivity setting.
All measurements performed at 3.6V VBATT and 25°C, with tests following Bluetooth V4.1 standard tests.
There are two gain settings for Sensitivity, high gain (-95dBm) and low gain (-93dBm). Low gain has lower current
consumption.
9.2.2
Transmitter Performance
The transmitter has fine step power control with Pout variable in <3dB steps below 0dBm and in <0.5dB steps above
0dBm.
Table 9-2.
SAMB11 BLE Transmitter Performance
Parameter
Frequency
Minimum
Typical
2,402
Output power range
-20
0
Maximum output power
3.5
In-band Spurious (N±2)
-45
In-band Spurious (N±3)
-50
Maximum
Unit
2,480
MHz
3.5
dBm
2nd harmonic Pout
-41
3rd harmonic Pout
-41
4th harmonic Pout
-41
5th harmonic Pout
-41
Frequency deviation
±250
kHz
TX peak current draw
3.0 (1)
mA
At 0dBm TX output power.
All measurements performed at 3.6V VBATT and 25°C, with tests following Bluetooth V4.1 standard tests.
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9.3
Atmel Bluetooth SmartConnect Stack
The SAMB11 has a completely integrated Bluetooth Low Energy stack on chip, fully qualified, mature, and
Bluetooth V4.1 compliant.
Customer applications interface with the BLE protocol stack through the Atmel BLE API, which supports direct
access to the GAP, SMP, ATT, GATT client / server, and L2CAP service layer protocols in the embedded firmware.
The stack includes numerous BLE profiles for applications like:

Smart Energy

Consumer Wellness

Home Automation

Security

Proximity Detection

Entertainment

Sports and Fitness

Automotive
Together with the Atmel Studio Software Development environment, additional customer profiles can be easily
developed.
The Atmel Bluetooth SmartConnect software development kit is based on Keil and IAR™ compiler tools and
contains numerous application code examples for embedded and hosted modes.
In addition to the protocol stack, drivers for each peripheral hardware block are provided.
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10
External Interfaces
10.1
Overview
SAMB11 external interfaces include: 2xSPI Master/Slave (SPI0 and SPI1), 2xI2C Master/Slave (I2C0 and I2C1),
2xI2C Slave-only (I2C2), 2xUART (UART1 and UART2), 1xSWD, and General Purpose Input/Output (GPIO) pins.
For specific programming instructions, refer to SAMB11 Programming Guide.
Table 10-1 illustrates the different peripheral functions that are software selectable for each pin. This allows for
maximum flexibility of mapping desired interfaces on GPIO pins. MUX1 option allows for any MEGAMUX option
from Table 10-2 to be assigned to a GPIO.
Table 10-1.
SAMB11 Pin-MUX Matrix of External Interfaces
Pin Name
34
Pin #
Pull
MUX0
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
LP_GPIO_0
5
Up
GPIO 0
MEGAMUX 0
SWD CLK
TEST OUT 0
LP_GPIO_1
6
Up
GPIO 1
MEGAMUX 1
SWD IO
TEST OUT 1
LP_GPIO_2
7
Up
GPIO 2
MEGAMUX 2
UART1 RXD
SPI1 SCK
SPI0 SCK
TEST OUT 2
LP_GPIO_3
8
Up
GPIO 3
MEGAMUX 3
UART1 TXD
SPI1 MOSI
SPI0 MOSI
TEST OUT 3
LP_GPIO_4
9
Up
GPIO 4
MEGAMUX 4
UART1 CTS
SPI1 SSN
SPI0 SSN
TEST OUT 4
LP_GPIO_5
12
Up
GPIO 5
MEGAMUX 5
UART1 RTS
SPI1 MISO
SPI0 MISO
TEST OUT 5
LP_GPIO_6
13
Up
GPIO 6
MEGAMUX 6
UART2 RXD
SPI0 SCK
TEST OUT 6
LP_GPIO_7
14
Up
GPIO 7
MEGAMUX 7
UART2 TXD
SPI0 MOSI
TEST OUT 7
LP_GPIO_8
15
Up
GPIO 8
MEGAMUX 8
I2C0 SDA
I2C2 SDA
SPI0 SSN
TEST OUT 8
LP_GPIO_9
16
Up
GPIO 9
MEGAMUX 9
I2C0 SCL
I2C2 SCL
SPI0 MISO
TEST OUT 9
LP_GPIO_10
17
Up
GPIO 10
MEGAMUX 10
SPI0 SCK
TEST OUT 10
LP_GPIO_11
18
Up
GPIO 11
MEGAMUX 11
SPI0 MOSI
TEST OUT 11
LP_GPIO_12
19
Up
GPIO 12
MEGAMUX 12
SPI0 SSN
TEST OUT 12
LP_GPIO_13
20
Up
GPIO 13
MEGAMUX 13
SPi0 MISO
TEST OUT 13
LP_GPIO_14
36
Up
GPIO 14
MEGAMUX 14
UART2 CTS
I2C1 SDA
TEST OUT 14
LP_GPIO_15
37
Up
GPIO 15
MEGAMUX 15
UART2 RTS
I2C1 SCL
TEST OUT 15
LP_GPIO_16
38
Up
GPIO 16
MEGAMUX 16
LP_GPIO_17
40
Up
GPIO 17
MEGAMUX 17
LP_GPIO_18
41
Up
GPIO 18
MEGAMUX 18
LP_GPIO_19
42
Up
GPIO 19
MEGAMUX 19
LP_GPIO_20
43
Up
GPIO 20
MEGAMUX 20
LP_GPIO_22
10
Up
GPIO 22
MEGAMUX 22
LP_GPIO_23
11
Up
GPIO 23
MEGAMUX 23
AO_GPIO_0
33
Up
GPIO 31
WAKEUP
RTC CLK IN
32KHZ CLKOUT
AO_GPIO_1
34
Up
GPIO 30
WAKEUP
RTC CLK IN
32KHZ CLKOUT
AO_GPIO_2
35
Up
GPIO 29
WAKEUP
RTC CLK IN
32KHZ CLKOUT
SPI1 SSN
SPI0 SCK
TEST OUT 16
I2C2 SDA
SPI1 SCK
SPI0 MOSI
TEST OUT 17
I2C2 SCL
SPI1 MISO
SPI0 SSN
TEST OUT 18
SPI1 MOSI
SPI0 MISO
TEST OUT 19
TEST OUT 20
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Pin Name
Pin #
Pull
MUX0
GPIO_MS1
24
Up
GPIO 47
GPIO_MS2
25
Up
GPIO 46
GPIO_MS3
27
Up
GPIO 45
GPIO_MS4
28
Up
GPIO 44
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
Table 10-2 shows the various software selectable MEGAMUX options that correspond to specific peripheral
functionality. Several MEGAMUX options provides an interface to manage Wi-Fi BLE coexistence issues.
Table 10-2.
SAMB11 Software Selectable MEGAMUX Options
MUX_Sel
Function
Notes
0
UART1 RXD
1
UART1 TXD
2
UART1 CTS
3
UART1 RTS
4
UART2 RXD
5
UART2 TXD
6
UART2 CTS
7
UART2 RTS
8
I2C0 SDA
9
I2C0 SCL
10
I2C1 SDA
11
I2C1 SCL
12
PWM 1
13
PWM 2
14
PWM 3
15
PWM 4
16
LP CLOCK OUT
32kHz clock output (RC Osc or RTC XO)
17
WLAN TX ACTIVE
Coexistence: Wi-Fi is currently transmitting
18
WLAN RX ACTIVE
Coexistence: Wi-Fi is currently receiving
19
BLE TX ACTIVE
Coexistence: BLE is currently transmitting
20
BLE RX ACTIVE
Coexistence: BLE is currently receiving
21
BLE IN PROCESS
Coexistence Signal
22
BLE MBSY
Coexistence Signal
23
BLE SYNC
Coexistence Signal
24
BLE RXNTX
Coexistence Signal
25
BLE PTI 0
Coexistence: BLE Priority
26
BLE PTI 1
Coexistence: BLE Priority
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MUX_Sel
Function
Notes
27
BLE PTI 2
Coexistence: BLE Priority
28
BLE PTI 3
Coexistence: BLE Priority
29
QUAD DEC X IN A
30
QUAD DEC X IN B
31
QUAD DEC Y IN A
32
QUAD DEC Y IN B
33
QUAD DEC Z IN A
34
QUAD DEC Z IN B
An example of peripheral assignment using these MEGAMUX options is as follows:

I2C0 pin-muxed on LP_GPIO_10 and LP_GPIO_11 via MUX1 and MEGAMUX=8 and 9

I2C1 pin-muxed on LP_GPIO_0 and LP_GPIO_1 via MUX1 and MEGAMUX=10 and 11

PWM pin-muxed on LP_GPIO_16 via MUX1 and MEGAMUX=12
Another example is to illustrate the available options for pin LP_GPIO_3, depending on the pin-MUX option
selected:
10.2

MUX0: the pin will function as bit 3 of the GPIO bus and is controlled by the GPIO controller in the ARM
subsystem

MUX1: any option from the MEGAMUX table can be selected, for example it can be a quad_dec, pwm, or
any of the other functions listed in the MEGAMUX table

MUX2: the pin will function as UART1 TXD; this can be also achieved with the MUX1 option via MEGAMUX,
but the MUX2 option allows a shortcut for the recommended pinout

MUX3: this option is not used and thus defaults to the GPIO option (same as MUX0)

MUX4: the pin will function as SPI1 MOSI (this option is not available through MEGAMUX)

MUX5: the pin will function as SPI0 MOSI (this option is not available through MEGAMUX)

MUX6: the pin will function as SPI FLASH SCK (this option is not available through MEGAMUX)

MUX7: the pin will function as bit 3 of the test output bus, giving access to various debug signals
I2C Master/Slave Interface
10.2.1 Description
The SAMB11 provides I2C Interface that can be configured as Slave or Master. The I2C Interface is a two-wire
serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). The SAMB11 I2C supports I2C
bus Version 2.1 - 2000 and can operate in the following speed modes:

Standard mode (100kb/s)

Fast mode (400kb/s)

High-speed mode (3.4Mb/s)
I2C
The
is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL
line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to perform wireAND functions on the bus. The maximum number of devices on the bus is limited by only the maximum
capacitance specification of 400pF. Data is transmitted in byte packages.
For specific information, refer to the Philips Specification entitled “The I2C -Bus Specification, Ver2.1”.
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10.2.2 I2C Interface Timing
The I2C Interface timing (common to Slave and Master) is provided in Figure 10-1. The timing parameters for Slave
and Master modes are specified in Table 10-3 and Table 10-4 respectively.
SAMB11 I2C Slave Timing Diagram
Figure 10-1.
tPR
tSUDAT
tHDDAT
tBUF
tSUSTO
SDA
tHL
tLH
tWL
SCL
tLH
tHDSTA
tHL
tWH
tPR
tPR
fSCL
tSUSTA
SAMB11 I2C Slave Timing Parameters
Table 10-3.
Parameter
Symbol
Min.
Max.
Units
400
kHz
SCL Clock Frequency
fSCL
0
SCL Low Pulse Width
tWL
1.3
SCL High Pulse Width
tWH
0.6
SCL, SDA Fall Time
tHL
300
SCL, SDA Rise Time
tLH
300
START Setup Time
tSUSTA
0.6
START Hold Time
tHDSTA
0.6
SDA Setup Time
tSUDAT
100
SDA Hold Time
tHDDAT
0
40
STOP Setup time
tSUSTO
0.6
Bus Free Time Between STOP
and START
tBUF
1.3
Glitch Pulse Reject
tPR
0
Remarks
µs
ns
This is dictated by external components
µs
ns
Slave and Master Default
Master Programming Option
µs
50
ns
SAMB11 I2C Master Timing Parameters
Table 10-4.
Standard mode
Parameter
Fast mode
High-speed mode
Units
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
100
0
400
0
3400
SCL Clock Frequency
fSCL
0
SCL Low Pulse Width
tWL
4.7
1.3
0.16
SCL High Pulse Width
tWH
4
0.6
0.06
SCL Fall Time
tHLSCL
kHz
µs
300
300
10
40
ns
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Standard mode
Parameter
Fast mode
High-speed mode
Units
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
SDA Fall Time
tHLSDA
300
300
10
80
SCL Rise Time
tLHSCL
1000
300
10
40
SDA Rise Time
tLHSDA
1000
300
10
80
START Setup Time
tSUSTA
4.7
0.6
0.16
START Hold Time
tHDSTA
4
0.6
0.16
SDA Setup Time
tSUDAT
250
100
10
SDA Hold Time
tHDDAT
5
40
0
STOP Setup time
tSUSTO
4
0.6
0.16
Bus Free Time Between STOP
and START
tBUF
4.7
1.3
Glitch Pulse Reject
tPR
µs
ns
10.3
0
70
µs
50
ns
SPI Master/Slave Interface
10.3.1 Description
SAMB11 provides a Serial Peripheral Interface (SPI) that can be configured as Master or Slave. The SPI Interface
pins are mapped as shown in Table 10-5. The SPI Interface is a full-duplex slave-synchronous serial interface.
When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers between
the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is
buffered, resulting in a high impedance drive onto the serial master receive line. The SPI Slave interface responds
to a protocol that allows an external host to read or write any register in the chip as well as initiate DMA transfers.
For the details of the SPI protocol and more specific instructions, refer to SAMB11 Programming Guide.
Table 10-5.
SAMB11 SPI Interface Pin Mapping
Pin Name
38
SPI Function
SSN
Active Low Slave Select
SCK
Serial Clock
MOSI
Master Out Slave In (Data)
MISO
Master In Slave Out (Data)
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10.3.2 SPI Interface Modes
The SPI Interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock Phase
(CPHA) settings. These modes are illustrated in Table 10-6 and Figure 10-2. The red lines in Figure 10-2
correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.
Table 10-6.
Figure 10-2.
SAMB11 SPI Modes
Mode
CPOL
CPHA
0
0
0
1
0
1
2
1
0
3
1
1
SAMB11 SPI Clock Polarity and Clock Phase Timing
CPOL = 0
SCK
CPOL = 1
SSN
CPHA = 0
RXD/TXD
(MOSI/MISO)
CPHA = 1
z
1
z
2
1
3
2
4
3
5
4
6
5
7
6
8
7
z
8
z
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10.3.3 SPI Slave Timing
The SPI Slave timing is provided in Figure 10-3 and Table 10-7.
Figure 10-3.
SAMB11 SPI Slave Timing Diagram
Table 10-7.
SAMB11 SPI Slave Timing Parameters
Parameter
40
Symbol
Min.
Max.
Units
2
MHz
Clock Input Frequency
fSCK
Clock Low Pulse Width
tWL
240
Clock High Pulse Width
tWH
240
Clock Rise Time
tLH
10
Clock Fall Time
tHL
10
Input Setup Time
tISU
5
Input Hold Time
tIHD
5
Output Delay
tODLY
0
Slave Select Setup Time
tSUSSN
5
Slave Select Hold Time
tHDSSN
5
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ns
20
10.3.4 SPI Master Timing
The SPI Master Timing is provided in Figure 10-4 and Table 10-8.
Figure 10-4.
SAMB11 SPI Master Timing Diagram
fSCK
tLH
tWH
tWL
SCK
tHL
SSN,
TXD
tODLY
tISU
tIHD
RXD
Table 10-8.
SAMB11 SPI Master Timing Parameters
Parameter
Min.
Max.
Units
4
MHz
Clock Output Frequency
fSCK
Clock Low Pulse Width
tWL
120
Clock High Pulse Width
tWH
120
Clock Rise Time
tLH
5
Clock Fall Time
tHL
5
Input Setup Time
tISU
5
Input Hold Time
tIHD
5
tODLY
0
Output Delay
10.4
Symbol
ns
5
UART Interface
SAMB11 provides Universal Asynchronous Receiver/Transmitter (UART) interfaces for serial communication. The
Bluetooth subsystem has two UART interfaces: a 4-pin interface for control and data transfer. The UART interfaces
are compatible with the RS-232 standard, where SAMB11 operates as Data Terminal Equipment (DTE). The 2-pin
UART has the receive and transmit pins (RXD and TXD), and the 4-pin UART has two additional pins used for flow
control/handshaking: Request To Send (RTS) and Clear To Send (CTS).
The RTS and CTS are used for hardware flow control; they MUST be connected to the
host MCU UART and enabled for the UART interface to be functional.
The pins associated with each UART interfaces can be enabled on several alternative pins by programming their
corresponding pin-MUX control registers (see Table 10-1 and Table 10-2 for available options).
The UART features programmable baud rate generation with fractional clock division, which allows transmission
and reception at a wide variety of standard and non-standard baud rates. The Bluetooth UART input clock is
selectable between 26MHz, 13MHz, 6.5MHz, and 3.25MHz. The clock divider value is programmable as 13 integer
bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in
the maximum supported baud rate of 26MHz/8.0 = 3.25MBd.
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The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types
(odd, even, mark, or space), and with one or two stop bits. It also has RX and TX FIFOs, which ensure reliable high
speed reception and low software overhead transmission. FIFO size is 4 x 8 for both RX and TX direction. The
UART also has status registers showing the number of received characters available in the FIFO and various error
conditions, as well the ability to generate interrupts based on these status bits.
An example of UART receiving or transmitting a single packet is shown in Figure 10-5. This example shows 7-bit
data (0x45), odd parity, and two stop bits.
For more specific instructions, refer to SAMB11 Programming Guide.
Figure 10-5.
10.5
Example of UART RX or TX packet
GPIOs
30 General Purpose Input/Output (GPIO) pins total, labeled LP_GPIO, GPIO_MS, and AO_GPIO, are available to
allow for application specific functions. Each GPIO pin can be programmed as an input (the value of the pin can be
read by the host or internal processor) or as an output. The host or internal processor can program output values.
LP_GPIO are digital interface pins, GPIO_MS are mixed signal/analog interface pins and AO_GPIO is an alwayson digital interface pin that can detect interrupt signals while in deep sleep mode for wake-up purposes.
The LP_GPIO have interrupt capability, but only when in active/standby mode. In sleep mode, they are turned off to
save power consumption.
10.6
Analog to Digital Converter (ADC)
10.6.1 Overview
The SAMB11 has an integrated Successive Approximation (SAR) ADC with 11-bit resolution and variable
conversion speed up 1MS/s. The key building blocks are the capacitive DAC, comparator, and synchronous SAR
engine as shown in Figure 10-6.
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Figure 10-6.
SAMB11 SAR ADC Block Diagram
The ADC reference voltage can be either generated internally or set externally via one of the four available Mixed
Signal GPIO pins on the SAMB11.
There are two modes of operation:
A.
High resolution (11-bit): Set the reference voltage to half the supply voltage or below. In this condition the
input signal dynamic range is equal to twice the reference voltage (ENOB=10bit).
B.
Medium Resolution (10-bit): Set the reference voltage to any value below supply voltage (up to supply
voltage - 300mV) and in this condition the input dynamic range is from zero to reference voltage (ENOB =
9bit).
There are four input channels that are time multiplexed to the input of the SAR ADC.
In power saving mode, the internal reference voltage is completely off and the reference voltage is set externally.
The ADC characteristics are summarized in Table 10-9.
Table 10-9.
SAR ADC Characteristics
1ks → 1MS
Conversion rate
Selectable Resolution
10 → 11bit
Power consumption
13.5µA (at 100KS/s) (1)
With external reference.
10.6.2 Timing
The ADC timing is shown in Figure 10-7. The input signal is sampled twice, in the first sampling cycle the input
range is defined either to be above reference voltage or below it and in the second sampling instant the ADC start
its normal operation.
The ADC takes two sampling instants and N-1 conversion cycle (N=ADC resolution) and one cycle to sample the
data out. Therefore, for 11-bit resolution it takes 13 clock cycles to do one Sample conversion.
The Input clock equals N+2 the sampling clock frequency (N is the ADC resolution).
CONV signal
: Gives indication about end of conversion.
SAMPL
: The input signal is sampled when this signal is high.
RST ENG
: When High SAR Engine is in reset mode (SAR engine output is set to mid-scale).
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Figure 10-7.
SAR ADC Timing
10.6.3 Performance
Table 10-10.
Static Performance of SAR ADC
Parameter
Condition
Input voltage range
Min.
Typ.
0
Resolution
11
Sample rate
100
Max.
Unit
VBAT
V
bits
1000
KSPS
Input offset
Internal VREF
-10
+10
mV
Gain error
Internal VREF
-4
+4
%
DNL
100KSPS. Internal VREF=1.6V.
Same result for external VREF.
-0.75
+1.75
INL
100KSPS. Internal VREF=1.6V.
Same result for external VREF.
THD
1kHz sine input at 100KSPS
73
SINAD
1kHz sine input at 100KSPS
62.5
SFDR
1kHz sine input at 100KSPS
73.7
LSB
-2
Conversion time
Current consumption
+2.5
dB
13
Using external VREF, at 100KSPS
13.5
Using internal VREF, at 100KSPS
25.0
Using external VREF, at 1MSPS
94
Using internal VREF, at 1MSPS
150
Using internal VREF, during VBAT
monitoring
100
Using internal VREF, during temperature
monitoring
50
cycles
µA
1.026 (1)
Mean value using VBAT=2.5V
V
Internal reference voltage
10.5
Standard deviation across parts
Without calibration
-55
+55
With offset and gain calibration
-17
+17
VBAT sensor accuracy
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mV
Parameter
Condition
Min.
-9
Without calibration
Typ.
Max.
Unit
+9
0C
Temperature sensor accuracy
-4
With offset calibration
+4
Effective VREF is 2xInternal Reference Voltage.
0
𝑇𝑐 = 25 𝐶 𝑉𝐵𝐴𝑇 = 3.0 𝑉, 𝑢𝑛𝑙𝑒𝑠𝑠 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒 𝑛𝑜𝑡𝑒𝑑
Figure 10-8.
INL of SAR ADC
INL 100KS/s 3V internal reference
3
INL (LSB)
2
1
0
-1
0
500
1000
1500
2000
-2
-3
Output Code
Figure 10-9.
DNL of SAR ADC
DNL 100KS/s 3V internal reference
2
INL (LSB)
1.5
1
0.5
0
-0.5 0
500
1000
1500
2000
-1
-1.5
Output Code
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Figure 10-10. Sensor ADC Dynamic Measurement with Sinusoidal Input
Notes:
1.
2.
250C, 3.6V VBAT, and 100kS/s
Input Signal: 1kHz sine wave, 3Vp-p amplitude
SNDR = 62.6dB
SFDR = 73.7dB
THD = 73.0db
Figure 10-11. Sensor ADC Dynamic Performance Summary at 100KSPS
Dynamic performance summary
74
SNR
SNDR
SFDR
THD
72
70
68
dB
66
64
62
60
58
56
54
46
0
0.5
1
1.5
2
input signal frequency in Hz
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2.5
3
4
x 10
10.7
Software Programmable Timer and Pulse Width Modulator
SAMB11 contains four individually configurable pulse width modulator (PWM) blocks to provide external control
voltages. The base frequency of the PWM block (fPWM_base) is derived from the XO clock (26MHz) or the RC
oscillator followed by a programmable divider.
The frequency of each PWM pulse (fPWM) is programmable in steps according to the following relationship:
𝑓𝑃𝑊𝑀 =
𝑓𝑃𝑊𝑀_𝑏𝑎𝑠𝑒
64 ∗ 2𝑖
𝑖 = 0,1,2, … , 8
The duty cycle of each PWM signal is configurable with 10-bit resolution (minimum duty cycle is 1/1024 and
maximum is 1023/1024).
𝑓𝑃𝑊𝑀𝑏𝑎𝑠𝑒 can be selected to have different values according to the following table. Minimum and maximum
frequencies supported for each clock selection are listed in the table as well.
Table 10-11.
10.8
fPWM Range for Different fPWM Base Frequencies
𝒇𝑷𝑾𝑴𝒃𝒂𝒔𝒆
fPWM max.
fPWM min.
26MHz
406.25kHz
6.347kHz
13MHz
203.125kHz
3.173kHz
6.5MHz
101.562kHz
1.586kHz
3.25MHz
50.781kHz
793.25Hz
Clock Output
SAMB11 has an ability to output a clock. The clock can be output to any GPIO pin via the test MUX. Note that this
feature requires that the ARM and BLE power domains stay on. If BLE is not used, the clocks to the BLE core are
gated off, resulting in small leakage. The following two methods can be used to output a clock.
10.8.1 Variable Frequency Clock Output Using Fractional Divider
SAMB11 can output the variable frequency ADC clock using a fractional divider of the 26MHz oscillator. This clock
needs to be enabled using bit 10 of the lpmcu_clock_enables_1 register. The clock frequency can be controlled by
the divider ratio using the sens_adc_clk_ctrl register (12-bits integer part, 8-bit fractional part).The division ratio can
vary from 2 to 4096 delivering output frequency between 6.35kHz to 13MHz. This is a digital divider with pulse
swallowing implementation so the clock edges may not be at exact intervals for the fractional ratios. However, it is
exact for integer division ratios.
10.8.2 Fixed Frequency Clock Output
SAMB11 can output the following fixed-frequency clocks:

52MHz derived from XO

26MHz derived from XO

2MHz derived from the 2MHz RC Osc.

31.25kHz derived from the 2MHz RC Osc.

32.768kHz derived from the RTC XO

26MHz derived from 26MHz RC Osc.

6.5MHz derived from XO

3.25MHz derived from 26MHz RC Osc.
For clocks 26MHz and above ensure that external pad load on the board is minimized to get a clean waveform.
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10.9
Three-axis Quadrature Decoder
SAMB11 has a three-axis Quadrature decoder (X, Y, and Z) that can determine the direction and speed of
movement on three axes, requiring in total six GPIO pins to interface with the sensors. The sensors are expected
to provide pulse trains as inputs to the quadrature decoder.
Each axis channel input will have two pulses with ±90 degrees phase shift depending on the direction of
movement. The decoder counts the edges of the two waveforms to determine the speed and uses the phase
relationship between the two inputs to determine the direction of motion.
The decoder is configured to interrupt ARM based on independent thresholds for each direction. Each quadrature
clock counter (X, Y, and Z) is an unsigned 16-bit counter and the system clock uses a programmable sampling
clock ranging from 26MHz, 13, 6.5, to 3.25MHz.
If wakeup is desired from threshold detection on an axis input, the always-on GPIO needs to be used.
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R1
C4
1.8pF
R3
DNI
LP_MS1
LP_MS2
3nH
C8
Y1
26MHz
C7
C5
DNI
5.6pF
5.6pF
An external
32.768KHz clock may
be used instead of
a cry stal. Signal must
be 1.2V max.
L4
0
Antenna Matching
Network. Place
right next to antenna
R2
DNI
ANTENNA
Place C17 as close
as possible to pin4.
Place C9 as close
as possible to pin 2.
Place C10 next to pin 1.
Place C15 next to pin 48.
C9 0.1uF
3.9pF
45
44
30
31
24
25
3
46
47
SAMB11
XO_N
XO_P
RTC_CLKP
RTC_CLKN
GPIO_MS1
GPIO_MS2
RFIO
TPP
TPN
U1
FB1
BLM03AG121SN1
2
32.768KHz
Y2
C6
1
C15 0.1uF
1.0uF
C17
VDD
C11 0.1uF
0
C10 0.1uF
2
1
4
48
VDDRF
VDD_VCO
VDD_AMS
VDD_SXDIG
LP_GPIO_22
LP_GPIO_23
10
11
FB2
VBAT
C12
R4
VDDIO
39
VSS
49
BLM03AG121SN1
1
2
2.2uF
6.3V
22
VBat_buck
0.01uF
1.0uF
LP_LDO_OUT_1P2
29
C20
C13
10uF
4V
C1
32
AO_GPIO_0
AO_GPIO_1
AO_GPIO_2
33
34
35
23
VDDC_PD4
CHIP_EN
GPIO_MS4
GPIO_MS3
LP_GPIO_20
LP_GPIO_19
LP_GPIO_18
LP_GPIO_17
LP_GPIO_16
LP_GPIO_15
LP_GPIO_14
LP_GPIO_13
LP_GPIO_12
LP_GPIO_11
LP_GPIO_10
LP_GPIO_9
LP_GPIO_8
LP_GPIO_7
LP_GPIO_6
LP_GPIO_5
LP_GPIO_4
LP_GPIO_3
LP_GPIO_2
LP_GPIO_1
LP_GPIO_0
VSW
26
28
27
43
42
41
40
38
37
36
20
19
18
17
16
15
14
13
12
9
8
7
6
5
21 L5
C1 & FB2 Required
only when using a
Li coin cell battery .
Place C1 next to
the battery .
SWDIO
SWCLK
VDDIO
9.1nH L6
Wake
LP_MS4
LP_MS3
If Wake f unction is
not used, connect
AO_GPIO_0 to ground
C14
LP_GPIO_20
LP_GPIO_19
4.7uF
LP_GPIO_18
6.3V
LP_GPIO_17
LP_GPIO_16
LP_GPIO_15
LP_GPIO_14
LP_GPIO_13
LP_GPIO_12
LP_GPIO_11
LP_GPIO_10
LP_GPIO_9
LP_GPIO_8
LP_GPIO_7
LP_GPIO_6
LP_GPIO_5
LP_GPIO_4
LP_GPIO_3
LP_GPIO_2
Test Point
Test Points or
Test Point header f or access
to debug pins.
4.7uH
Figure 11-1.
A0_TEST_MODE
11
Reference Design
SAMB11 – Reference Schematic.
LP_GPIO_23
LP_GPIO_22
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12
Bill of Material (BOM)
Figure 12-1.
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13
Electrical Characteristics
13.1
Absolute Maximum Ratings
Table 13-1.
Symbol
SAMB11 Absolute Maximum Ratings
Characteristic
Minimum
Maximum
VDDIO
I/O Supply Voltage
-0.3
5.0
VBATT
Battery Supply Voltage
-0.3
5.0
VIN(1)
Digital Input Voltage
-0.3
VDDIO
VAIN(2)
Analog Input Voltage
-0.3
1.5
VESDHBM(3)
ESD Human Body Model
TA
Storage Temperature
-1000, -2000(see notes below)
13.2
V
+1000, +2000(see notes below)
-65
150
Junction Temperature
2.
3.
Unit
oC
125
VIN corresponds to all the digital pins.
VAIN corresponds to all the analog pins.
For VESDHBM, each pin is classified as Class 1, or Class 2, or both:

The Class 1 pins include all the pins (both analog and digital)

The Class 2 pins include all digital pins only

VESDHBM is ±1kV for Class1 pins. VESDHBM is ±2kV for Class2 pins
Recommended Operating Conditions
Table 13-2.
Symbol
VDDIO
VBATT
SAMB11 Recommended Operating Conditions
Characteristic
I/O Supply Voltage (1)
Battery Supply Voltage
(1)
Operating Temperature
Minimum
Typical
Maximum
2.3
3
4.3
2.3
3
4.3
Units
V
-40
85
oC
VBATT must not be less than VDDIO.
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13.3
DC Characteristics
Table 13-3 provides the DC characteristics for the SAMB11 digital pads.
Table 13-3.
VDDIO
Condition
SAMB11 DC Electrical Characteristics
Characteristic
Minimum
Typical
Maximum
Input Low Voltage VIL
-0.30
0.63
Input High Voltage VIH
VDDIO-0.60
VDDIO+0.30
Unit
VDDIOM
Output Low Voltage VOL
Output High Voltage VOH
0.45
VDDIO-0.50
Input Low Voltage VIL
-0.30
0.65
Input High Voltage VIH
VDDIO-0.60
VDDIO+0.30
(up to 3.60)
VDDIOH
Output Low Voltage VOL
Output High Voltage VOH
V
0.45
VDDIO-0.50
Output Loading
20
Digital Input Load
6
All
pF
VDDIOM
Pad drive strength
(regular pads) (1)
3.4
6.6
VDDIOH
Pad drive strength
(regular pads) (1)
10.5
14
VDDIOM
Pad drive strength
(high-drive pads) (1)
6.8
13.2
VDDIOH
Pad drive strength
(high-drive pads) (1)
21
28
mA
The following are high-drive pads: GPIO_8, GPIO_9; all other pads are regular.
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14
Errata
Issue:
In the ATSAMB11 Datasheet, the measured advertisement current for the cases listed in
Table 6-3 will be higher than what is reported.
SDK5.0 does not resemble the same conditions where Table 6-3 has been measured.
For example:
The power and timing parameters in the SDK5.0 release have not been fully optimized to
their final values.
IDRAM1 and IDRAM2 are always enabled/retained for ROM patches and application
development.
SDK5.0 enables clocks to different peripheral blocks to allow easier application
development.
Continuous access to the SWD debug interface is needed. Therefore, debug clocks cannot
be turned OFF.
A small sample measurement has been performed they show the following results:
Measurement condition:

1-sec adverting interval

37 byte advertising payload

Connectable beacon

Advertising on three channels (37, 38, 39)

VBAT and VDDIO are set to 3.3V
Average advertising current: 13.65µA
Average sleep current between beacons: 2.00µA
With VBAT set to 3.6V, the average advertising current under the same conditions is 12.67µA.
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15
Document Revision History
Doc Rev.
Date
Comments
1.
2.
42426C
02/2016
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Updated current numbers in the feature list.
Updated DC/DC Converter data ion section 6.2 and Table 6-1 and provided efficiency
graph in Figure 6-2.
Updated current numbers and added comments in Table 6-3.
Updated advertising current chart in Figure 6-3.
Revised Notes in Section 6.5, updated Figure 6-5 and Figure 6-6.
New figure for Clock Architecture in Figure 7-1.
Revised values in Table 7-1.
Added new figures in Figure 7-2 and Figure 7-3.
Updated capacitance value in section 7.2.
Updated voltage value in Table 7-3.
Added table for 26MHz on-chip programming in Table 7-4.
Updated capacitance value and text in section 7.3.1.
Added 32kHz RC Oscillator performance charts in Section 7.3.
Revised and added more detailed data to Section 8.1.
Updated eFuse and Flash information Sections 8.3, 8.4, and Figure 8-2.
Updated Receiver performance numbers and comments in Table 9-1.
Updated Transmitter performance numbers and comments in Table 9-2.
Added notice about UART Flow Control in Section 10.4.
19. Replaced the whole ADC performance Table 10-10.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
54
Revised values in SPI Slave timing in Table 10-7.
Revised values on SPI Master timing in Table 10-8.
Updated ADC power consumption and added comment in Table 10-9.
Replaced ADC performance charts: Figure 10-8 and Figure 10-9.
Added new ADC performance charts: Figure 10-10 and Figure 10-11.
Added fpwm range table in Table 10-11 for the software Programmable times.
Revised reference schematics in Section 11.
Revised Table 13-1 showing more Pad drive strength.
Added section 14 Errata.
Several minor corrections in the text and according to the template.
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Doc Rev.
Date
Comments
42426B
07/2015
1. Updated feature list (peripherals, clock, and power bullets).
2. Updated pinout information in Section 4.
3. Updated power architecture drawing in (Figure 6-1).
4. Added DC/DC converter description (Section 6.2).
5. Updated power consumption numbers and description (Section 6.3).
6. Minor correction in power-up sequence (Section 6.4).
7. Minor correction in POR and BOD description (Section 6.5).
8. Updated clocking description, figures, charts, and numbers (Section 6.5).
9. Updated eFuse map (Figure 8-2).
10. Updated receiver and transmitter performance numbers (Table 9-1 and Table 9-2).
11. Updated pin MUX description and tables (Section 10.1).
12. Merged I2C master and slave into one section (Section 10.2).
13. Added SPI master (Section 10.3), updated description and fixed typos in timing.
14. Removed SPI Flash from the document.
15. Updated ADC performance numbers and added figures (Section 10.6).
16. Updated PWM numbers and added table (Section 10.7).
17. Added Clock Output section (Section 10.8).
18. Updated max VBATT and VDDIO voltage and added a note on VBATT (Section 13.2).
19. Added pad drive strength numbers (Table 13-3).
20. Miscellaneous minor updates, corrections, and formatting changes throughout the document.
42426A
03/2015
Initial document release.
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