Atmel BTLC1000-MR110CA BLE Module DATASHEET Description The BTLC1000-MR110CA is an ultra-low power Bluetooth® SMART (BLE 4.1) module with Integrated Transceiver, Modem, MAC, PA, TR Switch, and Power Management Unit (PMU). It can be used as a Bluetooth Low Energy link controller or data pump with external host MCU. The qualified Bluetooth® Smart protocol stack is stored in dedicated ROM, the firmware includes L2CAP service layer protocols, Security Manager, Attribute protocol (ATT), Generic Attribute Profile (GATT) and the Generic Access Profile (GAP). Additionally, application profiles such as Proximity, Thermometer, Heart Rate, Blood Pressure and many others are supported and included in the protocol stack. The module contains all circuitry required including a ceramic high gain antenna, 26MHz crystal and PMU circuitry. The customer simply needs to place the module on his board and provide power and a 32 KHz Real Time Clock or crystal. Features Complies with Bluetooth V4.1, ETSI EN 300 328 and EN 300 440 Class 2, FCC CFR47 Part 15, ARIB STD-T66, and TELEC Bluetooth Certification o QD ID Controller (see declaration D028678) o QD ID Host (see declaration D028679 2.4GHz transceiver and Modem o -95dBm/ -93dBm programmable receiver sensitivity o -20 to +3.5dBm programmable TX output power o Integrated T/R switch o Single wire antenna connection ARM Cortex-M0 32-bit processor o Single wire Debug (SWD) interface o 4-channel DMA controller o Brown out detector and Power On Reset o Watch Dog Timer Memory o 128kB embedded RAM (96kB available for application) o 128kB embedded ROM Hardware Security Accelerators o AES-128 o SHA-256 Peripherals o 12 digital and 1 wake-up GPIO o 2 Mixed Signal GPIOs o Programmable 96kΩ pull-up or pull-down resistor for each GPIO o Retention capable GPIO pads o 1x SPI (Master/Slave) Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 2 o 2x I2C (Master/Slave) o 2x UART o 1x SPI Flash o 3-Axis quadrature decoder o 4x Pulse Width Modulation (PWM), 3 General Purpose Timers and 1 Wake up Timer o 2 channel 11-bit ADC Clock o Integrated 26MHz oscillator o 26MHz crystal oscillator o Fully integrated sleep oscillator o 32kHz RTC crystal oscillator Ultra Low power o Less than 1.15uA (8K RAM retention and RTC running) o 3.0mA peak TX current (VBAT=3.6V, 0dBm TX power) o 4.2mA peak RX current (VBAT=3.6V, -95dBm sensitivity) o Very low average advertisement current (dependent on advertisement interval) Integrated Power management o 1.8-4.3V input range for PMU o 1.62-4.3V input range for I/O o Fully integrated Buck DC-DC converter 2BTLC1000-MR110CA [DATA SHEET] Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 Table of Contents Description .......................................................................................................................... 1 Features .............................................................................................................................. 1 1 Ordering Information .................................................................................................... 5 2 Package Information ..................................................................................................... 5 3 Block Diagram ............................................................................................................... 6 4 Pin out Information ....................................................................................................... 7 4.1 4.2 4.3 5 Pin Assignment ....................................................................................................................................... 7 Pin Description ........................................................................................................................................ 8 Module Outline Drawing ........................................................................................................................ 10 Electrical Specifications ............................................................................................. 11 5.1 5.2 5.3 5.4 Absolute Maximum Ratings .................................................................................................................. 11 Recommended Operating Conditions ................................................................................................... 12 Restrictions for Power States ................................................................................................................ 12 Power Sequences ................................................................................................................................. 13 5.4.1 Power-up Sequence ..................................................................................................................... 13 5.4.2 Power-down Sequence................................................................................................................. 13 5.2 Digital I/O Pin Behavior During Power-Up Sequences .......................................................................... 14 5.5 RTC Pins............................................................................................................................................... 16 6 Characteristics ............................................................................................................ 17 6.1 6.2 6.3 Device States ........................................................................................................................................ 17 Receiver Performance .......................................................................................................................... 17 Transmitter Performance ...................................................................................................................... 18 7 Module Schematic ...................................................................................................... 19 8 Module Bill Of Materials ............................................................................................. 20 9 Application Schematic................................................................................................ 21 10 Placement and Routing Guidelines ........................................................................... 23 10.1 Power and Ground ................................................................................................................................ 23 11 Interferers .................................................................................................................... 23 12 Reference Documentation & Support ........................................................................ 24 12.1 Reference Documents .......................................................................................................................... 24 13 Certifications ............................................................................................................... 25 13.1 Agency Compliance .............................................................................................................................. 25 14 Errata ........................................................................................................................... 26 15 Revision History.......................................................................................................... 27 3 BTLC1000-MR110CA [DATA SHEET] Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 3 3 List of Figures Figure 1: Block Diagram ........................................................................................................................................................... 6 Figure 2: Top View .................................................................................................................................................................... 7 Figure 3: Module Dimensions (millimeters) ............................................................................................................................ 10 Figure 4: ATBTLC1000 Power-up Sequence ......................................................................................................................... 13 Figure 5: ATBTLC1000 Power-down Sequence..................................................................................................................... 14 Figure 7 : Module Schematic .................................................................................................................................................. 19 Figure 8: Module Bill Of Materials ........................................................................................................................................... 20 Figure 9: Reference Schematic Including 32.768KHz Crystal ................................................................................................ 21 Figure 10: Reference Schematic Without 32.768KHz Crystal ................................................................................................ 22 4 4BTLC1000-MR110CA [DATA SHEET] Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 1 Ordering Information Ordering Code Package Description ATBTLC1000-MR110CA 22 X 15mm Chip Antenna 2 Package Information Table 2-1. Parameter Package Size Pad Count ATBTLC1000-MR110 module Information(1) Value Units 12.700 X 20.152 Tolerance mm 24 Total Thickness 2.0874 Pad Pitch .9002 Pad Width .500 mm Exposed Pad size Note: 5 4.4 x 4.4 1. For details, see Package Drawing in section 4. BTLC1000-MR110CA [DATA SHEET] Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 5 5 3 Block Diagram Figure 1 shows the block diagram of the BTLC1000-MR110CA module. Figure 1: Block Diagram VDDIO VBAT Antenna Chip_En AO_GPIO_0 LP_GPIO BTLC1000 BLE 4.1 SOC GPIO_MS1/MS2 26 MHz From 32.768kHz crystal or clock 6 6BTLC1000-MR110CA [DATA SHEET] Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 Matching 4 Pin out Information 4.1 Pin Assignment Figure 2 shows the module top view and pin numbering. Figure 2: Top View 7 BTLC1000-MR110CA [DATA SHEET] Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 7 7 4.2 Pin Description Table 4-1 provides details for the module pin assignments and descriptions. Table 4-1. NO Name Pin Description Type Description Notes 1 Ground Power Ground Pin. Connect to PCB ground 2 LP_GPIO_0 I/O Used for Single Wire Debug Clock. Debug interface pin. Connect to a header or test point. 3 LP_GPIO_1 I/O Used for Single Wire Debug Data. Debug interface pin. Connect to a header or test point 4 LP_GPIO_2 I/O General Purpose I/O. Default function is Host UART RxD. 5 LP_GPIO_3 I/O General Purpose I/O. Default function is Host UART TxD. 6 VBAT Power Power Supply Pin for the on chip Power Management Unit (PMU). Connect to a 1.8V – 4.3V power supply. 7 LP_GPIO_8 I/O General Purpose I/O. Default function is Host UART CTS 8 LP_GPIO_9 I/O General Purpose I/O. Default function is Host UART RTS 9 Ground Power Ground Pin. Connect to PCB ground 10 LP_GPIO_10 I/O General Purpose I/O. Default function is SPI_SCK 11 LP_GPIO_11 I/O General Purpose I/O. Default function is SPI_MOSI 12 LP_GPIO_12 I/O General Purpose I/O. Default function is SPI_SSN 13 Ground Power Ground Pin. Connect to PCB ground 14 LP_GPIO_13 I/O General Purpose I/O. Default function is SPI_MISO 15 GPIO_MS1 I/O Mixed Signal I/O. Configurable to be a GPIO or ADC input. 16 GPIO_MS2 I/O Mixed Signal I/O. Configurable to be a GPIO or ADC input. 17 Chip_En Control Chip Enable. A high level turns on the On Chip PMU and enables operation of the device. Low disables the device and turns off the PMU. Control this pin with a host GPIO. If not used, tie to VDDIO. 18 RTC_CLKP Positive Pin for Real Time Clock Crystal. Connect to a 32.768KHz Crystal 8 8BTLC1000-MR110CA [DATA SHEET] Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 NO Name Type Description Notes 19 RTC_CLKN 20 AO_GPIO_0 I/O Always on GPIO_0. Used to wake up the device from sleep. 21 LP_GPIO_16 I/O General Purpose I/O. Default function is Debug UART RxD 22 VDDIO Power Power Supply Pin for the I/O pins. Connect to a 1.62V – 4.3V power supply. I/O supply can be less than or equal to VBAT 23 LP_GPIO_18 I/O General Purpose I/O. Default function is Debug UART TxD 24 Ground Power Ground Pin. Connect to PCB ground 25 Paddle Power Center Ground Paddle 9 Negative Pin for Real Time Clock Crystal. Connect to a 32.768KHz Crystal Connect to inner PCB ground plane with an array of vias. BTLC1000-MR110CA [DATA SHEET] Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 9 9 4.3 Module Outline Drawing Figure 3 shows the view of the module and the module dimensions. All dimensions are in mm. Figure 3: Module Dimensions (millimeters) 10 1BTLC1000-MR110CA [DATA SHEET] 0 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 5 Electrical Specifications 5.1 Absolute Maximum Ratings This section describes the minimum and maximum ratings the module can tolerate. Table 5-1. Symbol BTLC1000-MR110CA Absolute Maximum Ratings Characteristic Min Max Unit VDDIO I/O Supply Voltage -0.3 4.6 V VBAT Battery Supply Voltage -0.3 5.0 V VIN(1) Digital Input Voltage -0.3 VDDIO V VAIN(2) Analog Input Voltage -0.3 1.5 V VESDHBM(3) ESD Human Body Model -1000, -2000 (see notes below) +1000, +2000 (see notes below) V TA Storage Temperature -65 150 oC 125 oC Junction Temperature Notes: 1. VIN corresponds to all the digital pins 2. VAIN corresponds to the following analog pins: VDDRF_RX, VDDAMS, RFIO, XO_N, XO_P, VDD_SXDIG, VDD_VCO 3. For VESDHBM, each pin is classified as Class 1, or Class 2, or both: o The Class 1 pins include all the pins (both analog and digital) o The Class 2 pins include all digital pins only o VESDHBM is +/-1kV for Class1 pins. VESDHBM is +/-2kV for Class2 pins. 1 1 BTLC1000-MR110CA [DATA SHEET] 11 1 1 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 5.2 Recommended Operating Conditions Table 5-2. BTLC1000-MR110CA Recommended Operating Conditions Symbol Characteristic Min Typ Max Units VDDIO I/O Supply Voltage Low Range 1.62 1.80 4.3 V VBAT Battery Supply Voltage 1.8(note 1) 3.6 4.3 V Operating Temperature -40 85 oC Notes: 1. VBAT supply must be greater than or equal to VDDIO 5.3 Restrictions for Power States When VDDIO is off (either disconnected or at ground potential), a voltage must not be applied to the device pins. This is because each pin contains an ESD diode from the pin to the VDDIO supply. This diode will turn on when a voltage higher than one diode-drop is supplied to the pin. This in turn will try to power up the part through the VDDIO supply. If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be on. Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than 0.3V below ground to any pin. 12 1BTLC1000-MR110CA [DATA SHEET] 2 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 5.4 Power Sequences Describes that sequence and parameters for powering up and down the device. 5.4.1 Power-up Sequence The power-up sequence for BTLC1000 is shown in 0. The timing parameters are provided in Table 5-3. Figure 4: ATBTLC1000 Power-up Sequence VBATT t BIO VDDIO t IOCE CHIP_EN t SCS 32kHz RC Osc Table 5-3. ATBTLC1000 Power-up Sequence Timing Parameter Min. tBIO 0 Max. Units Description VBATT rise to VDDIO rise VBATT and VDDIO can rise simultaneously or can be tied together. VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating. ms tIOCE 0 tSCS 10 5.4.2 µs Notes CHIP_EN rise to 31.25kHz (2MHz/64) oscillator stabilizing Power-down Sequence The power-0down sequence for BTLC1000 is shown in 05. The timing parameters are provided in Table 5-4 1 3 BTLC1000-MR110CA [DATA SHEET] 13 1 3 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 Figure 5: ATBTLC1000 Power-down Sequence CHIP_EN t IOCE VDDIO t BIO VBATT 32kHz RC Osc Table 5-4. Parameter Min. tIOCE 0 ATBTLC1000 Power-down Sequence Timing Max. Units Description Notes CHIP_EN fall to VDDIO fall CHIP_EN must fall before VDDIO. CHIP_EN must be driven high or low, not left floating. VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. ms tBIO 5.2 0 Digital I/O Pin Behavior During Power-Up Sequences Table 5-6 describes the digital IO Pin states corresponding to device power modes. Table 5-5. Digital I/O Pin Behavior in Different Device States 14 Pull Up/Down VDDIO CHIP_EN RESETN Output Driver Input Driver Resistor (96 kΩ) Power_Down: core supply off High Low Low Disabled (Hi-Z) Disabled Disabled Power-On Reset: core supply on High High Low Disabled (Hi-Z) Disabled Enabled Power-On Default: core supply on, device out of reset but not programmed yet High High High Disabled (Hi-Z) Enabled Enabled Device State 1BTLC1000-MR110CA [DATA SHEET] 4 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 On_Doze/ On_Transmit/ On_Receive: core supply on, device programmed by firmware 1 5 High High High Programmed by firmware for each pin: Enabled or Disabled Opposite of Output Driver state Programmed by firmware for each pin: Enabled or Disabled BTLC1000-MR110CA [DATA SHEET] 15 1 5 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 5.5 RTC Pins Module pins 18 and 19 (RTC_CLKP and RTC_CLKN, respectively) are used for a 32.768KHz crystal. To be compliant with the BLE specifications for connection events, the frequency accuracy of this clock has to be within +/- 500ppm. Because of the low drift of the 32.768kHz crystal oscillator clock and the fact that it can be accurately calibrated (+/-25ppm), the power consumption of the BTLC1000 can be minimized by leaving radio circuits in low power sleep mode for as long as possible until they need to wake up for the next connection timed event. The block diagram in 2(a) shows how the internal low frequency Crystal Oscillator (XO) is connected to the external crystal. Typically, the crystal should be chosen to have a load capacitance of 7pF to minimize the oscillator current. Alternatively, if an external 32.768KHz clock is available, it can be used to drive the RTC_CLKP pin instead of using a crystal. The XO has 6pF internal capacitance on the RTC_CLKP pin. To bypass the crystal oscillator an external signal capable of driving 6pF can be applied to the RTC_CLK_P terminal as shown in Figure 6(b). This signal must be 1.2V maximum. RTC_CLK_N must be left unconnected when driving an external source into RTC_CLK_P. Figure 6: BTLC1000 Connections to Low Frequency Crystal Oscillator (a) Crystal oscillator is used, (b) crystal oscillator is bypassed Table 5-6. BTLC1000-MR110CA 32.768KHz External Clock Specification Parameter Min Oscillation frequency VinH 16 Typ Max 32.768 0.7 1BTLC1000-MR110CA [DATA SHEET] 6 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 Unit KHz 1.2 V Comments Must be able to drive 6pF load @ desired frequency High level input voltage Parameter Min VinL Stability – Temperature Typ Max Unit 0 0.2 V -250 +250 ppm Comments Low level input voltage 6 Characteristics 6.1 Device States Table 6-1. Device State BTLC1000-MR110CA Device States CHIP_EN VDDIO BLE_On_Transmit On On 3.0mA 0.0uA VBAT = 3.6V @ 0dBm Pout BLE_On_Receive On On 4.2mA 0.0uA VBAT = 3.6V Ultra Low Power On On 1.25uA 0.0uA With 8KB retention memory, BLE Timer & RTC enabled Power_Down GND On <0.05uA <0.05uA Chip Enable Off IVBAT (typical) Remark IVDDIO (typical) PLEASE ADD same Advertising current curves plot as BTLC1000 QFn DS stating the same conditions VBAT, POUT, full advertising payload 6.2 Receiver Performance Table 6-2. BTLC1000-MR110CA Receiver Performance Parameter Frequency Unit MHz Minimum Typical 2,402 Maximum 2,480 Sensitivity ( max RX Gain setting) dBm -95 Maximum Receive Signal Level dBm 0 CCI dB 13 ACI (N±1) dB 0 1 7 BTLC1000-MR110CA [DATA SHEET] 17 1 7 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 Parameter Unit Minimum Typical N+2 Blocker (Image) dB -20 N-2 Blocker dB -30 N+3 Blocker (Adj. Image) dB -32 N-3 Blocker dB -44 N±4 or greater dB Intermod (N+3, N+6) dBm -33 OOB (2GHz<f<2.399GHz) dBm -15 OOB (f<2GHz) dBm -10 Maximum -45 Note 1: Expected values for production silicon All measurements performed at 3.6V VBAT and 25C, with tests following Bluetooth V4.1 standard tests 6.3 Transmitter Performance Table 6-3. BTLC1000-MR110CA Transmitter Performance Parameter Unit Minimum Frequency MHz 2,402 2,480 Output Power Range dBm -20 3.5 Minimum Output Power Typical Maximum -55 In-band Spurious (N±2) dBm -40 In-band Spurious (N±3) dBm -50 2nd Harmonic Pout dBm -45 Frequency Dev kHz 250 All measurements performed at 3.6V VBAT and 25C, with tests following Bluetooth V4.1 standard tests 18 1BTLC1000-MR110CA [DATA SHEET] 8 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 7 Module Schematic Figure8 shows the module schematic. Figure 7 : Module Schematic 1 9 BTLC1000-MR110CA [DATA SHEET] 19 1 9 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 8 Module Bill Of Materials Figure 8 defines the module Bill of Materials. Figure 8: Module Bill of Materials 20 2BTLC1000-MR110CA [DATA SHEET] 0 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 9 Application Schematic The BTLC1000-MR110 module is fully self-contained. To use the module, just provide VBAT and VDDIO supplies. shows a typical design using the BTLC1000-MR110 module. The schematic shows several host interfaces: UART with Flow Control (4 wire) and SPI as well as an input to the ADC on the GPIO_MS2 pin. A user can choose the interface(s) required for their application. If a 32.768KHz Real Time Clock is not available in the system, a 32.768KHz crystal can be used. shows a design using a crystal for the Real Time Clock. The crystal should be specified with a load capacitance, CL=7pF and a total frequency error of 200ppm. Figure 9: Application Schematic Including 32.768KHz Crystal 2 1 BTLC1000-MR110CA [DATA SHEET] 21 2 1 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 Figure 10: Application Schematic Without 32.768KHz Crystal 22 2BTLC1000-MR110CA [DATA SHEET] 2 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 10 Placement and Routing Guidelines It is critical to follow the recommendations listed below to achieve the best RF performance: The board should have a solid ground plane. The center ground pad of the device must be solidly connected to the ground plane by using a 3 x 3 grid of vias. Each ground pin of the module should have a ground via placed either in the pad or right next to the pad going down to the ground plane. When the module is placed on the motherboard, a provision for the antenna must be made. There should be nothing under the portion of the module which contains the antenna. This means the antenna should not be placed directly on top of the motherboard PCB. This can be accomplished by, for example, placing the module at the edge of the board such that the module edge with the antenna extends beyond the main board edge by 6.5mm. Alternatively, a cut out in the motherboard can be provided under the antenna. The cutout should be at least 22mm x 6.5mm. Ground vias spaced 2.5mm apart should be placed all around the perimeter of the cutout. No large components should be placed near the antenna. Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking. Do not enclose the antenna within a metal shield. Keep any components which may radiate noise or signals within the 2.4GHz – 2.5GHz frequency band far away from the antenna or better yet, shield those components. Any noise radiated from the main board in this frequency band will degrade the sensitivity of the module. 10.1 Power and Ground Dedicate one layer as a ground plane. Make sure that this ground plane does not get broken up by routes. Power can route on all layers except the ground layer. Power supply routes should be heavy copper fill planes to insure the lowest possible inductance. The power pins of the module should have a via directly to the power plane as close to the pin as possible. Decoupling capacitors should have a via right next to the capacitor pin and this via should go directly down to the power plane – that is to say, the capacitor should not route to the power plane through a long trace. The ground side of the decoupling capacitor should have a via right next to the pad which goes directly down to the ground plane. Each decoupling capacitor should have it’s own via directly to the ground plane and directly to the power plane right next to the pad. The decoupling capacitors should be placed as close to the pin that it is filtering as possible. 11 Interferers One of the biggest problems with RF receivers is poor performance due to interferers on the board radiating noise into the antenna or coupling into the RF traces going to input LNA. Care must be taken to make sure that there is no noisy circuitry placed anywhere near the antenna or the RF traces. All noise generating circuits should also be shielded so they do not radiate noise that is picked up by the antenna. Also, make sure that no traces route underneath the RF portion of the BTLC1000. Also, make sure that no traces route underneath any of the RF traces from the antenna to the BTLC1000 input. This applies to all layers. Even if there is a ground plane on a layer between the RF route and another signal, the ground return current will flow on the ground plane and couple into the RF traces. 2 3 BTLC1000-MR110CA [DATA SHEET] 23 2 3 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 12 Reference Documentation & Support 12.1 Reference Documents Atmel offers a set of collateral documentation to ease integration and device ramp. The following list of documents available on Atmel web or integrated into development tools. Title Content Datasheet This document BTLC1000 SOC Datasheet Data sheet for the BTLC1000 SOC contained on this module. SW Design Guide SW Programmer guide 24 Integration guide with clear description of: High level Arch, overview on how to write a networking application, list all API, parameters and structures. Features of the device, SPI/handshake protocol between device and host MCU, with flow/sequence/state diagram, timing. Explain in details the flow chart and how to use each API to implement all generic use cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage & sample App note 2BTLC1000-MR110CA [DATA SHEET] 4 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 13 Certifications 13.1 Agency Compliance The BTLC1000-MR110CA has been tested and certified to meet the compliance for the following agencies: Bluetooth 4.1 o QD ID Controller (see declaration D028678) o QD ID Host: (see declaration D028679) FCC o FCC ID: 2ADHKBTLC1000 ETSI o EN 300 328 o EN 300 400 Class 2 ARIB o 2 5 CFR47 Part 15 STD-T66 TELEC BTLC1000-MR110CA [DATA SHEET] 25 2 5 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 14 Errata Issue: The measured current for the cases listed in Figure 6-3 will be higher than what is reported in the figure. This is because the Power number values in the SDK4.0 release have not been fully optimized to their final values. A small sample measurement has been performed on 10 samples and they show the following results: Measurement condition: - 1-sec adverting interval. 37 byte advertising payload. Connectable beacon Advertising on 3 channels (37,38,39). Vbatt and VDDIO are set to 3.3V. SAML21 has a measurement floor of 80nA which was compensated in the reported numbers (this number varies from board to board and needs to be compensated). The Average advertising current: 11.3uA The Average sleep current between beacons: 1.17uA The average current for the 10 boards was (including 80nA floor): Sample # Average Current (uA) 1 11.55 2 11.45 Work around: 3 11.45 4 11.7 5 11.4 6 11.25 7 10.95 8 11.2 9 11.6 10 11.4 Will be resolved in a SDK update. For a complete listing of development-support tools & documentation, visit http://www.atmel.com/ Or contact the nearest Atmel field representative. 26 2BTLC1000-MR110CA [DATA SHEET] 6 Atmel-42514C-ATBTLC1000-MR110CA-BLE-Module_Datasheet_12/2015 15 Revision History Doc Rev. Date Comments 42514C 12/2015 Updated performance numbers. Added UART Flow Control. Added clearer diagrams. Added Agency Certification section. 42514B 7/16/15 Updated for B0 silicon 42514A 4/15/2015 Atmel Corporation Initial release 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2015 Atmel Corporation. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. 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