ATA6616C/ATA6617C
8K/16K Flash Microcontroller with LIN Transceiver, 5V
Regulator and Watchdog
DATASHEET
General Features
● Single-package high performance, low power AVR® 8-bit microcontroller with LIN
transceiver, 5V regulator (85mA current capability) and watchdog
● Very low current consumption in sleep mode
● 8Kbytes/16Kbytes flash memory for application program
(Atmel® ATA6616C/ATA6617C)
● Supply voltage up to 40V
● Operating voltage: 5V to 27V
● Temperature range: Tcase –40°C to +125°C
● QFN38, 5mm 7mm package
Description
Atmel ATA6616C/ATA6617C is a System-in-Package (SiP) product, which is particularly
suited for complete LIN-bus node applications. It consists of two ICs in one package supporting highly integrated solutions for in-vehicle LIN networks. The first chip is the LINsystem-basis-chip (LIN-SBC) ATA6624, which has an integrated LIN transceiver, a 5V regulator (85mA) and a window watchdog. The second chip is an automotive microcontroller
from Atmel’s series of AVR 8-bit microcontroller with advanced RISC architecture, the
Atmel ATtiny87 with 8-Kbytes and the Atmel ATtiny167 with 16-Kbytes flash memory.
All pins of the LIN system basis chip as well as all pins of the AVR microcontroller are
bonded out to provide customers the same flexibility for their applications as they have
when using discrete parts.
In Section 1. “Atmel ATA6616C/ATA6617C LIN System in Package Solution (SIP)” on page
3 you will find the pin configuration for the complete SiP. In Section 3. “LIN System-basischip Block” on page 7 the LIN SBC is described, and in Section 4. “Atmel
ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616C/ATA6617C” on page 26 the
AVR is described in detail.
9132J-AUTO-01/15
Figure 1.
Application Diagram
LIN-bus
Atmel ATA6616C/ATA6617C
MCU
Atmel
ATtiny 87/167
2
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
LIN-SBC
Atmel
ATA6624
1.
Atmel ATA6616C/ATA6617C LIN System in Package Solution (SIP)
1.1
Pinning Atmel ATA6616C/ATA6617C
Table 1-1.
WAKE
LIN
GND
PA3
AVCC
AGND
PA4
PA5
PA6
PA7
PB7
PB6
Figure 1-1. Pinning QFN38
PB5
31 30 29 28 27 26 25 24 23 22 21 20
32
19
NTRIG
PB4
33
18
EN
VCC
34
17
VS
GND
35
16
VCC
GND
36
15
PVCC
GND
37
14
KL15
PB3
38
3
4
5
6
7
8
PB1
PB0
PA0
PA1
PA2
RXD
INH
TXD
MODE
TM
2
NRES
WD_OSC
1
13
9 10 11 12
PB2
Atmel
ATA6616C/ATA6617C
Pin Description
Pin
Symbol
1
PB2
Port B 2 I/O line (PCINT10/OC1AV/USCK/SCL)
2
PB1
Port B 1 I/O line (PCINT9/OC1BU/DO)
3
PB0
Port B 0 I/O line (PCINT8/OC1AU/DI/SDA)
4
PA0
Port A 0 I/O line (PCINT0/ADC0/RXD/RXLIN)
5
PA1
Port A 1 I/O line (PCINT1/ADC1/TXD/TXLIN)
6
PA2
Port A 2 I/O line (PCINT2/ADC2/OC0A/DO/MISO)
7
(1)
Receive data output
(1)
Battery-related output for controlling an external voltage regulator
RXD
8
INH
9
TXD(1)
10
NRES(1)
11
12
Function
WD_OSC
Transmit data input; active low output (strong pull down) after a local wake-up
request
(1)
(1)
TM
Output undervoltage and watchdog reset (open drain)
External resistor for adjustable watchdog timing
For factory testing only (tie to ground)
13
MODE(1)
14
(1)
Ignition detection (edge sensitive)
(1)
5V regulator sense input pin
15
16
KL_15
PVCC
(1)
VCC
17
VS(1)
18
(1)
19
20
21
Note:
1.
EN
For debug mode: Low watchdog is on; high watchdog is off
5V regulator output/driver pin
Battery supply
Enables the device into normal mode
(1)
Low level watchdog trigger input from microcontroller
(1)
High voltage input for local wake-up request; if not needed connect to VS
NTRIG
WAKE
GND(1)
System Ground LIN-SBC
This identifies the pins of the LIN SBC Atmel® ATA6624
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
3
Table 1-1.
Pin Description (Continued)
Pin
Note:
4
Symbol
(1)
Function
22
LIN
LIN bus line input/output
23
PA3
Port A 3 I/O line (PCINT3/ADC3/ISRC/INT0)
24
MCUAVCC
25
AGND
26
PA4
Port A 4 I/O line (PCINT4/ADC4/ICP1/DI/SDA/MOSI)
27
PA5
Port A 5 I/O line (PCINT5/ADC5/T1/USCK/SCL)
28
PA6
Port A 6 I/O line (PCINT6/ADC6/AIN0/SS)
29
PA7
Port A 7 I/O line (PCINT7/ADC7/AIN1)
30
PB7
Port B 7 I/O line (PCINT15/ADC10/OC1BX / RESET)
31
PB6
Port B 6 I/O line (PCINT14/ADC9/OC1AX/INT0)
32
PB5
Port B 5 I/O line (PCINT13/ADC8/OC1BW/XTAL2/CLKO)
33
PB4
Port B 4 I/O line (PCINT12/OC1AW/XTAL1/CLKI)
34
MCUVCC
35
GND
System ground
36
GND
Ground (optional)
37
GND
Ground (optional)
38
PB3
Port B 3 I/O line (PCINT11/OC1BV)
39
1.
Microcontroller analog supply voltage (referred to as AVCC pin in
Section 4. on page 26)
Analog ground
Microcontroller supply voltage (referred to as VCC pin in Section 4. on page 26)
Backside
Heat slug is connected to GND
This identifies the pins of the LIN SBC Atmel® ATA6624
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
2.
Absolute Maximum Ratings
Table 2-1.
Maximum Ratings of the SiP
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
±2
KV
CDM ESD STM 5.3.1
±1
KV
Machine Model ESD AEC-Q100-Rev.F (003)
±150
V
ESD according to IBEE LIN EMC
Test Spec. 1.0 following IEC 61000-4-2
- Pin VS, LIN, KL_15 (47k/100nF) to GND
- Pin WAKE (33 k serial resistor) to GND
±6
±5
KV
KV
±6
KV
ESD HBM following STM5.1 with 1.5k 100pF
- Pin VS, LIN, KL_15, WAKE to GND
Storage temperature
Operating temperature
(1)
Ts
–55
+150
°C
Tcase
–40
+125
°C
Thermal resistance junction to heat slug
Rthjc
Thermal resistance junctiion to ambient
Rthja
5
K/W
25
K/W
Thermal shutdown of VCC regulator
150
165
170
°C
Thermal shutdown of LIN output
150
165
170
°C
Thermal shutdown hysteresis
10
°C
Note:
1. Tcase means the temperature of the heat slug (backside). It is mandatory that this backside temperature is ≤ 125°C in
the application.
Table 2-2.
Maximum Ratings of the LIN-SBC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Supply voltage VS
VS
–0.3
Pulse time ≤ 500ms; Ta = 25°C
Output current IVCC ≤ 85mA
Pulse time ≤ 2min; Ta = 25°C
Output current IVCC ≤ 85mA
WAKE (with 33k serial resistor)
KL_15 (with 47k/100nF)
DC voltage
Transient voltage due to ISO7637 (coupling 1nF)
INH
- DC voltage
Typ.
Max.
Unit
+40
V
VS
+40
V
VS
27
V
–1
–150
+40
+100
V
V
–0.3
VS + 0.3
V
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
5
Table 2-2.
Maximum Ratings of the LIN-SBC (Continued)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
V
LIN
- DC voltage
–27
+40
Logic pins (RXD, TXD, EN, NRES, NTRIG,
WD_OSC, MODE, TM)
–0.3
+5.5
Output current NRES
INRES
PVCC DC voltage
VCC DC voltage
Table 2-3.
–0.3
–0.3
V
+2
mA
+5.5
+6.5
V
V
Maximum Ratings of the Microcontroller
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
Voltage on any pin except RESET with respect to
Ground
–0.5
MCUVCC + 0.5
V
Voltage on RESET with respect to GND
–0.5
13.0
V
Voltage on MCUVCC with respect to GND
–0.5
6.0
V
DC current per I/O pin
40.0
mA
DC current MCUVCC and GND pins
200.0
mA
Injection current at MCUVCC = 0V to 5V(2)
Notes: 1. Maximum current per port = ±30mA
±5.0
mA
2.
6
Functional corruption may occur
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
3.
LIN System-basis-chip Block
3.1
Features
●
●
●
●
●
●
Master and slave operation possible
Supply voltage up to 40V
Operating voltage VS = 5V to 27V
Typically 10µA supply current during sleep mode
Typically 57µA supply current in silent mode
Linear Low-drop voltage regulator, 85mA current capability:
●
Normal, fail-safe, and silent mode
●
In sleep mode VCC is switched off
●
●
●
●
●
●
●
●
●
●
●
●
●
3.2
VCC = 5.0V ±2%
VCC undervoltage detection (4ms reset time) and watchdog reset logical combined at open drain output NRES
Negative trigger input for watchdog
Boosting the voltage regulator possible with an external NPN transistor
LIN physical layer according to LIN 2.0, 2.1 specification and SAEJ2602-2
Wake-up capability via LIN-bus, wake pin, or Kl_15 pin
INH output to control an external voltage regulator or to switch off the master pull-up resistor
TXD time-out timer
Bus pin is overtemperature and short-circuit protected versus GND and battery
Adjustable watchdog time via external resistor
Advanced EMC and ESD performance
Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.0”
Interference and damage protection according to ISO7637
Description
The LIN-SBC is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2 specifications. It
has a low-drop voltage regulator with a 5V/85mA output and a window watchdog. The voltage regulator is able to source up
to 85mA, but if necessary the output can be boosted by an external NPN transistor.
The LIN-SBC is designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics.
Improved slope control at the LIN-driver ensures secure data communication up to 20kBaud. Sleep mode and silent mode
guarantee very low current consumption.
ATA6616C/ATA6617C [DATASHEET]
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Figure 3-1. Block Diagram
VS
Normal and
Fail-safe
Mode
INH
PVCC
Normal
Mode
Receiver
RXD
+
RF Filter
LIN
WAKE
KL_15
PVCC
TXD
Edge
Detection
Wake-up
Bus Timer
Slew Rate Control
TXD
Time-out
Timer
Control Unit
EN
Short Circuit and
Overtemperature
Protection
Debounce
Time
Normal/Silent/
Fail-safe Mode
5V
Undervoltage
Reset
OUT
Watchdog
GND
PVCC
8
TM
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
PVCC
Mode Select
Internal Testing
Unit
MODE
VCC
NTRIG
NRES
Adjustable
Watchdog
Oscillator
WD_OSC
3.3
Functional Description
3.3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical
layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN
1.0, LIN 1.1, LIN 1.2, LIN 1.3), without any restrictions.
3.3.2
Supply Pin (VS)
The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS
falls below VSth < 4V in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the
voltage regulator is switched on (i.e., output capability).
The supply current is typically 10µA in sleep mode and 57µA in silent mode.
3.3.3
Ground Pin (GND)
The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS.
The mandatory system ground is pin 5.
3.3.4
Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads up to 85mA. It is able to supply the microcontroller and other ICs
on the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore,
the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold
Vthun. To boost the maximum load current, an external NPN transistor with its base connected to the VCC pin and its emitter
connected to PVCC can be used.
3.3.5
Voltage Regulator Sense Pin (PVCC)
The PVCC is the sense input pin of the voltage regulator. For normal applications (i.e., when only using the internal output
transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected
to the output of this transistor, i.e., its emitter terminal.
3.3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN
2.x specification are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN
bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible
with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to
recessive bus state are slope controlled.
3.3.7
Input/Output Pin (TXD)
In normal mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to
ground in order to have a low LIN bus. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is
turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8mA.
and is latched to low if the last wake-up event was from pin WAKE or KL_15.
3.3.8
TXD Dominant Time-out Function
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in
dominant state. If TXD is forced to low for longer than tDOM > 6ms, the LIN-bus driver is switched to recessive state.
To reactivate the LIN-bus driver, switch TXD to high (> 10µs).
ATA6616C/ATA6617C [DATASHEET]
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3.3.9
Output Pin (RXD)
The Output pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at
RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically
5k to VCC. The AC characteristics can be defined with an external load capacitor of 20pF.
The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V).
3.3.10 Enable Input Pin (EN)
The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in normal mode with transmission
paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 5V/85mA output
capability.
If EN is switched to low while TXD is still high, the device is forced to silent mode. No data transmission is then possible, and
the current consumption is reduced to IVS typ. 57µA. The VCC regulator has its full functionality.
If EN is switched to low while TXD is low, the device is forced to sleep mode. No data transmission is possible, and the
voltage regulator is switched off.
3.3.11 Wake Input Pin (WAKE)
The Wake Input pin is a high-voltage input used to wake up the device from sleep mode or silent mode. It is usually
connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10µA, is
implemented.
If a local wake-up is not needed for the application, connect the Wake pin directly to the VS pin.
3.3.12 Mode Input Pin (MODE)
Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of
the connected microcontroller, connect the MODE pin to VCC and the watchdog is switched off.
3.3.13 TM Input Pin
The TM pin is used for final production measurements at Atmel. In normal application, it must always be connected to GND.
3.3.14 KL_15 Pin
The KL_15 pin is a high-voltage input used to wake up the device from Sleep or silent mode. It is an edge-sensitive pin (lowto-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is
switched on. Although KL_15 pin is at high voltage (VBatt), it is possible to switch the IC into Sleep or silent mode. Connect
the KL_15 pin directly to GND if you do not need it. A debounce timer with a typical TdbKL_15 of 160µs is implemented.
The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin
against voltage transients, a serial resistor of 47k and a ceramic capacitor of 100nF are recommended. With this RC
combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition
KL_15.
The wake-up time can also be increased by using external capacitors with higher values.
3.3.15 INH Output Pin
The INH Output pin is used to switch on an external voltage regulator during Normal or Fail-safe Mode. The INH pin is
switched off in Sleep or silent mode. It is possible to switch off the external 1k master resistor via the INH pin for master
node applications. The INH pin is switched off during VCC undervoltage reset.
3.3.16 Reset Output Pin (NRES)
The Reset Output pin, an open-drain output, switches to low during VCC undervoltage or a watchdog failure.
3.3.17 WD_OSC Output Pin
The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34k
and 120k to adjust the watchdog oscillator time.
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ATA6616C/ATA6617C [DATASHEET]
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3.3.18 NTRIG Input Pin
The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers
the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger.
3.3.19 Wake-up Events from Sleep or Silent Mode
●
●
●
●
3.4
LIN-bus
WAKE pin
EN pin
KL_15
Modes of Operation
Figure 3-2. Modes of Operation
a: VS > 5V
Unpowered Mode
VBatt = 0V
b: VS < 4V
c: Bus wake-up event
d: Wake up from WAKE or KL_15 pin
a
b
e: NRES switches to low
b
Fail-safe Mode
VCC: 5V
With undervoltage monitoring
Communication: OFF
Watchdog: ON
b
e
EN = 1
b
c+d+e
EN = 1
c+d
Go to silent command
EN = 0
Silent Mode
TXD = 1
Normal Mode
VCC: 5V
With undervoltage monitoring
Communication: OFF
Watchdog: OFF
Local wake-up event
EN = 1
VCC: 5V
With undervoltage
monitoring
Go to sleep command
Communication: ON
Watchdog: ON
Table 3-1.
EN = 0
Sleep Mode
TXD = 0
VCC: switched off
Communication: OFF
Watchdog: OFF
Modes of Operation
Mode of
Operation
Transceiver
VCC
Watchdog
WD_OSC
INH
RXD
LIN
Fail-safe
Off
5V
On
1.23V
On
High, except
after wake up
Recessive
Normal
On
5V
On
1.23V
On
LIN
depending
TXD depending
Silent
Off
5V
Off
0V
Off
High
Recessive
Sleep
Off
0V
Off
0V
Off
0V
Recessive
ATA6616C/ATA6617C [DATASHEET]
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3.4.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN interface in acoordance with the LIN specification LIN 2.x. The
voltage regulator is active and can source up to 85mA. The undervoltage detection is activated. The watchdog needs a
trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to fail-safe Mode.
3.4.2
Silent Mode
A falling edge at EN when TXD is high switches the IC into silent mode. The TXD Signal has to be logic high during the Mode
Select window (see Figure 3-3). The transmission path is disabled in silent mode. The overall supply current from VBatt is a
combination of the IVSsi = 57µA plus the VCC regulator output current IVCC.
The internal slave termination between the LIN pin and the VS pin is disabled in silent mode. Only a weak pull-up current
(typically 10µA) between the LIN pin and the VS pin is present. silent mode can be activated independently from the actual
level on the LIN, WAKE, or KL_15 pins. If an undervoltage condition occurs, NRES is switched to low, and the IC changes its
state to Fail-safe Mode.
A voltage lower than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on
the internal slave termination between the LIN pin and the VS pin.
Figure 3-3. Switch to Silent Mode
Normal Mode
Silent Mode
EN
TXD
Mode select window
td = 3.2μs
NRES
VCC
Delay time silent mode
td_silent = maximum 20μs
LIN
LIN switches directly to recessive mode
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and followed by a
rising edge at the LIN pin (see Figure 3-4 on page 13) results in a remote wake-up request. The device switches from silent
mode to Fail-safe Mode. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the
microcontroller (see Figure 3-4 on page 13). EN high can be used to switch directly to normal mode.
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ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Figure 3-4. LIN Wake-up from Silent Mode
Bus wake-up filtering time
tbus
Fail-safe mode
Normal mode
LIN bus
Node in silent mode
RXD
High
Low
High
TXD
Watchdog
VCC
voltage
regulator
Watchdog off
Start watchdog lead time td
Silent mode 5V
Fail safe mode 5V
Normal mode
EN High
EN
NRES
3.4.3
Undervoltage detection active
Sleep Mode
A falling edge at EN when TXD is low switches the IC into sleep mode. The TXD Signal has to be logic low during the Mode
Select window (Figure 3-5 on page 14). In order to avoid any influence to the LIN-pin during switching into sleep mode it is
possible to switch the EN up to 3.2µs earlier to LOW than the TXD. Therefore, the best and easiest way are two falling edges
at TXD and EN at the same time.The transmission path is disabled in sleep mode. The supply current IVSsleep from VBatt is
typically 10µA.
The VCC regulator and the INH output are switched off. NRES and RXD are low. The internal slave termination between the
LIN pin and VS pin is disabled, only a weak pull-up current (typically 10µA) between the LIN pin and the VS pin is present.
sleep mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin.
A voltage lower than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on
the internal slave termination between the LIN pin and the VS pin.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and followed by a
rising edge at pin LIN results in a remote wake-up request. The device switches from sleep mode to Fail-safe Mode.
The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the RXD pin to interrupt the
microcontroller (see Figure 3-6 on page 15).
ATA6616C/ATA6617C [DATASHEET]
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Figure 3-5. Switch to Sleep Mode
Normal Mode
Sleep Mode
EN
Mode select window
TXD
td = 3.2μs
NRES
VCC
Delay time sleep mode
td_sleep = maximum 20μs
LIN
LIN switches directly to recessive mode
3.4.4
Fail-safe Mode
The device automatically switches to Fail-safe Mode at system power up and the voltage regulator is switched on (see
Figure 3-7 on page 17).The NRES output switches to low for tres = 4ms and gives a reset to the microcontroller. LIN
communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to normal mode.
A power down of VBatt (VS < 4V) during Silent or sleep mode switches the IC into Fail-safe Mode. A low level at NRES
switches into Fail-safe Mode directly. During fail-safe Mode the TXD pin is an output and signals the last wake-up source.
3.4.5
Unpowered Mode
If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor
(see Figure 3-7 on page 17). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from
Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends
on the VCC capacitor and the load.
The NRES is low for the reset time delay treset. During this time, treset, no mode change is possible.
14
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Figure 3-6. LIN Wake-up from Sleep Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Normal Mode
LIN bus
RXD
Low
TXD
VCC
voltage
regulator
On state
Off state
Regulator wake-up time
EN High
EN
Reset
time
NRES
Microcontroller
start-up time delay
Watchdog
Watchdog off
3.5
Wake-up Scenarios from Silent or Sleep Mode
3.5.1
Remote Wake-up via Dominant Bus State
Start watchdog lead time td
A voltage lower than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver.
A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (> tBUS) and
followed by a rising edge at pin LIN result in a remote wake-up request. The device switches from Silent or sleep mode to
Fail-safe Mode. The VCC voltage regulator is/remains activated, the INH pin is switched to high, and the remote wake-up
request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller. A low level at the LIN pin in
the normal mode starts the bus wake-up filtering time, and if the IC is switched to Silent or sleep mode, it will receive a
wake-up after a positive edge at the LIN pin.
3.5.2
Local Wake-up via Pin WAKE
A falling edge at the WAKE pin followed by a low level maintained for a certain time period (> tWAKE) results in a local wakeup request. The device switches to fail-safe mode. The local wake-up request is indicated by a low level at the RXD pin to
generate an interrupt in the microcontroller and a strong pull down at TXD. When the WAKE pin is low, it is possible to switch
to Silent or sleep mode via pin EN. In this case, the wake-up signal has to be switched to high > 10µs before the negative
edge at WAKE starts a new local wake-up request.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
15
3.5.3
Local Wake-up via Pin KL_15
A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15) results in a local wake-up
request. The device switches into the Fail-safe Mode. The extra long wake-up time ensures that no transients at KL_15
create a wake-up. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the
microcontroller and a strong pull down at TXD. During high-level voltage at pin KL_15, it is possible to switch to Silent or
sleep mode via pin EN. In this case, the wake-up signal has to be switched to low > 250µs before the positive edge at KL_15
starts a new local wake-up request. With external RC combination, the time is even longer.
3.5.4
Wake-up Source Recognition
The device can distinguish between a local wake-up request (Wake or KL_15 pins) and a remote wake-up request (via LIN
bus). The wake-up source can be read on the TXD pin in Fail-safe Mode. A high level indicates a remote wake-up request
(weak pull up at the TXD pin); a low level indicates a local wake-up request (strong pull down at the TXD pin). The wake-up
request flag (signalled on the RXD pin) as well as the wake-up source flag (signalled on the TXD pin) is immediately reset if
the microcontroller sets the EN pin to high (see Figure 3-3 on page 12 and Figure 3-4 on page 13) and the IC is in normal
mode. The last wake-up source flag is stored and signalled in fail-safe mode at the TXD pin.
3.5.5
Fail-safe Features
●
During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the
chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of
Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off,
the VCC regulator works independently.
●
During a short-circuit from LIN to GND the IC can be switched into Sleep or silent mode. If the short-circuit
disappears, the IC starts with a remote wake-up.
●
The reverse current is very low < 2µA at the LIN pin during loss of VBatt. This is optimal behavior for bus systems
where some slave nodes are supplied from battery or ignition.
●
During a short circuit at VCC, the output limits the output current to IVCC_lin. Due to undervoltage, NRES switches to
low and sends a reset to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds the
value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on
again. Because of the Fail-safe Mode, the VCC voltage will switch on again even though EN is switched off from the
microcontroller. The microcontroller can start with its normal operation.
●
●
●
●
●
EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.
●
16
RXD pin is set floating if VBatt is disconnected.
TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.
If TXD is short-circuited to GND, it is possible to switch to sleep mode via ENABLE after tdom > 20ms.
If the WD_OSC pin has a short-circuit to GND and the NTRIG signal has a period time > 27ms, the watchdog runs
with an internal oscillator and guarantees a reset after the second NTRIG signal at the latest.
If the resistor at WO_OSC pin is disconnected, the watchdog runs with an internal oscillator and guarantees a reset
after the second NTRIG signal at the latest.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Voltage Regulator
The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the
microcontroller. It is recommended to use an electrolythic capacitor with C ≥ 1.8µF and a ceramic capacitor with C = 100nF.
The values of these capacitors can be varied by the customer, depending on the application.
The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. In
Figure 3-8 on page 17 the safe operating area of the Atmel® ATA6616C/ATA6617C is shown.
Figure 3-7. VCC Voltage Regulator: Ramp-up and Undervoltage Detection
VS
12V
5.5V
t
VCC
5V
Vthun
tVCC
tres_f
tReset
t
NRES
5V
t
Figure 3-8. Power Dissipation: Safe Operating Area VCC Output Current versus Supply Voltage VS at Different
Ambient Temperatures
90
80
Tamb = 100°C
70
IVCC (mA)
3.5.6
60
Tamb = 105°C
50
Tamb = 110°C
40
30
Tamb = 115°C
20
10
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
VS (V)
For programming purposes of the microcontroller it is potentially necessary to supply the VCC output via an external power
supply while the VS Pin of the system basis chip is disconnected. This will not affect the system basis chip.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
17
3.6
Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window
of Twd. The trigger signal must exceed a minimum time ttrigmin > 200ns. If a triggering signal is not received, a reset signal will
be generated at output NRES. After a watchdog reset, the IC starts with the lead time. The timing basis of the watchdog is
provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor Rwd_osc (34k to 120k).
During Silent or sleep mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as
lead time td. After wake up from Sleep or silent mode, the lead time td starts with the negative edge of the RXD output.
3.6.1
Typical Timing Sequence with RWD_OSC = 51k
The trigger signal Twd is adjustable between 20ms and 64ms using the external resistor RWD_OSC.
For example, with an external resistor of RWD_OSC = 51k ±1%, the typical parameters of the watchdog are as follows:
tosc = 0.405 RWD_OSC – 0.0004 (RWD_OSC)2 (RWD_OSC in k; tosc in µs)
tOSC = 19.6µs due to 51k
td = 7895 19.6µs = 155ms
t1 = 1053 19.6µs = 20.6ms
t2 = 1105 19.6µs = 21.6ms
tnres = constant = 4 ms
After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time treset
(typically 4ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead
time, td, follows the reset and is td = 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the
trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a
watchdog reset with tNRES = 4ms will reset the microcontroller after td = 155ms. The times t1 and t2 have a fixed relationship
between each other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6ms. To avoid
false triggering from glitches, the trigger pulse must be longer than tTRIG,min > 200ns. This slope serves to restart the
watchdog sequence. If the triggering signal fails in this open window t2, the NRES output will be drawn to ground. A
triggering signal during the closed window t1 immediately switches NRES to low.
Figure 3-9. Timing Sequence with RWD_OSC = 51k
VCC
Undervoltage Reset
NRES
Watchdog Reset
tnres = 4ms
treset = 4ms
td = 155ms
t1
t1 = 20.6ms
t2 = 21ms
twd
NTRIG
ttrig > 200ns
18
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
t2
3.6.2
Worst Case Calculation with RWD_OSC = 51 k
The internal oscillator has a tolerance of 20%. This means that t1 and t2 can vary by 20%. The worst case calculation for the
watchdog period twd is calculated below.
The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2.
t1,min = 0.8 t1 = 16.5ms, t1,max = 1.2 t1 = 24.8ms
t2,min = 0.8 t2 = 17.3ms, t2,max = 1.2 t2 = 26ms
twdmax = t1min + t2min = 16.5ms + 17.3ms = 33.8ms
twdmin = t1max = 24.8ms
twd = 29.3ms ±4.5ms (±15%)
A microcontroller with an oscillator tolerance of ±15% is sufficient to correctly supply the trigger inputs.
Table 3-2.
3.7
Typical Watchdog Timings
RWD_OSC
k
Oscillator
Period
tosc/µs
Lead
Time
td/ms
Closed
Window
t1/ms
Open Window
t2/ms
Trigger Period from
Microcontroller twd/ms
Reset Time
tnres/ms
34
13.3
105
14.0
14.7
19.9
4
51
19.61
154.8
20.64
21.67
29.32
4
91
33.54
264.80
35.32
37.06
50.14
4
120
42.84
338.22
45.11
47.34
64.05
4
Electrical Characteristics
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
1
1.1
1.2
1.3
Parameters
Test Conditions
Pin
Symbol
Min.
VS
VS
5
Sleep mode
VLIN > VS – 0.5V
VS < 14V (Tj = 25°C)
VS
IVSsleep
3
Sleep mode
VLIN > VS – 0.5V
VS < 14V (Tj = 125°C)
VS
IVSsleep
Bus recessive
VS < 14V (Tj = 25°C)
Without load at VCC
VS
Bus recessive
VS < 14V (Tj = 125°C)
Without load at VCC
Typ.
Max.
Unit
Type*
27
V
A
10
14
µA
B
5
11
16
µA
A
IVSsi
47
57
67
µA
B
VS
IVSsi
56
66
76
µA
A
VS Pin
Nominal DC voltage
range
Supply current in sleep
mode
Supply current in silent
mode
1.4
Bus recessive
Supply current in normal
VS < 14V
mode
Without load at VCC
VS
IVSrec
0.3
0.8
mA
A
1.5
Bus dominant
Supply current in normal
VS < 14V
mode
VCC load current 50mA
VS
IVSdom
50
53
mA
A
1.6
Supply current in failsafe Mode
VS
IVSfail
250
550
µA
A
Bus recessive
VS < 14V
Without load at VCC
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
19
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
1.7
1.8
2
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS undervoltage
threshold
VS
VSth
3.7
4.4
5
V
A
VS undervoltage
threshold hysteresis
VS
VSth_hys
V
A
RXD
IRXD
8
mA
A
0.4
V
A
7
k
A
0.2
RXD Output Pin
Normal mode
VLIN = 0V
VRXD = 0.4V
2.1
Low-level output sink
current
2.2
Low-level output voltage IRXD = 1mA
RXD
VRXDL
2.3
Internal resistor to VCC
RXD
RRXD
3
3
TXD Input/Output Pin
1.3
2.5
5
3.1
Low-level voltage input
TXD
VTXDL
–0.3
+0.8
V
A
3.2
High-level voltage input
TXD
VTXDH
2
VCC +
0.3V
V
A
3.3
Pull-up resistor
VTXD = 0V
TXD
RTXD
125
400
k
A
3.4
High-level leakage
current
VTXD = VCC
TXD
ITXD
–3
+3
µA
A
3.5
Fail-safe Mode
Low-level output sink
V = VS
current at local wake-up LIN
VWAKE = 0V
request
VTXD = 0.4V
TXD
ITXDwake
2
8
mA
A
EN
VENL
–0.3
+0.8
V
A
VCC +
0.3V
V
A
200
k
A
4
4.1
2.5
EN Input Pin
Low-level voltage input
4.2
High-level voltage input
4.3
Pull-down resistor
4.4
Low-level input current
5
250
EN
VENH
2
VEN = VCC
EN
REN
50
VEN = 0V
EN
IEN
–3
+3
µA
A
125
NTRIG Watchdog Input Pin
5.1
Low-level voltage input
NTRIG
VNTRIGL
–0.3
+0.8
V
A
5.2
High-level voltage input
NTRIG
VNTRIGH
2
VCC +
0.3V
V
A
5.3
Pull-up resistor
VNTRIG = 0V
NTRIG
RNTRIG
125
400
k
A
5.4
High-level leakage
current
VNTRIG = VCC
NTRIG
INTRIG
–3
+3
µA
A
6
250
Mode Input Pin
6.1
Low-level voltage input
MODE
VMODEL
–0.3
+0.8
V
A
6.2
High-level voltage input
MODE
VMODEH
2
VCC +
0.3V
V
A
6.3
Leakage current
MODE
IMODE
–3
+3
µA
A
VMODE = VCC or
VMODE = 0V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
7
Parameters
Pin
Symbol
Min.
IINH = –15mA
INIT
VINHH
VS –
0.75
INIT
RINH
INIT
IINHL
Typ.
Max.
Unit
Type*
VS
V
A
50
A
+3
µA
A
INH Output Pin
7.1
High-level voltage
7.2
Switch-on resistance
between VS and INH
7.3
Leakage current
8
Test Conditions
Sleep mode
VINH = 0V/27V, VS = 27V
30
–3
LIN Bus Driver: Bus Load Conditions:
Load 1 (Small): 1nF, 1k; Load 2 (Large): 10nF, 500; RRXD = 5k; CRXD = 20pF;
Load 3 (Medium): 6.8nF, 660 Characterized on Samples; 10.6 and 10.7 Specifies the Timing Parameters for Proper
Operation at 20Kbit/s, 10.8 and 10.9 at 10.4Kbit/s.
8.1
Driver recessive output
Load1/Load2
voltage
LIN
VBUSrec
8.2
Driver dominant voltage
VVS = 7V
Rload = 500
LIN
8.3
Driver dominant voltage
VVS = 18V
Rload = 500
8.4
Driver dominant voltage
8.5
0.9 VS
VS
V
A
V_LoSUP
1.2
V
A
LIN
V_HiSUP
2
V
A
VVS = 7.0V
Rload = 1000
LIN
V_LoSUP_1k
0.6
V
A
Driver dominant voltage
VVS = 18V
Rload = 1000
LIN
V_HiSUP_1k
0.8
V
A
8.6
Pull-up resistor to VS
The serial diode is
mandatory
LIN
RLIN
20
60
k
A
8.7
Voltage drop at the
serial diodes
In pull-up path with Rslave
ISerDiode = 10mA
LIN
VSerDiode
0.4
1.0
V
D
8.8
LIN current limitation
VBUS = VBatt_max
LIN
IBUS_LIM
40
120
200
mA
A
8.9
Input leakage current at
the receiver including
pull-up resistor as
specified
Input leakage current
Driver off
VBUS = 0V
VBatt = 12V
LIN
IBUS_PAS_do
–1
–0.35
mA
A
8.10
Leakage current LIN
recessive
Driver off
8V < VBatt < 18V
8V < VBUS < 18V
VBUS ≥ VBatt
LIN
IBUS_PAS_rec
8.11
Leakage current when
control unit
disconnected from
ground.
Loss of local ground
must not affect
communication in the
residual network.
GNDDevice = VS
VBatt = 12V
0V < VBUS < 18V
LIN
IBUS_NO_gnd
30
m
–10
10
20
µA
A
+0.5
+10
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
21
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
8.12
Leakage current at a
disconnected battery.
Node has to sustain the
VBatt disconnected
current that can flow
VSUP_Device = GND
under this condition.
0V < VBUS < 18V
Bus must remain
operational under this
condition.
Pin
Symbol
LIN
IBUS_NO_bat
LIN
VBUS_CNT
Min.
Typ.
Max.
Unit
Type*
0.1
2
µA
A
0.5
VS
0.525
VS
V
A
0.4 VS
V
A
V
A
0.175
VS
V
A
9
LIN Bus Receiver
9.1
Center of receiver
threshold
9.2
Receiver dominant state VEN = 5V
LIN
VBUSdom
9.3
Receiver recessive
state
VEN = 5V
LIN
VBUSrec
0.6 VS
9.4
Receiver input
hysteresis
Vhys = Vth_rec – Vth_dom
LIN
VBUShys
0.028
VS
9.5
Pre_Wake detection LIN
High-level input voltage
LIN
VLINH
VS – 2V
VS +
0.3V
V
A
9.6
Pre_Wake detection LIN
Activates the LIN receiver
Low-level input voltage
LIN
VLINL
–27
VS –
3.3V
V
A
10
Internal Timers
VBUS_CNT =
(Vth_dom + Vth_rec)/2
0.475
VS
0.1 VS
10.1
Dominant time for wakeVLIN = 0V
up via LIN bus
LIN
tbus
30
90
150
µs
A
10.2
Time delay for mode
change from Fail-safe
into normal mode via
EN pin
VEN = 5V
EN
tnorm
5
15
20
µs
A
10.3
Time delay for mode
change from normal
V = 0V
mode to sleep mode via EN
EN pin
EN
tsleep
2
7
12
µs
A
10.4
TXD dominant time-out
VTXD = 0V
time
TXD
tdom
6
13
20
ms
A
10.5
Time delay for mode
change from silent
V = 5V
mode into normal mode EN
via EN
EN
ts_n
5
15
40
µs
A
Duty cycle 1
THRec(max) = 0.744 VS
THDom(max) = 0.581 VS
VS = 7.0V to 18V
tBit = 50µs
D1 = tbus_rec(min)/(2 tBit)
LIN
D1
0.396
Duty cycle 2
THRec(min) = 0.422 VS
THDom(min) = 0.284 VS
VS = 7.6V to 18V
tBit = 50µs
D2 = tbus_rec(max)/(2 tBit)
LIN
D2
10.6
10.7
A
0.581
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
A
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Duty cycle 3
THRec(max) = 0.778 VS
THDom(max) = 0.616 VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min)/(2 tBit)
LIN
D3
0.417
10.9
Duty cycle 4
THRec(min) = 0.389 VS
THDom(min) = 0.251 VS
VS = 7.6V to 18V
tBit = 96µs
D4 = tbus_rec(max)/(2 tBit)
LIN
D4
10.10
Slope time falling and
rising edge at LIN
VS = 7.0V to 18V
LIN
tSLOPE_fall
tSLOPE_rise
10.8
11
Max.
Unit
Type*
A
0.590
3.5
A
22.5
µs
A
6
µs
A
+2
µs
A
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions CRXD = 20pF
11.1
Propagation delay of
V = 7.0V to 18V
receiver (Figure 3-10 on S
trx_pd = max(trx_pdr , trx_pdf)
page 25)
RXD
trx_pd
11.2
Symmetry of receiver
V = 7.0V to 18V
propagation delay rising S
trx_sym = trx_pdr – trx_pdf
edge minus falling edge
RXD
trx_sym
12
Typ.
–2
NRES Open Drain Output Pin
12.1
Low-level output voltage
VS ≥ 5.5V
INRES = 1mA
NRES
VNRESL
0.14
V
A
12.2
Low-level output low
10k to 5V
VCC = 0V
NRES
VNRESLL
0.14
V
A
12.3
Undervoltage reset time
VS ≥ 5.5V
CNRES = 20pF
NRES
treset
2
6
ms
A
12.4
Reset debounce time
for falling edge
VS ≥ 5.5V
CNRES = 20pF
NRES
tres_f
1.5
10
µs
A
13
Watchdog Oscillator
IWD_OSC = –200µA
VVS ≥ 4V
WD_
OSC
VWD_OSC
1.13
1.33
V
A
WD_
OSC
ROSC
34
120
k
A
4
13.1
Voltage at WD_OSC in
normal mode
13.2
Possible values of
resistor
13.3
Oscillator period
ROSC = 34k
tOSC
10.65
13.3
15.97
µs
A
13.4
Oscillator period
ROSC = 51k
tOSC
15.68
19.6
23.52
µs
A
13.5
Oscillator period
ROSC = 91k
tOSC
26.83
33.5
40.24
µs
A
13.6
Oscillator period
ROSC = 120k
tOSC
34.2
42.8
51.4
µs
A
14
1.23
Watchdog Timing Relative to tOSC
14.1
Watchdog lead time
after reset
td
7895
cycles
A
14.2
Watchdog closed
window
t1
1053
cycles
A
14.3
Watchdog open window
t2
1105
cycles
A
14.4
Watchdog reset time
NRES
ms
A
NRES
tnres
3.2
4
4.8
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6616C/ATA6617C [DATASHEET]
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23
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
15
KL_15 Pin
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
15.1
High-level input voltage Positive edge initializes a
RV = 47 k
wake-up
KL_15
VKL_15H
4
VS +
0.3V
V
A
15.2
Low-level input voltage
RV = 47 k
KL_15
VKL_15L
–1
+2
V
A
15.3
KL_15 pull-down
current
VS < 27V
VKL_15 = 27V
KL_15
IKL_15
50
65
µA
A
15.4
Internal debounce time
Without external capacitor
KL_15
TdbKL_15
80
160
250
µs
A
15.5
KL_15 wake-up time
RV = 47k, C = 100nF
KL_15
TwKL_15
0.4
2
4.5
ms
C
16
WAKE Pin
16.1
High-level input voltage
WAKE
VWAKEH
VS – 1V
VS +
0.3V
V
A
16.2
Low-level input voltage
Initializes a wake-up signal WAKE
VWAKEL
–1
VS –
3.3V
V
A
16.3
WAKE pull-up current
VS < 27V
VWAKE = 0V
WAKE
IWAKE
–30
µA
A
16.4
High-level leakage
current
VS = 27V
VWAKE = 27V
WAKE
IWAKEL
–5
+5
µA
A
16.5
Time of low pulse for
wake-up via WAKE pin
VWAKE = 0V
WAKE
IWAKEL
30
150
µs
A
5.5V < VS < 18V
(0mA to 50mA)
VCC
VCCnor
4.9
5.1
V
A
6V < VS < 18V
(0mA to 85mA)
VCC
VCCnor
4.9
5.1
V
C
VS – VD
5.1
V
A
250
mV
A
600
mV
A
200
mV
A
17
17.1
–10
70
VCC Voltage Regulator, PVCC = VCC
Output voltage VCC
17.2
Output voltage VCC at
low VS
4V < VS < 5.5V
VCC
VCClow
17.3
Regulator drop voltage
VS > 4V
IVCC = –20mA
VS,
VCC
VD1
17.4
Regulator drop voltage
VS > 4V
IVCC = –50mA
VS,
VCC
VD2
17.5
Regulator drop voltage
VS > 3.3V
IVCC = –15mA
VS,
VCC
VD3
17.6
Line regulation
5.5V < VS < 18V
VCC
VCCline
0.1
0.2
%
A
17.7
Load regulation
5mA < IVCC < 50mA
VCC
VCCload
0.1
0.5
%
A
17.8
Power supply ripple
rejection
10Hz to 100kHz
CVCC = 10µF
VS = 14V, IVCC = –15mA
VCC
dB
D
17.9
Output current limitation VS > 5.5V
mA
A
µF
D
17.10 External load capacity
0.2 < ESR < 5 at
100kHz
for phase margin ≥ 60°
400
50
VCC
IVCClim
–240
–130
VCC
Cload
1.8
10
–85
ESR < 0.2 at 100kHz
for phase margin ≥ 30°
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
24
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3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
17.11
VCC undervoltage
threshold
Referred to VCC
VS > 5.5V
VCC
VthunN
4.2
17.12
Hysteresis of
undervoltage threshold
Referred to VCC
VS > 5.5V
VCC
Vhysthun
250
17.13
Ramp-up time VS >
5.5V to VCC = 5V
CVCC = 2.2µF
Iload = –5mA at VCC
VCC
tVCC
130
Max.
Unit
Type*
4.8
V
A
mV
A
µs
A
300
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 3-10. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
trx_pdf(2)
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4.
Atmel ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616C/ATA6617C
4.1
Features
●
●
●
High performance, low power AVR® 8-bit microcontroller
Advanced RISC architecture
●
123 powerful instructions – most single clock cycle execution
●
32 8 general purpose working registers
●
Fully static operation
Non-volatile program and data memories
●
8Kbytes/16Kbytes of in-system programmable (ISP) program memory flash
●
512 bytes in-system programmable EEPROM
●
512 bytes internal SRAM
●
Programming lock for self-programming flash program and EEPROM data security
●
Low size LIN/UART software in-system programmable
●
●
●
26
Endurance: 100,000 write/erase cycles
Peripheral features
●
LIN 2.1 and 1.3 controller or 8-bit UART
●
8-bit asynchronous Timer/Counter0:
●
●
Endurance: 10,000 write/erase cycles
●
10-bit clock prescaler
●
1 output compare or 8-bit PWM channel
16-bit synchronous Timer/Counter1:
●
10-bit clock prescaler
●
External event counter
●
2 output compares units or 16-bit PWM channels each driving up to 4 output pins
●
Master/slave SPI serial interface,
●
Universal serial interface (USI) with start condition detector (master/slave SPI, TWI,...)
●
10-bit ADC:
●
11 Single ended channels
●
8 differential ADC channel pairs with programmable gain (8x or 20x)
●
On-chip analog comparator with selectable voltage reference
●
100µA ±10% current source (LIN node identification)
●
On-chip temperature sensor
●
Programmable watchdog timer with separate on-chip oscillator
Special microcontroller features
●
Dynamic clock switching (external/internal RC/watchdog clock) for power control, EMC reduction
●
DebugWIRE on-chip debug (OCD) system
●
Hardware in-system programmable (ISP) via SPI Port
●
External and internal interrupt sources
●
Interrupt and wake-up on pin change
●
Low power idle, ADC noise reduction, and power-down modes
●
Enhanced power-on reset circuit
●
Programmable brown-out detection circuit
●
Internal calibrated RC oscillator 8MHz
●
4MHz to 16MHz and 32KHz crystal/ceramic resonator oscillators
ATA6616C/ATA6617C [DATASHEET]
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●
●
I/O and Packages
●
16 programmable I/O lines
●
20-pin SOIC, 32-pad QFN and 20-pin TSSOP
Operating voltage:
●
●
2.7V to 5.5V for Atmel® ATtiny87/ATtiny167
Speed Grade:
●
0MHz to 8MHz at 2.7V to 5.5V (automotive temperature range: –40°C to +125°C)
●
0MHz to 16MHz at 4.5V to 5.5V (automotive temperature range: –40°C to +125°C)
4.2
Description
4.2.1
Comparison between Atmel ATtiny87 and Atmel ATtiny167
Atmel ATtiny87 and Atmel ATtiny167 are hardware and software compatible. They differ only in memory sizes as shown in
Table 4-1.
Table 4-1.
4.2.2
Memory Size Summary
Device
Flash
EEPROM
SRAM
Interrupt Vector size
ATtiny167
16KBytes
512Bytes
512Bytes
2-instruction-words / vector
ATtiny87
8KBytes
512Bytes
512Bytes
2-instruction-words / vector
Part Description
The Atmel ATtiny87/167 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture.
By executing powerful instructions in a single clock cycle, the Atmel ATtiny87/167 achieves throughputs approaching 1MIPS
per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The Atmel ATtiny87/167 provides the following features: 8K/16Kbyte of in-system programmable flash, 512bytes EEPROM,
512bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare
modes, one 8-bit high speed Timer/Counter, universal serial interface, a LIN controller, internal and external interrupts,
a 11-channel, 10-bit ADC, a programmable watchdog timer with internal oscillator, and three software selectable power
saving modes. The idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, analog comparator, and
interrupt system to continue functioning. The power-down mode saves the register contents, disabling all chip functions until
the next interrupt or hardware reset. The ADC noise reduction mode stops the CPU and all I/O modules except ADC, to
minimize switching noise during ADC conversions.
The device is manufactured using Atmel high density non-volatile memory technology. The on-chip ISP flash allows the
program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory
programmer or by an on-chip boot code running on the AVR core. The boot program can use any interface to download the
application program in the flash memory.
By combining an 8-bit RISC CPU with in-system self-programmable flash on a monolithic chip, the Atmel ATtiny87/167 is a
powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The Atmel ATtiny87/167 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
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4.2.3
Automotive Quality Grade
The Atmel® ATtiny87/167 have been developed and manufactured according to the most stringent requirements of the
international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive
characterization (temperature and voltage). The quality and reliability of the Atmel ATtiny87/167 have been verified during
regular product qualification as per AEC-Q100 grade 1.
As indicated in the ordering information paragraph, this document refers only to grade 1 products, for grade 0 products refer
to appendix A.
Table 4-2.
4.2.4
Temperature Grade Identification for Automotive Products
Temperature
Temperature
Identifier
Comments
–40°C/+125°C
Z
Grade 1
–40°C/+150°C
D
Grade 0
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR® microcontrollers
manufactured on the same process technology. Min. and Max values will be available after the device is characterized.
28
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4.2.5
Block Diagram
Figure 4-1. Block Diagram
GND
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits/
Clock
Generation
VCC
Power
Supervision
POR/BOD
and
RESET
debugWIRE
Flash
SRAM
Program
Logic
AVR CPU
EEPROM
AVCC
DATA BUS
AREF
Timer/
Counter-1
Timer/
Counter-0
SPI and USI
Analog
Comparator
A/D Conv.
Internal
Voltage
References
2
11
PORT B (8)
PORT A (8)
LIN/UART
RESET
XTAL[1; 2]
PB[0 to 7]
4.2.6
PA[0 to 7]
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.2.7
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code
examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors
include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C
compiler documentation for more details.
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4.3
AVR CPU Core
4.3.1
Overview
This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.
Figure 4-2. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status and
Control
32 x 8
General
Purpose
Registers
Control Lines
Indirect Addressing
Instruction
Decoder
Direct Addressing
Instruction
Register
ALU
Interrupt
Unit
Watchdog
Timer
A.D.C.
Analog
Comparator
I/O Module 1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
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In order to maximize performance and parallelism, the AVR® uses a harvard architecture – with separate memories and
buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions
to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This
allows single-cycle arithmetic logic unit (ALU) operation.
In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored
back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling
efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in
flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect
information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole
address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a
16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and
the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through
the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance
with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions.
The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5F.
4.3.2
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are
executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some
implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and
fractional format. See the “instruction set” section for a detailed description.
4.3.3
Status Register
The status register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the status register is
updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for
using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine and restored when returning from an
interrupt. This must be handled by software.
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4.3.3.1 SREG – AVR Status Register
The AVR® status register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then
performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is
set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the
SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit
from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic. See the
“instruction set description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the
“Instruction set description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the “Instruction Set Description” for
detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed
information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed
information.
32
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4.3.4
General Purpose Register File
The register file is optimized for the AVR® enhanced RISC instruction set. In order to achieve the required performance and
flexibility, the following input/output schemes are supported by the register file:
● One 8-bit output operand and one 8-bit result input
●
●
●
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 4-3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-3. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle
instructions.
As shown in Figure 4-3, each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the
file.
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4.3.4.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described
in Figure 4-4.
Figure 4-4. The X-, Y-, and Z-registers
15
X-register
7
XH
XL
0
7
R27 (0x1B)
15
Y-register
7
Z-register
7
R31 (0x1F)
0
R26 (0x1A)
YH
YL
0
7
R29 (0x1D)
15
0
0
0
R28 (0x1C)
ZH
ZL
0
7
0
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and
automatic decrement (see the instruction set reference for details).
4.3.5
Stack Pointer
The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after
interrupts and subroutine calls. The stack pointer register always points to the top of the stack. Note that the stack is
implemented as growing from higher memory locations to lower memory locations. This implies that a stack PUSH command
decreases the stack pointer.
The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are located. This stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The stack pointer must be set to point above 0x60. The stack pointer is decremented by one when data is pushed onto the
stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the stack with
subroutine call or interrupt. The stack pointer is incremented by one when data is popped from the stack with the POP
instruction, and it is incremented by two when data is popped from the stack with return from subroutine RET or return from
interrupt RETI.
The AVR® stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only
SPL is needed. In this case, the SPH register will not be present
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4.3.5.1 SPH and SPL – Stack Pointer Register
Bit
Read/Write
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
4.3.6
ISRAM end (See Table 4-3 on page 38)
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR® CPU is driven by the CPU
clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast
access register file concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 4-5. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 4-6 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 4-6. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
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4.3.7
Reset and Interrupt Handling
The AVR® provides several different interrupt sources. These interrupts and the separate reset vector each have a separate
program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic
one together with the global interrupt enable bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. The complete
list of vectors is shown in Section 4.8 “Interrupts” on page 76. The list also determines the priority levels of the different
interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the
external interrupt request 0.
4.3.7.1 Interrupt behavior
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can
write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
The I-bit is automatically set when a return from interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these
interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine,
and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt
flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and
remembered until the global interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any
pending interrupt is served.
Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from
an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed
after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can
be used to avoid interrupts during the timed EEPROM write sequence.
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Assembly Code Example
in
cli
sbi
sbi
out
r16, SREG
; store SREG value
; disable interrupts during timed sequence
EECR, EEMPE ; start EEPROM write
EECR, EEPE
SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending
interrupts, as shown in this example.
Assembly Code Example
sei
; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI();
/* set Global Interrupt Enable */
_SLEEP();
/* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
4.3.7.2 Interrupt Response Time
The interrupt execution response for all the enabled AVR® interrupts is four clock cycles minimum. After four clock cycles the
program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the program
counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock
cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is
served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four
clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the program counter (two
bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is set.
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4.4
AVR Memories
This section describes the different memories in the Atmel® ATtiny87/167. The AVR® architecture has two main memory
spaces, the data memory and the program memory space. In addition, the Atmel ATtiny87/167 features an EEPROM
memory for data storage. All three memory spaces are linear and regular.
Table 4-3.
Memory Mapping.
Memory
Flash
32 registers
I/O
Registers
Ext I/O
registers
Internal
SRAM
EEPROM
Notes:
4.4.1
Mnemonic
ATtiny87
8Kbytes
ATtiny167
Size
Flash size
Start address
-
16Kbytes
End address
Flash end
Size
-
Start address
-
0x0000
End address
-
0x001F
Size
-
64 bytes
Start address
-
0x0020
End address
-
0x005F
Size
-
160 bytes
Start address
-
0x0060
End address
-
0x00FF
0x0000
0x1FFF(1)
0x3FFF(1)
0x0FFF(1)
0x1FFF(1)
32 bytes
Size
ISRAM size
512 bytes
Start address
ISRAM start
0x0100
End address
ISRAM end
0x02FF
Size
E2 size
512 bytes
Start address
-
0x0000
End address
E2 end
0x01FF
1.
Byte address.
2.
Word (16-bit) address.
In-System Re-programmable Flash Program Memory
The Atmel ATtiny87/167 contains on-chip in-system reprogrammable flash memory for program storage (see “flash size” in
Table 4-3). Since all AVR instructions are 16 or 32 bits wide, the flash is organized as 16 bits wide. Atmel ATtiny87/167 does
not have separate boot loader and application program sections, and the SPM instruction can be executed from the entire
flash. See SELFPRGEN description in
Section 4.21.2.1 “Store Program Memory Control and Status Register – SPMCSR” on page 217 for more details.
The flash memory has an endurance of at least 10,000 write/erase cycles in automotive range. The Atmel ATtiny87/167
program counter (PC) address the program memory locations. Section 4.22 “Memory Programming” on page 222 contains a
detailed description on flash data serial downloading using the SPI pins.
Constant tables can be allocated within the entire program memory address space (see the LPM – load program memory
instruction description).
Timing diagrams for instruction fetch and execution are presented in
Section 4.3.6 “Instruction Execution Timing” on page 35.
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Figure 4-7. Program Memory Map
Program Memory
0x0000
Flash end
4.4.2
SRAM Data Memory
Figure 4-8 shows how the Atmel® ATtiny87/167 SRAM memory is organized.
The Atmel ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in the opcode for the IN and OUT instructions. For the extended I/O space in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
The data memory locations address both the register file, the I/O memory, extended I/O memory, and the internal data
SRAM. The first 32 locations address the register file, the next 64 location the standard I/O memory, then 160 locations of
extended I/O memory, and the next locations address the internal data SRAM (see “ISRAM size” in Table 4-3 on page 38).
The five different addressing modes for the data memory cover: direct, indirect with displacement, indirect, indirect with
pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 feature the indirect addressing
pointer registers.
The direct addressing reaches the entire data space.
The indirect with displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers and the internal data SRAM in the
Atmel ATtiny87/167 are all accessible through all these addressing modes. The register file is described in
Section 4.3.4 “General Purpose Register File” on page 33.
Figure 4-8. Data Memory Map
Data Memory
32 Registers
0x0000 - 0x001F
64 I/O Registers
160 Ext I/O Registers
0x0020 - 0x005F
0x0060 - 0x00FF
ISRAM Start
Internal SRAM
(ISRAM size)
ISRAM End
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4.4.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM access is
performed in two clkCPU cycles as described in Figure 4-9.
Figure 4-9. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address
Compute Address
Address valid
Data
Write
WR
Data
Read
RD
Memory Access Instruction
4.4.3
Next Instruction
EEPROM Data Memory
The Atmel® ATtiny87/167 contains EEPROM memory (see “E2 size” in Table 4-3 on page 38). It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase
cycles in automotive range. The access between the EEPROM and the CPU is described in the following, specifying the
EEPROM address registers, the EEPROM data register and the EEPROM control register.
Section 4.22 “Memory Programming” on page 222 contains a detailed description on EEPROM programming in SPI or
parallel programming mode.
4.4.3.1 EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access times for the EEPROM are given in Table 4-4 on page 44. A self-timing function, however, lets the user
software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some
precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section 4.4.3.6 “Preventing EEPROM Corruption” on page 42 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to Section 4.4.3.2 “Atomic Byte Programming” on page 40 and Section 4.4.3.3 “Split Byte Programming” on page 40
for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the
EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
4.4.3.2 Atomic Byte Programming
Using atomic byte programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address
into the EEARL register and data into EEDR register. If the EEPMn bits are zero, writing EEPE (within four cycles after
EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the
total programming time is given in Table 1. The EEPE bit remains set until the erase and write operations are completed.
While the device is busy with programming, it is not possible to do any other EEPROM operations.
4.4.3.3 Split Byte Programming
It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short
access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this
method, it is required that the locations to be written have been erased before the write operation. But since the erase and
write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations
(typically after power-up).
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4.4.3.4 Erase
To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after
EEMPE is written) will trigger the erase operation only (programming time is given in Table 1). The EEPE bit remains set
until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM
operations.
4.4.3.5 Write
To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing
the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in
Table 1-1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased
before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible
to do any other EEPROM operations.
The calibrated oscillator is used to time the EEPROM accesses. Make sure the oscillator frequency is within the
requirements described in Section 4.5.5.1 “OSCCAL – Oscillator Calibration Register” on page 58.
The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The
examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during
execution of these functions.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic
EECR,EEPE
rjmp
EEPROM_write
; Set Programming mode
ldi
r16, (0<<EEPM1)|(0<<EEPM0)
out
EECR, r16
; Set up address (r18:r17) in address register
out
EEARH, r18
out
EEARL, r17
; Write data (r16) to data register
out
EEDR, r16
; Write logical one to EEMPE
sbi
EECR,EEMPE
; Start eeprom write by setting EEPE
sbi
EECR,EEPE
ret
C Code Example
void EEPROM_write(unsigned char ucAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set Programming mode */
EECR = (0<<EEPM1)|(0<<EEPM0);
/* Set up address and data registers */
EEAR = ucAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts
are controlled so that no interrupts will occur during execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic
EECR,EEPE
rjmp
EEPROM_read
; Set up address (r18:r17) in address register
out
EEARH, r18
out
EEARL, r17
; Start eeprom read by writing EERE
sbi
EECR,EERE
; Read data from data register
in
r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned char ucAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = ucAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
4.4.3.6 Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the
EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design
solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to
the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly,
if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR® RESET active
(low) during periods of insufficient power supply voltage. This can be done by enabling the internal brown-out detector
(BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset
protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed
provided that the power supply voltage is sufficient.
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4.4.4
I/O Memory
The I/O space definition of the Atmel® ATtiny87/167 is shown in Section 4.26 “Register Summary” on page 256.
All Atmel ATtiny87/167 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the
LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O
space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set
section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
Atmel ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
4.4.4.1 General Purpose I/O Registers
The Atmel ATtiny87/167 contains three general purpose I/O registers. These registers can be used for storing any
information, and they are particularly useful for storing global variables and status flags.
The general purpose I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS,
and SBIC instructions.
4.4.5
Register Description
4.4.5.1 EEARH and EEARL – EEPROM Address Register
Bit
Bit
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
7
6
5
4
3
2
1
0
Read/Write
R
R
R
R
R
R
R
R/W
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
X
Initial Value
X
X
X
X
X
X
X
X
• Bit 7:1 – Reserved Bits
These bits are reserved for future use and will always read as 0 in Atmel ATtiny87/167.
• Bits 8:0 – EEAR8:0: EEPROM Address
The EEPROM address registers – EEARH and EEARL – specifies the high EEPROM address in the EEPROM space (see
“E2 size” in Table 4-3 on page 38). The EEPROM data bytes are addressed linearly between 0 and “E2 size”. The initial
value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
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4.4.5.2 EEDR – EEPROM Data Register
Bit
7
6
5
4
3
2
1
0
EEDR7
EEDR6
EEDR5
EEDR4
EEDR3
EEDR2
EEDR1
EEDR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EEDR
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation the EEDR register contains the data to be written to the EEPROM in the address given by
the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address
given by EEAR.
4.4.5.3 EECR – EEPROM Control Register
Bit
7
6
5
4
3
2
1
0
–
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
X
X
0
0
X
0
EECR
• Bit 7,6 – Res: Reserved Bits
These bits are reserved for future use and will always read as 0 in Atmel ATtiny87/167. After reading, mask out these bits.
For compatibility with future AVR® devices, always write these bits to zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM programming mode bits setting defines which programming action that will be triggered when writing EEPE. It
is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and
write operations in two different operations. The programming times for the different modes are shown in Table 4-4. While
EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is
busy programming.
Table 4-4.
EEPROM Mode Bits
Typical
Programming Time Operation
EEPM1
EEPM0
0
0
3.4ms
Erase and write in one operation (atomic operation)
0
1
1.8ms
Erase only
1
0
1.8ms
Write only
1
1
–
Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM ready interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the
interrupt. The EEPROM ready interrupt generates a constant interrupt when non-volatile memory is ready for programming.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is
zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero
after four clock cycles.
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• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM program enable signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the
EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical
one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is
cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM read enable signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the
EEAR register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one
instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles
before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write
operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register.
4.4.5.4 General Purpose I/O Register 2 – GPIOR2
Bit
7
6
5
4
3
2
1
0
GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
GPIOR2
4.4.5.5 General Purpose I/O Register 1 – GPIOR1
Bit
7
6
5
4
GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
GPIOR1
4.4.5.6 General Purpose I/O Register 0 – GPIOR0
Bit
7
6
5
4
GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00
4.5
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
GPIOR0
System Clock and Clock Options
The Atmel® ATtiny87/167 provides a large number of clock sources. They can be divided into two categories: internal and
external. Some external clock sources can be shared with the asynchronous timer. After reset, the clock source is
determined by the CKSEL Fuses. Once the device is running, software clock switching is possible to any other clock
sources.
Hardware controls are provided for clock switching management but some specific procedures must be observed. Clock
switching should be performed with caution as some settings could result in the device having an incorrect configuration.
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4.5.1
Clock Systems and their Distribution
Figure 4-10 presents the principal clock systems in the AVR® and their distribution. All of the clocks may not need to be
active at any given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using
different sleep modes or by using features of the dynamic clock switch circuit
(See Section 4.6 “Power Management and Sleep Modes” on page 62 and
Section 4.5.3 “Dynamic Clock Switch” on page 52). The clock systems are detailed below.
Figure 4-10. Clock Distribution
Asynchronous
Timer/Counter0
General I/O
ADC
CPU Core
RAM
Flash and
EEPROM
clkADC
clkI/O
clkCPU
AVR Clock
Control Unit
clkASY
clkFLASH
Reset Logic
Source clock
Watchdog Timer
Watchdog clock
Prescaler
Clock Switch
Multiplexer
Watchdog
Oscillator
CKOUT
Fuse
External Clock
Low-frequency
Crystal Oscillator
PB4/XTAL1/CLKI
Calibrated RC
Oscillator
Crystal
Oscillator
PB5/XTAL2/CLKO
4.5.1.1 CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with the AVR core operation. Examples of such modules are the
general purpose register file, the status register and the data memory holding the stack pointer. Halting the CPU clock
inhibits the core from performing general operations and calculations.
4.5.1.2 I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like synchronous Timer/Counter. The I/O clock is also used by the
external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such
interrupts to be detected even if the I/O clock is halted.
4.5.1.3 Flash Clock – clkFLASH
The flash clock controls operation of the flash interface. The flash clock is usually active simultaneously with the CPU clock.
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4.5.1.4 Asynchronous Timer Clock – clkASY
The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly from an external clock or an
external low frequency crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even
when the device is in sleep mode.
4.5.1.5 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise
generated by digital circuitry. This gives more accurate ADC conversion results.
4.5.2
Clock Sources
The device has the following clock source options, selectable by flash fuse bits (default) or by the CLKSELR register
(dynamic clock switch circuit) as shown below. The clock from the selected source is input to the AVR® clock generator, and
routed to the appropriate modules.
Table 4-5.
Device Clocking Options Select(1) versus PB4 and PB5 Functionality
CKSEL3..0(2)
CSEL3..0(3)
PB4
PB5
External clock
0000b
CLKI
CLKO - I/O
Calibrated internal RC oscillator 8.0MHz
0010b
I/O
CLKO - I/O
Watchdog oscillator 128kHz
0011b
I/O
CLKO - I/O
External low-frequency oscillator
01xxb
XTAL1
XTAL2
External crystal/ceramic resonator (0.4 - 0.9MHz)
100xb
XTAL1
XTAL2
External crystal/ceramic resonator (0.9 - 3.0MHz)
101xb
XTAL1
XTAL2
External crystal/ceramic resonator (3.0 - 8.0MHz)
110xb
XTAL1
XTAL2
XTAL1
XTAL2
Device Clocking Option
External crystal/ceramic resonator (8.0 - 16.0MHz)
111xb
Notes: 1. For all fuses “1” means unprogrammed while “0” means programmed
2.
Flash fuse bits
3.
CLKSELR register bits
The various choices for each clocking option are given in the following sections.
When the CPU wakes up from power-down or power-save, or when a new clock source is enabled by the dynamic clock
switch circuit, the selected clock source is used to time the start-up, ensuring stable oscillator operation before instruction
execution starts.
When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing
normal operation. The watchdog oscillator is used for timing this real-time part of the start-up sequence. The number of WDT
oscillator cycles used for each time-out is shown in Table 4-6.
Table 4-6.
Number of Watchdog Oscillator Cycles
Typ. Time-out (VCC = 5.0V)
Typ. Time-out (VCC = 5.0V)
Number of Cycles
4.1ms
4.3ms
512
65ms
69ms
8K (8,192)
4.5.2.1 Default Clock Source
At reset, the CKSEL and SUT fuse settings are copied into the CLKSELR register. The device will then use the clock source
and the start-up timings defined by the CLKSELR bits (CSEL3..0 and CSUT1:0).
The device is shipped with CKSEL Fuses = 0010 b, SUT fuses = 10 b, and CKDIV8 fuse programmed. The default clock
source setting is therefore the internal RC oscillator running at 8MHz with the longest start-up time and an initial system
clock divided by 8. This default setting ensures that all users can make their desired clock source setting using an in-system
or high-voltage programmer. This set-up must be taken into account when using ISP tools.
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4.5.2.2 Calibrated Internal RC Oscillator
By default, the internal RC oscillator provides an approximate 8.0MHz clock. The frequency is nominal at 5V and 25°C.
Though voltage and temperature dependent, this clock can be accurately calibrated by the user.
See Table 4-81 on page 239 and Section 4.25.7 “Internal Oscillator Speed” on page 254 for more details.
If selected, it can operate without external components. At reset, hardware loads the pre-programmed calibration value into
the OSCCAL register and thereby automatically configuring the RC oscillator. At 5V and 25° C, this calibration gives a
frequency of 8MHz ±1%. The tolerance of the internal RC oscillator remains better than ±10% within the whole automotive
temperature and voltage ranges (4.5V to 5.5V, –40°C to +125°C). The accuracy of this calibration is shown as factory
calibration in Table 4-81 on page 239.
By adjusting the OSCCAL register in software, see Section 4.5.5.1 “OSCCAL – Oscillator Calibration Register” on page 58,
it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is
shown as User calibration in Table 4-81 on page 239.
The watchdog oscillator will still be used for the watchdog timer and for the reset time-out even when this oscillator is used
as the device clock. For more information on the pre-programmed calibration value,
see the section Section 4.22.4 “Calibration Byte” on page 224.
Internal Calibrated RC Oscillator Operating Modes(1)
Table 4-7.
(2)
Frequency Range
Notes:
CKSEL3..0(3)(4)
CSEL3..0(5)
(MHz)
1.
7.6 - 8.4
0010
If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 fuse can be
programmed in order to divide the internal frequency by 8
2.
The frequency ranges are guideline values
3.
The device is shipped with this CKSEL = “0010”
4.
Flash Fuse bits.
5.
CLKSELR register bits
When this oscillator is selected, start-up times are determined by the SUT fuses or by CSUT field as shown in Table 4-8.
Table 4-8.
Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
SUT1..0(1)
CSUT1..0(2)
Start-up Time from
Power-down/save
Additional Delay from Reset
(VCC = 5.0V)
Recommended Usage
00(3)
6 CK
14CK
BOD enabled
01
6 CK
14CK + 4.1ms
Fast rising power
6 CK
14CK + 65ms
Slowly rising power
(4)
10
Notes:
48
11
1.
Flash fuse bits
Reserved
2.
CLKSELR register bits
3.
This setting is only available if RSTDISBL fuse is not set
4.
The device is shipped with this option selected
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4.5.2.3 128kHz Internal Oscillator
The 128kHz internal oscillator is a low power oscillator providing a clock of 128kHz. The frequency is nominal at 5V and
25°C. This clock may be selected as the system clock by programming CKSEL fuses or CSEL field as shown
in Table 4-5 on page 47.
When this clock source is selected, start-up times are determined by the SUT fuses or by CSUT field as shown
in Table 4-9.
Table 4-9.
Start-up Times for the 128kHz Internal Oscillator
SUT1..0(1)
CSUT1..0(2)
Start-up Time from
Power-down/save
Additional Delay
from Reset (VCC = 5.0V)
6 CK
14CK
01
6 CK
14CK + 4.1ms
Fast rising power
10
6 CK
14CK + 65ms
Slowly rising power
(3)
00
11
Notes: 1.
Recommended Usage
BOD enabled
Reserved
Flash fuse bits
2.
CLKSELR register bits
3.
This setting is only available if RSTDISBL fuse is not set
4.5.2.4 Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip
oscillator, as shown in Figure 4-11. Either a quartz crystal or a ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the
crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial
guidelines for choosing capacitors for use with crystals are given in Table 4-10. For ceramic resonators, the capacitor values
given by the manufacturer should be used.
Figure 4-11. Crystal Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
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The oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is
selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in Table 4-10.
Table 4-10. Crystal Oscillator Operating Modes
CKSEL3..1(1)
CSEL3..1(2)
Frequency Range (MHz)
100(3)
0.4 - 0.9
–
101
0.9 - 3.0
12 - 22
110
3.0 - 8.0
12 - 22
8.0 - 16.0
12 - 22
111
1. Flash fuse bits
Notes:
Recommended Range for Capacitors
C1 and C2 for Use with Crystals (pF)
2.
CLKSELR register bits
3.
This option should not be used with crystals, only with ceramic resonators
The CKSEL0 fuse together with the SUT1..0 fuses or CSEL0 together with CSUT1..0 field select the start-up times as shown
in Table 4-11.
Table 4-11. Start-up Times for the Crystal Oscillator Clock Selection
CKSEL0(1)
CSEL0(2)
SUT1..0(1)
CSUT1..0(2)
Start-up Time from
Power-down/save
Additional Delay
from Reset
(VCC = 5.0V)
0
00
258 CK(3)
14CK + 4.1ms
Ceramic resonator, fast
rising power
0
01
258 CK(3)
14CK + 65ms
Ceramic resonator, slowly
rising power
0
10(5)
1K (1024) CK(4)
14CK
Ceramic resonator, BOD
enabled
0
11
1K (1024)CK(4)
14CK + 4.1ms
Ceramic resonator, fast
rising power
1
00
1K (1024)CK(4)
14CK + 65ms
Ceramic resonator, slowly
rising power
1
01(5)
16K (16384) CK
14CK
Crystal oscillator, BOD
enabled
1
10
16K (16384) CK
14CK + 4.1ms
Crystal oscillator, fast
rising power
1
11
16K (16384) CK
14CK + 65ms
Crystal oscillator, slowly
rising power
Notes:
50
1.
Recommended Usage
Flash fuse bits.
2.
CLKSELR register bits.
3.
These options should only be used when not operating close to the maximum frequency of the device, and
only if frequency stability at start-up is not important for the application. These options are not suitable for
crystals.
4.
These options are intended for use with ceramic resonators and will ensure frequency stability at start-up.
They can also be used with crystals when not operating close to the maximum frequency of the device, and if
frequency stability at start-up is not important for the application.
5.
This setting is only available if RSTDISBL fuse is not set.
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4.5.2.5 Low-frequency Crystal Oscillator
To use a 32.768kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by
setting CKSEL fuses or CSEL field as shown in Table 4-5 on page 47. The crystal should be connected as shown
in Figure 4-12. Refer to the 32.768kHz crystal oscillator application note for details on oscillator operation and how to choose
appropriate values for C1 and C2.
The 32.768kHz watch crystal oscillator can be used by the asynchronous timer if the (high-frequency) crystal oscillator is not
running or if the external clock is not enabled (see Section 4.5.3.3 “Enable/Disable Clock Source” on page 54). The
asynchronous timer is then able to start itself this low-frequency crystal oscillator.
Figure 4-12. Low-frequency Crystal Oscillator Connections
C1 = 12 to 22pF
XTAL2
32.768KHz
XTAL1
C2 = 12 to 22pF
GND
12 to 22pF capacitors may be necessary if parasitic
impedance (pads, wires and PCB) is very low.
When this oscillator is selected, start-up times are determined by the SUT fuses or by CSUT field as shown in Table 4-12.
Table 4-12. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
SUT1..0(1)
CSUT1..0(2)
Start-up Time from
Power-down/save
Additional Delay from
Reset (VCC = 5.0V)
Recommended Usage
00
1K (1024) CK(3)
4.1ms
Fast rising power or BOD enabled
01
1K (1024) CK(3)
65ms
Slowly rising power
10
32K (32768) CK
65ms
Stable frequency at start-up
Notes:
11
1.
Reserved
Flash fuse bits
2.
CLKSELR register bits
3.
These options should only be used if frequency stability at start-up is not important for the application
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4.5.2.6 External Clock
To drive the device from this external clock source, CLKI should be driven as shown in Figure 4-13. To run the device on an
external clock, the CKSEL Fuses or CSEL field must be programmed as shown in Table 4-5 on page 47.
Figure 4-13. External Clock Drive Configuration
~
(XTAL2)
(CLKO)
External
Clock
Signal
CLKI
(XTAL1)
GND
When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as shown in Table 4-13
This external clock can be used by the asynchronous timer if the high or low frequency Crystal Oscillator is not running (see
Section 4.5.3.3 “Enable/Disable Clock Source” on page 54). The asynchronous timer is then able to enable this input.
Table 4-13. Start-up Times for the External Clock Selection
SUT1..0(1)
CSUT1..0(2)
Notes:
Start-up Time from
Power-down/save
Additional Delay from Reset
(VCC = 5.0V)
(3)
Recommended Usage
00
6CK
14CK (+ 4.1ms )
01
6CK
14CK + 4.1ms
Fast rising power
10
6CK
14CK + 65ms
Slowly rising power
11
1.
Flash fuse bits
2.
CLKSELR register bits
3.
Additional delay (+ 4ms) available if RSTDISBL fuse is set
BOD enabled
Reserved
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still
ensuring stable operation. Refer to Section 4.5.4 “System Clock Prescaler” on page 58 for details.
4.5.2.7 Clock Output Buffer
If not using a crystal oscillator, the device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse or COUT bit of CLKSELR register has to be programmed. This option is useful when the device clock is needed to
drive other circuits on the system. Note that the clock will not be output during reset and the normal operation of I/O pin will
be overridden when the fuses are programmed. If the System Clock Prescaler is used, it is the divided system clock that is
output.
4.5.3
Dynamic Clock Switch
4.5.3.1 Features
The Atmel® ATtiny87/167 provides a powerful dynamic clock switch circuit that allows users to turn on and off clocks of the
device on the fly. The built-in de-glitching circuitry allows clocks to be enabled or disabled asynchronously. This enables
efficient power management schemes to be implemented easily and quickly. In a safety application, the dynamic clock
switch circuit allows continuous monitoring of the external clock permitting a fallback scheme in case of clock failure.
The control of the dynamic clock switch circuit must be supervised by software. This operation is facilitated by the following
features:
● Safe commands, to avoid unintentional commands, a special write procedure must be followed to change the
CLKCSR register bits (Section 4.5.5.2 “CLKPR – Clock Prescaler Register” on page 59)
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●
●
Exclusive action, the actions are controlled by a decoding table (commands) written to the CLKCSR register. This
ensures that only one command operation can be launched at any time. The main actions of the decoding table are:
●
‘Disable Clock Source’,
●
‘Enable Clock Source’,
●
‘Request Clock Availability’,
●
‘Clock Source Switching’,
●
‘Recover System Clock Source’,
●
‘Enable Watchdog in Automatic Reload Mode’.
Command status return. The ‘Request Clock Availability’ command returns status via the CLKRDY bit in the
CLKCSR register. The ‘Recover System Clock Source’ command returns a code of the current clock source in the
CLKSELR register. This information is used in the supervisory software routines as shown in
Section 4.5.3.7 on page 54.
4.5.3.2 CLKSELR Register
Fuses Substitution
At reset, bits of the Low Fuse Byte are copied into the CLKSELR register. The content of this register can subsequently be
user modified to overwrite the default values from the Low Fuse Byte. CKSEL3..0, SUT1..0 and CKOUT fuses correspond
respectively to CSEL3..0, CSUT1:0 and ~(COUT) bits of the CLKSELR register as shown in Figure 4-14 on page 53.
Source Selection
The available codes of clock source are given in Table 4-5 on page 47.
Figure 4-14. Fuses Substitution and Clock Source Selection
Fuse:
Register:
Fuse Low Byte
CLKSELR
CKSEL[3..0]
SEL
Decoder
R/W Reg.
SEL-1
SEL-2
CSEL [3..0]
CSUT [1..0]
COUT
SEL-n
Reset
Default
CLKSEL [3..0]
SUT [1..0]
CKOUT
Internal
Data Bus
SEL-0
Selected
Configuration
SUT[1..0]
SCLKRq(*)
CKOUT
EN-0
SEL
Encoder
EN-1
SCLKRq(*):Command of Clock Control and Status Register
EN-2
Clock
Switch
Current
Configuration
EN-n
The CLKSELR register contains the CSEL, CSUT and COUT values which will be used by the ‘Enable/Disable Clock
Source’, ‘Request for Clock Availability’ or ‘Clock Source Switching’ commands.
Source Recovering
The ‘Recover System Clock Source’ command updates the CKSEL field of CLKSELR register (see Section 4.5.3.6 “System
Clock Source Recovering” on page 54).
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4.5.3.3 Enable/Disable Clock Source
The ‘Enable Clock Source’ command selects and enables a clock source configured by the settings in the CLKSELR
register. CSEL3..0 will select the clock source and CSUT1:0 will select the start-up time (just as CKSEL and SUT fuse bits
do). To be sure that a clock source is operating, the ‘Request for Clock Availability’ command must be executed after the
‘Enable Clock Source’ command. This will indicate via the CLKRDY bit in the CLKCSR register that a valid clock source is
available and operational.
The ‘Disable Clock Source’ command disables the clock source indicated by the settings of CLKSELR register (only
CSEL3..0). If the clock source indicated is currently the one that is used to drive the system clock, the command is not
executed.
Because the selected configuration is latched at clock source level, it is possible to enable many clock sources at a given
time (ex: the internal RC oscillator for system clock + an oscillator with external crystal). The user (code) is responsible of
this management.
4.5.3.4 COUT Command
The ‘CKOUT’ command allows to drive the CLKO pin. Refer to Section 4.5.2.7 “Clock Output Buffer” on page 52 for using.
4.5.3.5 Clock Availability
‘Request for Clock Availability’ command enables a hardware oscillation cycle counter driven by the selected source clock,
CSEL3..0. The count limit value is determined by the settings of CSUT1..0. The clock is declared ready (CLKRDY = 1) when
the count limit value is reached. The CLKRDY flag is reset when the count starts. Once set, this flag remains unchanged
until a new count is commanded. To perform this checking, the CKSEL and CSUT fields should not be changed while the
operation is running.
Note that once the new clock source is selected (‘Enable Clock Source’ command), the count procedure is automatically
started. The user (code) should wait for the setting of the CLKRDY flag in CLKSCR register before using a newly selected
clock.
At any time, the user (code) can ask for the availability of a clock source. The user (code) can request it by writing the
‘Request for Clock Availability’ command in the CLKSCR register. A full polling of the status of clock sources can thus be
done.
4.5.3.6 System Clock Source Recovering
The ‘Recover System Clock Source’ command returns the current clock source used to drive the system clock as per Table
4-5 on page 47. The CKSEL field of CLKSELR register is then updated with this returned value. There is no information on
the SUT used or status on CKOUT.
4.5.3.7 Clock Switching
To drive the system clock, the user can switch from the current clock source to any other of the following ones (one of them
being the current clock source):
1. Calibrated internal RC oscillator 8.0MHz,
2.
Internal watchdog oscillator 128kHz,
3.
External clock,
4.
External low-frequency oscillator,
5.
External crystal/ceramic resonator.
The clock switching is performed by a sequence of commands. First, the user (code) must make sure that the new clock
source is operating. Then the ‘Clock Source Switching’ command can be issued. Once this command has been successfully
completed using the ‘Recover System Clock Source’ command, the user (code) may stop the previous clock source. It is
strongly recommended to run this sequence only once the interrupts have been disabled. The user (code) is responsible for
the correct implementation of the clock switching sequence.
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Here is a “light” C-code that describes such a sequence of commands.
C Code Example
void ClockSwiching (unsigned char clk_number, unsigned char sut) {
#define
#define
#define
#define
CLOCK_RECOVER
CLOCK_ENABLE
CLOCK_SWITCH
CLOCK_DISABLE
0x05
0x02
0x04
0x01
unsigned char previous_clk, temp;
// Disable interrupts
temp = SREG; asm (“cli”);
// Save the current system clock source
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_RECOVER;
previous_clk = CLKSELR & 0x0F;
// Enable the new clock source
CLKSELR = ((sut << 4) & 0x30) | (clk_number & 0x0F);
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_ENABLE;
// Wait for clock validity
while ((CLKCSR & (1 << CLKRDY)) == 0);
// Switch clock source
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_SWITCH;
// Wait for effective switching
while (1)
{
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_RECOVER;
if ((CLKSELR & 0x0F) == (clk_number & 0x0F)) break;
}
// Shut down unneeded clock source
if (previous_clk != (clk_number & 0x0F)) {
CLKSELR = previous_clk;
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_DISABLE;
}
// Re-enable interrupts
SREG = temp;
}
Warning:
In the Atmel® ATtiny87/167, only one among the three external clock sources can be enabled at a given time.
Moreover, the enables of the external clock and of the external low-frequency oscillator are shared with the
asynchronous timer.
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4.5.3.8 Clock Monitoring
A safe system needs to monitor its clock sources. Two domains need to be monitored:
● Clock sources for peripherals,
●
Clocks sources for system clock generation.
In the first domain, the user (code) can easily check the validity of the clock(s) (see Section 4.5.3.4 “COUT Command” on
page 54). In the second domain, the lack of a clock results in the code not running. Thus, the presence of the system clock
needs to be monitored by hardware.
Using the on-chip watchdog allows this monitoring. Normally, the watchdog reloading is performed only if the code reaches
some specific software labels, reaching these labels proves that the system clock is running. Otherwise the watchdog reset
is enabled. This behavior can be considered as a clock monitoring.
If the standard watchdog functionality is not desired, the Atmel® ATtiny87/167 watchdog permits the system clock to be
monitored without having to resort to the complexity of a full software watchdog handler. The solution proposed in the Atmel
ATtiny87/167 is to automate the watchdog reloading with only one command, at the beginning of the session.
So, to monitor the system clock, the user will have two options:
1. Using the standard watchdog features (software reload),
2.
Or using the automatic reloading (hardware reload).
The two options are exclusive.
Warning:
These two options make sense ONLY if the clock source at RESET is an INTERNAL SOURCE. The fuse
settings determine this operation.
Figure 4-15. Watchdog Timer with Automatic Reloading
WD
Interrupt
Watchdog
WD
Reset
Watchdog Clock
Reload
WDIE
WDE
WDTCSR
WDIF
Register:
WDP
[3..0]
0
Automatic
Reolading
Mode
1
Enable
Checker
System CLK
Internal Bus
The ‘Enable Watchdog in Automatic Reload Mode’ command has priority over the standard watchdog enabling. In this mode,
only the reset function of the watchdog is enabled (no more watchdog interrupt). The WDP3..0 bits of the WDTCSR register
always determine the watchdog timer prescaling.
As the watchdog will not be active before executing the ‘Enable Watchdog in Automatic Reload Mode’ command, it is
recommended to activate this command before switching to an external clock source (See following notes).
Notes:
56
1.
ONLY the reset (watchdog reset included) disables this function. The Watchdog System Reset Flag (WDRF bit
of MCUSR register) can be used to monitor the reset cause.
2.
ONLY clock frequencies ≥ (4 WatchDog Clock frequency) can be monitored.
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Here is a “light” C-code of a clock switching function using automatic clock monitoring.
C Code Example
void ClockSwiching (unsigned char clk_number, unsigned char sut) {
CLOCK_RECOVER
CLOCK_ENABLE
CLOCK_SWITCH
CLOCK_DISABLE
WD_ARL_ENABLE
0x05
0x02
0x04
0x01
0x06
#define WD_2048CYCLES
0x07
#define
#define
#define
#define
#define
unsigned char previous_clk, temp;
// Disable interrupts
temp = SREG; asm (“cli”);
// Save the current system clock source
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_RECOVER;
previous_clk = CLKSELR & 0x0F;
// Enable the new clock source
CLKSELR = ((sut << 4) & 0x30) | (clk_number & 0x0F);
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_ENABLE;
// Wait for clock validity
while ((CLKCSR & (1 << CLKRDY)) == 0);
// Enable the watchdog in automatic reload mode
WDTCSR = (1 << WDCE) | (1 << WDE);
WDTCSR = (1 << WDE) | WD_2048CYCLES;
CLKCSR = 1 << CLKCCE;
CLKCSR = WD_ARL_ENABLE;
// Switch clock source
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_SWITCH;
// Wait for effective switching
while (1)
{
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_RECOVER;
if ((CLKSELR & 0x0F) == (clk_number & 0x0F)) break;
}
// Shut down unneeded clock source
if (previous_clk != (clk_number & 0x0F)) {
CLKSELR = previous_clk;
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_DISABLE;
}
// Re-enable interrupts
SREG = temp;
}
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4.5.4
System Clock Prescaler
4.5.4.1 Features
The Atmel® ATtiny87/167 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be
used to decrease power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and
clkFLASH are divided by a factor as shown in Table 4-14 on page 60.
4.5.4.2 Switching Time
When switching between prescaler settings, the system clock prescaler ensures that no glitches occur in the clock system
and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the
clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the
CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were readable, and the
exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 T2 before the new clock frequency is
active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period
corresponding to the new prescaler setting.
4.5.5
Register Description
4.5.5.1 OSCCAL – Oscillator Calibration Register
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OSCCAL
Device Specific Calibration Value
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process variations from the
oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator
frequency of 8.0MHz at 25°C. The application software can write this register to change the oscillator frequency. The
oscillator can be calibrated to any frequency in the range 7.3 - 8.1MHz within ±2% accuracy. Calibration outside that range is
not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected
accordingly. If the EEPROM or flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or flash
write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range,
setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of
OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in
that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1 will give a frequency
increment of less than 2% in the frequency range 7.3 - 8.1MHz.
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4.5.5.2 CLKPR – Clock Prescaler Register
Bit
7
6
5
4
CLKPCE
–
–
–
Read/Write
R/W
R
R
R
Initial Value
0
0
0
0
3
2
1
0
CLKPS3 CLKPS2 CLKPS1 CLKPS0
R/W
R/W
R/W
CLKPR
R/W
See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the
other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when
the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor
clear the CLKPCE bit.
• Bits 6:4 – Res: Reserved Bits
These bits are reserved bits in the Atmel® ATtiny87/167 and will always read as zero.
• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits can be
written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input
to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are
given in Table 4-14.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:
1. Write the clock prescaler change enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting in order not to disturb the procedure.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset
to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of eight at start up. This feature
should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present
operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The
application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the
CKDIV8 Fuse programmed.
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Table 4-14. Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
0
0
1
1
8
0
1
0
0
16
0
1
0
1
32
0
1
1
0
64
0
1
1
1
128
1
0
0
0
256
1
0
0
1
Reserved
1
0
1
0
Reserved
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
4.5.5.3 CLKCSR – Clock Control and Status Register
Bit
7
6
5
4
3
2
1
0
CLKCCE
–
–
CLKRDY
CLKC3
CLKC2
CLKC1
CLKC0
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
CLKCSR
• Bit 7 – CLKCCE: Clock Control Change Enable
The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The CLKCCE bit is only updated when
the other bits in CLKCSR are simultaneously written to zero. CLKCCE is cleared by hardware four cycles after it is written or
when the CLKCSR bits are written. Rewriting the CLKCCE bit within this time-out period does neither extend the time-out
period, nor clear the CLKCCE bit.
• Bits 6:5 – Res: Reserved Bits
These bits are reserved bits in the Atmel® ATtiny87/167 and will always read as zero.
• Bits 4 – CLKRDY: Clock Ready Flag
This flag is the output of the ‘Clock Availability’ logic.
This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’ command being entered.
It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is stable. The delay from the request
and the flag setting is not fixed, it depends on the clock start-up time, the clock frequency and, of course, if the clock is alive.
The user’s code has to differentiate between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’ condition.
• Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0
These bits define the command to provide to the ‘Clock Switch’ module. The special write procedure must be followed to
change the CLKC3..0 bits (See ”Bit 7 – CLKCCE: Clock Control Change Enable” on page 60.).
1. Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in CLKCSR to zero.
2.
Within 4 cycles, write the desired value to CLKCSR register while clearing CLKCCE bit.
Interrupts should be disabled when setting CLKCSR register in order not to disturb the procedure.
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Table 4-15. Clock Command List
Clock Command
CLKC3..0
No command
0000 b
Disable clock source
0001 b
Enable clock source
0010 b
Request for clock availability
0011 b
Clock source switch
0100 b
Recover system clock source code
0101 b
Enable watchdog in automatic reload mode
0110 b
CKOUT command
0111 b
No command
1xxx b
4.5.5.4 CLKSELR - Clock Selection Register
Bit
7
6
5
4
3
2
1
0
-
COUT
CSUT1
CSUT0
CSEL3
CSEL2
CSEL1
CSEL0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
~ (CKOUT)
fuse
SUT1..0
fuses
CLKSELR
CKSEL3..0
fuses
• Bit 7– Res: Reserved Bit
This bit is reserved bit in the Atmel® ATtiny87/167 and will always read as zero.
• Bit 6 – COUT: Clock Out
The COUT bit is initialized with ~(CKOUT) Fuse bit.
The COUT bit is only used in case of ‘CKOUT’ command. Refer to Section 4.5.2.7 “Clock Output Buffer” on page 52 for
using.
In case of ‘Recover System Clock Source’ command, COUT it is not affected (no recovering of this setting).
• Bits 5:4 – CSUT1:0: Clock Start-up Time
CSUT bits are initialized with the values of SUT Fuse bits.
In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock start-up time. Refer to
subdivisions of Section 4.5.2 “Clock Sources” on page 47 for code of clock start-up times.
In case of ‘Recover System Clock Source’ command, CSUT field is not affected (no recovering of SUT code).
• Bits 3:0 – CSEL3:0: Clock Source Select
CSEL bits are initialized with the values of CKSEL Fuse bits.
In case of ‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source Switch’ command, CSEL field
provides the code of the clock source. Refer to Table 4-5 on page 47 and subdivisions of Section 4.5.2 “Clock Sources” on
page 47 for clock source codes.
In case of ‘Recover System Clock Source’ command, CSEL field contains the code of the clock source used to drive the
Clock Control Unit as described in Figure 4-10 on page 46.
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4.6
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR® provides
various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
When enabled, the brown-out detector (BOD) actively monitors the power supply voltage during the sleep periods. To further
save power, it is possible to disable the BOD in some sleep modes. See Section 4.6.2 “BOD Disable” on page 62 for more
details.
4.6.1
Sleep Modes
Figure 4-10 on page 46 presents the different clock systems in the Atmel® ATtiny87/167, and their distribution. The figure is
helpful in selecting an appropriate sleep mode. Table 4-16 shows the different sleep modes, their wake up sources and BOD
disable ability.
Table 4-16. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Timer0
Other I/O
X
X
X
X
X
X
X
X
X
X(1)
X
X
X
X
X
X(1)
X
X
(1)
X
X
Power-down
Power-Save
X
Notes: 1. For INT1 and INT0, only level interrupt
X
X
Software
BOD Disable
USI Start Condition
X
SPM/EEPROM
Ready
X
INT1, INT0 and
Pin Change
X
Timer0 Osc.
Enable
X
Main Clock
Source Enabled
X
clkASY
WDT
Wake-up Sources
X
clkADC
clkIO
X
Oscillators
ADC
Idle
ADC Noise
Reduction
clkFLASH
Sleep Mode
clkCPU
Active Clock Domains
X
X
X
To enter any of the four sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be
executed. The SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC noise reduction, power-down,
or power-save) will be activated by the SLEEP instruction. See Table 4-17 on page 65 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles
in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP.
The contents of the register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during
sleep mode, the MCU wakes up and executes from the reset vector.
4.6.2
BOD Disable
When the brown-out detector (BOD) is enabled by BODLEVEL fuses, Table 4-69 on page 223, the BOD is actively
monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for
some of the sleep modes, see Table 4-16. The sleep mode power consumption will then be at the same level as when BOD
is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the
sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the VCC
level has dropped during the sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60µs to ensure that the BOD is
working correctly before the MCU continues executing code.
BOD disable is controlled by BODS bit (BOD Sleep) in the control register MCUCR, see Section 4.6.9.2 “MCUCR – MCU
Control Register” on page 65. Setting it to one turns off the BOD in relevant sleep modes, while a zero in this bit keeps BOD
active. Default setting keeps BOD active, i.e. BODS is cleared to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see Section 4.6.9.2 “MCUCR – MCU Control
Register” on page 65.
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4.6.3
Idle Mode
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but
allowing the SPI, analog comparator, ADC, USI start condition, asynchronous Timer/Counter, watchdog, and the interrupt
system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the SPI interrupts. If
wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the
ACD bit in the analog comparator control and status register – ACSR. This will reduce power consumption in Idle mode. If
the ADC is enabled, a conversion starts automatically when this mode is entered.
4.6.4
ADC Noise Reduction Mode
When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC noise reduction mode, stopping
the CPU but allowing the ADC, the external interrupts, the USI start condition, the asynchronous Timer/Counter and the
watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a
conversion starts automatically when this mode is entered. Apart from the ADC conversion complete interrupt, only an
external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a USI start condition interrupt, an
asynchronous Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or INT1 or a
pin change interrupt can wake up the MCU from ADC noise reduction mode.
4.6.5
Power-down Mode
When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter power-down mode. In this mode, the
external oscillator is stopped, while the external interrupts, the USI start condition, and the Watchdog continue operating (if
enabled). Only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, the USI start condition
interrupt, an external level interrupt on INT0 or INT1, or a pin change interrupt can wake up the MCU. This sleep mode
basically halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some
time to wake up the MCU. Refer to Section 4.9 “External Interrupts” on page 79 for details.
When waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes
effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the
same CKSEL fuses that define the reset time-out period, as described in Section 4.5.2 “Clock Sources” on page 47.
4.6.6
Power-save Mode
When the SM1..0 bits are written to 11, the SLEEP instruction makes the MCU enter power-save mode. This mode is
identical to power-down, with one exception:
If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0 will run during sleep. The
device can wake up from either timer overflow or output compare event from Timer/Counter0 if the corresponding
Timer/Counter0 interrupt enable bits are set in TIMSK0, and the global interrupt enable bit in SREG is set.
If the asynchronous timer is NOT clocked asynchronously, power-down mode is recommended instead of power-save mode
because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in powersave mode if AS0 is 0.
This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous modules, including
Timer/Counter0 if clocked asynchronously.
4.6.7
Power Reduction Register
The power reduction register (PRR), see Section 4.6.9.3 “PRR – Power Reduction Register” on page 66, provides a method
to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the
I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied,
hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by
clearing the bit in PRR, puts the module in the same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all
other sleep modes, the clock is already stopped.
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4.6.8
Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR® controlled system. In
general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as
possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following
modules may need special consideration when trying to achieve the lowest possible power consumption.
4.6.8.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any
sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to Section
4.18 “ADC – Analog to Digital Converter” on page 191 for details on ADC operation.
4.6.8.2 Analog Comparator
When entering Idle mode, the analog comparator should be disabled if not used. When entering ADC noise reduction mode,
the analog comparator should be disabled. In other sleep modes, the analog comparator is automatically disabled. However,
if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in
all sleep modes. Otherwise, the internal voltage reference will be enabled, independent of sleep mode. Refer to Section 4.19
“AnaComp - Analog Comparator” on page 209 for details on how to configure the analog comparator.
4.6.8.3 Brown-out Detector
If the brown-out detector is not needed by the application, this module should be turned off. If the brown-out detector is
enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption. Refer to Section 4.7.1.5 “Brown-out Detection”
on page 69 for details on how to configure the brown-out detector.
4.6.8.4 Internal Voltage Reference
The internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the ADC.
If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will
not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If
the reference is kept on in sleep mode, the output can be used immediately. Refer to Section 4.7.2 “Internal Voltage
Reference” on page 70 for details on the start-up time.
Output the internal voltage reference is not needed in the deeper sleep modes. This module should be turned off to reduce
significantly to the total current consumption. Refer to Section 4.17.3.1 “AMISCR – Analog Miscellaneous Control Register”
on page 190 for details on how to disable the internal voltage reference output.
4.6.8.5 Internal Current Source
The internal current source is not needed in the deeper sleep modes. This module should be turned off to reduce
significantly to the total current consumption. Refer to Section 4.17.3.1 “AMISCR – Analog Miscellaneous Control Register”
on page 190 for details on how to disable the internal current source.
4.6.8.6 Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it
will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute
significantly to the total current consumption. Refer to Section 4.7.3 “Watchdog Timer” on page 71 for details on how to
configure the watchdog timer.
4.6.8.7 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure
that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped,
the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section
Section 4.10.2.6 “Digital Input Enable and Sleep Modes” on page 88 for details on which pins are enabled. If the input buffer
is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input
pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the digital input
disable registers (DIDR1 and DIDR0). Refer to Section 4.18.12.6 “DIDR1 – Digital Input Disable Register 1” on page 207 and
Section 4.18.12.5 “DIDR0 – Digital Input Disable Register 0” on page 207 for details.
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4.6.8.8 On-chip Debug System
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the main clock source is
enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current
consumption.
4.6.9
Register Description
4.6.9.1 SMCR – Sleep Mode Control Register
The sleep mode Control Register contains control bits for power management.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
SM1
SM0
SE
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SMCR
• Bits 7..3 Res: Reserved Bits
These bits are unused bits in the Atmel® ATtiny87/167, and will always read as zero.
• Bits 2..1 – SM1..0: Sleep Mode Select Bits 1, and 0
These bits select between the four available sleep modes as shown in Table 4-17.
Table 4-17. Sleep Mode Select
SM1
SM0
0
0
Sleep Mode
Idle
0
1
ADC noise reduction
1
0
Power-down
1
1
Power-save
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To
avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the sleep enable
(SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.
4.6.9.2 MCUCR – MCU Control Register
Bit
7
6
5
4
3
2
1
0
–
BODS
BODSE
PUD
–
–
–
–
Read/Write
R
R/W
R/W
R/W
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 4-16 on page 62. Writing to the
BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR. To disable BOD in relevant sleep modes,
both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be
set to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to
turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed
sequence.
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4.6.9.3 PRR – Power Reduction Register
Bit
7
6
5
4
3
2
1
0
–
–
PRLIN
PRSPI
PRTIM1
PRTIM0
PRUSI
PRADC
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PRR
• Bit 7 - Res: Reserved bit
This bit is reserved in Atmel® ATtiny87/167 and will always read as zero.
• Bit 6 - Res: Reserved bit
This bit is reserved in Atmel ATtiny87/167 and will always read as zero.
• Bit5 - PRLIN: Power Reduction LIN / UART controller
Writing a logic one to this bit shuts down the LIN by stopping the clock to the module. When waking up the LIN again, the LIN
should be re initialized to ensure proper operation.
• Bit 4 - PRSPI: Power Reduction Serial Peripheral Interface
If using debugWIRE on-chip debug System, this bit should not be written to one.
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up
the SPI again, the SPI should be re initialized to ensure proper operation.
• Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will
continue like before the shutdown.
• Bit 2 - PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module in synchronous mode (AS0 is 0). When the
Timer/Counter0 is enabled, operation will continue like before the shutdown.
• Bit 1 - PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the
USI should be re-initialized to ensure proper operation.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator
cannot use the ADC input MUX when the ADC is shut down.
4.7
System Control and Reset
4.7.1
Reset
4.7.1.1 Resetting the AVR
During reset, all I/O registers are set to their initial values, and the program starts execution from the reset vector. The
instruction placed at the reset vector must be an RJMP – relative jump – instruction to the reset handling routine. If the
program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at
these locations. The circuit diagram in Figure 4-16 shows the reset circuit. Tables in Section 4.23.3 “RESET Characteristics”
on page 239 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR® are immediately reset to their initial state when a reset source goes active. This does not require
any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to
reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through
the SUT and CKSEL Fuses. The different selections for the delay period are presented in Section 4.5.2 “Clock Sources” on
page 47.
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4.7.1.2 Reset Sources
The Atmel® ATtiny87/167 has four sources of reset:
● Power-on reset: The MCU is reset when the supply voltage is below the power-on reset threshold (VPOT).
●
External reset: The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse
length.
●
Watchdog system reset: The MCU is reset when the watchdog Timer period expires and the watchdog system reset
mode is enabled.
●
Brown-out reset: The MCU is reset when the supply voltage VCC is below the brown-out reset threshold (VBOT) and the
brown-out detector is enabled.
Figure 4-16. Reset Circuit
DATA BUS
WDRF
BORF
EXTRF
PORF
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
VCC
Pull-up Resistor
RSTDISBL
Reset Circuit
S
Q
RESET
Spike
Filter
COUNTER RESET
R
Watchdog
Timer
INTERNAL RESET
Brown-out
Reset Circuit
BODLEVEL [2..0]
Watchdog
Oscillator
Clock
Generator
CK
Delay Counters
TIMEOUT
CKSEL [3..0]
SUT [1..0]
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4.7.1.3 Power-on Reset
A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in Table 4-84 on
page 240. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the startup reset, as well as to detect a failure in supply voltage.
A power-on reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold
voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal
is activated again, without any delay, when VCC decreases below the detection level.
Figure 4-17. MCU Start-up, RESET Tied to VCC
V CCRR
VPORMAX
V CC
VPOT
VPORMIN
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 4-18. MCU Start-up, RESET Extended Externally
V CCRR
V CC
VPOR
RESET
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
4.7.1.4 External Reset
An external reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see
Table 4-83 on page 239) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate
a reset. When the applied signal reaches the reset threshold voltage – VRST – on its positive edge, the delay counter starts
the MCU after the time-out period – tTOUT – has expired. The external reset can be disabled by the RSTDISBL fuse, see
Table 4-70 on page 223.
Figure 4-19. External Reset During Operation
VCC
RESET
V RST
tTOUT
TIME-OUT
INTERNAL
RESET
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4.7.1.5 Brown-out Detection
Atmel® ATtiny87/167 has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level during operation by
comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL fuses (Table 4-85 on
page 240). The trigger level has a hysteresis to ensure spike free brown-out detection. The hysteresis on the detection level
should be interpreted as VBOT+ = VBOT + VHYST / 2 and VBOT– = VBOT – VHYST / 2.
When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT– in Figure 4-20), the brown-out reset
is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 4-20), the delay counter starts the
MCU after the time-out period tTOUT has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in
Table 4-86 on page 240.
Figure 4-20. Brown-out Reset During Operation
V CC
VBOT-
VBOT+
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
4.7.1.6 Watchdog System Reset
When the watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse,
the delay timer starts counting the time-out period tTOUT. Refer to Section 4.7.3 “Watchdog Timer” on page 71 for details on
operation of the watchdog timer.
Figure 4-21. Watchdog System Reset During Operation
V CC
RESET
1 CK Cycle
WD
TIME-OUT
RESET
TIME-OUT
tTOUT
INTERNAL
RESET
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4.7.1.7 MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
WDRF
BORF
EXTRF
PORF
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
MCUSR
See Bit Description
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the Atmel® ATtiny87/167, and will always read as zero.
• Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a watchdog system reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as
possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by
examining the reset flags.
4.7.2
Internal Voltage Reference
Atmel ATtiny87/167 features an internal bandgap reference. This reference is used for brown-out detection, and it can be
used as an input to the analog comparator or the ADC.
4.7.2.1 Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in
Table 4-87 on page 240. To save power, the reference is not always turned on. The reference is on during the following
situations:
1. When the BOD is enabled (by programming the BODLEVEL [2:0] fuses).
2.
When the bandgap reference is connected to the analog comparator (by setting the ACIRS bit in ACSR).
3.
When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACIRS bit or enabling the ADC, the user must always allow the
reference to start up before the output from the analog comparator or ADC is used. To reduce power consumption in powerdown mode or in power-save, the user can avoid the three conditions above to ensure that the reference is turned off before
entering in these power reduction modes.
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4.7.3
Watchdog Timer
Atmel® ATtiny87/167 has an Enhanced Watchdog Timer (WDT). The main features are:
● Clocked from separate on-chip oscillator
●
●
●
4 operating modes
●
Interrupt
●
System reset
●
Interrupt and system reset
●
Clock monitoring
Selectable time-out period from 16ms to 8s
Possible hardware fuse watchdog always on (WDTON) for fail-safe mode
4.7.3.1 Watchdog Timer Behavior
The watchdog timer (WDT) is a timer counting cycles of a separate on-chip 128KHz oscillator.
Figure 4-22. Watchdog Timer
~128kHz
Oscillator
OSC/1024K
OSC/256K
OSC/512K
OSC/64K
OSC/128K
OSC/32K
OSC/8K
OSC/16K
WATCHDOG
RESET
OSC/4K
OSC/2K
Watchdog
Prescaler
WDP0
WDP1
WDP2
WDP3
CLOCK
MONITORING
MCU RESET
WDE
WDIF
INTERRUPT
WDIE
The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it
is required that the system uses the WDR - watchdog timer reset - instruction to restart the counter before the time-out value
is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.
In interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from
sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations,
giving an interrupt when the operation has run longer than expected. In system reset mode, the WDT gives a reset when the
timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and
system reset mode, combines the other two modes by first giving an interrupt and then switch to system reset mode. This
mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
The watchdog always on (WDTON) fuse, if programmed, will force the watchdog timer to system reset mode. With the fuse
programmed the system reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further
ensure program security, alterations to the watchdog set-up must follow timed sequences. The sequence for clearing WDE
and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the watchdog change enable bit (WDCE) and WDE. A logic one must
be written to WDE regardless of the previous value of the WDE bit.
2.
Within the next four clock cycles, write the WDE and watchdog prescaler bits (WDP) as desired, but with the
WDCE bit cleared. This must be done in one operation.
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The following code example shows one assembly and one C function for turning off the watchdog timer. The example
assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the
execution of these functions.
Assembly Code Example(1)
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in
r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out
MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
lds r16, WDTCR
ori
r16, (1<<WDCE) | (1<<WDE)
sts WDTCR, r16
; Turn off WDT
ldi
r16, (0<<WDE)
sts WDTCR, r16
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
__enable_interrupt();
}
Notes:
72
1.
See Section 4.2.7 “About Code Examples” on page 29.
2.
If the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. If the code is not set up to
handle the watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation,
the application software should always clear the watchdog system reset flag (WDRF) and the
WDE control bit in the initialization routine, even if the watchdog is not in use.
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog
Timer.
Assembly Code Example(1)
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
lds r16, WDTCR
ori
r16, (1<<WDCE) | (1<<WDE)
sts WDTCR, r16
; -- Got four cycles to set the new values from here ; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi
r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCR, r16
; -- Finished setting new values, used 2 cycles ; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed sequence */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Notes:
1.
See Section 4.2.7 “About Code Examples” on page 29.
2.
The Watchdog Timer should be reset before any change of the WDP bits, since a change
in the WDP bits can result in a time-out when switching to a shorter time-out period.
4.7.3.2 Clock Monitoring
The Watchdog Timer can be used to detect a loss of system clock. This configuration is driven by the dynamic clock switch
circuit. Please refer to Section 4.5.3.8 “Clock Monitoring” on page 56 for more information.
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4.7.3.3 Watchdog Timer Control Register - WDTCR
Bit
7
6
5
4
3
2
1
0
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
X
0
0
0
WDTCR
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the watchdog timer and the watchdog timer is configured for interrupt. WDIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a
logic one to the flag. When the I-bit in SREG and WDIE are set, the watchdog time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the status register is set, the Watchdog Interrupt is enabled. If WDE is cleared
in combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is executed if timeout in the watchdog timer occurs.
If WDE is set, the watchdog timer is in interrupt and system reset mode. The first time-out in the watchdog timer will set
WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the watchdog
goes to system reset mode). This is useful for keeping the watchdog timer security while using the interrupt. To stay in
interrupt and system reset mode, WDIE must be set after each interrupt. This should however not be done within the
interrupt service routine itself, as this might compromise the safety-function of the watchdog system reset mode. If the
interrupt is not executed before the next time-out, a system reset will be applied.
If the watchdog timer is used as clock monitor (c.f. Section • “Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0” on page 60), the
system reset mode is enabled and the interrupt mode is automatically disabled.
Table 4-18. Watchdog Timer Configuration
Clock
Monitor
WDTON
WDE
WDIE
Mode
Action on Time-out
x
0
0
0
Stopped
None
(1)
(1)
(1)
System reset mode
Reset
On
y
Off
Note:
1.
y
y
0
0
1
Interrupt mode
Interrupt
0
1
0
System reset mode
Reset
0
1
1
Interrupt and system reset mode
Interrupt, then go to system reset
mode
1
x
x
System reset mode
Reset
At least one of these three enables (WDTON, WDE and WDIE) equal to 1
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler
bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF
must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the
failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the watchdog timer prescaling when the watchdog timer is running. The different prescaling
values and their corresponding time-out periods are shown in Table 4-19 on page 75.
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Table 4-19. Watchdog Timer Prescale Select
WDP3
WDP2
WDP1
WDP0
Number of
WDT Oscillator Cycles
Typical Time-out
at VCC = 5.0V
0
0
0
0
2K (2048) cycles
16ms
0
0
0
1
4K (4096) cycles
32ms
0
0
1
0
8K (8192) cycles
64ms
0
0
1
1
16K (16384) cycles
0.125s
0
1
0
0
32K (32768) cycles
0.25s
0
1
0
1
64K (65536) cycles
0.5s
0
1
1
0
128K (131072) cycles
1.0s
0
1
1
1
256K (262144) cycles
2.0s
1
0
0
0
512K (524288) cycles
4.0s
1
0
0
1
1024K (1048576) cycles
8.0s
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Reserved
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4.8
Interrupts
This section describes the specifics of the interrupt handling as performed in Atmel® ATtiny87/167. For a general explanation
of the AVR® interrupt handling, refer to Section 4.3.7 “Reset and Interrupt Handling” on page 36.
4.8.1
Innterrupt Vectors in Atmel ATtiny87/167
Table 4-20. Reset and Interrupt Vectors in Atmel ATtiny87/167
76
Program Address
Vector
Nb.
ATtiny87
ATtiny167
Source
Interrupt Definition
1
0x0000
0x0000
RESET
External pin, power-on reset, brown-out reset
and watchdog system reset
2
0x0001
0x0002
INT0
External interrupt request 0
3
0x0002
0x0004
INT1
External interrupt request 1
4
0x0003
0x0006
PCINT0
Pin change interrupt request 0
5
0x0004
0x0008
PCINT1
Pin change interrupt request 1
6
0x0005
0x000A
WDT
Watchdog time-out interrupt
7
0x0006
0x000C
TIMER1 CAPT
Timer/Counter1 capture event
8
0x0007
0x000E
TIMER1 COMPA
Timer/Counter1 compare match A
9
0x0008
0x0010
TIMER1 COMPB
Timer/Coutner1 compare match B
10
0x0009
0x0012
TIMER1 OVF
Timer/Counter1 overflow
11
0x000A
0x0014
TIMER0 COMPA
Timer/Counter0 compare match A
12
0x000B
0x0016
TIMER0 OVF
Timer/Counter0 overflow
13
0x000C
0x0018
LIN TC
LIN/UART transfer complete
14
0x000D
0x001A
LIN ERR
LIN/UART error
15
0x000E
0x001C
SPI, STC
SPI Serial transfer complete
16
0x000F
0x001E
ADC
ADC conversion complete
17
0x0010
0x0020
EE READY
EEPROM ready
18
0x0011
0x0022
ANALOG COMP
Analog comparator
19
0x0012
0x0024
USI START
USI start condition detection
20
0x0013
0x0026
USI OVF
USI counter overflow
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4.8.2
Program Setup in ATtiny87
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny87 is (2-byte step - using
“rjmp” instruction):
Address(1)
Label Code
Comments
0x0000
rjmp
RESET
; Reset Handler
0x0001
rjmp
INT0addr
; IRQ0 Handler
0x0002
rjmp
INT1addr
; IRQ1 Handler
0x0003
rjmp
PCINT0addr
; PCINT0 Handler
0x0004
rjmp
PCINT1addr
; PCINT1 Handler
0x0005
rjmp
WDTaddr
; Watchdog Timer Handler
0x0006
rjmp
ICP1addr
; Timer1 Capture Handler
0x0007
rjmp
OC1Aaddr
; Timer1 Compare A Handler
0x0008
rjmp
OC1Baddr
; Timer1 Compare B Handler
0x0009
rjmp
OVF1addr
; Timer1 Overflow Handler
0x000A
rjmp
OC0Aaddr
; Timer0 Compare A Handler
0x000B
rjmp
OVF0addr
; Timer0 Overflow Handler
0x000C
rjmp
LINTCaddr
; LIN Transfer Complete Handler
0x000D
rjmp
LINERRaddr
; LIN Error Handler
0x000E
rjmp
SPIaddr
; SPI Transfer Complete Handler
0x000F
rjmp
ADCCaddr
; ADC Conversion Complete Handler
0x0010
rjmp
ERDYaddr
; EEPROM Ready Handler
0x0011
rjmp
ACIaddr
; Analog Comparator Handler
0x0012
rjmp
USISTARTaddr ; USI Start Condition Handler
0x0013
rjmp
USIOVFaddr
; USI Overflow Handler
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
...
...
Note:
RESET: ldi
r16, high(RAMEND); Main program start
out
SPH,r16
; Set Stack Pointer to top of RAM
ldi
r16, low(RAMEND)
out
SPL,r16
sei
; Enable interrupts
<instr> xxx
...
...
16-bit address
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4.8.3
Program Setup in ATtiny167
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny167 is (4-byte step using “jmp” instruction):
Address(1)
Label Code
Comments
0x0000
jmp
RESET
; Reset Handler
0x0002
jmp
INT0addr
; IRQ0 Handler
0x0004
jmp
INT1addr
; IRQ1 Handler
0x0006
jmp
PCINT0addr
; PCINT0 Handler
0x0008
jmp
PCINT1addr
; PCINT1 Handler
0x000A
jmp
WDTaddr
; Watchdog Timer Handler
0x000C
jmp
ICP1addr
; Timer1 Capture Handler
0x000E
jmp
OC1Aaddr
; Timer1 Compare A Handler
0x0010
jmp
OC1Baddr
; Timer1 Compare B Handler
0x0012
jmp
OVF1addr
; Timer1 Overflow Handler
0x0014
jmp
OC0Aaddr
; Timer0 Compare A Handler
0x0016
jmp
OVF0addr
; Timer0 Overflow Handler
0x0018
jmp
LINTCaddr
; LIN Transfer Complete Handler
0x001A
jmp
LINERRaddr
; LIN Error Handler
0x001C
jmp
SPIaddr
; SPI Transfer Complete Handler
0x001E
jmp
ADCCaddr
; ADC Conversion Complete Handler
0x0020
jmp
ERDYaddr
; EEPROM Ready Handler
0x0022
jmp
ACIaddr
; Analog Comparator Handler
0x0024
jmp
USISTARTaddr ; USI Start Condition Handler
0x0026
jmp
USIOVFaddr
; USI Overflow Handler
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
...
...
Note:
78
1.
RESET: ldi
r16, high(RAMEND); Main program start
out
SPH,r16
; Set Stack Pointer to top of RAM
ldi
r16, low(RAMEND)
out
SPL,r16
sei
; Enable interrupts
<instr> xxx
...
...
16-bit address
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4.9
External Interrupts
4.9.1
Overview
The external interrupts are triggered by the INT1..0 pins or any of the PCINT15..0 pins. Observe that, if enabled, the
interrupts will trigger even if the INT1..0 or PCINT15..0 pins are configured as outputs. This feature provides a way of
generating a software interrupt.
The pin change interrupt PCINT1 will trigger if any enabled PCINT15..8 pin toggles. The pin change interrupt PCINT0 will
trigger if any enabled PCINT7..0 pin toggles. The PCMSK1 and PCMSK0 registers control which pins contribute to the pin
change interrupts. pin change interrupts on PCINT15..0 are detected asynchronously. This implies that these interrupts can
be used for waking the part also from sleep modes other than Idle mode.
The INT1..0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification
for the external interrupt control register A – EICRA. When the INT1..0 interrupts are enabled and are configured as level
triggered, the interrupts will trigger as long as the pin is held low. The recognition of falling or rising edge interrupts on
INT1..0 requires the presence of an I/O clock, described in Section 4.5.1 “Clock Systems and their Distribution” on page 46.
Low level interrupts and the edge interrupt on INT1..0 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except idle
mode.
Note that if a level triggered interrupt is used for wake-up from power-down or power-save, the required level must be held
long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the
start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and
CKSEL fuses as described in Section 4.5.1 “Clock Systems and their Distribution” on page 46.
4.9.2
Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in Figure 4-23.
Figure 4-23. Timing of Pin Change Interrupts
0
pcint_sync
PCINT[I]
pin
D
Q
pin_lat
D
Q
pin_sync
pcint_in[i]
LE
D
Q
D
pcint_set/flag
Q
D
Q
PCIFn
(interrupt flag)
7
PCINT [I] bit
(of PCMSKn)
clk
clk
clk
PCINT[i] pin
pin_lat
pin_sync
pcint_in[i]
pcint_sync
pcint_set/flag
PCIFn
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4.9.3
External Interrupts Register Description
4.9.3.1 External Interrupt Control Register A – EICRA
The external interrupt control register A contains control bits for interrupt sense control.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
ISC11
ISC10
ISC01
ISC00
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EICRA
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the Atmel® ATtiny87/167, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.
The level and edges on the external INT1 pin that activate the interrupt are defined in Table 4-21. The value on the INT1 pin
is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low
level must be held until the completion of the currently executing instruction to generate an interrupt.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The external interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.
The level and edges on the external INT0 pin that activate the interrupt are defined in Table 4-21. The value on the INT0 pin
is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low
level must be held until the completion of the currently executing instruction to generate an interrupt.
Table 4-21. Interrupt Sense Control
ISCn1
ISCn0
Description
0
0
The low level of INTn generates an interrupt request.
0
1
Any logical change on INTn generates an interrupt request.
1
0
The falling edge of INTn generates an interrupt request.
1
1
The rising edge of INTn generates an interrupt request.
4.9.3.2 External Interrupt Mask Register – EIMSK
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
INT1
INT0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EIMSK
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel ATtiny87/167, and will always read as zero.
• Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the status register (SREG) is set (one), the external pin interrupt is enabled.
The interrupt sense control1 bits 1/0 (ISC11 and ISC10) in the external interrupt control register A (EICRA) define whether
the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an
interrupt request even if INT1 is configured as an output. The corresponding interrupt of external interrupt request 1 is
executed from the INT1 interrupt vector.
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• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the status register (SREG) is set (one), the external pin interrupt is enabled.
The interrupt sense control0 bits 1/0 (ISC01 and ISC00) in the external interrupt control register A (EICRA) define whether
the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an
interrupt request even if INT0 is configured as an output. The corresponding interrupt of external interrupt request 0 is
executed from the INT0 interrupt vector.
4.9.3.3 External Interrupt Flag Register – EIFR
Bit
7
6
5
4
3
2
1
0
–
–
–
–
Read/Write
R
R
R
R
–
–
INTF1
INTF0
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EIFR
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel® ATtiny87/167, and will always read as zero.
• Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG
and the INT1 bit in EIMSK are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG
and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
4.9.3.4 Pin Change Interrupt Control Register – PCICR
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
PCIE1
PCIE0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCICR
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel ATtiny87/167, and will always read as zero.
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled.
Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of pin change interrupt
request is executed from the PCI1 interrupt vector. PCINT15..8 pins are enabled individually by the PCMSK1 register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 0 is enabled. Any
change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is
executed from the PCI0 interrupt vector. PCINT7..0 pins are enabled individually by the PCMSK0 register.
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4.9.3.5 Pin Change Interrupt Flag Register – PCIFR
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
PCIF1
PCIF0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCIFR
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel® ATtiny87/167, and will always read as zero.
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and
the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and
the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
4.9.3.6 Pin Change Mask Register 1 – PCMSK1
Bit
7
6
5
4
3
2
PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10
1
0
PCINT9
PCINT8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK1
• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8
Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and
the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin
change interrupt on the corresponding I/O pin is disabled.
4.9.3.7 Pin Change Mask Register 0 – PCMSK0
Bit
7
6
5
4
3
2
1
0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK0
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the
PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
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4.10
I/O-Ports
4.10.1 Introduction
All AVR® ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction
of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI
instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors
(if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability.
The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with
a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 4-24.
Refer to Section 4.23 “Electrical Characteristics” on page 237 for a complete list of parameters.
Figure 4-24. I/O Pin Equivalent Schematic
Rpu
Pxn
Logic
Cpin
See Figure
”General Digital I/O”
for Details
All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for
the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the
precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The
physical I/O registers and bit locations are listed in Section 4.10.4 “Register Description for I/O Ports” on page 101.
Three I/O memory address locations are allocated for each port, one each for the data register – PORTx, data direction
register – DDRx, and the port input pins – PINx. The port input pins I/O location is read only, while the data register and the
data direction register are read/write. However, writing a logic one to a bit in the PINx register, will result in a toggle in the
corresponding bit in the data register. In addition, the pull-up disable – PUD bit in MCUCR or PUDx in PORTCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as general digital I/O is described in Section 4.10.2 “Ports as General Digital I/O” on page 84. Most port
pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes
with the port pin is described in Section 4.10.3 “Alternate Port Functions” on page 89. Refer to the individual module sections
for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as
general digital I/O.
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4.10.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 4-25 shows a functional description of one I/Oport pin, here generically called Pxn.
Figure 4-25. General Digital I/O(1)
PUD
Q
D
DDxn
Q
CLR
RESET
WDx
1
Q
Pxn
D
0
PORTxn
Q
CLR
WPx
RESET
SLEEP
DATA BUS
RDx
WRx
RRx
Synchronizer
RPx
D
Q
D
Q
PINxn
L
Q
Q
CLKI/O
PUD:
SLEEP:
CLKI/O:
Note:
84
1.
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PORTx REGISTER
WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD
are common to all ports.
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4.10.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Section 4.10.4 “Register Description
for I/O Ports” on page 101, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O
address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output
pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pullup resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are
tri-stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is
written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
4.10.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI assembler
instruction can be used to toggle one single bit in a port.
4.10.2.3 Break-before-make Switching
In the break-before-make mode when switching the DDRxn bit from input to output an immediate tri-state period lasting one
system clock cycle is introduced as indicated in Figure 4-26. For example, if the system clock is 4MHz and the DDRxn is
written to make an output, the immediate tri-state period of 250ns is introduced, before the value of PORTxn is seen on the
port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system clock cycles. The
break-before-make is a port-wise mode and it is activated by the port-wise BBMx enable bits. For further information about
the BBMx bits, see Section 4.10.3.2 “Port Control Register – PORTCR” on page 91. When switching the DDRxn bit from
output to input there is no immediate tri-state period introduced.
Figure 4-26. Break Before Make, Switching between Input and Output
SYSTEM CLOCK
R16
0x02
R17
0x01
INSTRUCTIOS
out DDRx, r16
PORTx
DDRx
nop
out DDRx, r17
0x55
0x01
0x02
Px0
0x01
tri-state
immediate tri-state cycle
Px1
tri-state
tri-state
immediate tri-state cycle
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4.10.2.4 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0, 0) and output high ({DDxn, PORTxn} = 1, 1), an intermediate state
with either pull-up enabled {DDxn, PORTxn} = 0, 1) or output low ({DDxn, PORTxn} = 1, 0) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR register or the PUDx bit in PORTCR register can be set to
disable all pull-ups in the port.
Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state
({DDxn, PORTxn} = 0, 0) or the output high state ({DDxn, PORTxn} = 1, 1) as an intermediate step.
Table 4-22 summarizes the control signals for the pin value.
Table 4-22. Port Pin Configurations
DDxn
PORTxn
PUD (in MCUCR)(1)
I/O
0
0
X
Input
No
Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if ext. pulled low.
0
1
1
Input
No
Tri-state (Hi-Z)
1
0
X
Output
No
Output low (sink)
1
X
Output
Or port-wise PUDx bit in PORTCR register.
No
Output high (source)
1
Note:
1.
Pull-up
Comment
4.10.2.5 Reading the Pin Value
Independent of the setting of data direction bit DDxn, the port pin can be read through the PINxn register bit. As shown in
Figure 4-25, the PINxn register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if
the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 4-27 shows a timing
diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation
delays are denoted tpd,max and tpd,min respectively.
Figure 4-27. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK
INSTRUCTIOS
XXX
XXX
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
tpd, max
tpd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is
low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal
value is latched when the system clock goes low. It is clocked into the PINxn register at the succeeding positive clock edge.
As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½
system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 4-28 on page 87.
The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the
synchronizer is 1 system clock period.
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Figure 4-28. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIOS
0xFF
out PORTx, r16
nop
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
tpd
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as
input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed,
a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi
r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out
PORTB,r16
out
DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in
r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
Note:
1. For the assembly program, two temporary registers are used to minimize the time from
pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2
and 3 as low and redefining bits 0 and 1 as strong high drivers.
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4.10.2.6 Digital Input Enable and Sleep Modes
As shown in Figure 4-25, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal
denoted SLEEP in the figure, is set by the MCU sleep controller in power-down or power-save mode to avoid high power
consumption if some input signals are left floating, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP
is active also for these pins. SLEEP is also overridden by various other alternate functions as described in Section 4.10.3
“Alternate Port Functions” on page 89.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge,
Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding external interrupt
flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the
requested logic change.
4.10.2.7Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital
inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current
consumption in all other modes where the digital inputs are enabled (reset, active mode and idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will
be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or
pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if
the pin is accidentally configured as an output.
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4.10.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 4-29 shows how the port pin control
signals from the simplified Figure 4-25 can be overridden by alternate functions. The overriding signals may not be present
in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR® microcontroller family.
Figure 4-29. Alternate Port Functions(1)
PUOExn
1
PUOVxn
PUD
0
DDOExn
1
DDOVxn
0
D
Q
DDxn
Q
CLR
RESET
WDx
RDx
PVOExn
1
PVOVxn
Q
0
D
0
PORTxn
Q
DIEOExn
1
0
DIEOVxn
DATA BUS
1
Pxn
PTOExn
CLR
RESET
WRx
WPx
RRx
SLEEP
Synchronizer
RPx
D SET Q
D
Q
PINxn
L
CLR
Q
CLR
Q
CLKI/O
DIxn
AIOxn
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn:
DIEOVxn:
SLEEP:
PTOExn:
Note:
1.
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
Pxn DIGITAL INPUT ENABLE OVERRIDE ENABLE
Pxn DIGITAL INPUT ENABLE OVERRIDE VALUE
SLEEP CONTROL
Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
CLK:I/O
DIxn:
AIOxn:
PULL-UP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD
are common to all ports. All other signals are unique for each pin.
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Table 4-23 summarizes the function of the overriding signals. The pin and port indexes from Figure 4-29 are not shown in the
succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
Table 4-23. Generic Description of Overriding Signals for Alternate Functions
Signal Name
Full Name
Description
PUOE
Pull-up override enable
If this signal is set, the pull-up enable is controlled by the PUOV signal. If this
signal is cleared, the pull-up is enabled when {DDxn, PORTxn, (PUD or
PDUx)} = 0, 1, 0.
PUOV
Pull-up override value
If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared,
regardless of the setting of the DDxn, PORTxn, PUD and PUDx register bits.
DDOE
Data direction override
enable
If this signal is set, the output driver enable is controlled by the DDOV signal.
If this signal is cleared, the output driver is enabled by the DDxn register bit.
DDOV
Data direction override
value
If DDOE is set, the output driver is enabled/disabled when DDOV is
set/cleared, regardless of the setting of the DDxn register bit.
PVOE
Port value override
enable
If this signal is set and the output driver is enabled, the port value is
controlled by the PVOV signal. If PVOE is cleared, and the output driver is
enabled, the port value is controlled by the PORTxn register bit.
PVOV
Port value override value
If PVOE is set, the port value is set to PVOV, regardless of the setting of the
PORTxn register bit.
PTOE
Port toggle override
enable
If PTOE is set, the PORTxn register bit is inverted.
DIEOE
Digital input enable
override enable
If this bit is set, the digital input enable is controlled by the DIEOV signal. If
this signal is cleared, the digital input enable is determined by MCU state
(normal mode, sleep mode).
DIEOV
Digital input enable
override value
If DIEOE is set, the digital input is enabled/disabled when DIEOV is
set/cleared, regardless of the MCU state (normal mode, sleep mode).
DI
Digital input
This is the digital input to alternate functions. In the figure, the signal is
connected to the output of the Schmitt Trigger but before the synchronizer.
Unless the digital input is used as a clock source, the module with the
alternate function will use its own synchronizer.
AIO
Analog input/output
This is the analog input/output to/from alternate functions. The signal is
connected directly to the pad, and can be used
bi-directionally.
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the
alternate function. Refer to the alternate function description for further details.
4.10.3.1 MCU Control Register – MCUCR
Bit
7
6
5
4
3
2
1
0
–
BODS
BODSE
PUD
–
–
–
–
Read/Write
R
R/W
R/W
R/W
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are
configured to enable the pull-ups ({DDxn, PORTxn} = 0, 1). See Section 4.10.2.1 “Configuring the Pin” on page 85 for more
details about this feature.
90
ATA6616C/ATA6617C [DATASHEET]
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4.10.3.2 Port Control Register – PORTCR
Bit
7
6
5
4
3
2
1
0
-
-
BBMB
BBMA
-
-
PUDB
PUDA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTCR
• Bits 5, 4 – BBMx: Break-Before-Make Mode Enable
When these bits are written to one, the port-wise break-before-make mode is activated. The intermediate tri-state cycle is
then inserted when writing DDRxn to make an output. For further information, see Section 4.10.2.3 “Break-before-make
Switching” on page 85.
• Bits 1, 0 – PUDx: Port-Wise Pull-up Disable
When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled even if the DDxn and PORTxn
registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0, 1). The port-wise pull-up disable bits are ORed with
the global pull-up disable bit (PUD) from the MCUCR register. See Section 4.10.2.1 “Configuring the Pin” on page 85 for
more details about this feature.
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4.10.3.3 Alternate Functions of Port A
The Port A pins with alternate functions are shown in Table 4-24.
Table 4-24. Port A Pins Alternate Functions
Port Pin
Alternate Function
PCINT7 (pin change interrupt 7)
ADC7 (ADC input channel 7)
PA7
AIN1 (analog comparator positive input)
XREF (internal voltage reference output)
AREF (external voltage reference input)
PCINT6 (pin change interrupt 6)
PA6
ADC6 (ADC input channel 6)
AIN0 (analog comparator negative input)
SS (SPI slave select input)
PCINT5 (pin change interrupt 5)
ADC5 (ADC input channel 5)
PA5
T1 (Timer/Counter1 clock input)
USCK (three-wire mode USI Alternate clock input)
SCL (two-wire mode USI Alternate clock input)
SCK (SPI master clock)
PCINT4 (pin change interrupt 4)
ADC4 (ADC input channel 4)
PA4
ICP1 (Timer/Counter1 input capture trigger)
DI (three-wire mode USI Alternate data input)
SDA (two-wire mode USI Alternate data input/output)
MOSI (SPI master output/slave input)
PCINT3 (pin change interrupt 3)
PA3
ADC3 (ADC input channel 3)
ISRC (current source pin)
INT1 (external interrupt1 input)
PCINT2 (pin change interrupt 2)
ADC2 (ADC input channel 2)
PA2
OC0A (output compare and PWM output A for Timer/Counter0)
DO (three-wire mode USI Alternate data output)
MISO (SPI master input/slave output)
PCINT1 (pin change interrupt 1)
PA1
ADC1 (ADC input channel 1)
TXD (UART transmit pin)
TXLIN (LIN transmit pin)
PCINT0 (pin change interrupt 0)
PA0
ADC0 (ADC input channel 0)
RXD (UART receive pin)
RXLIN (LIN receive pin)
92
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The alternate pin configuration is as follows:
• PCINT7/ADC7/AIN1/XREF/AREF – Port A, Bit7
PCINT7: Pin change interrupt, source 7.
ADC7: Analog to digital converter, channel 7.
AIN1: Analog comparator positive input. This pin is directly connected to the positive input of the analog comparator.
XREF: Internal voltage reference output. The internal voltage reference 2.56V or 1.1V is output when XREFEN is set and if
either 2.56V or 1.1V is used as reference for ADC conversion. When XREF output is enabled, the pin port pull-up and
digital output driver are turned off.
AREF: External voltage reference input for ADC. The pin port pull-up and digital output driver are disabled when the pin is
used as an external voltage reference input for ADC or as when the pin is only used to connect a bypass capacitor for
the voltage reference of the ADC.
• PCINT6/ADC6/AIN0/SS – Port A, Bit6
PCINT6: Pin change interrupt, source 6.
ADC6: Analog to digital converter, channel 6.
AIN0: Analog comparator negative input. This pin is directly connected to the negative input of the analog comparator.
SS: SPI slave select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of
DDA6. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data
direction of this pin is controlled by DDA6. When the pin is forced to be an input, the pull-up can still be controlled by
the PORTA6 bit.
• PCINT5/ADC5/T1/USCK/SCL/SCK – Port A, Bit5
PCINT5: Pin change interrupt, source 5.
ADC5: Analog to digital converter, channel 5.
T1: Timer/Counter1 clock input.
USCK: Three-wire mode USI clock input.
SCL: Two-wire mode USI clock input.
SCK: SPI master clock output, slave clock input pin. When the SPI is enabled as a slave, this pin is configured as an input
regardless of the setting of DDA5. When the SPI is enabled as a master, the data direction of this pin is controlled by
DDA5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTA5 bit.
• PCINT4/ADC4/ICP1/DI/SDA/MOSI – Port A, Bit 4
PCINT4: Pin change interrupt, source 4.
ADC4: Analog to digital converter, channel 4.
ICP1: Timer/Counter1 input capture trigger. The PA3 pin can act as an input capture pin for Timer/Counter1.
DI:
Three-wire mode USI data input. USI three-wire mode does not override normal port functions, so pin must be
configure as an input for DI function.
SDA: Two-wire mode serial interface (USI) data input / output.
MOSI: SPI master output / slave input. When the SPI is enabled as a slave, this pin is configured as an input regardless of
the setting of DDA3. When the SPI is enabled as a master, the data direction of this pin is controlled by DDA3. When
the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTA3 bit.
• PCINT3/ADC3/ISRC/INT1 – Port A, Bit 3
PCINT3: Pin Change Interrupt, source 3.
ADC3: Analog to digital converter, channel 3.
ISCR: Current source output pin. While current is sourced by the current source module, the user can use the analog to
digital converter channel 4 (ADC4) to measure the pin voltage.
INT1: External interrupt, source 1. The PA4 pin can serve as an external interrupt source.
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• PCINT2/ADC2/OC0A/DO/MISO – Port A, Bit 2
PCINT2: Pin change interrupt, source 2.
ADC2: Analog to digital converter, channel 2.
OC0A: Output compare match A or output PWM A for Timer/Counter0. The pin has to be configured as an output (DDA2 set
(one)) to serve these functions.
DO: Three-wire mode USI data output. Three-wire mode data output overrides PORTA2 and it is driven to the port when the
data direction bit DDA2 is set. PORTA2 still enables the pull-up, if the direction is input and PORTA2 is set (one).
MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured
as an input regardless of the setting of DDA2. When the SPI is enabled as a salve, the data direction of this pin is
controlled by DDA2. When the pin is forced to be an input, the pull-up can still be controlled by PORTA2.
• PCINT1/ADC1/TXD/TXLIN – Port A, Bit 1
PCINT1: Pin change interrupt, source 1.
ADC1: Analog to digital converter, channel 1.
TXD: UART transmit pin. When the UART transmitter is enabled, this pin is configured as an output regardless the value of
DDA1. PORTA1 still enables the pull-up, if the direction is input and PORTA2 is set (one).
TXLIN: LIN transmit pin. When the LIN is enabled, this pin is configured as an output regardless the value of DDA1.
PORTA1 still enables the pull-up, if the direction is input and PORTA2 is set (one).
• PCINT0/ADC0/RXD/RXLIN – Port A, Bit 0
PCINT0: Pin change interrupt, source 0.
ADC0: Analog to digital converter, channel 0.
RXD: UART receive pin. When the UART receiver is enabled, this pin is configured as an input regardless of the value of
DDA0. When the pin is forced to be an input, a logical one in PORTA0 will turn on the internal pull-up.
RXLIN: LIN receive pin. When the LIN is enabled, this pin is configured as an input regardless of the value of DDA0. When
the pin is forced to be an input, a logical one in PORTA0 will turn on the internal pull-up.
94
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9132J–AUTO–01/15
Table 4-25 and Table 4-26 relate the alternate functions of Port A to the overriding signals shown in Figure 4-29 on page 89.
Table 4-25. Overriding Signals for Alternate Functions in PA7..PA4
Signal
Name
PA7/PCINT7/
ADC7/AIN1
/XREF/AREF
PA6/PCINT6/
ADC6/AIN0/SS
PA5/PCINT5/ADC5/
T1/USCK/SCL/SCK
PA4/PCINT4/ADC4/
ICP1/DI/SDA/MOSI
PUOE
0
SPE & MSTR
SPE & MSTR
SPE & MSTR
PUOV
0
PORTA6 & PUD
PORTA5 & PUD
PORTA4 & PUD
DDOE
0
SPE & MSTR
(SPE & MSTR) |
(USI_2_WIRE & USIPOS)
(SPE & MSTR) |
(USI_2_WIRE & USIPOS)
{ (SPE & MSTR) ?
DDOV
0
0
(USI_SCL_HOLD | PORTA5)
& DDRA6
(0) :
(USI_SHIFTOUT | PORTA4)
& DDRA4) }
PVOE
0
0
(SPE & MSTR) |
(USI_2_WIRE & USIPOS
& DDRA5)
(SPE & MSTR) |
(USI_2_WIRE & USIPOS
& DDRA4)
{ (SPE & MSTR) ?
{ (SPE & MSTR) ?
(SCK_OUTPUT) :
(MOSI_OUTPUT) :
~ (USI_2_WIRE & USIPOS
& DDRA5) }
~ (USI_2_WIRE & USIPOS
& DDRA4) }
PVOV
0
0
PTOE
0
0
USI_PTOE & USIPOS
0
ADC7D |
ADC6D |
(PCIE0 & PCMSK07)
(PCIE0 & PCMSK06)
ADC5D |
(USISIE & USIPOS) |
(PCIE0 & PCMSK05)
ADC4D |
(USISIE & USIPOS) |
(PCIE0 & PCMSK04)
DIEOV
PCIE0 & PCMSK07
PCIE0 & PCMSK06
(USISIE & USIPOS) |
(PCIE0 & PCMSK05)
(USISIE & USIPOS) |
(PCIE0 & PCMSK04)
DI
PCINT7
PCINT6 -/- SS
PCINT5 -/- T1
-/- USCK -/- SCL -/- SCK
PCINT4 -/- ICP1
-/- DI -/- SDA -/- MOSI
AIO
ADC7 -/- AIN1 -/XREF -/- AREF
ADC6 -/- AIN0
ADC5
ADC4
DIEOE
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Table 4-26. Overriding Signals for Alternate Functions in PA3..PA0
Signal
Name
PA3/PCINT3/ADC3/
ISRC/INT1
PA2/PCINT2/ADC2/
OC0A/DO/MISO
PA1/PCINT1/ADC1/
TXD/TXLIN
PA0/PCINT0/ADC0/
RXD/RXLIN
PUOE
0
SPE & MSTR
LIN_TX_ENABLE
LIN_RX_ENABLE
PUOV
PORTA3 & PUD
PORTA2 & PUD
DDOE
0
SPE & MSTR
LIN_TX_ENABLE
LIN_RX_ENABLE
DDOV
0
0
LIN_TX_ENABLE
0
0
(SPE & MSTR) |
(USI_2_WIRE & USI_3_WIRE &
USIPOS) |
OC0A
LIN_TX_ENABLE
0
PVOE
{ (LIN_TX_ENABLE) ?
(0) : (PORTA1 & PUD) }
PORTA0 & PUD
{ (SPE & MSTR) ?
(MISO_OUTPUT) :
PVOV
0
{ (LIN_TX_ENABLE) ?
( ( USI_2_WIRE & USI_3_WIRE &
USIPOS ) ?
(USI_SHIFTOUT) : (OC0A) ) }
(LIN_TX) : (0) }
PTOE
0
0
0
0
ADC2D |
ADC1D |
ADC0D |
(PCIE0 & PCMSK02)
(PCIE0 & PCMSK01)
(PCIE0 & PCMSK00)
PCIE0 & PCMSK02
PCIE0 & PCMSK01
PCIE0 & PCMSK00
ADC3D |
DIEOE
INT1_ENABLE |
(PCIE0 & PCMSK03)
DIEOV
96
INT1_ENABLE |
(PCIE0 & PCMSK03)
0
DI
PCINT3 -/- INT1
PCINT2 -/- MISO
PCINT1
PCINT0
AIO
ADC3 -/- ISRC
ADC2
ADC1
ADC0
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
4.10.3.4 Alternate Functions of Port B
The Port B pins with alternate functions are shown in Table 4-27.
Table 4-27. Port B Pins Alternate Functions
Port Pin
Alternate Functions
PCINT15 (pin change interrupt 15)
ADC10 (ADC input channel 10)
PB7
OC1BX (output compare and PWM output B-X for Timer/Counter1)
RESET (reset input pin)
dW (debugWIRE I/O)
PCINT14 (pin change interrupt 14)
PB6
ADC9 (ADC input channel 9)
OC1AX (output compare and PWM output A-X for Timer/Counter1)
INT0 (external interrupt0 input)
PCINT13 (pin change interrupt 13)
ADC8 (ADC input channel 8)
PB5
OC1BW (output compare and PWM output B-W for Timer/Counter1)
XTAL2 (chip clock oscillator pin 2)
CLKO (system clock output)
PCINT12 (pin change interrupt 12)
PB4
OC1AW (output compare and PWM output A-W for Timer/Counter1)
XTAL1 (chip clock oscillator pin 1)
CLKI (external clock input)
PB3
PCINT11 (pin change interrupt 11)
OC1BV (output compare and PWM output B-V for Timer/Counter1)
PCINT10 (pin change interrupt 10)
PB2
OC1AV (output compare and PWM output A-V for Timer/Counter1)
USCK (three-wire mode USI Default clock input)
SCL (two-wire mode USI Default clock input)
PCINT9 (pin change interrupt 9)
PB1
OC1BU (output compare and PWM output B-U for Timer/Counter1)
DO (three-wire mode USI Default data output)
PCINT8 (pin change interrupt 8)
PB0
OC1AU (output compare and PWM output A-U for Timer/Counter1)
DI (three-wire mode USI Default data input)
SDA (two-wire mode USI Default data input / output)
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The alternate pin configuration is as follows:
• PCINT15/ADC10/OC1BX/RESET/dW – Port B, Bit 7
PCINT15: Pin change interrupt, source 15.
ADC10: Analog to digital converter, channel 10.
OC1BX: Output compare and PWM output B-X for Timer/Counter1. The PB7 pin has to be configured as an output (DDB7
set (one)) to serve this function. The OC1BX pin is also the output pin for the PWM mode timer function (c.f. OC1BX
bit of TCCR1D register).
RESET: Reset input pin. When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will
have to rely on power-on reset and brown-out reset as its reset sources. When the RSTDISBL Fuse is
unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin. If PB7 is used as
a reset pin, DDB7, PORTB7 and PINB7 will all read 0.
dW:
When the debugWIRE enable (DWEN) fuse is programmed and Lock bits are unprogrammed, the RESET port pin is
configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication
gateway between target and emulator.
• PCINT14/ADC9/OC1AX/INT0 – Port B, Bit 6
PCINT14: Pin change interrupt, source 14.
ADC9: Analog to digital converter, channel 9.
OC1AX: Output compare and PWM output A-X for Timer/Counter1. The PB6 pin has to be configured as an output (DDB6
set (one)) to serve this function. The OC1AX pin is also the output pin for the PWM mode timer function (c.f. OC1AX
bit of TCCR1D register).
INT0: External Interrupt0 input. The PB6 pin can serve as an external interrupt source.
• PCINT13/ADC8/OC1BW/XTAL2/CLKO – Port B, Bit 5
PCINT13: Pin change interrupt, source 13.
ADC8: Analog to digital converter, channel 8.
OC1BW: Output compare and PWM output B-W for Timer/Counter1. The PB5 pin has to be configured as an output (DDB5
set (one)) to serve this function. The OC1BW pin is also the output pin for the PWM mode timer function (c.f. OC1BW
bit of TCCR1D register).
XTAL2: Chip clock oscillator pin 2. Used as clock pin for crystal oscillator or low-frequency crystal oscillator. When used as a
clock pin, the pin can not be used as an I/O pin.
CLKO: Divided system clock output. The divided system clock can be output on the PB5 pin. The divided system clock will
be output if the CKOUT Fuse is programmed, regardless of the PORTB5 and DDB5 settings. It will also be output
during reset.
• PCINT12/OC1AW/XTAL1/CLKI – Port B, Bit 4
PCINT12: Pin change interrupt, source 12.
OC1AW: Output compare and PWM output A-W for Timer/Counter1. The PB4 pin has to be configured as an output (DDB4
set (one)) to serve this function. The OC1AW pin is also the output pin for the PWM mode timer function (c.f. OC1AW
bit of TCCR1D register).
XTAL1: Chip clock oscillator pin 1. Used for all chip clock sources except internal calibrated RC oscillator. When used as a
clock pin, the pin can not be used as an I/O pin.
CLKI: External clock input. When used as a clock pin, the pin can not be used as an I/O pin.
Note:
98
If PB4 is used as a clock pin (XTAL1 or CLKI), DDB4, PORTB4 and PINB4 will all read 0.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
• PCINT11/OC1BV – Port B, Bit 3
PCINT11: Pin change interrupt, source 11.
OC1BV: Output compare and PWM output B-V for Timer/Counter1. The PB3 pin has to be configured as an output (DDB3
set (one)) to serve this function. The OC1BV pin is also the output pin for the PWM mode timer function (c.f. OC1BV
bit of TCCR1D register).
• PCINT10/OC1AV/USCK/SCL – Port B, Bit 2
PCINT10: Pin change interrupt, source 10.
OC1AV: Output compare and PWM output A-V for Timer/Counter1. The PB2 pin has to be configured as an output (DDB2
set (one)) to serve this function. The OC1AV pin is also the output pin for the PWM mode timer function (c.f. OC1AV
bit of TCCR1D register).
USCK: Three-wire mode USI clock input.
SCL: Two-wire mode USI clock input.
• PCINT9/OC1BU/DO – Port B, Bit 1
PCINT9: Pin change interrupt, source 9.
OC1BU: Output compare and PWM output B-U for Timer/Counter1. The PB1 pin has to be configured as an output (DDB1
set (one)) to serve this function. The OC1BU pin is also the output pin for the PWM mode timer function (c.f. OC1BU
bit of TCCR1D register).
DO:
Three-wire mode USI data output. Three-wire mode data output overrides PORTB1 and it is driven to the port when
the data direction bit DDB1 is set. PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one).
• PCINT8/OC1AU/DI/SDA – Port B, Bit 0
IPCINT8: Pin change interrupt, source 8.
OC1AU: Output compare and PWM output A-U for Timer/Counter1. The PB0 pin has to be configured as an output (DDB0
set (one)) to serve this function. The OC1AU pin is also the output pin for the PWM mode timer function (c.f. OC1AU
bit of TCCR1D register).
DI:
Three-wire mode USI data input. USI three-wire mode does not override normal port functions, so pin must be
configure as an input for DI function.
SDA: Two-wire mode serial interface (USI) data input/output.
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Table 4-28 and Table 4-29 relate the alternate functions of Port B to the overriding signals shown in Figure 4-29 on page 89.
Table 4-28. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name
PB7/PCINT15/ADC10/
OC1BX/RESET/dW
PB6/PCINT14/ADC9/
OC1AX/INT0
PB5/PCINT13/ADC8/
OC1BW/XTAL2/CLKO
PB4/PCINT12/
OC1AW/XTAL1/CLKI
PUOE
0
0
0
0
PUOV
0
0
0
0
DDOE
0
0
0
0
DDOV
0
0
PVOE
0
OC1A_ENABLE &
OC1AW
OC1A
OC1B
OC1A
0
0
0
OC1B_ENABLE & OC1BX OC1A_ENABLE & OC1AX
PVOV
OC1B
PTOE
0
DIEOE
0
OC1B_ENABLE &
OC1BW
ADC9D |
ADC10D |
ADC8D |
INT0_ENABLE |
(PCIE1 & PCMSK15)
(PCIE1 & PCMSK14)
INT0_ENABLE |
DIEOV
PCIE1 & PCMSK15
DI
PCINT15
AIO
RESET -/- ADC10 -/-
(PCIE1 & PCMSK13)
(PCIE1 & PCMSK13)
PCIE1 & PCMSK13
1
PCINT14 -/- INT1
PCINT13
PCINT12
ADC9 -/- ISRC
ADC8 -/- XTAL2
XTAL1 -/- CLKI
(PCIE1 & PCMSK14)
Table 4-29. Overriding Signals for Alternate Functions in PB3..PB0
Signal
Name
PB3/PCINT11/
OC1BV
PB2/PCINT10/
OC1AV/USCK/SCL
PB1/PCINT9/
OC1BU/DO
PB0/IPCINT8/
OC1AU/DI/SDA
PUOE
0
0
0
0
PUOV
0
0
0
0
DDOE
0
(USI_2_WIRE & USIPOS)
0
(USI_SCL_HOLD |
DDOV
0
PVOE
OC1B_ENABLE &
OC1BV
PORTB2)
& DDRB2
0
(USI_2_WIRE &
USIPOS)
(USI_SHIFTOUT |
PORTB0) & DDRB0)
(USI_2_WIRE &
(USI_2_WIRE &
(USI_2_WIRE &
USI_3_WIRE &
USIPOS &
USIPOS &
DDRB2) |
DDRB0) |
USIPOS) |
(OC1A_ENABLE & OC1AV) (OC1B_ENABLE & OC1BU) (OC1A_ENABLE & OC1AU)
{ (USI_2_WIRE &
{ (USI_2_WIRE &
USIPOS &
DDRB2) ?
(0) : (OC1A) }
(USI_SHIFTOUT) : (OC1B) }
0
USI_PTOE & USIPOS
0
0
DIEOE
PCIE1 & PCMSK11
(USISIE & USIPOS) |
(PCIE1 & PCMSK10)
PCIE1 & PCMSK9
(USISIE & USIPOS) |
(PCIE1 & PCMSK8)
DIEOV
1
(USISIE & USIPOS) |
(PCIE1 & PCMSK10)
1
(USISIE & USIPOS) |
(PCIE1 & PCMSK8)
DI
PCINT11
PCINT10 -/- USCK -/- SCL
PCINT9
PCINT8 -/- DI -/- SDA
AIO
0
0
0
0
PVOV
OC1B
PTOE
100
{ (USI_2_WIRE &
USI_3_WIRE &
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
USIPOS) ?
USIPOS &
DDRB0) ?
(0) : (OC1A) }
4.10.4 Register Description for I/O Ports
4.10.4.1 Port A Data Register – PORTA
Bit
7
6
5
4
3
2
1
0
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTA
4.10.4.2 Port A Data Direction Register – DDRA
Bit
7
6
5
4
3
2
1
0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DDRA
4.10.4.3 Port A Input Pins Register – PINA
Bit
7
6
5
4
3
2
1
0
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Read/Write
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4
3
2
1
0
PINA
4.10.4.4 Port B Data Register – PORTB
Bit
7
6
5
PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTB
4.10.4.5 Port B Data Direction Register – DDRB
Bit
7
6
5
4
3
2
1
0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DDRB
4.10.4.6 Port B Input Pins Register – PINB
Bit
7
6
5
4
3
2
1
0
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PINB
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4.11
8-bit Timer/Counter0 and Asynchronous Operation
Timer/Counter0 is a general purpose, single channel, 8-bit timer/cunter module. The main features are:
4.11.1 Features
●
●
●
●
●
●
●
Single channel counter
Clear timer on compare match (auto reload)
Glitch-free, phase correct pulse width modulator (PWM)
Frequency generator
10-bit clock prescaler
Overflow and compare match interrupt sources (TOV0 and OCF0A)
Allows clocking from external crystal (i.e. 32kHz watch crystal) independent of the I/O clock
4.11.2 Overview
Many register and bit references in this section are written in general form.
● A lower case “n” replaces the Timer/Counter number, in this case 0. However, when using the register or bit defines in
a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
●
A lower case “x” replaces the output compare unit channel, in this case A. However, when using the register or bit
defines in a program, the precise form must be used, i.e., OCR0A for accessing Timer/Counter0 output compare
channel A value and so on.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 4-30. CPU accessible I/O registers, including I/O bits
and I/O pins, are shown in bold. The device-specific I/O register and bit locations are listed in the Section 4.11.11 “8-bit
Timer/Counter Register Description” on page 113.
Figure 4-30. 8-bit Timer/Counter0 Block Diagram
TCCRnx
TOVn
(Int. Req.)
Count
Clear
Control Logic
Direction
clkTn
XTAL2
BOTTOM
Oscillator
TOP
Prescaler
Timer/Counter
TCNTn
=0
XTAL1
= 0xFF
clkI/O
DATA BUS
OCnx
(Int. Req.)
Waveform
Generation
=
OCnx
OCRnx
Synchronized Status Flags
clkI/O
Synchronization Unit
clkASY
Status flags
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ASSRn
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Asynchronous Mode
select (ASn)
The Timer/Counter (TCNT0) and output compare register (OCR0A) are 8-bit registers. Interrupt request (shorten as Int.Req.)
signals are all visible in the timer interrupt flag register (TIFR0). All interrupts are individually masked with the timer interrupt
mask register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the XTAL1/2 pins, as
detailed later in this section. The asynchronous operation is controlled by the asynchronous status register (ASSR). The
clock select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer
clock (clkT0).
The double buffered output compare register (OCR0A) is compared with the Timer/Counter value at all times. The result of
the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output
compare pin (OC0A). Section 4.11.5 “Output Compare Unit” on page 104 for details. The compare match event will also set
the compare flag (OCF0A) which can be used to generate an output compare interrupt request.
4.11.2.1 Definitions
The following definitions are used extensively throughout the section:
BOTTOM
The counter reaches the BOTTOM when it becomes zero (0x00).
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value
stored in the OCR0A Register. The assignment is dependent on the mode of operation.
4.11.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source
is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter control
register (TCCR0).The clock source clkT0 is by default equal to the MCU clock, clkI/O. When the AS0 bit in the ASSR Register
is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to XTAL1 and XTAL2 or directly
from XTAL1. For details on asynchronous operation, see Section 4.11.11.5 “Asynchronous Status Register – ASSR” on page
116. For details on clock sources and prescaler, see Section 4.11.10 “Timer/Counter0 Prescaler” on page 112.
4.11.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 4-31 shows a block diagram
of the counter and its surrounding environment.
Figure 4-31. Counter Unit Block Diagram
TOVn
(Int. Req.)
DATA BUS
XTAL2
Count
TCNTn
Clear
Oscillator
Control Logic
clkTn
Prescaler
clkTnS
XTAL1
Direction
Bottom
Top
clkI/O
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Signal description (internal signals):
count
Increment or decrement TCNT0 by 1.
direction
Selects between increment and decrement.
clear
Clear TCNT0 (set all bits to zero).
clkT0
Timer/Counter0 clock.
top
Signalizes that TCNT0 has reached maximum value.
bottom
Signalizes that TCNT0 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
clkT0 can be generated from an external or internal clock source, selected by the clock select bits (CS02:0). When no clock
source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter control
register (TCCR0A). There are close connections between how the counter behaves (counts) and how waveforms are
generated on the output compare output OC0A. For more details about advanced counting sequences and waveform
generation, see Section 4.11.7 “Modes of Operation” on page 106.
The Timer/Counter overflow flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can
be used for generating a CPU interrupt.
4.11.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the output compare register (OCR0A). Whenever TCNT0 equals
OCR0A, the comparator signals a match. A match will set the output compare flag (OCF0A) at the next timer clock cycle. If
enabled (OCIE0A = 1), the output compare flag generates an output compare interrupt. The OCF0A flag is automatically
cleared when the interrupt is executed. Alternatively, the OCF0A flag can be cleared by software by writing a logical one to
its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by
the WGM01:0 bits and compare output mode (COM0A1:0) bits. The max and bottom signals are used by the waveform
generator for handling the special cases of the extreme values in some modes of operation (see Section 4.11.7 “Modes of
Operation” on page 106).
Figure 4-32 shows a block diagram of the output compare unit.
Figure 4-32. Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
=
(8-bit Comparator)
OCFnx (Int. Req.)
Top
Bottom
Waveform Generator
OCnx
FOCn
WGMn1:0
COMnX1:0
The OCR0A register is double buffered when using any of the pulse width modulation (PWM) modes. For the normal and
clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the
update of the OCR0A compare register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0A register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR0A buffer register, and if double buffering is disabled the CPU will access the OCR0A directly.
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4.11.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force
output compare (FOC0A) bit. Forcing compare match will not set the OCF0A flag or reload/clear the timer, but the OC0A pin
will be updated as if a real compare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set,
cleared or toggled).
4.11.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 register will block any compare match that occurs in the next timer clock cycle, even
when the timer is stopped. This feature allows OCR0A to be initialized to the same value as TCNT0 without triggering an
interrupt when the Timer/Counter clock is enabled.
4.11.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks
involved when changing TCNT0 when using the output compare channel, independently of whether the Timer/Counter is
running or not. If the value written to TCNT0 equals the OCR0A value, the compare match will be missed, resulting in
incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is
downcounting.
The setup of the OC0A should be performed before setting the data direction register for the port pin to output. The easiest
way of setting the OC0A value is to use the force output compare (FOC0A) strobe bit in normal mode. The OC0A register
keeps its value even when changing between waveform generation modes.
Be aware that the COM0A1:0 bits are not double buffered together with the compare value. Changing the COM0A1:0 bits
will take effect immediately.
4.11.6 Compare Match Output Unit
The compare output mode (COM0A1:0) bits have two functions. The waveform generator uses the COM0A1:0 bits for
defining the output compare (OC0A) state at the next compare match. Also, the COM0A1:0 bits control the OC0A pin output
source. Figure 4-33 shows a simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT)
that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A
Register, not the OC0A pin.
Figure 4-33. Compare Match Output Logic
COMnx1
COMnx0
FOCnx
Waveform
Generator
D
Q
1
OCnx
Pin
OCnx
0
DATA BUS
D
Q
PORT
D
clkI/O
Q
DDR
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4.11.6.1 Compare Output Function
The general I/O port function is overridden by the output compare (OC0A) from the waveform generator if either of the
COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the data direction register
(DDR) for the port pin. The data direction register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A
value is visible on the pin. The port override function is independent of the waveform generation mode.
The design of the output compare pin logic allows initialization of the OC0A state before the output is enabled. Note that
some COM0A1:0 bit settings are reserved for certain modes of operation. See Section 4.11.11 “8-bit Timer/Counter Register
Description” on page 113.
4.11.6.2 Compare Output Mode and Waveform Generation
The waveform generator uses the COM0A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the
COM0A1:0 = 0 tells the waveform generator that no action on the OC0A register is to be performed on the next compare
match. For compare output actions in the non-PWM modes refer to Table 4-30 on page 113. For fast PWM mode, refer to
Table 4-31 on page 113, and for phase correct PWM refer to Table 4-32 on page 114.
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the FOC0A strobe bits.
4.11.7 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of
the waveform generation mode (WGM01:0) and compare output mode (COM0A1:0) bits. The compare output mode bits do
not affect the counting sequence, while the waveform generation mode bits do. The COM0A1:0 bits control whether the
PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0A1:0 bits
control whether the output should be set, cleared, or toggled at a compare match (see Section 4.11.6 “Compare Match
Output Unit” on page 105).
For detailed timing information refer to Section 4.11.8 “Timer/Counter Timing Diagrams” on page 110.
4.11.7.1 Normal Mode
The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value
(TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag (TOV0) will be
set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a ninth bit, except
that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 flag,
the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter
value can be written anytime.
The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate
waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.
4.11.7.2 Clear Timer on Compare Match (CTC) Mode
In clear timer on compare or CTC mode (WGM01:0 = 2), the OCR0A register is used to manipulate the counter resolution. In
CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top
value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 4-34. The counter value (TCNT0) increases until a compare match
occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.
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Figure 4-34. CTC Mode, Timing Diagram
OCnx Interrupt
Flag Set
TCNTn
OCnx
(Toggle)
Period
(COMnx1:0 = 1)
1
2
3
4
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt
is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value
close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC
mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of
TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap
around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare
match by setting the compare output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the
port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of
fOC0A = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation:
f clk_I/O
f OCnx = ---------------------------------------------------2 N 1 + OCRnx
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts from MAX to
0x00.
4.11.7.3 Fast PWM Mode
The fast pulse width modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation
option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to
MAX then restarts from BOTTOM. In non-inverting compare output mode, the output compare (OC0A) is cleared on the
compare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting compare output mode, the output is set on
compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode
can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast
PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared
at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 4-35. The TCNT0 value is in
the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A
and TCNT0.
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Figure 4-35. Fast PWM Mode, Timing Diagram
OCRnx Interrupt
Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter overflow flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt
handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to
two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (see
Table 4-31 on page 113). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set
as output. The PWM waveform is generated by setting (or clearing) the OC0A register at the compare match between
OCR0A and TCNT0, and clearing (or setting) the OC0A Register at the timer clock cycle the counter is cleared (changes
from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ------------------N 256
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the fast
PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle.
Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by
the COM0A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0A to toggle its logical
level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of foc0A = fclk_I/O/2
when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the
Output Compare unit is enabled in the fast PWM mode.
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4.11.7.4Phase Correct PWM Mode
The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option.
The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX
and then from MAX to BOTTOM. In non-inverting compare output mode, the output compare (OC0A) is cleared on the
compare match between TCNT0 and OCR0A while upcounting, and set on the compare match while downcounting. In
inverting output compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is
incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The
TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 4-36. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent
compare matches between OCR0A and TCNT0.
Figure 4-36. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt
Flag Set
OCRnx Update
TOVn Interrupt
Flag Set
TCNTn
OCnx
(COMnx[1:0] = 2)
OCnx
(COMnx[1:0] = 3)
Period
1
2
3
The Timer/Counter overflow flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to
generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the
COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM0A1:0 to three (See Table 4-32 on page 114). The actual OC0A value will only be visible on the port pin if the data
direction for the port pin is set as output.
The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and
TCNT0 when the counter increments, and setting (or clearing) the OC0A register at compare match between OCR0A and
TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated
by the following equation:
f clk_I/O
f OCnxPCPWM = ------------------N 510
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase
correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the
output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
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4.11.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT0) is therefore shown as a clock
enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter oscillator clock. The figures include
information on when interrupt flags are set. Figure 4-37 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 4-37. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
BOTTOM
BOTTOM + 1
TOVn
Figure 4-38 shows the same timing data, but with the prescaler enabled.
Figure 4-38. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
MAX - 1
MAX
TOVn
Figure 4-39 shows the setting of OCF0A in all modes except CTC mode.
Figure 4-39. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
OCRnx - 1
OCRnx
OCFnx
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OCRnx
OCRnx + 1
OCRnx Value
OCRnx + 2
Figure 4-40 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Figure 4-40. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC)
TOP - 1
OCRnx
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
4.11.9 Asynchronous Operation of Timer/Counter0
When Timer/Counter0 operates asynchronously, some considerations must be taken.
● Warning: When switching between asynchronous and synchronous clocking of Timer/Counter0, the timer registers
TCNT0, OCR0A, and TCCR0A might be corrupted. A safe procedure for switching clock source is:
a) Disable the Timer/Counter0 interrupts by clearing OCIE0A and TOIE0.
b) Select clock source by setting AS0 and EXCLK as appropriate.
c) Write new values to TCNT0, OCR0A, and TCCR0A.
d) To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB.
e) Clear the Timer/Counter0 interrupt flags.
f) Enable interrupts, if needed.
●
If an 32.768kHz watch crystal is used, the CPU main clock frequency must be more than four times the oscillator or
external clock frequency.
●
When writing to one of the registers TCNT0, OCR0A, or TCCR0A, the value is transferred to a temporary register,
and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the
temporary register have been transferred to its destination. Each of the three mentioned registers have their individual
temporary register, which means that e.g. writing to TCNT0 does not disturb an OCR0A write in progress. To detect
that a transfer to the destination register has taken place, the asynchronous status register – ASSR has been
implemented.
●
When entering power-save mode after having written to TCNT0, OCR0A, or TCCR0A, the user must wait until the
written register has been updated if Timer/Counter0 is used to wake up the device. Otherwise, the MCU will enter
sleep mode before the changes are effective. This is particularly important if the Output Compare0 interrupt is used to
wake up the device, since the output compare function is disabled during writing to OCR0A or TCNT0. If the write
cycle is not finished, and the MCU enters sleep mode before the OCR0UB bit returns to zero, the device will never
receive a compare match interrupt, and the MCU will not wake up.
●
If Timer/Counter0 is used to wake the device up from Power-save mode, precautions must be taken if the user wants
to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up
and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake
up. If the user is in doubt whether the time before re-entering Power-save mode is sufficient, the following algorithm
can be used to ensure that one TOSC1 cycle has elapsed:
a) Write a value to TCCR0A, TCNT0, or OCR0A.
b) Wait until the corresponding update busy flag in ASSR returns to zero.
c) Enter power-save or ADC noise reduction mode.
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●
When the asynchronous operation is selected, the oscillator for Timer/Counter0 is always running, except in powerdown mode. After a power-up reset or wake-up from power-down mode, the user should be aware of the fact that this
oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before
using Timer/Counter0 after power-up or wake-up from power-down mode. The contents of all Timer/Counter0
registers must be considered lost after a wake-up from power-down mode due to unstable clock signal upon start-up,
no matter whether the oscillator is in use or a clock signal is applied to the XTAL1 pin.
●
Description of wake up from power-save mode when the timer is clocked asynchronously: When the interrupt
condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always
advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.
●
Reading of the TCNT0 register shortly after wake-up from power-save may give an incorrect result. Since TCNT0 is
clocked on the asynchronous clock, reading TCNT0 must be done through a register synchronized to the internal I/O
clock domain (CPU main clock). Synchronization takes place for every rising XTAL1 edge. When waking up from
power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT0 will read as the previous value (before
entering sleep) until the next rising XTAL1 edge. The phase of the XTAL1 clock after waking up from power-save
mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading
TCNT0 is thus as follows:
a) Write any value to either of the registers OCR0A or TCCR0A.
b) Wait for the corresponding update busy flag to be cleared.
c) Read TCNT0.
●
During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes
3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can
read the timer value causing the setting of the interrupt flag. The Output Compare pin is changed on the timer clock
and is not synchronized to the processor clock.
4.11.10 Timer/Counter0 Prescaler
Figure 4-41. Prescaler for Timer/Counter0
XTAL2
Clear
10-bit T/C Prescaler
XTAL1
clkTnS/8
1
1
EXCLK
ASn
PSRn
0
CSn0
CSn1
CSn2
Timer/Countern Clock Source
clkTn
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clkTnS/1024
clkTnS
clkTnS/256
0
clkTnS/128
0
clkTnS/64
Oscillator
clkTnS/32
clkI/O
The clock source for Timer/Counter0 is named clkT0S. clkT0S is by default connected to the main system I/O clock clkIO. By
setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked from the XTAL oscillator or XTAL1 pin. This enables
use of Timer/Counter0 as a real time counter (RTC).
A crystal can then be connected between the XTAL1 and XTAL2 pins to serve as an independent clock source for
Timer/Counter0.
A external clock can also be used using XTAL1 as input. Setting AS0 and EXCLK enables this configuration.
For Timer/Counter0, the possible prescaled selections are: clkT0S/8, clkT0S/32, clkT0S/64, clkT0S/128, clkT0S/256, and
clkT0S/1024. Additionally, clkT0S as well as 0 (stop) may be selected. Setting the PSR0 bit in GTCCR resets the prescaler.
This allows the user to operate with a predictable prescaler.
4.11.11 8-bit Timer/Counter Register Description
4.11.11.1 Timer/Counter0 Control Register A – TCCR0A
Bit
7
6
COM0A1 COM0A0
5
4
3
2
1
0
–
–
–
–
WGM01
WGM00
Read/Write
R/W
R/W
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR0A
• Bit 7:6 – COM0A1:0: Compare Match Output Mode A
These bits control the output compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output
overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR)
bit corresponding to OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. Table 4-30
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM).
Table 4-30. Compare Output Mode, non-PWM Mode
COM0A1
COM0A0
Description
0
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC0A on compare match.
1
0
Clear OC0A on compare match.
1
1
Set OC0A on compare match.
Table 4-31 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Table 4-31. Compare Output Mode, Fast PWM Mode(1)
COM0A1
COM0A0
0
0
0
1
1
0
1
1
Note:
1.
Description
Normal port operation, OC0A disconnected.
Clear OC0A on compare match.
Set OC0A at BOTTOM (non-inverting mode).
Set OC0A on compare match.
Clear OC0A at BOTTOM (inverting mode).
A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 4.11.7.3 “Fast PWM Mode” on page 107 for more
details.
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Table 4-32 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode.
Table 4-32. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
0
0
0
1
1
0
1
1
Note:
1.
Description
Normal port operation, OC0A disconnected.
Clear OC0A on compare match when up-counting.
Set OC0A on compare match when down-counting.
Set OC0A on compare match when up-counting.
Clear OC0A on compare match when down-counting.
A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 4.11.7.4 “Phase Correct PWM Mode” on page 109
for more details.
• Bit 5:2 – Res: Reserved Bits
These bits are reserved in the Atmel® ATtiny87/167 and will always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of
waveform generation to be used, see Table 4-33. Modes of operation supported by the Timer/Counter unit are: normal mode
(counter), clear timer on compare match (CTC) mode, and two types of pulse width modulation (PWM) modes (see Section
4.11.7 “Modes of Operation” on page 106).
Table 4-33. Waveform Generation Mode Bit Description
Mode
WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter
Mode of Operation
TOP
Update of
OCR0A at
TOV0 Flag
Set on(1)(2)
0
0
0
Normal
0xFF
Immediate
MAX
1
0
1
PWM, phase correct
0xFF
TOP
BOTTOM
2
1
0
CTC
OCR0A
Immediate
MAX
1
Fast PWM
0xFF
TOP
MAX
3
Notes:
114
1.
1
MAX = 0xFF
2.
BOTTOM = 0x00
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4.11.11.2 Timer/Counter0 Control Register B – TCCR0B
Bit
7
6
5
4
3
2
1
0
FOC0A
–
–
–
–
CS02
CS01
CS00
Read/Write
W
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR0B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating
in PWM mode. When writing a logical one to the FOC0A bit, an immediate compare match is forced on the Waveform
Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is
implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced
compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6:3 – Res: Reserved Bits
These bits are reserved in the Atmel® ATtiny87/167 and will always read as zero.
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 4-34.
Table 4-34. Clock Select Bit Description
CS02
CS01
CS00
Description
0
0
0
No clock source (Timer/Counter stopped).
0
0
1
clkT0S (No prescaling)
0
1
0
clkT0S/8 (from prescaler)
0
1
1
clkT0S/32 (from prescaler)
1
0
0
clkT0S/64 (from prescaler)
1
0
1
clkT0S/128 (from prescaler)
1
1
0
clkT0S/256 (from prescaler)
1
1
1
clkT0S/1024 (from prescaler)
4.11.11.3 Timer/Counter0 Register – TCNT0
Bit
7
6
5
4
3
2
1
0
TCNT07
TCNT06
TCNT05
TCNT04
TCNT03
TCNT02
TCNT01
TCNT00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCNT0
The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter.
Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter
(TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0x
register.
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4.11.11.4 Output Compare Register A – OCR0A
Bit
7
6
5
4
3
2
1
0
OCR0A7 OCR0A6 OCR0A5 OCR0A4 OCR0A3 OCR0A2 OCR0A1 OCR0A0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
OCR0A
The output compare register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A
match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin.
4.11.11.5 Asynchronous Status Register – ASSR
Bit
7
6
5
–
EXCLK
AS0
4
3
Read/Write
R
R/W
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
TCN0UB OCR0AUB
2
–
1
0
TCR0AUB TCR0BUB
ASSR
• Bit 7 – Res: Reserved Bit
This bit is reserved in the Atmel® ATtiny87/167 and will always read as zero.
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an
external clock can be input on XTAL1 pin instead of an external crystal. Writing to EXCLK should be done before
asynchronous operation is selected. Note that the crystal oscillator will only run when this bit is zero.
• Bit 5 – AS0: Asynchronous Timer/Counter0
When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O and the Timer/Counter0 acts as a
synchronous peripheral.
When AS0 is written to one, Timer/Counter0 is clocked from the low-frequency crystal oscillator (Section 4.5.2.5 “Lowfrequency Crystal Oscillator” on page 51) or from external clock on XTAL1 pin (Section 4.5.2.6 “External Clock” on page 52)
depending on EXCLK setting. When the value of AS0 is changed, the contents of TCNT0, OCR0A, and TCCR0A might be
corrupted.
AS0 also acts as a flag: Timer/Counter0 is clocked from the low-frequency crystal or from external clock ONLY IF the
calibrated internal RC oscillator or the internal watchdog oscillator is used to drive the system clock. After setting AS0, if the
switching is available, AS0 remains to 1, else it is forced to 0.
• Bit 4 – TCN0UB: Timer/Counter0 Update Busy
When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been
updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT0 is
ready to be updated with a new value.
• Bit 3 – OCR0AUB: Output Compare 0 Register A Update Busy
When Timer/Counter0 operates asynchronously and OCR0A is written, this bit becomes set. When OCR0A has been
updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR0A is
ready to be updated with a new value.
• Bit 2 – Res: Reserved Bit
This bit is reserved in the Atmel ATtiny87/167 and will always read as zero.
• Bit 1 – TCR0AUB: Timer/Counter0 Control Register A Update Busy
When Timer/Counter0 operates asynchronously and TCCR0A is written, this bit becomes set. When TCCR0A has been
updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0A
is ready to be updated with a new value.
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• Bit 0 – TCR0BUB: Timer/Counter0 Control Register B Update Busy
When Timer/Counter0 operates asynchronously and TCCR0B is written, this bit becomes set. When TCCR0B has been
updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0B
is ready to be updated with a new value.
If a write is performed to any of the four Timer/Counter0 registers while its update busy flag is set, the updated value might
get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT0, OCR0A, TCCR0A and TCCR0B are different. When reading TCNT0, the actual timer
value is read. When reading OCR0A, TCCR0A or TCCR0B the value in the temporary storage register is read.
4.11.11.6 Timer/Counter0 Interrupt Mask Register – TIMSK0
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
OCIE0A
TOIE0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIMSK0
• Bit 7:2 – Res: Reserved Bits
These bits are reserved in the Atmel® ATtiny87/167 and will always read as zero.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one and the I-bit in the status register is set (one), the Timer/Counter0 compare match A
interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the
OCF0A bit is set in the Timer/Counter0 interrupt flag register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one and the I-bit in the status register is set (one), the Timer/Counter0 overflow interrupt is
enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in
the Timer/Counter0 interrupt flag register – TIFR0.
4.11.11.7 Timer/Counter0 Interrupt Flag Register – TIFR0
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
OCF0A
TOV0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIFR0
• Bit 7:2 – Res: Reserved Bits
These bits are reserved in the Atmel ATtiny87/167 and will always read as zero.
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0A – output
compare register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 compare
match Interrupt Enable), and OCF0A are set (one), the Timer/Counter0 compare match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG
I-bit, TOIE0A (Timer/Counter0 overflow interrupt enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is
executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00.
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4.11.11.8 General Timer/Counter Control Register – GTCCR
Bit
7
6
5
4
3
2
1
0
TSM
–
–
–
–
–
PSR0
PSR1
Read/Write
R/W
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
GTCCR
• Bit 1 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If the
bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been
reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter
Synchronization Mode” on page 119 for a description of the Timer/Counter synchronization mode.
4.12
Timer/Counter1 Prescaler
4.12.1 Overview
Most bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number.
4.12.1.1 Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest
operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of
four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8,
fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.
4.12.1.2 Prescaler Reset
The prescaler is free running, i.e., operates independently of the clock select logic of the Timer/Counter. Since the prescaler
is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a
prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler
(6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1
to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be
taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the
prescaler period for all Timer/Counters it is connected to.
4.12.1.3 External Clock Source
An external clock source applied to the T1 pin can be used as Timer/Counter clock (clkT1). The T1 pin is sampled once
every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the
edge detector. Figure 4-42 shows a functional equivalent block diagram of the T1 synchronization and edge detector logic.
The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period
of the internal system clock.
The edge detector generates one clkT1 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects.
Figure 4-42. T1 Pin Sampling
Tn
D
Q
D
Q
D
Tn_sync
(to Clock
Select Logic)
Q
LE
clkI/O
Synchronization
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Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been
applied to the T1 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1 has been
stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The
external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50 %
duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the
sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle
caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of
an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 4-43. Prescaler for Timer/Counter1(1)
CK/256
CK/8
PSRn
CK/1024
10-bit T/C Prescaler
Clear
CK/64
clkI/O
0
Tn
Synchronization
CSn0
CSn1
CSn2
clkTn
Timer/Counter n Clock Source
Note:
1.
The synchronization logic on the input pin (T1) is shown in Figure 4-42.
4.12.2 Timer/Counter1 Prescalers Register Description
4.12.2.1General Timer/Counter Control Register – GTCCR
Bit
7
6
5
4
3
2
1
0
TSM
–
–
–
–
–
PSR0
PSR1
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
GTCCR
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter synchronization mode. In this mode, the value that is written to the
PSR0 and PSR1 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the
corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing
during configuration. When the TSM bit is written to zero, the PSR0 and PSR1 bits are cleared by hardware, and the
Timer/Counters start counting simultaneously.
• Bit 0 – PSR1: Prescaler Reset Timer/Counter1
When this bit is one, Timer/Counter1 prescaler will be reset. This bit is normally cleared immediately by hardware, except if
the TSM bit is set.
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4.13
16-bit Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal
timing measurement. The main features are:
4.13.1 Features
●
●
●
●
●
●
●
●
●
●
●
●
True 16-bit design (i.e., allows 16-bit PWM)
Two independent output compare units
Four controlled output pins per output compare unit
Double buffered output compare registers
One input capture unit
Input capture noise canceler
Clear timer on compare match (auto reload)
Glitch-free, phase correct pulse width modulator (PWM)
Variable PWM period
Frequency generator
External event counter
Four independent interrupt sources (TOV1, OCF1A, OCF1B, and ICF1)
4.13.2 Overview
Many register and bit references in this section are written in general form.
● A lower case “n” replaces the Timer/Counter number, in this case 1. However, when using the register or bit defines in
a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
●
A lower case “x” replaces the output compare unit channel, in this case A or B. However, when using the register or bit
defines in a program, the precise form must be used, i.e., OCR1A for accessing Timer/Counter1 output compare
channel A value and so on.
●
A lower case “i” replaces the index of the output compare output pin, in this case U, V, W or X. However, when using
the register or bit defines in a program, the precise form must be used.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 4-44. CPU accessible I/O registers, including I/O
bits and I/O pins, are shown in bold. The device-specific I/O register and bit locations are listed in the Section 4.13.11 “16-bit
Timer/Counter Register Description” on page 141.
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Figure 4-44. 16-bit Timer/Counter1 Block Diagram(1)
TOVn (Int. Req.)
Count
Clear
Direction
Clock Select
Control Logic
clkTn
TOP
BOTTOM
=
=
Edge
Detector
Tn
(from Prescaler)
Timer/Counter
TCNTn
0
OCnA (Int. Req.)
Waveform
Generation
=
OCnAU
OCnAV
OCRnA
Fixed
TOP
Value
OCnAW
DATA BUS
OCnAX
OCnB (Int. Req.)
Waveform
Generation
=
OCnBU
OCnBV
OCRnB
OCnBW
OCnBX
(From Analog
Comparator Output)
ICFn (Int. Req.)
Edge
Detector
ICRn
TCCRnA
Note:
1.
TCCRnB
Noise
Canceler
ICPn
TCCRnC
Refer to Table 4-27 on page 97, and Table 4-24 on page 92 for Timer/Counter1 pin placement and description.
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4.13.2.1 Registers
The Timer/Counter (TCNT1), output compare registers (OCR1A/B), and input capture register (ICR1) are all 16-bit registers.
special procedures must be followed when accessing the 16-bit registers. These procedures are described in Section 4.13.3
“Accessing 16-bit Registers” on page 123. The Timer/Counter control registers (TCCR1A/B) are 8-bit registers and have no
CPU access restrictions. Interrupt requests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt
flag register (TIFR1). All interrupts are individually masked with the timer interrupt mask register (TIMSK1). TIFR1 and
TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The clock select
logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer
clock (clkTn).
The double buffered output compare registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result
of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output
compare pins, see Section 4.13.7 “Output Compare Units” on page 128. The compare match event will also set the compare
match flag (OCF1A/B) which can be used to generate an output compare interrupt request.
The input capture register can capture the Timer/Counter value at a given external (edge triggered) event on either the input
capture pin (ICP1) or on the analog comparator pins (Section 4.19 “AnaComp - Analog Comparator” on page 209). The input
capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A
register, the ICR1 register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A
register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing
the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 register can be used as an alternative,
freeing the OCR1A to be used as PWM output.
4.13.2.2 Definitions
The following definitions are used extensively throughout the section:
BOTTOM
122
The counter reaches the BOTTOM when it becomes 0x0000.
MAX
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65,535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF,
0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 register. The
assignment is dependent of the mode of operation.
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4.13.3 Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR® CPU via the 8-bit data bus. The
16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for
temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers
within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit
register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the
16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit
register is copied into the temporary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve
using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the
high byte.
4.13.3.1 Code Examples
The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the
temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 registers. Note that when
using “C”, the compiler handles the 16-bit access.
Assembly Code Examples(1)
...
; Set TCNT1 to 0x01FF
ldi
r17,0x01
ldi
r16,0xFF
sts
TCNT1H,r17
sts
TCNT1L,r16
; Read TCNT1 into r17:r16
lds
r16,TCNT1L
lds
r17,TCNT1H
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...
Note:
The example code assumes that the part specific header file is included
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two
instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or
any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when
both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during
the 16-bit access.
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The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B
or ICR1 registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
lds
r16,TCNT1L
lds
r17,TCNT1H
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1(void)
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note:
1. The example code assumes that the part specific header file is included.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B
or ICR1 registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
sts
TCNT1H,r17
sts
TCNT1L,r16
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1(unsigned int i)
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
Note:
1. The example code assumes that the part specific header file is included1
The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1.
4.13.3.2 Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only
needs to be written once. However, note that the same rule of atomic operation described previously also applies in this
case.
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4.13.4 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock
select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter control register B (TCCR1B).
For details on clock sources and prescaler, see Section 4.12 “Timer/Counter1 Prescaler” on page 118.
4.13.5 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 4-45 shows a block
diagram of the counter and its surroundings.
Figure 4-45. Counter Unit Block Diagram
DATA BUS
(8-bit)
TOVn
(Int. Req.)
TEMP (8-bit)
Clock Select
Count
TCNTnH (8-bit)
TCNTnL (8-bit)
TCNTnH (16-bit Counter)
Clear
Control Logic
clkTn
Edge
Detector
Tn
Direction
(From Prescaler)
TOP
BOTTOM
Signal description (internal signals):
Count
Increment or decrement TCNT1 by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNT1 (set all bits to zero).
clkT1
Timer/Counter clock.
TOP
Signalize that TCNT1 has reached maximum value.
BOTTOM
Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) containing the upper eight bits of
the counter, and counter low (TCNT1L) containing the lower eight bits. The TCNT1H register can only be indirectly accessed
by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register
(TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with
the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value
within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1
Register when the counter is counting that will give unpredictable results. The special cases are described in the sections
where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1).
The clkT1 can be generated from an external or internal clock source, selected by the clock select bits (CS12:0). When no
clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU,
independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the waveform generation mode bits (WGM13:0) located in the
Timer/Counter control registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the output compare outputs OC1A/B. For more details about
advanced counting sequences and waveform generation, see Section 4.13.9 “Modes of Operation” on page 133.
The Timer/Counter overflow flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can
be used for generating a CPU interrupt.
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4.13.6 Input Capture Unit
The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp
indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or
alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and
other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
The input capture unit is illustrated by the block diagram shown in Figure 4-46. The elements of the block diagram that are
not directly a part of the input capture unit are gray shaded.
Figure 4-46. Input Capture Unit Block Diagram
DATA BUS (8-bit)
TEMP (8-bit)
ICRnH (8-bit)
TCNTnH (8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
ICRn (16-bit Register)
WRITE
TCNTnL (8-bit)
ACIC
ICNCn
ICESn
Noise
Canceler
Edge
Detector
ICPn
+
-
ICFn (Int. Req.)
ACO
Analog
Comparator
When a change of the logic level (an event) occurs on the input capture pin (ICP1), alternatively on the analog comparator
output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is
triggered, the 16-bit value of the counter (TCNT1) is written to the input capture register (ICR1). The input capture flag (ICF1)
is set at the same system clock as the TCNT1 value is copied into ICR1 register. If enabled (ICIE1 = 1), the input capture flag
generates an input capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the
ICF1 flag can be cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the input capture register (ICR1) is done by first reading the low byte (ICR1L) and then the high
byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the
CPU reads the ICR1H I/O location it will access the TEMP register.
The ICR1 register can only be written when using a waveform generation mode that utilizes the ICR1 register for defining the
counter’s TOP value. In these cases the waveform generation mode (WGM13:0) bits must be set before the TOP value can
be written to the ICR1 register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location
before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to Section 4.13.3 “Accessing 16-bit Registers” on page 123.
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4.13.6.1 Input Capture Trigger Source
The main trigger source for the input capture unit is the input capture pin (ICP1). Only Timer/Counter1 can alternatively use
the analog comparator output as trigger source for the input capture unit. The analog comparator is selected as trigger
source by setting the analog comparator input capture (ACIC) bit in the analog comparator control and status register
(ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag must therefore be cleared after
the change.
Both the input capture pin (ICP1) and the analog comparator output (ACO) inputs are sampled using the same technique as
for the T1 pin (Figure 4-42 on page 118). The edge detector is also identical. However, when the noise canceler is enabled,
additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the
input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a waveform generation
mode that uses ICR1 to define TOP.
An input capture can be triggered by software by controlling the port of the ICP1 pin.
4.13.6.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored
over four samples, and all four must be equal for changing the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the input capture noise canceler (ICNC1) bit in Timer/Counter control register B
(TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied
to the input, to the update of the ICR1 register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
4.13.6.3 Using the Input Capture Unit
The main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming
events. The time between two events is critical. If the processor has not read the captured value in the ICR1 register before
the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect.
When using the input capture interrupt, the ICR1 register should be read as early in the interrupt handler routine as possible.
Even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the
maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the input capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation,
is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the
edge sensing must be done as early as possible after the ICR1 register has been read. After a change of the edge, the input
capture flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICF1 flag is not required (if an interrupt handler is used).
4.13.7 Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the output compare register (OCR1A/B). If TCNT equals
OCR1A/B the comparator signals a match. A match will set the output compare flag (OCF1A/B) at the next timer clock cycle.
If enabled (OCIE1A/B = 1), the output compare flag generates an output compare interrupt. The OCF1A/B flag is
automatically cleared when the interrupt is executed. Alternatively the OCF1A/B flag can be cleared by software by writing a
logical one to its I/O bit locations. The waveform generator uses the match signal to generate an output according to
operating mode set by the waveform generation mode (WGM13:0) bits and compare output mode (COM1A/B1:0) bits. The
TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in
some modes of operation (see Section 4.13.9 “Modes of Operation” on page 133).
A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In
addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform
generator.
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Figure 4-47 shows a block diagram of the output compare unit. The elements of the block diagram that are not directly a part
of the Output Compare unit are gray shaded.
Figure 4-47. Output Compare Unit, Block Diagram
DATA BUS (8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
OCRnx Buffer (16-bit Register)
OCRnxH (8-bit)
TCNTnL (8-bit)
TCNTn (16-bit Counter)
OCRnxL (8-bit)
OCRnx (16-bit Register)
=
(16-bit Comparator)
OCFnx (Int. Req.)
OCnxU
TOP
Waveform Generator
OCnxV
BOTTOM
WGMn3:0
COMnx1:0
OCnxW
OCnxX
The OCR1A/B register is double buffered when using any of the twelve pulse width modulation (PWM) modes. For the
normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR1A/B compare register to either TOP or BOTTOM of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR1A/B register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR1A/B buffer register, and if double buffering is disabled the CPU will access the OCR1A/B directly. The
content of the OCR1A/B (buffer or compare) register is only changed by a write operation (the Timer/Counter does not
update this register automatically as the TCNT1 and ICR1 register). Therefore OCR1A/B is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers.
Writing the OCR1A/B registers must be done via the TEMP register since the compare of all 16 bits is done continuously.
The high byte (OCR1A/BH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP register
will be updated by the value written. Then when the low byte (OCR1A/BL) is written to the lower eight bits, the high byte will
be copied into the upper 8-bits of either the OCR1A/B buffer or OCR1A/B compare register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to Section 4.13.3 “Accessing 16-bit Registers” on page 123.
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4.13.7.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force
output compare (FOC1A/B) bit. Forcing compare match will not set the OCF1A/B flag or reload/clear the timer, but the
OC1A/Bi pins will be updated as if a real compare match had occurred (the COM1A/B1:0 bits settings define whether the
OC1A/Bi pins are set, cleared or toggled - if the respective OCnxi bit is set).
4.13.7.2 Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 register will block any compare match that occurs in the next timer clock cycle, even when the
timer is stopped. This feature allows OCR1A/B to be initialized to the same value as TCNT1 without triggering an interrupt
when the Timer/Counter clock is enabled.
4.13.7.3 Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks
involved when changing TCNT1 when using any of the output compare channels, independent of whether the Timer/Counter
is running or not. If the value written to TCNT1 equals the OCR1A/B value, the compare match will be missed, resulting in
incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The
compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value
equal to BOTTOM when the counter is downcounting.
The setup of the OC1A/B should be performed before setting the data direction register for the port pin to output. The easiest
way of setting the OC1A/B value is to use the force output compare (FOC1A/B) strobe bits in normal mode. The OC1A/B
register keeps its value even when changing between waveform generation modes.
Be aware that the COM1A/B1:0 bits are not double buffered together with the compare value. Changing the COM1A/B1:0
bits will take effect immediately.
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4.13.8 Compare Match Output Unit
The compare output mode (COM1A/B1:0) bits have two functions. The waveform generator uses the COM1A/B1:0 bits for
defining the output compare (OC1A/B) state at the next compare match. Secondly the COM1A/B1:0 and OCnxi bits control
the OC1A/Bi pin output source. Figure 4-49 shows a simplified schematic of the logic affected by the COM1A/B1:0 and
OCnxi bit setting. The I/O registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O
port control registers (DDR and PORT) that are affected by the COM1A/B1:0 and OCnxi bits are shown. When referring to
the OC1A/B state, the reference is for the internal OC1A/B Register, not the OC1A/Bi pin. If a system reset occur, the
OC1A/B register is reset to “0”.
Figure 4-48. Compare Match Output
OC1AU (*)
PINB0
1
20 PB0/ OC1AU
PORTB0
0
DDB0
OC1AV (*)
PINB2
1
18 PB2/ OC1AV
PORTB2
0
DDB2
OC1AW(*)
PINB4
1
14 PB4/ OC1AW
PORTB4
OCR1A
16-bit Register
0
DDB4
COM1A0
COM1A1
OC1AX (*)
PINB6
OCF1A
1
Waveform
Generation
=
12 PB6/ OC1AX
PORTB6
0
FOC1A
Count
Clear
Direction
TCNT1
16-bit Counter
WGM10
WGM11
WGM12
WGM13
DDB6
TOP
BOTTOM
FOC1B
OC1BU (*)
=
OCF11
PINB1
1
Waveform
Generation
19 PB1/ OC1BU
PORTB1
0
DDB1
COM1B0
OCR1B
16-bit Register
COM1B1
OC1BV (*)
PINB3
1
17 PB3/ OC1BV
PORTB2
0
DDB3
OC1BW (*)
PINB5
1
13 PB5/ OC1BW
PORTB4
0
DDB5
OC1BX (*)
PINB7
1
(*)
OC1xi: TCCR1D register bit
11 PB7/ OC1BX
PORTB7
0
DDB7
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Figure 4-49. Compare Match Output Logic
OCnxi
COMnx1
COMnx0
FOCnx
Waveform
Generator
D
Q
1
OCnxi
Pin
OCnx
0
DATA BUS
D
Q
PORT
D
clkI/O
Q
DDR
4.13.8.1 Compare Output Function
The general I/O port function is overridden by the output compare (OC1A/B) from the waveform generator if either of the
COM1A/B1:0 bits are set and if OCnxi respective bit is set in TCCR1D register. However, the OC1A/Bi pin direction (input or
output) is still controlled by the data direction register (DDR) for the port pin. The data direction register bit for the OC1A/Bi
pin (DDR_OC1A/Bi) must be set as output before the OC1A/B value is visible on the pin. The port override function is
generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 4-35, Table 4-36
and Table 4-37 for details.
The design of the output compare pin logic allows initialization of the OC1A/B state before the output is enabled. Note that
some COM1A/B1:0 bit settings are reserved for certain modes of operation. See Section 4.13.11 “16-bit Timer/Counter
Register Description” on page 141.
The COM1A/B1:0 bits have no effect on the input capture unit.
4.13.8.2 Compare Output Mode and Waveform Generation
The waveform generator uses the COM1A/B1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the
COM1A/B1:0 = 0 tells the waveform generator that no action on the OC1A/B register is to be performed on the next compare
match. For compare output actions in the non-PWM modes refer to Table 4-35 on page 141. For fast PWM mode refer to
Table 4-36 on page 141, and for phase correct and phase and frequency correct PWM refer to Table 4-37 on page 142.
A change of the COM1A/B1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the FOC1A/B strobe bits.
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4.13.9 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of
the waveform generation mode (WGM13:0) and compare output mode (COM1A/B1:0) bits. The compare output mode bits
do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1A/B1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the
COM1A/B1:0 bits control whether the output should be set, cleared or toggle at a compare match (see Section 4.13.8
“Compare Match Output Unit” on page 131). The OCnxi bits over control the setting of the COM1A/B1:0 bits as shown in
Figure 4-49 on page 132.
For detailed timing information refer to Section 4.13.10 “Timer/Counter Timing Diagrams” on page 139.
4.13.9.1 Normal Mode
The simplest mode of operation is the normal mode (WGM13:0 = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value
(MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter overflow flag (TOV1)
will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit,
except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1
flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new
counter value can be written anytime.
The input capture unit is easy to use in normal mode. However, observe that the maximum interval between the external
events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt
or the prescaler must be used to extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using the output compare to generate
waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.
4.13.9.2 Clear Timer on Compare Match (CTC) Mode
In clear timer on compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 register are used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A
(WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its
resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of
counting external events.
The timing diagram for the CTC mode is shown in Figure 4-50. The counter value (TCNT1) increases until a compare match
occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
Figure 4-50. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnAi
(Toggle)
Period
(COMnA1:0 = 1)
1
2
3
4
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An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag
according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used
for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none
or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new
value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The
counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare
match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using
OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each compare
match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the
port pin unless the data direction for the pin is set to output (DDR_OC1A = 1) and OC1Ai is set. The waveform generated will
have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by
the following equation:
f clk_I/O
f OCnA = ----------------------------------------------------2 N 1 + OCRnA
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to
0x0000.
4.13.9.3 Fast PWM Mode
The fast pulse width modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM
waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter
counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting compare output mode, the output compare
(OC1A/B) is set on the compare match between TCNT1 and OCR1A/B, and cleared at TOP. In inverting Compare Output
mode output is cleared on compare match and set at TOP. Due to the single-slope operation, the operating frequency of the
fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dualslope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total
system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum
resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to
MAX). The PWM resolution in bits can be calculated by using the following equation:
log TOP + 1
R FPWM = --------------------------------log 2
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF,
0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15).
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in
Figure 4-51. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between
OCR1A/B and TCNT1. The OC1A/B interrupt flag will be set when a compare match occurs.
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Figure 4-51. Fast PWM Mode, Timing Diagram
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnxi
(COMnx1:0 = 2)
OCnxi
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
The Timer/Counter overflow flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 flag is set
at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the
interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between
the TCNT1 and the OCR1A/B. Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCR1A/B registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 register is
not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low
prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then
be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A register however, is double
buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the
value written will be put into the OCR1A buffer register. The OCR1A compare register will then be updated with the value in
the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle
as the TCNT1 is cleared and the TOV1 flag is set.
Using the ICR1 register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A register is
free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by
changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins. Setting the COM1x1:0 bits
to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1A/B1:0 to three
(see Table 4-36 on page 141). The actual OC1A/B value will only be visible on the port pin if the data direction for the port pin
is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is generated by setting (or clearing) the OC1A/B
Register at the compare match between OCR1A/B and TCNT1, and clearing (or setting) the OC1A/B Register at the timer
clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = -----------------------------------N 1 + TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represents special cases when generating a PWM waveform output in the
fast PWM mode. If the OCR1A/B is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer
clock cycle. Setting the OCR1A/B equal to TOP will result in a constant high or low output (depending on the polarity of the
output set by the COM1A/B1:0 bits).
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A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical
level on each compare match (COM1A1:0 = 1). The waveform generated will have a maximum frequency of
fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the
double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
4.13.9.4 Phase Correct PWM Mode
The phase correct pulse width modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high
resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency
correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and
then from TOP to BOTTOM. In non-inverting compare output mode, the output compare (OC1A/B) is cleared on the
compare match between TCNT1 and OCR1A/B while upcounting, and set on the compare match while downcounting. In
inverting output compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A.
The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or
OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
log TOP + 1
R PCPWM = --------------------------------log 2
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A
(WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to
TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 4-52. The figure
shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram
shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM
outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1.
The OC1A/B interrupt flag will be set when a compare match occurs.
Figure 4-52. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnxi
(COMnx1:0 = 2)
OCnxi
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is
used for defining the TOP value, the OC1A or ICF1 flag is set accordingly at the same timer clock cycle as the OCR1A/B
Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each
time the counter reaches the TOP or BOTTOM value.
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When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between
the TCNT1 and the OCR1A/B. Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1A/B registers are written. As the third period shown in Figure 4-52 illustrates, changing the TOP actively while the
Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found
in the time of update of the OCR1A/B register. Since the OCR1A/B update occurs at TOP, the PWM period starts and ends
at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising
slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The
difference in length gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP
value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the
two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins. Setting the
COM1A/B1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the
COM1A/B1:0 to three. The actual OC1A/B value will only be visible on the port pin if the data direction for the port pin is set
as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is generated by setting (or clearing) the OC1A/B register
at the compare match between OCR1A/B and TCNT1 when the counter increments, and clearing (or setting) the OC1A/B
register at compare match between OCR1A/B and TCNT1 when the counter decrements. The PWM frequency for the output
when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = ------------------------------2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B register represent special cases when generating a PWM waveform output in the
phase correct PWM mode. If the OCR1A/B is set equal to BOTTOM the output will be continuously low and if set equal to
TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite
logic values.
4.13.9.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct pulse width modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9)
provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct
PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from
BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting compare output mode, the output compare
(OC1A/B) is cleared on the compare match between TCNT1 and OCR1A/B while upcounting, and set on the compare match
while downcounting. In inverting compare output mode, the operation is inverted. The dual-slope operation gives a lower
maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dualslope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1A/B
register is updated by the OCR1A/B buffer register, (see Figure 4-52 on page 136 and Figure 4-53 on page 138).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The
minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A
set to MAX). The PWM resolution in bits can be calculated using the following equation:
log TOP + 1
R PFCPWM = --------------------------------log 2
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in
ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the
count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct
and frequency correct PWM mode is shown on Figure 4-53. The figure shows phase and frequency correct PWM mode
when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B interrupt flag will be set when
a compare match occurs.
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Figure 4-53. Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx/ TOP Update and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnxi
(COMnx1:0 = 2)
OCnxi
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter overflow flag (TOV1) is set at the same timer clock cycle as the OCR1A/B registers are updated with the
double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag
set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur
between the TCNT1 and the OCR1A/B.
As Figure 4-53 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the
OCR1A/B Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives
symmetrical output pulses and is therefore frequency correct.
Using the ICR1 register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A register is
free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by
changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins.
Setting the COM1A/B1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by
setting the COM1A/B1:0 to three (See Table on page 142). The actual OC1A/B value will only be visible on the port pin if the
data direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is generated by
setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B and TCNT1 when the counter
increments, and clearing (or setting) the OC1A/B Register at compare match between OCR1A/B and TCNT1 when the
counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by
the following equation:
f clk_I/O
f OCnxPFCPWM = ------------------------------2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represents special cases when generating a PWM waveform output in the
phase correct PWM mode. If the OCR1A/B is set equal to BOTTOM the output will be continuously low and if set equal to
TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
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4.13.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the
following figures. The figures include information on when interrupt flags are set, and when the OCR1A/B register is updated
with the OCR1A/B buffer value (only for modes utilizing double buffering). Figure 4-54 shows a timing diagram for the setting
of OCF1A/B.
Figure 4-54. Timer/Counter Timing Diagram, Setting of OCF1A/B, No Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCRnx
OCFnx
Figure 4-55 shows the same timing data, but with the prescaler enabled.
Figure 4-55. Timer/Counter Timing Diagram, Setting of OCF1A/B, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
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Figure 4-56 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM
mode the OCR1A/B Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by
BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM.
Figure 4-56. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP -1
TOP -2
TOVn (FPWM)
and ICFn
(if used as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 4-57 shows the same timing data, but with the prescaler enabled.
Figure 4-57. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICFn
(if used as TOP)
OCRnx
(Update at TOP)
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Old OCRnx Value
New OCRnx Value
4.13.11 16-bit Timer/Counter Register Description
4.13.11.1 Timer/Counter1 Control Register A – TCCR1A
Bit
7
6
5
4
3
2
1
0
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR1A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the output compare pins (OC1Ai and OC1Bi respectively) behavior. If one or both of
the COM1A1:0 bits are written to one, the OC1Ai output overrides the normal port functionality of the I/O pin it is connected
to. If one or both of the COM1B1:0 bit are written to one, the OC1Bi output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the data direction register (DDR) bit and OC1xi bit (TCCR1D) corresponding to the
OC1Ai or OC1Bi pin must be set in order to enable the output driver.
When the OC1Ai or OC1Bi is connected to the pin, the function of the COM1A/B1:0 bits is dependent of the WGM13:0 bits
setting. Table 4-35 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode
(non-PWM).
Table 4-35. Compare Output Mode, non-PWM
OC1Ai
OC1Bi
COM1A1
COM1B1
0
1
COM1A0
COM1B0
Description
x
x
0
0
0
1
Toggle OC1A/OC1B on compare match.
1
0
Clear OC1A/OC1B on compare match (Set output to low level).
1
1
Set OC1A/OC1B on compare match (Set output to high level).
Normal port operation, OC1A/OC1B disconnected.
Table 4-36 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode.
Table 4-36. Compare Output Mode, Fast PWM(1)
OC1Ai
OC1Bi
COM1A1
COM1B1
COM1A0
COM1B0
0
x
x
1
0
0
1
0
1
1
1
0
1
1
1
Note:
1.
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B disconnected.
WGM13=1: Toggle OC1A on compare match, OC1B reserved.
Clear OC1A/OC1B on compare match
Set OC1A/OC1B at TOP
Set OC1A/OC1B on compare match
Clear OC1A/OC1B at TOP
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See Section 4.13.9.3 “Fast PWM Mode” on page
134 for more details.
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Table 4-37 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and
frequency correct, PWM mode.
Table 4-37. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
OC1Ai
OC1Bi
COM1A1
COM1B1
COM1A0
COM1B0
0
x
x
1
0
0
1
0
1
1
1
0
1
1
1
Note:
1.
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B disconnected.
WGM13=1: Toggle OC1A on compare match, OC1B reserved.
Clear OC1A/OC1B on compare match when up-counting.
Set OC1A/OC1B on compare match when downcounting.
Set OC1A/OC1B on compare match when up-counting.
Clear OC1A/OC1B on compare match when downcounting.
A special case occurs when OC1A/OC1B equals TOP and COM1A1/COM1B1 is set. See Section 4.13.9.4
“Phase Correct PWM Mode” on page 136 for more details.
• Bit 3:2 – Reserved Bits
These bits are reserved for future use.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 4-38. Modes of
operation supported by the Timer/Counter unit are: normal mode (counter), clear timer on compare match (CTC) mode, and
three types of pulse width modulation (PWM) modes (see Section 4.13.9 “Modes of Operation” on page 133).
Table 4-38. Waveform Generation Mode Bit Description(1)
Mode
WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10 Timer/Counter
(PWM10) Mode of Operation
TOP
Update of
OCR1A/B at
0
0
0
0
0
1
0
0
0
1
2
0
0
1
3
0
0
4
0
1
5
0
6
0
7
Normal
0xFFFF
Immediate
MAX
PWM, phase correct, 8-bit
0x00FF
TOP
BOTTOM
0
PWM, phase correct, 9-bit
0x01FF
TOP
BOTTOM
1
1
PWM, phase correct, 10-bit
0x03FF
TOP
BOTTOM
0
0
CTC
OCR1A
Immediate
MAX
1
0
1
Fast PWM, 8-bit
0x00FF
TOP
TOP
1
1
0
Fast PWM, 9-bit
0x01FF
TOP
TOP
0
1
1
1
Fast PWM, 10-bit
0x03FF
TOP
TOP
8
1
0
0
0
PWM, phase and frequency
correct
ICR1
BOTTOM
BOTTOM
9
1
0
0
1
PWM, phase and frequency
correct
OCR1A
BOTTOM
BOTTOM
10
1
0
1
0
PWM, phase correct
ICR1
TOP
BOTTOM
11
1
0
1
1
PWM, phase correct
OCR1A
TOP
BOTTOM
12
1
1
0
0
CTC
ICR1
Immediate
MAX
13
1
1
0
1
(Reserved)
–
–
–
14
1
1
1
0
Fast PWM
ICR1
TOP
TOP
15
Note:
1.
142
ATA6616C/ATA6617C [DATASHEET]
TOV1 Flag
Set on
1
1
1
1
Fast PWM
OCR1A
TOP
TOP
The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality
and location of these bits are compatible with previous versions of the timer.
9132J–AUTO–01/15
4.13.11.2 Timer/Counter1 Control Register B – TCCR1B
Bit
7
6
5
4
3
2
1
0
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR1B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the input capture noise canceler. When the noise canceler is activated, the input from the
input capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for
changing its output. The input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the input capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is
written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge
will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the input capture register
(ICR1). The event will also set the input capture flag (ICF1), and this can be used to cause an input capture interrupt, if this
interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B
Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when
TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 4-54 on page 139 and
Figure 4-55 on page 139.
Table 4-39. Clock Select Bit Description
CS12
CS11
CS10
Description
0
0
0
No clock source (Timer/Counter stopped).
0
0
1
clkI/O/1 (no prescaling)
0
1
0
clkI/O/8 (from prescaler)
0
1
1
clkI/O/64 (from prescaler)
1
0
0
clkI/O/256 (from prescaler)
1
0
1
clkI/O/1024 (from prescaler)
1
1
0
External clock source on T1 pin. Clock on falling edge.
1
1
1
External clock source on T1 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is
configured as an output. This feature allows software control of the counting.
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4.13.11.3 Timer/Counter1 Control Register C – TCCR1C
Bit
7
6
5
4
3
2
1
FOC1A
FOC1B
–
–
–
–
–
0
–
Read/Write
R/W
R/W
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
TCCR1C
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring
compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode.
When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the waveform generation
unit. The OC1nx output is changed according to its COM1A/B1:0 and OC1nx bits setting. Note that the FOC1A/FOC1B bits
are implemented as strobes. Therefore it is the value present in the COM1A/B1:0 bits that determine the effect of the forced
compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC)
mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
4.13.11.4 Timer/Counter1 Control Register D – TCCR1D
Bit
7
6
5
4
3
2
1
0
OC1BX
OC1BW
OC1BV
OC1BU
OC1AX
OC1AW
OC1AV
OC1AU
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR1D
• Bit 7:4 – OC1Bi: Output Compare Pin Enable for Channel B
The OC1Bi bits enable the output compare pins of channel B as shown in Figure 4-49 on page 132.
• Bit 3:0 – OC1Ai: Output Compare Pin Enable for Channel A
The OC1Ai bits enable the output compare pins of channel A as shown in Figure 4-49 on page 132.
4.13.11.5 Timer/Counter1 – TCNT1H and TCNT1L
Bit
7
6
5
4
3
2
1
0
TCNT1[15:8]
TCNT1H
TCNT1[7:0]
TCNT1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for
write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See Section 4.13.3 “Accessing 16-bit Registers”
on page 123.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1
and one of the OCR1A/B Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units.
144
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9132J–AUTO–01/15
4.13.11.6 Output Compare Register A – OCR1AH and OCR1AL
Bit
7
6
5
4
3
2
1
0
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
OCR1AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
2
1
0
4.13.11.7 Output Compare Register B – OCR1BH and OCR1BL
Bit
7
6
5
4
3
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The output compare registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match
can be used to generate an output compare interrupt, or to generate a waveform output on the OC1A/B pin.
The output compare registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when
the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This
temporary register is shared by all the other 16-bit registers. See Section 4.13.3 “Accessing 16-bit Registers” on page 123.
4.13.11.8 Input Capture Register – ICR1H and ICR1L
Bit
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The input capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the
analog comparator output for Timer/Counter1). The input capture can be used for defining the counter TOP value.
The input capture register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary
register is shared by all the other 16-bit registers. See Section 4.13.3 “Accessing 16-bit Registers” on page 123.
4.13.11.9 Timer/Counter1 Interrupt Mask Register – TIMSK1
Bit
7
6
5
4
3
2
1
0
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
Read/Write
R
R
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIMSK1
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIE1: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1
input capture interrupt is enabled. The corresponding interrupt vector (see Section 4.8.1 “Innterrupt Vectors in Atmel
ATtiny87/167” on page 76) is executed when the ICF1 flag, located in TIFR1, is set.
• Bit 4..3 – Reserved Bits
These bits are reserved for future use.
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• Bit 2 – OCIE1B: Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1
output compare B Match interrupt is enabled. The corresponding interrupt vector (see Section 4.8.1 “Innterrupt Vectors in
Atmel ATtiny87/167” on page 76) is executed when the OCF1B flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1
output compare A match interrupt is enabled. The corresponding interrupt vector (see Section 4.8.1 “Innterrupt Vectors in
Atmel ATtiny87/167” on page 76) is executed when the OCF1A flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1
overflow interrupt is enabled. The corresponding interrupt vector (see Section 4.8.1 “Innterrupt Vectors in Atmel
ATtiny87/167” on page 76) is executed when the TOV1 flag, located in TIFR1, is set.
4.13.11.10Timer/Counter1 Interrupt Flag Register – TIFR1
Bit
7
6
5
Read/Write
Initial Value
0
4
3
2
1
0
–
–
ICF1
R
R
R/W
–
–
OCF1B
OCF1A
TOV1
R
R
R/W
R/W
R/W
0
0
0
0
0
0
0
TIFR1
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICF1: Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the input capture register (ICR1) is set by the WGM13:0
to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the input capture interrupt vector is executed. Alternatively, ICF1 can be cleared by
writing a logic one to its bit location.
• Bit 4..3 – Reserved Bits
These bits are reserved for future use.
• Bit 2 – OCF1B: Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output compare register B (OCR1B).
Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the output compare match B interrupt vector is executed. Alternatively, OCF1B can be
cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output compare register A (OCR1A).
Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the output compare match A interrupt vector is executed. Alternatively, OCF1A can be
cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In normal and CTC modes, the TOV1 flag is set when the
timer overflows. Refer to Table 4-38 on page 142 for the TOV1 flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 overflow interrupt vector is executed. Alternatively, TOV1 can be
cleared by writing a logic one to its bit location.
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4.14
SPI - Serial Peripheral Interface
The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the Atmel® ATtiny87/167 and
peripheral devices or between several AVR® devices. The Atmel ATtiny87/167 SPI includes the following features:
4.14.1 Features
●
●
●
●
●
●
●
●
Full-duplex, three-wire synchronous data transfer
Master or slave operation
LSB first or MSB first data transfer
Seven programmable bit rates
End of transmission interrupt flag
Write collision flag protection
Wake-up from idle mode
Double speed (CK/2) master SPI mode
Figure 4-58. SPI Block Diagram(1)
MISO
S
clkI/O
MSB
M
M
LSB
8-bit Shift Register
Read Data Buffer
Pin
Control
Logic
Divider
/2/4/8/16/32/64/128
Clock
SPI Clock (Master)
SPR0
DORD
SPR0
SPR1
CPHA
CPOL
SPI Control Register
8
SPI Interrupt
Request
MSTR
SPIE
SPI Status Register
DORD
SPI2X
8
SPE
MSTR
SPE
WCOL
SPIF
SPE
MSTR
SPR1
SPI2X
M
SS
SPI Control
1.
SCK
S
Clock
Logic
Select
Note:
MOSI
S
8
Internal
Data Bus
Refer to Table 4-24 on page 92 for SPI pin placement.
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The interconnection between master and slave CPUs with SPI is shown in Figure 4-59. The system consists of two shift
registers, and a master clock generator. The SPI master initiates the communication cycle when pulling low the slave select
SS pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master
generates the required clock pulses on the SCK line to interchange data. Data is always shifted from master to slave on the
master out – slave in, MOSI, line, and from slave to master on the master in – slave out, MISO, line. After each data packet,
the master will synchronize the slave by pulling high the slave select, SS, line.
When configured as a master, the SPI interface has no automatic control of the SS line. This must be handled by user
software before communication can start. When this is done, writing a byte to the SPI data register starts the SPI clock
generator, and the hardware shifts the eight bits into the slave. After shifting one byte, the SPI clock generator stops, setting
the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is
requested. The master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high
the slave select, SS line. The last incoming byte will be kept in the buffer register for later use.
When configured as a slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high.
In this state, software may update the contents of the SPI data register, SPDR, but the data will not be shifted out by
incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of
transmission flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR register is set, an interrupt is requested. The
slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be
kept in the buffer register for later use.
Figure 4-59. SPI Master-slave Interconnection
MSB
MASTER
LSB
MISO
MISO
MSB
8 Bit Shift Register
SPI
Clock Generator
SLAVE
LSB
8 Bit Shift Register
MOSI
MOSI
SCK
SCK
SS
Shift
Enable
SS
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to
be transmitted cannot be written to the SPI data register before the entire shift cycle is completed. When receiving data,
however, a received character must be read from the SPI data register before the next character has been completely
shifted in. Otherwise, the first byte is lost.
In SPI slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock
signal, the frequency of the SPI clock should never exceed fclkio/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 4-40. For
more details on automatic port overrides, refer to Section 4.10.3 “Alternate Port Functions” on page 89.
Table 4-40. SPI Pin Overrides(1)
Pin
Direction, Master SPI
Direction, Slave SPI
MOSI
User defined
Input
MISO
Input
User defined
SCK
User defined
Input
SS
Note:
1.
148
User defined
Input
See Section 4.10.3.4 “Alternate Functions of Port B” on page 97 for a detailed description of how to define the
direction of the user defined SPI pins.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
DDR_SPI in the examples must be replaced by the actual data direction register controlling the SPI pins. DD_MOSI,
DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2,
replace DD_MOSI with DDB2 and DDR_SPI with DDRB.
Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi
r17,(1<<DD_MOSI)|(1<<DD_SCK)
out
DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi
r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out
SPCR,r17
ret
SPI_MasterTransmit:
; Start transmission of data (r16)
out
SPDR,r16
Wait_Transmit:
; Wait for transmission complete
in
r17,SPSR
sbrs
r17,SPIF
rjmp
Wait_Transmit
ret
C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
Note:
void SPI_MasterTransmit(char cData)
{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)));
}
1. The example code assumes that the part specific header file is included.
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
Assembly Code Example(1)
SPI_SlaveInit:
; Set MISO output, all others input
ldi
r17,(1<<DD_MISO)
out
DDR_SPI,r17
; Enable SPI
ldi
r17,(1<<SPE)
out
SPCR,r17
ret
SPI_SlaveReceive:
; Wait for reception complete
sbis
SPSR,SPIF
rjmp
SPI_SlaveReceive
; Read received data and return
in
r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
Note:
150
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)));
/* Return data register */
return SPDR;
}
1. The example code assumes that the part specific header file is included.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
4.14.2 SS Pin Functionality
4.14.2.1 Slave Mode
When the SPI is configured as a slave, the slave select (SS) pin is always input. When SS is held low, the SPI is activated,
and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are
inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once
the SS pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock
generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any
partially received data in the shift register.
4.14.2.2 Master Mode
When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be
driving the SS pin of the SPI slave.
If SS is configured as an input, it must be held high to ensure master SPI operation. If the SS pin is driven low by peripheral
circuitry when the SPI is configured as a master with the SS pin defined as an input, the SPI system interprets this as
another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the
following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave,
the MOSI and SCK pins become inputs.
2.
The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine
will be executed.
Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possibility that SS is driven low, the
interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set
by the user to re-enable SPI master mode.
4.14.2.3 SPI Control Register – SPCR
Bit
7
6
5
4
3
2
1
0
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and if the global interrupt enable bit in
SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and slave SPI mode when written logic zero. If SS is configured as an
input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have
to set MSTR to re-enable SPI master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure
4-60 on page 154 and Figure 4-61 on page 154 for an example. The CPOL functionality is summarized below:
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Table 4-41. CPOL Functionality
CPOL
Leading Edge
Trailing Edge
0
Rising
Falling
1
Falling
Rising
• Bit 2 – CPHA: Clock Phase
The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK.
Refer to Figure 4-60 and Figure 4-61 for an example. The CPOL functionality is summarized below:
Table 4-42. CPHA Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
Setup
1
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The
relationship between SCK and the clkIO frequency fclkio is shown in the following table.
Table 4-43. Relationship Between SCK and the Oscillator Frequency
152
SPI2X
SPR1
SPR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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SCK Frequency
fclkio/4
fclkio/16
fclkio/64
fclkio/128
fclkio/2
fclkio/8
fclkio/32
fclkio/64
4.14.2.4 SPI Status Register – SPSR
Bit
7
6
5
4
3
2
1
0
SPIF
WCOL
–
–
–
–
–
SPI2X
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts
are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by
first reading the SPI Status Register with SPIF set, then accessing the SPI data register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are
cleared by first reading the SPI status register with WCOL set, and then accessing the SPI data register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the Atmel® ATtiny87/167 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK frequency) will be doubled when the SPI is in master mode (see
Table 4-43). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as slave,
the SPI is only guaranteed to work at fclkio/4 or lower.
The SPI interface on the Atmel ATtiny87/167 is also used for program memory and EEPROM downloading or uploading.
See Section 4.22.8 “Serial Downloading” on page 233 for serial programming and verification.
4.14.2.5 SPI Data Register – SPDR
Bit
7
6
5
4
3
2
1
0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
X
X
X
X
X
X
X
X
SPDR
Undefined
• Bits 7:0 - SPD7:0: SPI Data
The SPI data register is a read/write register used for data transfer between the register file and the SPI shift register. Writing
to the register initiates data transmission. Reading the register causes the shift register receive buffer to be read.
4.14.3 Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits
CPHA and CPOL. The SPI data transfer formats are shown in Figure 4-60 and Figure 4-61 on page 154. Data bits are
shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing Table 4-41 on page 152 and Table 4-42 on page 152, as done below.
Table 4-44. CPOL Functionality
Leading Edge
Trailing Edge
SPI Mode
CPOL=0, CPHA=0
Sample (Rising)
Setup (Falling)
0
CPOL=0, CPHA=1
Setup (Rising)
Sample (Falling)
1
CPOL=1, CPHA=0
Sample (Falling)
Setup (Rising)
2
CPOL=1, CPHA=1
Setup (Falling)
Sample (Rising)
3
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Figure 4-60. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB
LSB first (DORD =1) LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
Figure 4-61. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD =1)
154
MSB
LSB
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Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
4.15
USI – Universal Serial Interface
4.15.1 Features
●
●
●
●
●
●
Two-wire synchronous data transfer (master or slave)
Three-wire synchronous data transfer (master or slave)
Data received interrupt
Wake-up from idle mode
In two-wire mode: Wake-up from all sleep modes, including power-down mode
Two-wire start condition detector with interrupt capability
4.15.2 Overview
The universal serial interface, or USI, provides the basic hardware resources needed for serial communication. Combined
with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than
solutions based on software only. Interrupts are included to minimize the processor load.
A simplified block diagram of the USI is shown on Figure 4-62. CPU accessible I/O registers, including I/O bits and I/O pins,
are shown in bold. The device-specific I/O Register and bit locations are listed in the Section 4.15.5 “Register Descriptions”
on page 161.
Figure 4-62. Universal Serial Interface, Block Diagram
D
DO
Q
(Output only)
LE
(Input/ Open Drain))
Bit0
Bit7
DI/ SDA
3
2
USIDR
1
0
TIM0 COMP
4-bit Counter
USIDC
USIPF
USIOIF
USISIF
DATA BUS
USIDB
3
2
0
1
1
0
[1]
USISR
USCK/ SCL (Input/ Open Drain))
CLOCK
HOLD
Two-wire Clock
Control Unit
USITC
USICLK
USICS0
USICS1
USIWM0
USIWM1
USIOIE
USISIE
2
USICR
The 8-bit USI data register is directly accessible via the data bus and contains the incoming and outgoing data. The register
has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The USI data register is a
serial shift register and the most significant bit that is the output of the serial shift register is connected to one of two output
pins depending of the wire mode configuration. A transparent latch is inserted between the USI data register output and
output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is
always sampled from the data input (DI) pin independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the USI data
register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number
of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock
source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the
number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 compare match or
from software.
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The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also
generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows.
4.15.3 Functional Descriptions
4.15.3.1Three-wire Mode
The USI three-wire mode is compliant to the serial peripheral Interface (SPI) mode 0 and 1, but does not have the slave
select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this
mode are: DI, DO, and USCK.
Figure 4-63. Three-wire Mode Operation, Simplified Diagram
DO
DI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
USCK
SLAVE
DO
DI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
USCK
PORTxn
MASTER
Figure 4-63 shows two USI units operating in three-wire mode, one as master and one as slave. The two USI data register
are interconnected in such way that after eight USCK clocks, the data in each register are interchanged. The same clock
also increments the USI’s 4-bit counter. The counter overflow (interrupt) flag, or USIOIF, can therefore be used to determine
when a transfer is completed. The clock is generated by the master device software by toggling the USCK pin via the PORT
Register or by writing a one to the USITC bit in USICR.
Figure 4-64. Three-wire Mode, Timing Diagram
CYCLE
1
(Reference)
2
3
4
5
6
7
8
USCK
USCK
DO
MSB
DI
MSB
A
156
B
C
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
D
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E
The three-wire mode timing is shown in Figure 4-64 on page 156 At the top of the figure is a USCK cycle reference. One bit
is shifted into the USI data register (USIDR) for each of these cycles. The USCK timing is shown for both external clock
modes. In external clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (data register is shifted
by one) at negative edges. External clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., samples data
at negative and changes the output at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 4-64 on page 156), a bus transfer involves the following steps:
1. The slave device and master device sets up its data output and, depending on the protocol used, enables its output driver (mark A and B). The output is set up by writing the data to be transmitted to the USI data register.
Enabling of the output is done by setting the corresponding bit in the port data direction register. Note that point A
and B does not have any specific order, but both must be at least one half USCK cycle before point C where the
data is sampled. This must be done to ensure that the data setup requirement is satisfied. The 4-bit counter is
reset to zero.
2.
The master generates a clock pulse by software toggling the USCK line twice (C and D). The bit value on the
slave and master’s data input (DI) pin is sampled by the USI on the first edge (C), and the data output is changed
on the opposite edge (D). The 4-bit counter will count both edges.
3.
Step 2. is repeated eight times for a complete register (byte) transfer.
4.
After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer is completed.
The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt
will wake up the processor if it is set to Idle mode. Depending of the protocol used the slave device can now set its
output to high impedance.
4.15.3.2 SPI Master Operation Example
The following code demonstrates how to use the USI module as a SPI Master:
SPITransfer:
sts
USIDR,r16
ldi
r16,(1<<USIOIF)
sts
USISR,r16
ldi
r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
SPITransfer_loop:
sts
USICR,r16
lds
r16, USISR
sbrs
r16, USIOIF
rjmp
SPITransfer_loop
lds
r16,USIDR
ret
The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are
enabled as output in the DDRA or DDRB register. The value stored in register r16 prior to the function is called is transferred
to the slave device, and when the transfer is completed the data received from the slave is stored back into the r16 register.
The second and third instructions clears the USI counter overflow flag and the USI counter value. The fourth and fifth
instruction set three-wire mode, positive edge shift register clock, count at USITC strobe, and toggle USCK. The loop is
repeated 16 times.
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The following code demonstrates how to use the USI module as a SPI master with maximum speed (fsck = fck/4):
SPITransfer_Fast:
sts
ldi
ldi
USIDR,r16
r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)
r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
USICR,r16; MSB
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16; LSB
USICR,r17
lds
ret
r16,USIDR
4.15.3.3 SPI Slave Operation Example
The following code demonstrates how to use the USI module as a SPI slave:
init:
ldi
r16,(1<<USIWM0)|(1<<USICS1)
sts
USICR,r16
...
SlaveSPITransfer:
sts
USIDR,r16
ldi
r16,(1<<USIOIF)
sts
USISR,r16
SlaveSPITransfer_loop:
lds
r16, USISR
sbrs
r16, USIOIF
rjmp
SlaveSPITransfer_loop
lds
r16,USIDR
ret
The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO is configured as
output and USCK pin is configured as input in the DDR register. The value stored in register r16 prior to the function is called
is transferred to the master device, and when the transfer is completed the data received from the master is stored back into
the r16 register.
Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets threewire mode and positive edge USI data register clock. The loop is repeated until the USI counter overflow flag is set.
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4.15.3.4 Two-wire Mode
The USI two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input
noise filtering. Pin names used by this mode are SCL and SDA.
Figure 4-65. Two-wire Mode Operation, Simplified Diagram
VCC
SDA
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCL
Two-wire
Clock
Control Unit
HOLD
SCL
SLAVE
SDA
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCL
PORTxn
MASTER
Figure 4-65 shows two USI units operating in two-wire mode, one as master and one as slave. It is only the physical layer
that is shown since the system operation is highly dependent of the communication scheme used. The main differences
between the master and slave operation at this level, is the serial clock generation which is always done by the master, and
only the slave uses the clock control unit. Clock generation must be implemented in software, but the shift operation is done
automatically by both devices. Note that only clocking on negative edge for shifting data is of practical use in this mode. The
slave can insert wait states at start or end of transfer by forcing the SCL clock low. This means that the master must always
check if the SCL line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The
clock is generated by the master by toggling the USCK pin via the PORT register.
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to
control the data flow.
Figure 4-66. Two-wire Mode, Typical Timing Diagram
SDA
SCL
1 to 7
S
A
ADDRESS
B
C
8
9
1 to 8
9
1 to 8
9
R/W
ACK
DATA
ACK
DATA
ACK
D
E
P
F
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Referring to the timing diagram (Figure 4-66 on page 159), a bus transfer involves the following steps:
1. The a start condition is generated by the master by forcing the SDA low line while the SCL line is high (A). SDA
can be forced low either by writing a zero to bit 7 of the shift register, or by setting the corresponding bit in the
PORT register to zero. Note that the USI data register bit must be set to one for the output to be enabled. The
slave device’s start detector logic (Figure 4-67) detects the start condition and sets the USISIF flag. The flag can
generate an interrupt if necessary.
2.
In addition, the start detector will hold the SCL line low after the master has forced an negative edge on this line
(B). This allows the slave to wake up from sleep or complete its other tasks before setting up the USI data register
to receive the address. This is done by clearing the start condition flag and reset the counter.
3.
The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shift it
into the USI data register at the positive edge of the SCL clock.
4.
After eight bits are transferred containing slave address and data direction (read or write), the slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has addressed, it releases the SCL
line and waits for a new start condition.
5.
If the slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL line
low again (i.e., the counter register must be set to 14 before releasing SCL at (D)). Depending of the R/W bit the
master or slave enables its output. If the bit is set, a master read operation is in progress (i.e., the slave drives the
SDA line) The slave can hold the SCL line low after the acknowledge (E).
6.
Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the master (F). Or a
new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last received. When the master does
a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted.
Figure 4-67. Start Condition Detector, Logic Diagram
USISIF
D
SDA
Q
CLR
D
Q
CLOCK
HOLD
CLR
SCL
Write (USISIF)
4.15.3.5 Start Condition Detector
The start condition detector is shown in Figure 4-67 The SDA line is delayed (in the range of 50 to 300ns) to ensure valid
sampling of the SCL line. The start condition detector is only enabled in two-wire mode.
The start condition detector is working asynchronously and can therefore wake up the processor from the power-down sleep
mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature in this
case the oscillator start-up time set by the CKSEL fuses (see Section 4.5.1 “Clock Systems and their Distribution” on page
46) must also be taken into the consideration. Refer to the USISIF bit description for further details.
4.15.4 Alternative USI Usage
When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design.
4.15.4.1 Half-duplex Asynchronous Data Transfer
By utilizing the USI data register in three-wire mode, it is possible to implement a more compact and higher performance
UART than by software only.
4.15.4.2 4-bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked externally,
both clock edges will generate an increment.
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4.15.4.3 12-bit Timer/Counter
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit counter.
4.15.4.4 Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt. The overflow flag and interrupt
enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit.
4.15.4.5 Software Interrupt
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
4.15.5 Register Descriptions
4.15.5.1 USIDR – USI Data Register
Bit
7
6
5
4
3
2
1
0
USID7
USID6
USID5
USID4
USID3
USID2
USID1
USID0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
USIDR
• Bits 7:0 – USID7..0: USI Data
When accessing the USI data register (USIDR) the serial register can be accessed directly. If a serial clock occurs at the
same cycle the register is written, the register will contain the value written and no shift is performed. A (left) shift operation is
performed depending of the USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a
Timer/Counter0 compare match, or directly by software using the USICLK strobe bit. Note that even when no wire mode is
selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used
by the USI data register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch to the most significant bit
(bit 7) of the data register. The output latch is open (transparent) during the first half of a serial clock cycle when an external
clock source is selected (USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The output
will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is
sampled and data output is changed on opposite clock edges.
Note that the corresponding data direction register to the pin must be set to one for enabling data output from the USI data
register.
4.15.5.2 USIBR – USI Buffer Register
Bit
7
6
5
4
3
2
1
0
USIB7
USIB6
USIB5
USIB4
USIB3
USIB2
USIB1
USIB0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
USIBR
• Bits 7:0 – USID7..0: USI Buffer
The content of the serial register is loaded to the USI buffer register when the transfer is completed, and instead of
accessing the USI data register (the serial register) the USI data buffer can be accessed when the CPU reads the received
data. This gives the CPU time to handle other program tasks too as the controlling of the USI is not so timing critical. The USI
flags as set same as when reading the USIDR register.
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4.15.5.3 USISR – USI Status Register
The status register contains interrupt flags, line status flags and the counter value.
Bit
7
6
5
4
3
USISIF
USIOIF
USIPF
USIDC
USICNT3
2
1
0
Read/Write
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
USICNT2 USICNT1 USICNT0
USISR
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition is detected. When output disable
mode or three-wire mode is selected and (USICSx = 11b & USICLK = 0) or (USICS = 10b & USICLK = 0), any edge on the
SCK pin sets the flag.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the global interrupt enable flag are set.
The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of
USCL in two-wire mode.
A start condition interrupt will wake up the processor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An interrupt will be generated when
the flag is set while the USIOIE bit in USICR and the global interrupt enable flag are set. The flag will only be cleared if a one
is written to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.
A counter overflow interrupt will wake up the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When two-wire mode is selected, the USIPF flag is set (one) when a stop condition is detected. The flag is cleared by writing
a one to this bit. Note that this is not an interrupt flag. This signal is useful when implementing Two-wire bus master
arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the USI data register differs from the physical pin value. The flag is only valid when twowire mode is used. This signal is useful when implementing two-wire bus master arbitration.
• Bits 3:0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a
Timer/Counter0 compare match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting
of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing
to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source
(USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input (USCK/SCL) are can still be used by
the counter.
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4.15.5.4 USICR – USI Control Register
Bit
7
6
5
4
3
2
1
0
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
W
W
Initial Value
0
0
0
0
0
0
0
0
USICR
The control register includes interrupt enable control, wire mode setting, clock select setting, and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt when the USISIE and the
global interrupt enable flag is set to one, this will immediately be executed. Refer to the USISIF bit description for further
details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt when the USIOIE and the global
interrupt enable flag is set to one, this will immediately be executed. Refer to the USIOIF bit description on page 162 for
further details.
• Bit 5:4 – USIWM1:0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data
and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI data
register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations
between USIWM1:0 and the USI operation is summarized in Table 4-45 on page 164.
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Table 4-45. Relations between USIWM1..0 and the USI Operation
USIWM1 USIWM0 Description
0
0
Outputs, clock hold, and start detector disabled. Port pins operates as normal.
Three-wire mode. Uses DO, DI, and USCK pins.
0
The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode.
However, the corresponding DDR bit still controls the data direction. When the port pin is set as input
the pins pull-up is controlled by the PORT bit.
1
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation. When
operating as master, clock pulses are software generated by toggling the PORT Register, while the
data direction is set to output. The USITC bit in the USICR Register can be used for this purpose.
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1).
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and uses open-collector
output drives. The output drivers are enabled by setting the corresponding bit for SDA and SCL in the
DDR Register.
1
When the output driver is enabled for the SDA pin, the output driver will force the line SDA low if the
output of the USI Data Register or the corresponding bit in the PORT Register is zero. Otherwise the
SDA line will not be driven (i.e., it is released). When the SCL pin output driver is enabled the SCL line
will be forced low if the corresponding bit in the PORT Register is zero, or by the start detector.
Otherwise the SCL line will not be driven.
0
The SCL line is held low when a start detector detects a start condition and the output is enabled.
Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL pin inputs is not
affected by enabling this mode. Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
1
1
Note:
1.
Same operation as for the Two-wire mode described above, except that the SCL line is also held low
when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared.
The DI and USCK pins are renamed to serial data (SDA) and serial clock (SCL) respectively to avoid confusion between the modes of operation.
• Bit 3:2 – USICS1:0: Clock Source Select
These bits set the clock source for the USI data register and counter. The data output latch ensures that the output is
changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL).
When software strobe or Timer/Counter0 compare match clock option is selected, the output latch is transparent and
therefore the output is changed immediately. Clearing the USICS1:0 bits enables software strobe option. When using this
option, writing a one to the USICLK bit clocks both the USI data register and the counter. For external clock source
(USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by
the USITC strobe bit.
Table 4-46 shows the relationship between the USICS1..0 and USICLK setting and clock source used for the USI data
register and the 4-bit counter.
Table 4-46. Relations between the USICS1..0 and USICLK Setting
164
USICS1
USICS0
USICLK
USI Data Register Clock Source
4-bit Counter Clock Source
0
0
0
No clock
No clock
0
0
1
Software clock strobe (USICLK)
Software clock strobe (USICLK)
0
1
X
Timer/Counter0 compare match
Timer/Counter0 compare match
1
0
0
External, positive edge
External, both edges
1
1
0
External, negative edge
External, both edges
1
0
1
External, positive edge
Software clock strobe (USITC)
1
1
1
External, negative edge
Software clock strobe (USITC)
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• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the USI data register to shift one step and the counter to increment by one, provided
that the USICS1..0 bits are set to zero and by doing so the software clock strobe option is selected. The output will change
immediately when the clock strobe is executed, i.e., in the same instruction cycle. The value shifted into the USI data register
is sampled the previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a clock
select register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-bit counter (see
Table 4-46 on page 164).
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0. The toggling is independent
of the setting in the data direction register, but if the PORT value is to be shown on the pin the DDB2 must be set as output
(to one). This feature allows easy clock generation when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will
directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master
device.
4.15.5.5 USIPP – USI Pin Position
Bit
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
USIPOS
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
USIPP
• Bits 7:1 – Res: Reserved Bits
These bits are reserved bits in the Atmel® ATtiny87/167 and always reads as zero.
• Bit 0 – USIPOS: USI Pin Position
Setting or clearing this bit changes the USI pin position.
Table 4-47. USI Pin Position
USIPOS
0
1
PortB
(Default)
Port A
(Alternate)
USI Pin Position
DI, SDA
PB0 - (PCINT8/OC1AU)
DO
PB1 - (PCINT9/OC1BU)
USCK, SCL
PB2 - (PCINT10/OC1AV)
DI, SDA
PA4 - (PCINT4/ADC4/ICP1/MOSI)
DO
PA2 - (PCINT2/ADC2/OC0A/MISO)
USCK, SCL
PA5 - (PCINT5/ADC5/T1/SCK)
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4.16
LIN/UART - Local Interconnect Network Controller or UART
The LIN (local interconnect network) is a serial communications protocol which efficiently supports the control of
mechatronics nodes in distributed automotive applications. The main properties of the LIN bus are:
● Single master with multiple slaves concept
●
●
●
●
●
Low cost silicon implementation based on common UART/SCI interface
Self synchronization with on-chip oscillator in slave node
Deterministic signal transmission with signal propagation time computable in advance
Low cost single-wire implementation
Speed up to 20Kbit/s.
LIN provides a cost efficient bus communication where the bandwidth and versatility of CAN are not required. The
specification of the line driver/receiver needs to match the ISO9141 NRZ-standard.
If LIN is not required, the controller alternatively can be programmed as Universal Asynchronous serial Receiver and
Transmitter (UART).
4.16.1 LIN Features
●
●
●
●
●
●
●
●
●
Hardware implementation of LIN 2.1 (LIN 1.3 compatibility)
Small, CPU efficient and independent master/slave routines based on “LIN Work Flow Concept” of LIN 2.1
specification
Automatic LIN header handling and filtering of irrelevant LIN frames
Automatic LIN response handling
Extended LIN error detection and signaling
Hardware frame time-out detection
“Break-in-data” support capability
Automatic re-synchronization to ensure proper frame integrity
Fully flexible extended frames support capabilities
4.16.2 UART Features
●
●
●
●
●
Full duplex operation (independent serial receive and transmit processes)
Asynchronous operation
High resolution baud rate generator
Hardware support of 8 data bits, odd/even/no parity bit, 1 stop bit frames
Data over-run and framing error detection
4.16.3 LIN Protocol
4.16.3.1 Master and Slave
A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave
task. All other nodes contain a slave task only.
Figure 4-68. LIN Cluster with One Master Node and “n” Slave Nodes
master node
master task
slave node
1
slave node
n
slave task
slave task
slave task
LIN bus
The master task decides when and which frame shall be transferred on the bus. The slave tasks provide the data
transported by each frame. Both the master task and the slave task are parts of the frame handler
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4.16.3.2 Frames
A frame consists of a header (provided by the master task) and a response (provided by a slave task).
The header consists of a BREAK and SYNC pattern followed by a PROTECTED IDENTIFIER. The identifier uniquely
defines the purpose of the frame. The slave task appointed for providing the response associated with the identifier transmits
it. The response consists of a DATA field and a CHECKSUM field.
Figure 4-69. Master and Slave Tasks Behavior in LIN Frame
HEADER
Master Task
HEADER
RESPONSE
Slave Task 1
RESPONSE
Slave Task 2
The slave tasks waiting for the data associated with the identifier receives the response and uses the data transported after
verifying the checksum.
Figure 4-70. Structure of a LIN Frame
FRAME SLOT
HEADER
BREAK
RESPONSE
PROTECTED
IDENTIFIER
SYNC
Field
Field
Break Delimiter
Field
Response Space
DATA 0
DATA n
Field
CHECKSUM
Field
Field
Inter Byte Space
Inter Frame Space
Each byte field is transmitted as a serial byte, LSB first
4.16.3.3 Data Transport
Two types of data may be transported in a frame; signals or diagnostic messages.
● Signals
Signals are scalar values or byte arrays that are packed into the data field of a frame. A signal is always present at the
same position in the data field for all frames with the same identifier.
●
Diagnostic messages
Diagnostic messages are transported in frames with two reserved identifiers. The interpretation of the data field
depends on the data field itself as well as the state of the communicating nodes.
4.16.3.4 Schedule Table
The master task (in the master node) transmits frame headers based on a schedule table. The schedule table specifies the
identifiers for each header and the interval between the start of a frame and the start of the following frame. The master
application may use different schedule tables and select among them.
4.16.3.5 Compatibility with LIN 1.3
LIN 2.1 is a super-set of LIN 1.3.
A LIN 2.1 master node can handle clusters consisting of both LIN 1.3 slaves and/or LIN 2.1 slaves. The master will then
avoid requesting the new LIN 2.1 features from a LIN 1.3 slave:
● Enhanced checksum,
●
●
●
Re-configuration and diagnostics,
Automatic baud rate detection,
“Response error” status monitoring.
LIN 2.1 slave nodes can not operate with a LIN 1.3 master node (e.g. the LIN1.3 master does not support the enhanced
checksum).
The LIN 2.1 physical layer is backwards compatible with the LIN1.3 physical layer. But not the other way around. The LIN 2.1
physical layer sets greater requirements, i.e. a master node using the LIN 2.1 physical layer can operate in a LIN 1.3 cluster.
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4.16.4 LIN/UART Controller
The LIN/UART controller is divided in three main functions:
● Tx LIN header function,
●
●
Rx LIN header function,
LIN response function.
These functions mainly use two services:
● Rx service,
●
Tx service.
Because these two services are basically UART services, the controller is also able to switch into an UART function.
4.16.4.1 LIN Overview
The LIN/UART controller is designed to match as closely as possible to the LIN software application structure. The LIN
software application is developed as independent tasks, several slave tasks and one master task (see Section 4.16.3.4 on
page 167). The Atmel® ATtiny87/167 conforms to this perspective. The only link between the master task and the slave task
will be at the cross-over point where the interrupt routine is called once a new identifier is available. Thus, in a master node,
housing both master and slave task, the Tx LIN Header function will alert the slave task of an identifier presence. In the same
way, in a slave node, the Rx LIN Header function will alert the slave task of an identifier presence.
When the slave task is warned of an identifier presence, it has first to analyze it to know what to do with the response.
Hardware flags identify the presence of one of the specific identifiers from 60 (0x3C) up to 63 (0x3F).
For LIN communication, only four interrupts need to be managed:
● LIDOK: New LIN identifier available,
●
●
●
LRXOK: LIN response received,
LTXOK: LIN response transmitted,
LERR: LIN Error(s).
The wake-up management can be automated using the UART wake-up capability and a node sending a minimum of 5 low
bits (0xF0) for LIN 2.1 and 8 low bits (0x80) for LIN 1.3. Pin change interrupt on LIN wake-up signal can be also used to exit
the device of one of its sleep modes.
Extended frame identifiers 62 (0x3E) and 63 (0x3F) are reserved to allow the embedding of user-defined message formats
and future LIN formats. The byte transfer mode offered by the UART will ensure the upwards compatibility of LIN slaves with
accommodation of the LIN protocol.
4.16.4.2 UART Overview
The LIN/UART controller can also function as a conventional UART. By default, the UART operates as a full duplex
controller. It has local loop back circuitry for test purposes. The UART has the ability to buffer one character for transmit and
two for receive. The receive buffer is made of one 8-bit serial register followed by one 8-bit independent buffer register.
Automatic flag management is implemented when the application puts or gets characters, thus reducing the software
overhead. Because transmit and receive services are independent, the user can save one device pin when one of the two
services is not used. The UART has an enhanced baud rate generator providing a maximum error of 2% whatever the clock
frequency and the targeted baud rate.
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4.16.4.3 LIN/UART Controller Structure
Figure 4-71. LIN/UART Controller Block Diagram
clkI/O
RxD
Prescaler
Finite State Machine
Sample /bit
BAUD_RATE
FSM
Get Byte
Put Byte
Frame Time-out
RX
TxD
TX
Synchronization
Monitoring
Data FIFO
BUFFER
4.16.4.4 LIN/UART Command Overview
Figure 4-72. LIN/UART Command Dependencies
Tx
Response
Tx
Header
IDOK
TXOK
Rx Header
or
LIN Abort
Tx
Response
RXOK
Automatic
Return
Recommended
Way
LIN
DISABLE
UART
Possible
Way
Byte
Transfer
Rx
Byte
Full
Duplex
Tx
Byte
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Table 4-48. LIN/UART Command List
LENA
LCMD[2]
LCMD[1]
LCMD[0]
Command
0
x
x
x
Disable peripheral
0
Rx header - LIN abort
0
Tx header
LCMD[2..0]=000 after Tx
0
Rx response
LCMD[2..0]=000 after Rx
1
Tx response
LCMD[2..0]=000 after Tx
0
0
Byte transfer
1
0
Rx Byte
0
1
Tx Byte
1
1
Full duplex
1
1
LIN withdrawal
1
0
1
Comment
no CRC, no time out
LTXDL=LRXDL=0
(LINDLR: read only register)
4.16.4.5 Enable/Disable
Setting the LENA bit in LINCR register enables the LIN/UART controller. To disable the LIN/UART controller, LENA bit must
be written to 0. No wait states are implemented, so, the disable command is taken into account immediately.
4.16.4.6 LIN Commands
Clearing the LCMD[2] bit in LINCR register enables LIN commands.
As shown in Table 4-48, four functions controlled by the LCMD[1..0] bits of LINCR register are available (c.f. Figure 4-72 on
page 169).
Rx Header/LIN Abort Function
This function (or state) is mainly the withdrawal mode of the controller.
When the controller has to execute a master task, this state is the start point before enabling a Tx header command.
When the controller has only to execute slave tasks, LIN header detection/acquisition is enabled as background function. At
the end of such an acquisition (Rx header function), automatically the appropriate flags are set, and in LIN 1.3, the LINDLR
register is set with the uncoded length value.
This state is also the start point before enabling the Tx or the Rx Response command.
A running function (i.e. Tx header, Tx or Rx response) can be aborted by clearing LCMD[1..0] bits in LINCR register (see
Section 4.16.5.11 “Break-in-data” on page 179). In this case, an abort flag - LABORT - in LINERR register will be set to
inform the other software tasks. No wait states are implemented, so, the abort command is taken into account immediately.
Rx Header function is responsible for:
● The BREAK field detection,
170
●
●
The hardware re-synchronization analyzing the SYNCH field,
●
●
The starting of the Frame_Time_Out,
The reception of the PROTECTED IDENTIFIER field, the parity control and the update of the LINDLR register in case
of LIN 1.3,
The checking of the LIN communication integrity.
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Tx Header Function
In accordance with the LIN protocol, only the master task must enable this function. The header is sent in the appropriate
timed slots at the programmed baud rate (c.f. LINBRR and LINBTR registers).
The controller is responsible for:
● The transmission of the BREAK field - 13 dominant bits,
●
●
The transmission of the SYNCH field - character 0x55,
The transmission of the PROTECTED IDENTIFIER field. It is the full content of the LINIDR register (automatic check
bits included).
At the end of this transmission, the controller automatically returns to Rx Header / LIN Abort state (i.e. LCMD[1..0] = 00) after
setting the appropriate flags. This function leaves the controller in the same setting as after the Rx Header function. This
means that, in LIN 1.3, the LINDLR register is set with the uncoded length value at the end of the Tx Header function.
During this function, the controller is also responsible for:
● The starting of the Frame_Time_Out,
●
The checking of the LIN communication integrity.
Rx and TX Response Functions
These functions are initiated by the slave task of a LIN node. They must be used after sending an header (master task) or
after receiving an header (considered as belonging to the slave task). When the TX response order is sent, the transmission
begins. A Rx response order can be sent up to the reception of the last serial bit of the first byte (before the stop-bit).
In LIN 1.3, the header slot configures the LINDLR register. In LIN 2.1, the user must configure the LINDLR register, either
LRXDL[3..0] for Rx Response either LTXDL[3..0] for Tx Response.
When the command starts, the controller checks the LIN13 bit of the LINCR register to apply the right rule for computing the
checksum. Checksum calculation over the DATA bytes and the PROTECTED IDENTIFIER byte is called enhanced
checksum and it is used for communication with LIN 2.1 slaves. Checksum calculation over the DATA bytes only is called
classic checksum and it is used for communication with LIN 1.3 slaves. Note that identifiers 60 (0x3C) to 63 (0x3F) shall
always use classic checksum.
At the end of this reception or transmission, the controller automatically returns to Rx Header / LIN Abort state (i.e.
LCMD[1..0] = 00) after setting the appropriate flags.
If an LIN error occurs, the reception or the transmission is stopped, the appropriate flags are set and the LIN bus is left to
recessive state.
During these functions, the controller is responsible for:
● The initialization of the checksum operator,
●
●
●
●
The transmission or the reception of ‘n’ data with the update of the checksum calculation,
The transmission or the checking of the CHECKSUM field,
The checking of the Frame_Time_Out,
The checking of the LIN communication integrity.
While the controller is sending or receiving a response, BREAK and SYNCH fields can be detected and the identifier of this
new header will be recorded. Of course, specific errors on the previous response will be maintained with this identifier
reception.
Handling Data of LIN response
A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LINSEL register, repeated
accesses to the LINDAT register perform data read or data write (c.f. Section 4.16.5.15 “Data Management” on page 181).
Note that LRXDL[3..0] and LTXDL[3..0] are not linked to the data access.
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4.16.4.7 UART Commands
Setting the LCMD[2] bit in LINENR register enables UART commands.
Tx Byte and Rx Byte services are independent as shown in Table 4-48 on page 170.
● Byte Transfer: the UART is selected but both Rx and Tx services are disabled,
●
●
●
Rx Byte: only the Rx service is enable but Tx service is disabled,
Tx Byte: only the Tx service is enable but Rx service is disabled,
Full Duplex: the UART is selected and both Rx and Tx services are enabled.
This combination of services is controlled by the LCMD[1..0] bits of LINENR register (c.f. Figure 4-72 on page 169).
Data Handling
The FIFO used for LIN communication is disabled during UART accesses. LRXDL[3..0] and LTXDL[3..0] values of LINDLR
register are then irrelevant. LINDAT register is then used as data register and LINSEL register is not relevant.
Rx Service
Once this service is enabled, the user is warned of an in-coming character by the LRXOK flag of LINSIR register. Reading
LINDAT register automatically clears the flag and makes free the second stage of the buffer. If the user considers that the incoming character is irrelevant without reading it, he directly can clear the flag (see specific flag management described in
Section 4.16.6.2 on page 183).
The intrinsic structure of the Rx service offers a 2-byte buffer. The fist one is used for serial to parallel conversion, the
second one receives the result of the conversion. This second buffer byte is reached reading LINDAT register. If the 2-byte
buffer is full, a new in-coming character will overwrite the second one already recorded. An OVRERR error in
LINERR register will then accompany this character when read.
A FERR error in LINERR register will be set in case of framing error.
Tx Service
If this service is enabled, the user sends a character by writing in LINDAT register. Automatically the LTXOK flag of
LINSIR register is cleared. It will rise at the end of the serial transmission. If no new character has to be sent, LTXOK flag
can be cleared separately (see specific flag management described in Section 4.16.6.2 “LIN Status and Interrupt Register LINSIR” on page 183).
There is no transmit buffering. No error is detected by this service.
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4.16.5 LIN / UART Description
4.16.5.1 Reset
The AVR® core reset logic signal also resets the LIN/UART controller. Another form of reset exists, a software reset
controlled by LSWRES bit in LINCR register. This self-reset bit performs a partial reset as shown in Table 4-49.
Table 4-49. Reset of LIN/UART Registers
Register
Name
Reset Value
LSWRES Value
LIN control register
LINCR
0000 0000 b
0000 0000 b
LIN status and interrupt register
LINSIR
0000 0000 b
0000 0000 b
LIN enable interrupt register
LINENIR
0000 0000 b
xxxx 0000 b
LIN error register
LINERR
0000 0000 b
0000 0000 b
LIN bit timing register
LINBTR
0010 0000 b
0010 0000 b
LIN baud rate register low
LINBRRL
0000 0000 b
uuuu uuuu b
LIN baud rate register high
LINBRRH
0000 0000 b
xxxx uuuu b
LIN data length register
LINDLR
0000 0000 b
0000 0000 b
LIN identifier register
LINIDR
1000 0000 b
1000 0000 b
LIN data buffer selection
LINSEL
0000 0000 b
xxxx 0000 b
LIN data
LINDAT
0000 0000 b
0000 0000 b
Comment
x=unknown
u=unchanged
4.16.5.2 Clock
The I/O clock signal (clki/o) also clocks the LIN/UART controller. It is its unique clock.
4.16.5.3 LIN Protocol Selection
LIN13 bit in LINCR register is used to select the LIN protocol:
● LIN13 = 0 (default): LIN 2.1 protocol,
●
LIN13 = 1: LIN 1.3 protocol.
The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic checksum in LIN
1.3).
This bit is irrelevant for UART commands.
4.16.5.4 Configuration
Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller in the following
configuration (Table 4-50).
Table 4-50. Configuration Table versus Mode
Mode
LIN
UART
LCONF[1..0]
Configuration
00 b
LIN standard configuration (default)
01 b
No CRC field detection or transmission
10 b
Frame_Time_Out disable
11 b
Listening mode
00 b
8-bit data, no parity and 1 stop-bit
01 b
8-bit data, even parity and 1 stop-bit
10 b
8-bit data, odd parity and 1 stop-bit
11 b
Listening mode, 8-bit data, no parity and 1 stop-bit
The LIN configuration is independent of the programmed LIN protocol.
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The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this mode, the TXLIN output pin is
disabled and the RXLIN input pin is always enabled. The same scheme is available in UART mode.
Figure 4-73. Listening Mode
internal
Tx LIN
TXLIN
LISTEN
internal
1
Rx LIN
0
RXLIN
4.16.5.5 Busy Signal
LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by hardware. It signals that the
controller is busy with LIN or UART communication.
Busy Signal in LIN Mode
Figure 4-74. Busy Signal in LIN Mode
FRAME SLOT
RESPONSE
HEADER
LIN Bus
BREAK
Field
1) LBUSY
PROTECTED
IDENTIFIER
SYNC
Field
DATA 0
Field
DATA n
Field
CHECKSUM
Field
Field
Node providing the master task
2) LBUSY
Node providing a slave task
Node providing neither the master task, neither a slave task
3) LBUSY
LCMD = Tx Header
LIDOK
LCMD = Tx or Rx Response
LTXOK or LRXOK
When the busy signal is set, some registers are locked, user writing is not allowed:
● “LIN Control Register” - LINCR - except LCMD[2..0], LENA and LSWRES,
●
●
●
●
“LIN Baud Rate Registers” - LINBRRL and LINBRRH,
“LIN Data Length Register” - LINDLR,
“LIN Identifier Register” - LINIDR,
“LIN Data Register” - LINDAT.
If the busy signal is set, the only available commands are:
● LCMD[1..0] = 00 b, the abort command is taken into account at the end of the byte,
●
●
LENA = 0 and/or LCMD[2] = 0, the kill command is taken into account immediately,
LSWRES = 1, the reset command is taken into account immediately.
Note that, if another command is entered during busy signal, the new command is not validated and the LOVRERR bit flag of
the LINERR register is set. The on-going transfer is not interrupted.
Busy Signal in UART Mode
During the byte transmission, the busy signal is set. This locks some registers from being written:
● “LIN Control Register” - LINCR - except LCMD[2..0], LENA and LSWRES,
●
“LIN Data Register” - LINDAT.
The busy signal is not generated during a byte reception.
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4.16.5.6 Bit Timing
Baud rate Generator
The baud rate is defined to be the transfer rate in bits per second (bps):
● BAUD: Baud rate (in bps),
●
●
●
fclki/o: System I/O clock frequency,
LDIV[11..0]: Contents of LINBRRH & LINBRRL registers - (0-4095), the pre-scaler receives clki/o as input clock.
LBT[5..0]: Least significant bits of - LINBTR register- (0-63) is the number of samplings in a LIN or UART bit (default
value 32).
Equation for calculating baud rate:
BAUD = fclki/o / LBT[5..0] x (LDIV[11..0] + 1)
Equation for setting LINDIV value:
LDIV[11..0] = (fclki/o / LBT[5..0] x BAUD) - 1
Note that in reception a majority vote on three samplings is made.
Re-synchronization in LIN Mode
When waiting for Rx header, LBT[5..0] = 32 in LINBTR register. The re-synchronization begins when the BREAK is detected.
If the BREAK size is not in the range (10.5 bits min., 28 bits max. — 13 bits nominal), the BREAK is refused. The
re-synchronization is done by adjusting LBT[5..0] value to the SYNCH field of the received header (0x55). Then the
PROTECTED IDENTIFIER is sampled using the new value of LBT[5..0]. The re-synchronization implemented in the
controller tolerates a clock deviation of ±20% and adjusts the baud rate in a ±2% range.
The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be reset to 32 for the next
header.
The LINBTR register can be used to (software) re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
Handling LBT[5..0]
LDISR bit of LINBTR register is used to:
● Disable the re-synchronization (for instance in the case of LIN master node),
●
To enable the setting of LBT[5..0] (to manually adjust the baud rate especially in the case of UART mode). A minimum
of 8 is required for LBT[5..0] due to the sampling operation.
Note that the LENA bit of LINCR register is important for this handling (see Figure 4-75).
Figure 4-75. Handling LBT[5..0]
Write in LINBTR Register
=1
LENA ?
=0
(LINCR bit4)
LDISR
=1
to write
=0
LBT[5..0] forced to 0x20
LDISR forced to 0
Enable re-synch. in LIN mode
LBT[5..0] = LBT[5..0] to write
(LBT [5 to 0] min = 8)
LDISR forced to 1
Disable re-synch. in LIN mode
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4.16.5.7 Data Length
Section 4.16.4.6 “LIN Commands” on page 170 describes how to set or how are automatically set the LRXDL[3..0] or
LTXDL[3..0] fields of LINDLR register before receiving or transmitting a response.
In the case of Tx response the LRXDL[3..0] will be used by the hardware to count the number of bytes already successfully
sent.
In the case of Rx response the LTXDL[3..0] will be used by the hardware to count the number of bytes already successfully
received.
If an error occurs, this information is useful to the programmer to recover the LIN messages.
Data Length in LIN 2.1
● If LTXDL[3..0]=0 only the CHECKSUM will be sent,
● If LRXDL[3..0]=0 the first byte received will be interpreted as the CHECKSUM,
● If LTXDL[3..0] or LRXDL[3..0] >8, values will be forced to 8 after the command setting and before sending or receiving
of the first byte.
Data Length in LIN 1.3
● LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decoding the data length code
contained in the received PROTECTED IDENTIFIER (LRXDL = LTXDL).
●
Via the above mechanism, a length of 0 or >8 is not possible.
Data Length in Rx Response
Figure 4-76. LIN2.1 - Rx Response - No Error
LIDOK
LIN Bus
LRXDL (*)
4
LTXDL (*)
?
LRXOK
1st Byte
2nd Byte
3rd Byte
4th Byte
DATA-0
DATA-1
DATA-2
DATA-3
CHECKSUM
1
2
3
4
0
LBUSY
LCMD = Rx Response
LCMD2 to 0 = 000b
LINDLR = 0x?4
(*): LRXDL and LTXDL updated by user
176
●
●
●
●
●
The user initializes LRXDL field before setting the Rx response command,
●
If no error occurs, LRXOK is set after the reception of the CHECKSUM, LRXDL will be unchanged (and
LTXDL = LRXDL).
After setting the Rx response command, LTXDL is reset by hardware,
LRXDL field will remain unchanged during Rx (during busy signal),
LTXDL field will count the number of received bytes (during busy signal),
If an error occurs, Rx stops, the corresponding error flag is set and LTXDL will give the number of received bytes
without error,
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Data Length in Tx Response
Figure 4-77. LIN1.3 - Tx Response - No Error
LIDOK
LIN Bus
LRXDL (*)
4
LTXDL (*)
4
1st Byte
2nd Byte
3rd Byte
4th Byte
DATA-0
DATA-1
DATA-2
DATA-3
0
1
2
LTXOK
CHECKSUM
3
4
LBUSY
LCMD2..0 = 000b
LCMD = Tx Response
(*): LRXDL and LTXDL updated by Rx Response or Tx Response task
●
●
●
●
●
The user initializes LTXDL field before setting the Tx response command,
●
If no error occurs, LTXOK is set after the transmission of the CHECKSUM, LTXDL will be unchanged (and
LRXDL = LTXDL).
After setting the Tx response command, LRXDL is reset by hardware,
LTXDL will remain unchanged during Tx (during busy signal),
LRXDL will count the number of transmitted bytes (during busy signal),
If an error occurs, Tx stops, the corresponding error flag is set and LRXDL will give the number of transmitted bytes
without error,
Data Length after Error
Figure 4-78. Tx Response - Error
LERR
LIN Bus
1st Byte
2nd Byte
DATA-0
DATA-1
3rd Byte
DATA-2
ERROR
LRXDL
4
LTXDL
4
0
1
2
LBUSY
LCMD2..0 = 000b
LCMD = Tx Response
Note:
Information on response (ex: error on byte) is only available at the end of the serialization/de-serialization of
the byte.
Data Length in UART Mode
● The UART mode forces LRXDL and LTXDL to 0 and disables the writing in LINDLR register,
● Note that after reset, LRXDL and LTXDL are also forced to 0.
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4.16.5.8 xxOK Flags
There are three xxOK flags in LINSIR register:
● LIDOK: LIN IDentifier OK
It is set at the end of the header, either by the Tx header function or by the Rx header. In LIN 1.3, before generating
LIDOK, the controller updates the LRXDL and LTXDL fields in LINDLR register.
It is not driven in UART mode.
●
LRXOK: LIN RX response complete
It is set at the end of the response by the Rx response function in LIN mode and once a character is received in UART
mode.
●
LTXOK: LIN TX response complete
It is set at the end of the response by the Tx response function in LIN mode and once a character has been sent in
UART mode.
These flags can generate interrupts if the corresponding enable interrupt bit is set in the LINENIR register (see Section
4.16.5.13 “Interrupts” on page 180).
4.16.5.9 xxERR Flags
LERR bit of the LINSIR register is an logical ‘OR’ of all the bits of LINERR register (see Section 4.16.5.13 “Interrupts” on
page 180). There are eight flags:
● LBERR = LIN Bit ERRor.
A unit that is sending a bit on the bus also monitors the bus. A LIN bit error will be flagged when the bit value that is
monitored is different from the bit value that is sent. After detection of a LIN bit error the transmission is aborted.
●
LCERR = LIN Checksum ERRor.
A LIN checksum error will be flagged if the inverted modulo-256 sum of all received data bytes (and the protected
identifier in LIN 2.1) added to the checksum does not result in 0xFF.
●
LPERR = LIN Parity ERRor (identifier).
A LIN parity error in the IDENTIFIER field will be flagged if the value of the parity bits does not match with the identifier
value. (See LP[1:0] bits in Section 4.16.6.8 “LIN Identifier Register - LINIDR” on page 186). A LIN slave application
does not distinguish between corrupted parity bits and a corrupted identifier. The hardware does not undertake any
correction. However, the LIN slave application has to solve this as:
●
known identifier (parity bits corrupted),
●
or corrupted identifier to be ignored,
●
or new identifier.
●
LSERR = LIN Synchronization ERRor.
A LIN synchronization error will be flagged if a slave detects the edges of the SYNCH field outside the given
tolerance.
●
LFERR = LIN Framing ERRor.
A framing error will be flagged if dominant STOP bit is sampled.
Same function in UART mode.
●
LTOERR = LIN Time Out ERRor.
A time-out error will be flagged if the MESSAGE frame is not fully completed within the maximum length TFrame_Maximum
by any slave task upon transmission of the SYNCH and IDENTIFIER fields (see Section 4.16.5.10 “Frame Time Out”
on page 179).
●
LOVERR = LIN OVerrun ERRor.
Overrun error will be flagged if a new command (other than LIN Abort) is entered while ‘Busy signal’ is present.
In UART mode, an overrun error will be flagged if a received byte overwrites the byte stored in the serial input buffer.
●
LABORT
LIN abort transfer reflects a previous LIN Abort command (LCMD[2..0] = 000) while ‘Busy signal’ is present.
After each LIN error, the LIN controller stops its previous activity and returns to its withdrawal mode (LCMD[2..0] = 000 b) as
illustrated in Figure 4-78 on page 177.
Writing 1 in LERR of LINSIR register resets LERR bit and all the bits of the LINERR register.
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4.16.5.10 Frame Time Out
According to the LIN protocol, a frame time-out error is flagged if: T Frame > T Frame_Maximum.
This feature is implemented in the LIN/UART controller.
Figure 4-79. LIN Timing and Frame Time-out
TFrame
THeader
BREAK
TResponse
PROTECTED
IDENTIFIER
SYNC
Field
Field
Field
DATA 0
DATA n
Field
CHECKSUM
Field
Field
Maximum before Time-out
Nominal
THeader_Nominal
=
34 x TBit
THeader_Maximum
=
1.4 x THeader_Nominal
TResponse_Nominal
=
10 (Number_of_Data + 1) x TBit
TResponse_Maximum
=
1.4 x TResponse_Nominal
TFrame_Nominal
=
THeader_ Nominal + TResponse_Nominal
TFrame_Maximum
=
THeader_ Maximum + TResponse_Maximum
4.16.5.11 Break-in-data
According to the LIN protocol, the LIN/UART controller can detect the BREAK/SYNC field sequence even if the break is
partially superimposed with a byte of the response. When a BREAK/SYNC field sequence happens, the transfer in progress
is aborted and the processing of the new frame starts.
● On slave node(s), an error is generated (i.e. LBERR in case of Tx Response or LFERR in case of Rx Response).
Information on data error is also available, refer to the Section “Data Length after Error” on page 177.
●
On master node, the user (code) is responsible for this aborting of frame. To do this, the master task has first to abort
the on-going communication (clearing LCMD bits - LIN Abort command) and then to apply the Tx Header command.
In this case, the abort error flag - LABORT - is set.
On the slave node, the BREAK detection is processed with the synchronization setting available when the LIN/UART
controller processed the (aborted) response. But the re-synchronization restarts as usual. Due to a possible difference of
timing reference between the BREAK field and the rest of the frame, the time-out values can be slightly inaccurate.
4.16.5.12 Checksum
The last field of a frame is the checksum.
In LIN 2.1, the checksum contains the inverted eight bit sum with carry over all data bytes and the protected identifier. This
calculation is called enhanced checksum.
n
n
CHECKSUM = 255 – unsigned char DATAn + PROTECTED ID + unsigned char DATA n + PROTECTED ID » 8
0
0
In LIN 1.3, the checksum contains the inverted eight bit sum with carry over all data bytes. This calculation is called classic
checksum.
n
n
CHECKSUM = 255 – unsigned char DATAn + unsigned char DATAn » 8
0
0
Frame identifiers 60 (0x3C) to 61 (0x3D) shall always use classic checksum.
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4.16.5.13 Interrupts
As shown in Figure 4-80 on page 180, the four communication flags of the LINSIR register are combined to drive two
interrupts. Each of these flags have their respective enable interrupt bit in LINENIR register.
(see Section 4.16.5.8 “xxOK Flags” on page 178 and Section 4.16.5.9 “xxERR Flags” on page 178).
Figure 4-80. LIN Interrupt Mapping
LINERR.7
LABORT
LINERR.6
LTOERR
LINERR.5
LOVERR
LINERR.4
LINSIR.3
LFERR
LIN ERR
LERR
LINERR.3
LSERR
LINENIR.3
LPERR
LENERR
LINERR.2
LINERR.1
LINENIR.2
LENIDOK
LINENIR.1
LENTXOK
LINENIR.0
LENRXOK
LINSIR.2
LIDOK
LCERR
LINERR.0
LINSIR.1
LIN TC
LTXOK
LBERR
LINSIR.0
LRXOK
4.16.5.14 Message Filtering
Message filtering based upon the whole identifier is not implemented. Only a status for frame headers having 0x3C, 0x3D,
0x3E and 0x3F as identifier is available in the LINSIR register.
Table 4-51. Frame Status
LIDST[2..0]
Frame Status
0xx b
No specific identifier
100 b
60 (0x3C) identifier
101 b
61 (0x3D) identifier
110 b
62 (0x3E) identifier
111 b
63 (0x3F) identifier
The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a classic checksum (sum over
the data bytes only). Software will be responsible for switching correctly the LIN13 bit to provide/check this expected
checksum (the insertion of the ID field in the computation of the CRC is set - or not - just after entering the Rx or Tx response
command).
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4.16.5.15 Data Management
LIN FIFO Data Buffer
To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer accessible). This FIFO is
accessed via the LINDX[2..0] field of LINSEL register through the LINDAT register.
LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can be read or written. The data
index is automatically incremented after each LINDAT access if the LAINC (active low) bit is cleared. A roll-over is
implemented, after data index = 7 it is data index=0. Otherwise, if LAINC bit is set, the data index needs to be written
(updated) before each LINDAT access.
The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1, and so on. Nevertheless,
LINSEL must be initialized by the user before use.
UART Data Register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be for data out and in read
access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
4.16.5.16 OCD Support
When a debugger break occurs, the state machine of the LIN/UART controller is stopped (included frame time-out) and
further communication may be corrupted.
4.16.6 LIN/UART Register Description
Table 4-52. LIN/UART Register Bits Summary
Name
LINCR
LINSIR
LINENIR
LINERR
LINBTR
LINBRRL
LINBRRH
LINDLR
LINIDR
LINSEL
LINDAT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSWRES
LIN13
LCONF1
LCONF0
LENA
LCMD2
LCMD1
LCMD0
0
R/W
0
LIDST2
0
R
R
LABORT
R
0
LIDST0
R/W
LTOERR
R
0
R/W
R
R/W
0
0
R
0
—
0
0
R
0
R/W
R/W
0
0
R/(W)
R/W
0
R/W
R
R/W
LID4/LDL0
R
0
0
R
0
R/W
—
R/W
0
LDATA5
0
0
R/W
R/W
0
R/W
R/W
LRXDL3
0
R/W
0
R/W
0
R/W
R/W
R/W
R/Wone
LRXOK
0
R/Wone
0
0
R/W
LPERR
0
R
0
R/(W)
R/W
0
R/W
LRXDL2
0
R/W
R/W
0
R/W
R/W
0
R/W
R/W
R/W
R/(W)
LDIV0
0
R/W
LDIV8
0
R/W
LRXDL0
0
R/W
LID1
0
R/W
LID0
0
LINDX1
0
LDATA2
0
R/(W)
LRXDL1
0
LINDX2
0
R
LBT0
LDIV9
LID2
0
LBERR
0
LDIV1
0
LDIV10
0
R
R/W
LBT1
LDIV2
0
R/W
LCERR
0
LBT2
LDATA3
0
LTXOK
0
R/W
0
LAINC
R
0
LENRXOK
LID3
LDATA4
0
R/(W)
R/Wone
R/W
LENTXOK
LDIV3
0
—
R
R
0
LENIDOK
LDIV11
LTXDL0
0
R/W
R/W
LIDOK
0
LBT3
—
R
R/Wone
LSERR
0
LDIV4
0
LID5/LDL1
LDATA6
0
LBT4
LTXDL1
0
—
LDATA7
R/W
R
0
LERR
0
LFERR
—
LP0
R
R/(W)
R/W
LENERR
R
0
LDIV5
0
LTXDL2
0
LP1
1
R/W
—
LTXDL3
0
1
LDIV6
0
—
0
R
R
0
LOVERR
R
0
LBUSY
—
R
0
R/W
0
LBT5
LDIV7
0
R
0
LDISR
0
0
—
R
0
R/W
0
—
R
0
0
LIDST1
0
—
0
R/W
R/W
LINDX0
0
LDATA1
0
R/W
R/W
R/W
LDATA0
0
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R/W
181
4.16.6.1 LIN Control Register - LINCR
Bit
7
6
5
4
3
2
1
0
LSWRES
LIN13
LCONF1
LCONF0
LENA
LCMD2
LCMD1
LCMD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
LINCR
• Bit 7 - LSWRES: Software Reset
● 0 = No action,
●
1 = Software reset (this bit is self-reset at the end of the reset procedure).
• Bit 6 - LIN13: LIN 1.3 mode
● 0 = LIN 2.1 (default),
●
1 = LIN 1.3.
• Bit 5:4 - LCONF[1:0]: Configuration
a. LIN mode (default = 00):
b.
●
00 = LIN standard configuration (listen mode “off”, CRC “on” & Frame_Time_Out “on”,
●
01 = No CRC, No Frame_Time_Out (listen mode “off”),
●
10 = No Frame_Time_Out (listen mode “off” & CRC “on”),
●
11 = Listening mode (CRC “on” & Frame_Time_Out “on”).
UART mode (default = 00):
●
00 = 8-bit, no parity (listen mode “off”),
●
01 = 8-bit, even parity (listen mode “off”),
●
10 = 8-bit, odd parity (listen mode “off”),
●
11 = Listening mode, 8-bit, no parity.
• Bit 3 - LENA: Enable
● 0 = Disable (both LIN and UART modes),
●
1 = Enable (both LIN and UART modes).
• Bit 2:0 - LCMD[2..0]: Command and mode
The command is only available if LENA is set.
182
●
000 = LIN Rx header - LIN abort,
●
001 = LIN Tx header,
●
010 = LIN Rx response,
●
011 = LIN Tx response,
●
100 = UART Rx and Tx Byte disable,
●
11x = UART Rx Byte enable,
●
1x1 = UART Tx Byte enable.
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4.16.6.2 LIN Status and Interrupt Register - LINSIR
Bit
7
6
5
4
3
2
1
0
LIDST2
LIDST1
LIDST0
LBUSY
LERR
LIDOK
LTXOK
LRXOK
Read/Write
R
R
R
R
R/Wone
R/Wone
R/Wone
R/Wone
Initial Value
0
0
0
0
0
0
0
0
LINSIR
• Bits 7:5 - LIDST[2:0]: Identifier Status
● 0xx = no specific identifier,
●
100 = Identifier 60 (0x3C),
●
101 = Identifier 61 (0x3D),
●
110 = Identifier 62 (0x3E),
●
111 = Identifier 63 (0x3F).
• Bit 4 - LBUSY: Busy Signal
● 0 = Not busy,
●
1 = Busy (receiving or transmitting).
• Bit 3 - LERR: Error Interrupt
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective enable bit - LENERR - is set
in LINENIR.
●
0 = No error,
●
1 = An error has occurred.
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also resets all LINERR bits.
In UART mode, this bit is also cleared by reading LINDAT.
• Bit 2 - LIDOK: Identifier Interrupt
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
●
0 = No identifier,
●
1 = Slave task: Identifier present, master task: Tx Header complete.
The user clears this bit by writing 1, in order to reset this interrupt.
• Bit 1 - LTXOK: Transmit Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR.
●
0 = No Tx,
●
1 = Tx response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
• Bit 0 - LRXOK: Receive Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR.
●
0 = No Rx
●
1 = Rx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
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4.16.6.3 LIN Enable Interrupt Register - LINENIR
Bit
7
6
5
4
3
-
-
-
-
LENERR
2
1
0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
LENIDOK LENTXOK LENRXOK
LINENIR
• Bits 7:4 - Reserved Bits
● These bits are reserved for future use. For compatibility with future devices, they must be written to zero when
LINENIR is written.
• Bit 3 - LENERR: Enable Error Interrupt
● 0 = Error interrupt masked,
●
1 = Error interrupt enabled.
• Bit 2 - LENIDOK: Enable Identifier Interrupt
● 0 = Identifier interrupt masked,
●
1 = Identifier interrupt enabled.
• Bit 1 - LENTXOK: Enable Transmit Performed Interrupt
● 0 = Transmit performed interrupt masked,
●
1 = Transmit performed interrupt enabled.
• Bit 0 - LENRXOK: Enable Receive Performed Interrupt
● 0 = Receive performed interrupt masked,
●
1 = Receive performed interrupt enabled.
4.16.6.4 LIN Error Register - LINERR
Bit
7
6
5
LABORT LTOERR LOVERR
4
3
2
1
0
LFERR
LSERR
LPERR
LCERR
LBERR
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bit 7 - LABORT: Abort Flag
● 0 = No warning,
●
1 = LIN abort command occurred.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 6 - LTOERR: Frame_Time_Out Error Flag
● 0 = No error,
●
1 = Frame_Time_Out error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 5 - LOVERR: Overrun Error Flag
● 0 = No error,
●
1 = Overrun error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 4 - LFERR: Framing Error Flag
● 0 = No error,
●
1 = Framing error.
This bit is cleared when LERR bit in LINSIR is cleared.
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LINERR
• Bit 3 - LSERR: Synchronization Error Flag
● 0 = No error,
●
1 = Synchronization error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 2 - LPERR: Parity Error Flag
● 0 = No error,
●
1 = Parity error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 1 - LCERR: Checksum Error Flag
● 0 = No error,
●
1 = Checksum error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 0 - LBERR: Bit Error Flag
● 0 = No error,
●
1 = Bit error.
This bit is cleared when LERR bit in LINSIR is cleared.
4.16.6.5 LIN Bit Timing Register - LINBTR
Bit
7
6
5
4
3
2
1
0
LDISR
-
LBT5
LBT4
LBT3
LBT2
LBT1
LBT0
Read/Write
R/W
R
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
Initial Value
0
0
1
0
0
0
0
0
LINBTR
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
● 0 = Bit timing re-synchronization enabled (default),
●
1 = Bit timing re-synchronization disabled.
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
Gives the number of samples of a bit.
sample-time = (1 / fclki/o) x (LDIV[11..0] + 1)
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
4.16.6.6 LIN Baud Rate Register - LINBRR
Bit
7
6
5
4
3
2
1
0
LDIV7
LDIV6
LDIV5
LDIV4
LDIV3
LDIV2
LDIV1
LDIV0
LINBRRL
LINBRRH
-
-
-
-
LDIV11
LDIV10
LDIV9
LDIV8
Bit
15
14
13
12
11
10
9
8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 15:12 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be written to zero when
LINBRR is written.
• Bits 11:0 - LDIV[11:0]: Scaling of clki/o Frequency
The LDIV value is used to scale the entering clki/o frequency to achieve appropriate LIN or UART baud rate.
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4.16.6.7 LIN Data Length Register - LINDLR
Bit
7
6
5
4
3
2
1
0
LTXDL3
LTXDL2
LTXDL1
LTXDL0
LRXDL3
LRXDL2
LRXDL1
LRXDL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
LINDLR
• Bits 7:4 - LTXDL[3:0]: LIN Transmit Data Length
In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max).
In UART mode this field is unused.
• Bits 3:0 - LRXDL[3:0]: LIN Receive Data Length
In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max).
In UART mode this field is unused.
4.16.6.8 LIN Identifier Register - LINIDR
Bit
7
6
5
4
3
2
1
0
LP1
LP0
LID5 /
LDL1
LID4 /
LDL0
LID3
LID2
LID1
LID0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:6 - LP[1:0]: Parity
In LIN mode:
LP0 = LID4 ^ LID2 ^ LID1 ^ LID0
LP1 = ! ( LID1 ^ LID3 ^ LID4 ^ LID5 )
In UART mode this field is unused.
• Bits 5:4 - LDL[1:0]: LIN 1.3 Data Length
In LIN 1.3 mode:
●
00 = 2-byte response,
●
01 = 2-byte response,
●
10 = 4-byte response,
●
11 = 8-byte response.
In UART mode this field is unused.
• Bits 3:0 - LID[3:0]: LIN 1.3 Identifier
In LIN 1.3 mode: 4-bit identifier.
In UART mode this field is unused.
• Bits 5:0 - LID[5:0]: LIN 2.1 Identifier
In LIN 2.1 mode: 6-bit identifier (no length transported).
In UART mode this field is unused.
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LINIDR
4.16.6.9 LIN Data Buffer Selection Register - LINSEL
Bit
7
6
5
4
3
2
1
0
-
-
-
-
LAINC
LINDX2
LINDX1
LINDX0
Read/Write
-
-
-
-
R/W
R/W
R/W
R/W
Initial Value
-
-
-
-
0
0
0
0
LINSEL
• Bits 7:4 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be written to zero when
LINSEL is written.
• Bit 3 - LAINC: Auto Increment of Data Buffer Index
In LIN mode:
●
0 = Auto incrementation of FIFO data buffer index (default),
●
1 = No auto incrementation.
In UART mode this field is unused.
• Bits 2:0 - LINDX 2:0: FIFO LIN Data Buffer Index
In LIN mode: location (index) of the LIN response data byte into the FIFO data buffer. The FIFO data buffer is
accessed through LINDAT.
In UART mode this field is unused.
4.16.6.10 LIN Data Register - LINDAT
Bit
7
6
5
4
3
2
1
0
LDATA7
LDATA6
LDATA5
LDATA4
LDATA3
LDATA2
LDATA1
LDATA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
LINDAT
• Bits 7:0 - LDATA[7:0]: LIN Data In / Data out
In LIN mode: FIFO data buffer port.
In UART mode: data register (no data buffer - no FIFO).
●
In Write access, data out.
●
In Read access, data in.
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4.17
ISRC - Current Source
4.17.1 Features
●
●
100µA constant current source
±10% absolute accuracy
The Atmel® ATtiny87/167 features a 100µA ±10% current source. Up on request, the current is flowing through an external
resistor. The voltage can be measured on the dedicated pin shared with the ADC. Using a resistor in series with a ≤ 0.5%
tolerance is recommended. To protect the device against big values, the ADC must be configured with AVCC as internal
reference to perform the first measurement. Afterwards, another internal reference can be chosen according to the previous
measured value to refine the result.
When ISRCEN bit is set, the ISRC pin sources 100µA. Otherwise this pin keeps its initial function.
Figure 4-81. Current Source Block Diagram
AVCC
100μA
ISRCEN
ADCn/ ISRC
ADC Input
External
Resistor
4.17.2 Typical Applications
4.17.2.1 LIN Current Source
During the configuration of a LIN node in a cluster, it may be necessary to attribute dynamically an unique physical address
to every cluster node. The way to do it is not described in the LIN protocol.
The current source offers an excellent solution to associate a physical address to the application supported by the LIN node.
A full dynamic node configuration can be used to set-up the LIN nodes in a cluster.
Atmel ATtiny87/167 proposes to have an external resistor used in conjunction with the current source. The device measures
the voltage to the boundaries of the resistance via the analog to digital converter. The resulting voltage defines the physical
address that the communication handler will use when the node will participate in LIN communication.
In automotive applications, distributed voltages are very disturbed. The internal current source solution of Atmel
ATtiny87/167 immunizes the address detection the against any kind of voltage variations.
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Table 4-53. Example of Resistor Values(±5%) for a 8-address System (AVCC = 5V(1))
Resistor Value
Rload (Ohm)
0
1 000
0.1
40
1
2 200
0.22
88
2
3 300
0.33
132
3
4 700
0.47
188
4
6 800
0.68
272
5
10 000
1
400
6
15 000
1.5
600
2.2
880
7
Note:
1.
22 000
5V range: Max Rload 30K
3V range: Max Rload 15K
Typical Measured
Voltage (V)
Minimum
Reading with a
2.56V ref
Physical
Address
Typical Reading
with a 2.56V ref
Maximum
Reading with a
2.56V ref
Table 4-54. Example of Resistor Values (±1%) for a 16-address System (AVCC = 5V(1))
Typical Measured
Voltage (V)
Minimum
Reading with a
2.56V ref
Typical Reading
with a 2.56V ref
Maximum
Reading with a
2.56V ref
1 000
0.1
38
40
45
1 200
0.12
46
48
54
2
1500
0.15
57
60
68
3
1800
0.18
69
72
81
4
2200
0.22
84
88
99
5
2700
0.27
104
108
122
6
3300
0.33
127
132
149
7
4700
0.47
181
188
212
8
6 800
0.68
262
272
306
9
8 200
0.82
316
328
369
10
10 000
1.0
386
400
450
11
12 000
1.2
463
480
540
12
15 000
1.5
579
600
675
13
18 000
1.8
694
720
810
14
22 000
2.2
849
880
989
2.7
1023
1023
1023
Physical
Address
Resistor Value
Rload (Ohm)
0
1
15
Note:
1.
27 000
5V range: Max Rload 30K
3V range: Max Rload 15K
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4.17.2.2 Current Source for Low Cost Transducer
An external transducer based on a variable resistor can be connected to the current source.
This can be, for instance:
● A thermistor, or temperature-sensitive resistor, used as a temperature sensor,
●
●
A CdS photoconductive cell, or luminosity-sensitive resistor, used as a luminosity sensor,
...
Using the current source with this type of transducer eliminates the need for additional parts otherwise required in resistor
network or wheatstone bridge.
4.17.2.3 Voltage Reference for External Devices
An external resistor used in conjunction with the current source can be used as voltage reference for external devices. Using
a resistor in series with a lower tolerance than the current source accuracy (≤ 2%) is recommended. Table 4-54 on page 189
gives an example of voltage references using standard values of resistors.
4.17.2.4 Threshold Reference for Internal Analog Comparator
An external resistor used in conjunction with the current source can be used as threshold reference for internal analog
comparator (see Section 4.19 “AnaComp - Analog Comparator” on page 209). This can be connected to AIN0 (negative
analog compare input pin) as well as AIN1 (positive analog compare input pin). Using a resistor in series with a lower
tolerance than the current source accuracy (≤ 2%) is recommended. Table 4-54 gives an example of threshold references
using standard values of resistors.
4.17.3 Control Register
4.17.3.1 AMISCR – Analog Miscellaneous Control Register
Bit
7
6
5
4
3
-
-
-
-
-
2
1
0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
AREFEN XREFEN ISRCEN
AMISCR
• Bit 0 – ISRCEN: Current Source Enable
Writing this bit to one enables the Current Source as shown in Figure 4-81. It is recommended to use DIDR register bit
function when ISRCEN is set and to turn off the current source once the ADC measurement is done.
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4.18
ADC – Analog to Digital Converter
4.18.1 Features
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
10-bit resolution
1.0LSB integral non-linearity
±2LSB absolute accuracy
13 - 260µs conversion time (low - high resolution)
Up to 15kSPS at maximum resolution
11 multiplexed single ended input channels
8 differential input pairs with selectable gain
Temperature sensor input channel
Voltage from internal current source driving (ISRC)
Optional left adjustment for ADC result readout
0 - AVCC ADC input voltage range
Selectable 1.1V/2.56V ADC voltage reference
Free running or single conversion mode
ADC start conversion by auto triggering on interrupt sources
Interrupt on ADC conversion complete
Sleep mode noise canceler
Unipolar/bipolar input mode
Input polarity reversal mode
4.18.2 Overview
The Atmel® ATtiny87/167 features a 10-bit successive approximation ADC. The ADC is connected to a 11-channel analog
multiplexer which allows 16 differential voltage input combinations and 11 single-ended voltage inputs constructed from the
pins PA7..PA0 or PB7..PB4. The differential input is equipped with a programmable gain stage, providing amplification steps
of 8x or 20x on the differential input voltage before the A/D conversion. The single-ended voltage inputs refer to 0V (AGND).
The ADC contains a sample and hold circuit which ensures that the input voltage to the ADC is held at a constant level
during conversion. A block diagram of the ADC is shown in Figure 4-82.
Internal reference voltages of nominally 1.1V or 2.56V are provided on-chip. Alternatively, AVCC can be used as reference
voltage for single ended channels. There are also options to output the internal 1.1V or 2.56V reference voltages or to input
an external voltage reference and turn-off the internal voltage reference. These options are selected using the REFS[1:0]
bits of the ADMUX control register and using AREFEN and XREFEN bits of the AMISCR control register.
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Figure 4-82. Analog to Digital Converter Block Schematic
Internal
2.56/ 1.1V
Reference
ADC Data Register
(ADCH/ ADCL)
Interrupt
Flags
Trigger
Select
ADC[9..0]
ADSC
ADATE
ADTS[2..0]
ADIF
ADEN
ADSP[2..0]
ADLAR
MUX[4..0]
REFS0
BIN
ADC Control and Status
Register A and B (ADCSRA/ ADCRB)
ADC Multiplexer
Select (ADMUX)
REFS1
AREFEN
XREFEN
Analog Misc.
(AMISCR)
ADC Conversion
Complete IRQ
ADIF
ADIE
8-bit Data Bus
Prescaler
Start
Mux.
Decoder
Conversion Logic
Sample and Hold
Comparator
AVCC
-
10-bit DAC
+
AGND
AVCC/4
Bandgap
Reference
Temperature
Sensor
ADC10
ADC9
ADC8
AREF
ADC7
XREF
Pos.
Input
Mux.
ADC Multiplexer
Output
ADC6
ADC5
ADC4
ISRC/ ADC3
+
ADC2
-
ADC1
x8/ x20 Gain
Amplifier
ADC0
Neg.
Input
Mux.
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Mux.
4.18.3 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value
represents AGND and the maximum value represents the voltage on AVCC, the voltage reference on AREF pin or an internal
1.1V/2.56V voltage reference.
The voltage reference for the ADC may be selected by writing to the REFS[1..0] bits in ADMUX and AREFEN bit in AMISCR.
The AVCC supply, the AREF pin or an internal 1.1V / 2.56V voltage reference may be selected as the ADC voltage reference.
The analog input channel and differential gain are selected by writing to the MUX[4..0] bits in ADMUX register. Any of the 11
ADC input pins ADC[10..0] can be selected as single ended inputs to the ADC. The positive and negative inputs to the
differential gain amplifier are described in Table 4-59.
If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input
pair by the selected gain factor 8x or 20x, according to the setting of the MUX[4..0] bits in ADMUX register. This amplified
value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed
altogether.
The on-chip temperature sensor is selected by writing the code defined in Table 4-59 to the MUX[4..0] bits in ADMUX
register when its dedicated ADC channel is used as an ADC input.
A specific ADC channel (defined in Table 4-59) is used to measure the voltage to the boundaries of an external resistance
flowing by a current driving by the internal current source (ISRC).
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA register. Voltage reference and input channel
selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is
recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC data registers, ADCH and ADCL. By default, the result is
presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX register.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must
be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is
read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before
ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the
ADCH and ADCL registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers
is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
4.18.4 Starting a Conversion
A single conversion is started by writing a logical one to the ADC start conversion bit, ADSC. This bit stays high as long as
the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel
is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel
change.
Alternatively, a conversion can be triggered automatically by various sources. Auto triggering is enabled by setting the ADC
auto trigger enable bit, ADATE in ADCSRA register. The trigger source is selected by setting the ADC trigger select bits,
ADTS in ADCSRB register (see description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on
the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting
conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be
started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an
interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in SREG register is cleared.
A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to
trigger a new conversion at the next interrupt event.
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Figure 4-83. ADC Auto Trigger Logic
CLKIO
ADTS[2:0]
START
ADIF
ADATE
ADC Prescaler
CLKADC
SOURCE 1
...
...
...
...
Conversion
Logic
Edge
Detector
SOURCE n
ADSC
Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion
has finished. The ADC then operates in free running mode, constantly sampling and updating the ADC data register. The
first conversion must be started by writing a logical one to the ADSC bit in ADCSRA register. In this mode the ADC will
perform successive conversions independently of whether the ADC interrupt flag, ADIF is cleared or not.
If auto triggering is enabled, single conversions can be started by writing ADSC in ADCSRA register to one. ADSC can also
be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of
how the conversion was started.
4.18.5 Prescaling and Conversion Timing
Figure 4-84. ADC Prescaler
Reset
CK/64
CK/128
CK/32
CK/16
CK/8
CK/4
7-bit ADC Prescaler
CK/2
ADEN
START
CKIO
ADPS0
ADPS1
ADPS2
By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get
maximum resolution. If a lower resolution than 10bits is needed, the input clock frequency to the ADC can be higher than
200kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above
100kHz. The prescaling is set by the ADPS bits in ADCSRA register. The prescaler starts counting from the moment the
ADC is switched on by setting the ADEN bit in ADCSRA register. The prescaler keeps running for as long as the ADEN bit is
set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA register, the conversion starts at the following
rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA
register is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
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The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 14.5 ADC clock
cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC data registers,
and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a
new conversion will be initiated on the first rising ADC clock edge.
When auto triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger
event to the start of conversion. In this mode, the sample-and-hold takes place 2 ADC clock cycles after the rising edge on
the trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
In free running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains
high. For a summary of conversion times, see Table 4-55.
Figure 4-85. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
Conversion
First Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock
ADEN
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
MUX and REFS
Update
Conversion
Complete
Sample and Hold
MUX and REFS
Update
Figure 4-86. ADC Timing Diagram, Single Conversion
One Conversion
Cycle Number
1
2
3
4
5
6
7
8
9
Next Conversion
10
11
12
13
1
2
3
ADC Clock
ADSC
ADIF
Sign and MSB of Result
ADCH
LSB of Result
ADCL
Sample and Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
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Figure 4-87. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Cycle Number
1
2
3
4
5
6
7
8
9
Next Conversion
10
11
12
13
1
2
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Sample and Hold
Prescaler
Reset
Prescaler
Reset
Conversion
Complete
MUX and REFS
Update
Figure 4-88. ADC Timing Diagram, Free Running Conversion
One Conversion
11
Cycle Number
12
13
Next Conversion
1
2
3
4
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Sample and Hold
Conversion
Complete
MUX and REFS
Update
Table 4-55. ADC Conversion Time
Sample and Hold
(Cycles from Start of Conversion)
Conversion Time (Cycles)
First conversion
13.5cycles
25cycles
Normal conversions
1.5cycles
13cycles
2cycles
13.5cycles
Condition
Auto Triggered conversions
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4.18.6 Changing Channel or Reference Selection
The MUX[4:0] and REFS[1:0] bits in the ADMUX register are single buffered through a temporary register to which the CPU
has random access. This ensures that the channels and reference selection only takes place at a safe point during the
conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion
starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating
resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA register is set). Note that the
conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new
channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If auto triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when
updating the ADMUX register, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX register is changed in this
period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in
the following ways:
a. When ADATE or ADEN is cleared.
b.
During conversion, minimum one ADC clock cycle after the trigger event.
c.
After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
4.18.6.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is
selected:
In single conversion mode, always select the channel before starting the conversion. The channel selection may be changed
one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete
before changing the channel selection.
In free running mode, always select the channel before starting the first conversion. The channel selection may be changed
one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete,
and then change the channel selection. Since the next conversion has already started automatically, the next result will
reflect the previous channel selection. Subsequent conversions will reflect the new channel selection.
4.18.6.2 ADC Voltage Reference
The voltage reference for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed
VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 1.1V/2.56V voltage reference or
external AREF pin. The first ADC conversion result after switching voltage reference source may be inaccurate, and the user
is advised to discard this result.
4.18.7 ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core
and other I/O peripherals. The noise canceler can be used with ADC noise reduction and idle mode. To make use of this
feature, the following procedure should be used:
a. Make sure that the ADC is enabled and is not busy converting. Single conversion mode must be selected and the
ADC conversion complete interrupt must be enabled.
b.
Enter ADC noise reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.
c.
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and
execute the ADC conversion complete interrupt routine. If another interrupt wakes up the CPU before the ADC
conversion is complete, that interrupt will be executed, and an ADC conversion complete interrupt request will be
generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command
is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC noise
reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power
consumption.
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4.18.7.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 4-89. An analog source applied to ADCn is
subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the
ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined
resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10k or less. If such a source is used,
the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long
time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present to avoid distortion from unpredictable
signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the
signals as inputs to the ADC.
Figure 4-89. Analog Input Circuitry
IIH
ADCn
1 to 100kΩ
IIL
CS/H = 14pF
VCC/2
4.18.7.2 Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If
conversion accuracy is critical, the noise level can be reduced by applying the following techniques:
a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and
keep them well away from high-speed switching digital tracks.
198
b.
Use the ADC noise canceler function to reduce induced noise from the CPU.
c.
If any port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress.
ATA6616C/ATA6617C [DATASHEET]
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4.18.7.3 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read
as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
● Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value:
0 LSB.
Figure 4-90. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
●
VREF Input Voltage
Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF)
compared to the ideal transition (at 1.5LSB below maximum). Ideal value: 0 LSB
Figure 4-91. Gain Error
Output Code
Gain
Error
Ideal ADC
Actual ADC
VREF Input Voltage
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●
Integral mon-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual
transition compared to an ideal transition for any code. Ideal value: 0LSB.
Figure 4-92. Integral Non-linearity (INL)
INL
Output Code
Ideal ADC
Actual ADC
VREF Input Voltage
●
Differential non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent
transitions) from the ideal code width (1LSB). Ideal value: 0LSB.
Figure 4-93. Differential Non-linearity (DNL)
Output Code
0x3FF
1 LSB
DNL
0x000
0
200
VREF Input Voltage
●
Quantization error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages
(1 LSB wide) will code to the same value. Always ±0.5LSB.
●
Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for
any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal
value: ±0.5LSB.
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4.18.8 ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC result registers (ADCL,
ADCH). The form of the conversion result depends on the type of the conversion as there are three types of conversions:
single ended conversion, unipolar differential conversion and bipolar differential conversion.
4.18.8.1 Single Ended Conversion
For single ended conversion, the result is:
V IN 1024
ADC = --------------------------V REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 4-58 on page 203 and
Table 4-59 on page 204). 0x000 represents analog ground, and 0x3FF represents the selected voltage reference minus one
LSB. The result is presented in one-sided form, from 0x3FF to 0x000.
4.18.8.2 Unipolar Differential Conversion
If differential channels and an unipolar input mode are used, the result is:
V POS – V NEG 1024
ADC = -------------------------------------------------------- GAIN
V REF
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage
reference (see Table 4-58 on page 203 and Table 4-59 on page 204). The voltage on the positive pin must always be larger
than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in onesided form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 8x or 20x.
4.18.8.3 Bipolar Differential Conversion
As default the ADC converter operates in the unipolar input mode, but the bipolar input mode can be selected by writing the
BIN bit in the ADCSRB register to one. In the bipolar input mode two-sided voltage differences are allowed and thus the
voltage on the negative input pin can also be larger than the voltage on the positive input pin. If differential channels and a
bipolar input mode are used, the result is:
V POS – V NEG 512
ADC = ----------------------------------------------------- GAIN
V REF
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage
reference. The result is presented in two’s complement form, from 0x200 (–512d) through 0x000 (+0d) to 0x1FF (+511d). The
GAIN is either 8x or 20x.
However, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses one bit of the converter
dynamic range. Then, if the user wants to perform the conversion with the maximum dynamic range, the user can perform a
quick polarity check of the result and use the unipolar differential conversion with selectable differential input pair. When the
polarity check is performed, it is sufficient to read the MSB of the result (ADC9 in ADCH register). If the bit is one, the result
is negative, and if this bit is zero, the result is positive.
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4.18.9 Temperature Measurement
The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC input.
MUX[4..0] bits in ADMUX register enables the temperature sensor. The internal 1.1V voltage reference must also be
selected for the ADC voltage reference source in the temperature sensor measurement. When the temperature sensor is
enabled, the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor.
The measured voltage has a linear relationship to the temperature as described in Table 4-56. The voltage sensitivity is
approximately 1LSB/°C and the accuracy of the temperature measurement is ±10°C using manufacturing calibration values
(TS_GAIN, TS_OFFSET). The values described in Table 4-56 are typical values. However, due to the process variation the
temperature sensor output varies from one chip to another.
Table 4-56. Temperature versus Sensor Output Voltage (Typical Case): Example ADC Values
Temperature/°C
–40°C
+25°C
+85°C
0x00F6
0x0144
0c01B8
4.18.10 Manufacturing Calibration
Calibration values determined during test are available in the signature row.
The temperature in degrees Celsius can be calculated using the formula:
ADCH « 8 ADCL – 273 + 25 – TS_OFFSET 128
T = ------------------------------------------------------------------------------------------------------------------------------------------------ + 25
TS_GAIN
Where:
a. ADCH & ADCL are the ADC data registers,
b.
is the temperature sensor gain
c.
TSOFFSET is the temperature sensor offset correction term
TS_GAIN is the unsigned fixed point 8-bit temperature sensor gain factor in 1/128th units stored in the signature
row
TS_OFFSET is the signed twos complement temperature sensor offset reading stored in the signature row. See
Table 4-65 on page 219 for signature row parameter address.
The following code example allows to read Signature Row data:
.equ TS_GAIN = 0x0005
.equ TS_OFFSET = 0x0003
LDI R30,LOW(TS_GAIN)
LDI R31,HIGH (TS_GAIN)
RCALL Read_signature_row
MOV R17,R16; Save R16 result
LDI R30,LOW(TS_OFFSET)
LDI R31,HIGH (TS_OFFSET)
RCALL Read_signature_row
; R16 holds TS_OFFSET and R17 holds TS_GAIN
Read_signature_row:
IN R16,SPMCSR; Wait for SPMEN ready
SBRC R16,SPMEN; Exit loop here when SPMCSR is free
RJMP Read_signature_row
LDI R16,((1<<SIGRD)|(1<<SPMEN)); We need to set SIGRD and SPMEN
together
OUT SPMCSR,R16; and execute the LPM within 3 cycles
LPM R16,Z
RET
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4.18.11 Internal Voltage Reference Output
The internal voltage reference is output on XREF pin as described in Table 4-57 if the ADC is turned on (see Section 4.7.2.1
“Voltage Reference Enable Signals and Start-up Time” on page 70). Addition of an external filter capacitor (5 - 10nF) on
XREF pin may be necessary. XREF current load must be from 1µA to 100µA with VCC from 2.7V to 5.5V for XREF = 1.1V
and with VCC from 4.5V to 5.5V for XREF = 2.56V.
XREF pin can be coupled to an analog input of the ADC.
Table 4-57. Internal Voltage Reference Output
XREFEN(1)
REFS1(2)
REFS0(3)
0
x
x
Hi-Z, the pin can be used as AREF input or other alternate functions.
(2)
0
1
XREF = 1.1V(3)
1
1(1)
Notes: 1.
Voltage Reference Output (Iload ≤ 100µA)
1
1
XREF = 2.56V(3)(4)
See ”Bit 1 – XREFEN: Internal Voltage Reference Output Enable” on page 208.
2.
See ”Bit 7:6 – REFS1:REFS0: Voltage Reference Selection Bits” on page 203.
3.
In these configurations, the pin pull-up must be turned off and the pin digital output must be set in Hi-Z.
4.
VCC in range 4.5 to 5.5V.
4.18.12 Register Description
4.18.12.1 ADMUX – ADC Multiplexer Selection Register
Bit
7
6
5
4
3
2
1
0
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADMUX
• Bit 7:6 – REFS1:REFS0: Voltage Reference Selection Bits
These bits and AREFEN bit from the analog miscellaneous control register (AMISCR) select the voltage reference for the
ADC, as shown in Table 4-58. If these bits are changed during a conversion, the change will not go in effect until this
conversion is complete (ADIF in ADCSRA register is set). Whenever these bits are changed, the next conversion will take 25
ADC clock cycles. If active channels are used, using AVCC or an external AREF higher than (AVCC – 1V) is not
recommended, as this will affect ADC accuracy. The internal voltage reference options may not be used if an external
voltage is being applied to the AREF pin.
Table 4-58. Voltage Reference Selections for ADC
REFS1
REFS0
AREFEN
Voltage Reference (VREF) Selection
X
0
0
AVCC used as voltage reference, disconnected from AREF pin.
X
0
1
External voltage reference at AREF pin (AREF ≥ 2.0V)
0
1
0
Internal 1.1V voltage reference.
1
1
0
Internal 2.56V voltage reference.
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. Write one to ADLAR to left
adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC data register
immediately, regardless of any ongoing conversions. For a complete description of this bit, see Section 4.18.12.3 “ADCL and
ADCH – The ADC Data Register” on page 206.
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
These bits select which combination of analog inputs are connected to the ADC. In case of differential input, gain selection is
also made with these bits. Refer to Table 4-59 for details. If these bits are changed during a conversion, the change will not
go into effect until this conversion is complete (ADIF in ADCSRA register is set).
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Table 4-59. Input Channel Selections
MUX[4..0]
Single Ended Input
0 0000
ADC0 (PA0)
0 0001
ADC1 (PA1)
0 0010
ADC2 (PA2)
0 0011
ADC3 / ISRC (PA3)
0 0100
ADC4 (PA4)
0 0101
ADC5 (PA5)
0 0110
ADC6 (PA6)
0 0111
ADC7 / AREF (PA7)
0 1000
ADC8 (PB5)
0 1001
ADC9 (PB6)
0 1010
ADC10 (PB7)
0 1011
Temperature Sensor
0 1100
Bandgap Reference (1.1 V)
0 1101
AVCC/4
0 1110
GND (0V)
0 1111
(reserved)
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
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Negative Differential
Input
Gain
NA
NA
NA
ADC0 (PA0)
ADC1 (PA1)
ADC1 (PA1)
ADC2 (PA2)
ADC2 (PA2)
ADC3 (PA3)
ADC4 (PA4)
ADC5 (PA5)
ADC5 (PA5)
ADC6 (PA6)
ADC6 (PA6)
ADC7 (PA7)
ADC8 (PB5)
ADC9 (PB6)
ADC9 (PB6)
ADC10 (PB7)
N/A
1 1001
204
Positive Differential
Input
8x
20x
8x
20x
8x
20x
8x
20x
8x
20x
8x
20x
8x
20x
8x
20x
4.18.12.2 ADCSRA – ADC Control and Status Register A
Bit
7
6
5
4
3
2
1
0
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRA
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is
in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In single conversion mode, write this bit to one to start each conversion. In free running mode, write this bit to one to start the
first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at
the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs
initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing
zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, auto triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of
the selected trigger signal. The trigger source is selected by setting the ADC trigger select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC conversion complete
interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if
doing a read-modify-write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions
are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC conversion complete interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock to the ADC.
Table 4-60. ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
2
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
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4.18.12.3 ADCL and ADCH – The ADC Data Register
ADLAR = 0
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
8
–
–
–
–
–
–
ADC9
ADC8
ADCH
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADLAR = 1
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
8
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADC1
ADC0
–
–
–
–
–
–
ADCL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC data register is not updated until ADCH is read. Consequently, if the result is left adjusted and
no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set,
the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in Section 4.18.8 “ADC Conversion Result” on page 201.
4.18.12.4 ADCSRB – ADC Control and Status Register B
Bit
7
6
5
4
3
2
1
0
BIN
ACME
ACIR1
ACIR0
–
ADTS2
ADTS1
ADTS0
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRB
• Bit 7– BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the
ADCSRB register. In the unipolar mode only one-sided conversions are supported and the voltage on the positive input must
always be larger than the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In the
bipolar mode two-sided conversions are supported and the result is represented in the two’s complement form. In the
unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit.
• Bit 3 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to zero when ADCSRB register is
written.
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• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA register is written to one, the value of these bits selects which source will trigger an ADC conversion.
If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the
selected interrupt flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a
positive edge on the trigger signal. If ADEN in ADCSRA register is set, this will start a conversion. Switching to free running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC interrupt flag is set.
Table 4-61. ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
0
0
0
Trigger Source
Free running mode
0
0
1
Analog comparator
0
1
0
External interrupt request 0
0
1
1
Timer/Counter1 compare match A
1
0
0
Timer/Counter1 overflow
1
0
1
Timer/Counter1 compare match B
1
1
0
Timer/Counter1 capture event
1
1
1
Watchdog interrupt request
4.18.12.5 DIDR0 – Digital Input Disable Register 0
Bit
7
6
ADC7D / ADC6D /
AIN1D
AIN0D
5
4
3
2
1
0
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DIDR0
• Bits 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN
register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital
input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
4.18.12.6 DIDR1 – Digital Input Disable Register 1
Bit
7
6
5
4
3
2
1
0
-
ADC10D
ADC9D
ADC8D
-
-
-
-
Read/Write
R
R/W
R/W
R/W
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
DIDR1
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to zero when DIDR1 register is
written.
• Bits 6..4 – ADC10D..ADC8D: ADC10..8 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN
register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC10:8 pin and the digital
input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
• Bits 3:0 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be written to zero when DIDR1 is
written.
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4.18.12.7 AMISCR – Analog Miscellaneous Control Register
Bit
7
6
5
4
3
-
-
-
-
-
2
1
0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
AREFEN XREFEN ISRCEN
AMISCR
• Bits 7:3 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be written to zero when AMISCR is
written.
• Bit 2 – AREFEN: External Voltage Reference Input Enable
When this bit is written logic one, the voltage reference for the ADC is input from AREF pin as described in Table 4.18.11 on
page 203. If active channels are used, using AVCC or an external AREF higher than (AVCC – 1V) is not recommended, as this
will affect ADC accuracy. The internal voltage reference options may not be used if an external voltage is being applied to
the AREF pin. It is recommended to use DIDR register bit function (digital input disable) when AREFEN is set.
• Bit 1 – XREFEN: Internal Voltage Reference Output Enable
When this bit is written logic one, the internal voltage reference 1.1V or 2.56V is output on XREF pin as described in Table
4.18.11 on page 203. It is recommended to use DIDR register bit function (digital input disable) when XREFEN is set.
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4.19
AnaComp - Analog Comparator
The analog comparator compares the input values on the positive pin (AIN1) and negative pin (AIN0). When the voltage on
the positive pin is higher than the voltage on the negative pin, the analog comparator output, ACO, is set. The comparator
can trigger a separate interrupt, exclusive to the analog comparator. The user can select Interrupt triggering on comparator
output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 4-94.
Figure 4-94. Analog Comparator Block Diagram(1)(2)
ADC Multiplexer
Output(1)
AVCC
ACME
ACO
ADEN
ACD
AIN1
(PA7)
ACI
+
Interrupt
Sensivity
Control
-
16-bit Timer/ Counter
Input Capture
Analog Comparator
Interrupt
AIN0
(PA6)
(from ADC)
ACIS1
ACIS0
ACIE
ACIRS
Internal
2.56/ 1.1V
Reference
REFS0
REFS1
1.1V
2.56V
2.56V/2
2.56V/4
2.56V/8
ACIR0
ACIR1
Notes:
1.
See Table 4-63 on page 212 and Table 4-64 on page 212
2.
Refer to Table 4-24 on page 92 for Analog Comparator pin placement.
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4.19.1 Register Description
4.19.1.1 ADC Control and Status Register B – ADCSRB
Bit
7
6
5
4
3
2
1
0
BIN
ACME
ACIR1
ACIR0
—
ADTS2
ADTS1
ADTS0
Read/Write
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRB
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the
positive input to the analog comparator. When this bit is written logic zero, AIN1 is applied to the positive input of the analog
comparator.
When the analog to digital converter (ADC) is configured as single ended input channel, it is possible to select any of the
ADC[10..0] pins to replace the positive input to the analog comparator. The ADC multiplexer (MUX[4..0]) is used to select
this input, and consequently, the ADC must be switched off to utilize this feature.
• Bits 5, 4 – ACIR1, ACIR0: Analog Comparator Internal Voltage Reference Select
When ACIRS bit is set in ADCSRA register, these bits select a voltage reference for the negative input to the analog
comparator, see Table 4-64 on page 212.
4.19.1.2 ACSR – Analog Comparator Control and Status Register
Bit
7
6
5
4
3
2
1
0
ACD
ACIRS
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
N/A
0
0
0
0
0
ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn
off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the
analog comparator interrupt must be disabled by clearing the ACIE bit of ACSR register. Otherwise an interrupt can occur
when the bit is changed.
• Bit 6 – ACIRS: Analog Comparator Internal Reference Select
When this bit is set an internal reference voltage replaces the negative input to the analog comparator (c.f. Table 4-64 on
page 212). If ACIRS is cleared, AIN0 is applied to the negative input to the analog comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a
delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The
analog comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the status register is set, the analog comparator interrupt is activated.
When written logic zero, the interrupt is disabled.
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• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the analog
comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the
comparator utilize the noise canceler and edge select features of the Timer/Counter1 input capture interrupt. When written
logic zero, no connection between the analog comparator and the input capture function exists. To make the comparator
trigger the Timer/Counter1 input capture interrupt, the ICIE1 bit in the timer interrupt mask register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the analog comparator interrupt. The different settings are shown
in Table 4-62.
Table 4-62. ACIS1 / ACIS0 Settings
ACIS1
ACIS0
0
0
Comparator interrupt on output toggle
0
1
Reserved
1
0
Comparator interrupt on falling output edge
1
Note:
Interrupt Mode
1
Comparator interrupt on rising output edge
When changing the ACIS1/ACIS0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.
4.19.1.3 DIDR0 – Digital Input Disable Register 0
Bit
7
6
ADC7D / ADC6D /
AIN1D
AIN0D
5
4
3
2
1
0
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DIDR0
• Bits 7,6 – AIN1D, AIN0D: AIN1D and AIN0D Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding analog compare pin is disabled. The
corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN0/1
pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the
digital input buffer.
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4.19.2 Analog Comparator Inputs
4.19.2.1 Analog Compare Positive Input
It is possible to select any of the inputs of the ADC positive input multiplexer to replace the positive input to the analog
comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this
feature. If the analog comparator multiplexer enable bit (ACME in ADCSRB register) is set and the ADC is switched off
(ADEN in ADCSRA register is zero), MUX[4..0] in ADMUX register select the input pin to replace the positive input to the
analog comparator, as shown in Table 4-63. If ACME is cleared or ADEN is set, AIN1 pin is applied to the positive input to
the analog comparator.
Table 4-63. Analog Comparator Positive Input
ACME
ADEN
MUX[4..0]
Analog Comparator Positive Input - Comment
0
x
x xxxxb
AIN1
x
1
x xxxxb
AIN1
1
0
0 0000b
ADC0
1
0
0 0001b
ADC1
1
0
0 0010b
ADC2
1
0
0 0011b
ADC3 / ISRC
1
0
0 0100b
ADC4
1
0
0 0101b
ADC5
1
0
0 0110b
ADC6
1
0
0 0111b
ADC7
1
0
0 1000b
ADC8
1
0
0 1001b
ADC9
1
0
0 1010b
ADC10
1
0
Other
ADC switched on
ADC switched off
This doesn’t make sense - don’t use
4.19.2.2 Analog Compare Negative Input
It is possible to select an internal voltage reference to replace the negative input to the analog comparator. The output of a
2-bit DAC using the internal voltage reference of the DAC is available when ACIRS bit of ACSR register is set. The voltage
reference division factor is done by ACIR[1..0] of ADCSRB register. If ACIRS is cleared, AIN0 pin is applied to the negative
input to the analog comparator.
Table 4-64. Analog Comparator Negative Input
ACIRS
ACIR[1..0]
REFS[1..0]
0
x
x
Analog Comparator Negative Input - Comment
AIN0
0 0b
1
x
0 1b
Reserved
1 0b
212
1
0 0b
1 1b
2.56V - using internal 2.56V voltage reference
1
0 1b
1 1b
1.28V (1/2 of 2.56V) - using internal 2.56V voltage reference
1
1 0b
1 1b
0.64V (1/4 of 2.56V - using internal 2.56V voltage reference
1
1 1b
1 1b
0.32V (1/8 of 2.56V) - using internal 2.56V voltage reference
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4.20
DebugWIRE On-chip Debug System
4.20.1 Features
●
●
●
●
●
●
●
●
●
●
Complete program flow control
Emulates all on-chip functions, both digital and analog, except RESET pin
Real-time operation
Symbolic debugging support (both at C and assembler source level, or for other HLLs)
Unlimited number of program break points (using software break points)
Non-intrusive operation
Electrical characteristics identical to real device
Automatic configuration system
High-speed operation
Programming of non-volatile memories
4.20.2 Overview
The debugWIRE on-chip debug system uses a one-wire, bi-directional interface to control the program flow, execute AVR®
instructions in the CPU and to program the different non-volatile memories.
4.20.3 Physical Interface
When the debugWIRE enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system
within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with
pull-up enabled and becomes the communication gateway between target and emulator.
Figure 4-95. The debugWIRE Setup
+1.8 to +5.5V
VCC
dW
dW (RESET)
GND
Figure 4-95 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock
is not affected by debugWIRE and will always be the clock source selected by the CKSEL fuses.
When designing a system where debugWIRE will be used, the following observations must be made for correct operation:
● Pull-up resistors on the dW/(RESET) line must not be smaller than 10k. The pull-up resistor is not required for
debugWIRE functionality.
●
●
●
Connecting the RESET pin directly to VCC will not work.
Capacitors connected to the RESET pin must be disconnected when using debugWire.
All external reset sources must be disconnected.
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4.20.4 Software Break Points
DebugWIRE supports program memory break points by the AVR® BREAK instruction. Setting a break point in AVR Studio®
will insert a BREAK instruction in the program memory. The instruction replaced by the BREAK instruction will be stored.
When program execution is continued, the stored instruction will be executed before continuing from the program memory. A
break can be inserted manually by putting the BREAK instruction in the program.
The flash must be re-programmed each time a break point is changed. This is automatically handled by AVR Studio through
the debugWIRE interface. The use of break points will therefore reduce the flash data retention. Devices used for debugging
purposes should not be shipped to end customers.
4.20.5 Limitations of DebugWIRE
The debugWIRE communication pin (dW) is physically located on the same pin as external reset (RESET). An external reset
source is therefore not supported when the debugWIRE is enabled.
The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU
is running. When the CPU is stopped, care must be taken while accessing some of the I/O registers via the debugger (AVR
Studio).
A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the
power consumption while in sleep. Thus, the DWEN fuse should be disabled when debugWire is not used.
4.20.6 DebugWIRE Related Register in I/O Memory
The following section describes the registers used with the debugWire.
4.20.6.1 DebugWIRE Data Register – DWDR
Bit
7
6
5
4
3
2
1
0
DWDR[7:0]
DWDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The DWDR register provides a communication channel from the running program in the MCU to the debugger. This register
is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations.
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4.21
Flash Programming
The device provides a self-programming mechanism for downloading and uploading program code by the MCU itself. The
self-programming can use any available data interface (i.e. LIN, USART, ...) and associated protocol to read code and write
(program) that code into the program memory.
The program memory is updated in a page by page fashion. Before programming a page with the data stored in the
temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the
buffer can be filled either before the page erase command or between a page erase and a page write operation:
● Alternative 1, fill the buffer before a page erase
●
●
Fill temporary page buffer
●
Perform a page erase
●
Perform a page write
Alternative 2, fill the buffer after page erase
●
Perform a page erase
●
Fill temporary page buffer
●
Perform a page write
If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page
buffer) before the erase, and then be re-written. When using alternative 1, the boot loader provides an effective read-modifywrite feature which allows the user software to first read the page, do the necessary changes, and then write back the
modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased.
The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the
page erase and page write operation is addressing the same page.
4.21.1 Self-programming the Flash
4.21.1.1 Performing Page Erase by SPM
To execute page erase, set up the address in the Z-pointer, write “00000011 b” to SPMCSR and execute SPM within four
clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the
Z-register. Other bits in the Z-pointer will be ignored during this operation.
● The CPU is halted during the page erase operation.
4.21.1.2 Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001b” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address
the data in the temporary buffer. The temporary buffer will auto-erase after a page write operation or by writing the CTPB bit
in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address
without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
4.21.1.3 Performing a Page Write
To execute page write, set up the address in the Z-pointer, write “00000101b” to SPMCSR and execute SPM within four
clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other
bits in the Z-pointer must be written to zero during this operation.
● The CPU is halted during the page write operation.
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4.21.2 Addressing the Flash during Self-programming
The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file.
The number of bits actually used is implementation dependent.
Bit
Bit
15
14
13
12
11
10
9
8
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
ZH (R31)
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
ZL (R30)
7
6
5
4
3
2
1
0
Since the flash is organized in pages (see Table 4-73 on page 225), the program counter can be treated as having two
different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most
significant bits are addressing the pages. This is shown in Figure 4-96.
Note that the page erase and page write operations are addressed independently. Therefore it is of major importance that
the software addresses the same page in both the page erase and page write operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the flash byte-by-byte, also the
LSB (bit Z0) of the Z-pointer is used.
Figure 4-96. Addressing the Flash During SPM(1)
BIT
15
ZPCMSB
ZPAGEMSB
1 0
0
PCMSB
PROGRAM COUNTER
Z-POINTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PCWORD
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
INSTRUCTION WORD
PCWORD [PAGEMSB:0]
00
01
02
PAGEEND
Note:
216
1.
The different variables used in Table 4-66 are listed in Table 4-73 on page 225.
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4.21.2.1 Store Program Memory Control and Status Register – SPMCSR
The store program memory control and status register contains the control bits needed to control the boot loader operations.
Bit
7
6
5
4
3
2
1
0
–
RWWSB
SIGRD
CTPB
RFLB
PGWRT
PGERS
SPMEN
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPMCSR
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the Atmel® ATtiny87/167 and will always read as zero.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting read-while-write. It will always read as zero in Atmel ATtiny87/167.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from
the signature row into the destination register. See Section 4.21.2.4 “Reading the Signature Row from Software” on page
219 for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be
lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits
or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See Section 4.21.2.3 “Reading the Fuse and
Lock Bits from Software” on page 218 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write,
with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1
and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire page write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page
erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will
auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted
during the entire page write operation.
• Bit 0 – SPMEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either SIGRD, CTPB, RFLB,
PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is
written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.
The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM
instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the
operation is completed.
Writing any other combination than “10 0001b”, “01 0001b”, “00 1001b”, “00 0101b”, “00 0011b” or “00 0001b” in the lower six
bits will have no effect.
Note:
Only one SPM instruction should be active at any time.
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4.21.2.2 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to flash. Reading the fuses and lock bits from
software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit
(EEPE) in the EECR register and verifies that the bit is cleared before writing to the SPMCSR register.
4.21.2.3 Reading the Fuse and Lock Bits from Software
It is possible to read both the fuse and lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set
the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the RFLB and
SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN
bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or
no SPM instruction is executed within four CPU cycles. When RFLB and SPMEN are cleared, LPM will work as described in
the Instruction set Manual.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0001)
–
–
–
–
–
–
LB2
LB1
The algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. To read the fuse
low byte, load the Z-pointer with 0x0000 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is
executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the fuse low byte (FLB)
will be loaded in the destination register as shown below. See Table 4-71 on page 224 for a detailed description and mapping
of the fuse low byte.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0000)
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the fuse high byte (FHB), load 0x0003 in the Z-pointer. When an LPM instruction is executed within
three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the fuse high byte will be loaded in the
destination register as shown below. See Table 4-70 on page 223 for detailed description and mapping of the fuse high byte.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0003)
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Similarly, when reading the extended fuse byte (EFB), load 0x0002 in the Z-pointer. When an LPM instruction is executed
within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte will be
loaded in the destination register as shown below. See Table 4-69 on page 223 for detailed description and mapping of the
extended fuse byte.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0002)
–
–
–
–
–
–
–
EFB0
Fuse and lock bits that are programmed, will be read as zero. Fuse and lock bits that are unprogrammed, will be read as
one.
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4.21.2.4 Reading the Signature Row from Software
To read the signature row from software, load the Z-pointer with the signature byte address given in Table 4-65 on page 219
and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the
SIGRD and SPMEN bits are set in SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD
and SPMEN bits will auto-clear upon completion of reading the signature row lock bits or if no LPM instruction is executed
within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
Table 4-65. Signature Row Addressing
Note:
Signature Byte
Z-Pointer Address
Device signature byte 0
0x0000
Device signature byte 1
0x0002
Device signature byte 2
0x0004
8MHz RC oscillator calibration byte
0x0001
TSOFFSET - Temp sensor offset
0x0003
TSGAIN - Temp sensor gain
All other addresses are reserved for future use.
0x0005
4.21.2.5 Preventing Flash Corruption
During periods of low VCC, the flash program can be corrupted because the supply voltage is too low for the CPU and the
flash to operate properly. These issues are the same as for board level systems using the flash, and the same design
solutions should be applied.
A flash program corruption can be caused by two situations when the voltage is too low.
● First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
●
Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. Keep the AVR® RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal brown-out detector (BOD) if the operating voltage matches the detection level. If not, an
external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the
write operation will be completed provided that the power supply voltage is sufficient.
2.
Keep the AVR core in power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR register and thus the flash from
unintentional writes.
4.21.2.6 Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time flash accesses. Table 4-66 shows the typical programming time for flash
accesses from the CPU.
Table 4-66. SPM Programming Time
Symbol
Min Programming Time
Max Programming Time
Flash write (page erase, page write, and write lock
bits by SPM)
3.7ms
4.5ms
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4.21.2.7 Simple Assembly Code Example for a Boot Loader
Note that the RWWSB bit will always be read as zero in Atmel® ATtiny87/167. Nevertheless, it is recommended to check this
bit as shown in the code example, to ensure compatibility with devices supporting Read-While-Write.
;- The routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y-pointer
; the first data location in Flash is pointed to by the Z-pointer
;- Error handling is not included
;- Registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
;
loophi (r25), spmcsrval (r20)
; -Storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
.equ
PAGESIZEB = PAGESIZE*2
.org SMALLBOOTSTART
Write_page:
;
ldi
rcall
Page Erase
spmcsrval, (1<<PGERS) | (1<<SELFPGEN)
Do_spm
;
ldi
rcall
Clear temporary page buffer
spmcsrval, (1<<CPTB) | (1<<SELFPGEN)
Do_spm
;
ldi
ldi
Transfer data from RAM to Flash temporary page buffer
looplo, low(PAGESIZEB)
; init loop variable
loophi, high(PAGESIZEB)
; not required for PAGESIZEB<=256
Wrloop:
ld
ld
ldi
rcall
adiw
sbiw
brne
220
r0, Y+
r1, Y+
spmcsrval, (1<<SELFPGEN)
Do_spm
ZH:ZL, 2
loophi:looplo, 2
Wrloop
; use subi for PAGESIZEB<=256
;
subi
sbci
ldi
rcall
Execute Page Write
ZL, low(PAGESIZEB)
; restore pointer
ZH, high(PAGESIZEB)
; not required for PAGESIZEB<=256
spmcsrval, (1<<PGWRT) | (1<<SELFPGEN)
Do_spm
;
ldi
rcall
Clear temporary page buffer
spmcsrval, (1<<CPTB) | (1<<SELFPGEN)
Do_spm
;
ldi
ldi
subi
sbci
Read back and check, optional
looplo, low(PAGESIZEB)
; init loop variable
loophi, high(PAGESIZEB)
; not required for PAGESIZEB<=256
YL, low(PAGESIZEB)
; restore pointer
YH, high(PAGESIZEB)
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; AGESIZEB is page size in BYTES, not words
Rdloop:
lpm
ld
cpse
rjmp
sbiw
brne
;
;
;
Return:
in
sbrs
ret
;
ldi
call
rjmp
Do_spm:
;
Wait_spm:
in
sbrc
rjmp
;
;
in
cli
;
Wait_ee:
sbic
rjmp
;
out
spm
;
out
ret
r0, Z+
r1, Y+
r0, r1
Error
loophi:looplo, 1
Rdloop
; use subi for PAGESIZEB<=256
To ensure compatibility with devices supporting Read-While-Write
Return to RWW section
Verify that RWW section is safe to read
temp1, SPMCSR
temp1, RWWSB
; If RWWSB is set, the RWW section is not
ready yet
Clear temporary page buffer
spmcsrval, (1<<CPTB) | (1<<SELFPGEN)
Do_spm
Return
Check for previous SPM complete
temp1, SPMCSR
temp1, SELFPGEN
Wait_spm
Input: spmcsrval determines SPM action
Disable interrupts if enabled, store status
temp2, SREG
Check that no EEPROM write access is present
EECR, EEPE
Wait_ee
SPM timed sequence
SPMCSR, spmcsrval
Restore SREG (to enable interrupts if originally enabled)
SREG, temp2
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4.22
Memory Programming
4.22.1 Program and Data Memory Lock Bits
The Atmel® ATtiny87/167 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain
the additional features listed in Table 4-68. The Lock bits can only be erased to “1” with the Chip Erase command. The Atmel
ATtiny87/167 has no separate Boot Loader section.
Table 4-67. Lock Bit Byte(1)
Lock Bit Byte
Bit No
Description
Default Value
7
–
1 (unprogrammed)
6
–
1 (unprogrammed)
5
–
1 (unprogrammed)
4
–
1 (unprogrammed)
3
–
1 (unprogrammed)
2
–
1 (unprogrammed)
1
Lock bit
1 (unprogrammed)
LB1
0
Lock bit
“1” means unprogrammed, “0” means programmed.
1 (unprogrammed)
LB2
Note:
1.
Table 4-68. Lock Bit Protection Modes(1)(2)
Memory Lock Bits
LB Mode
LB2
LB1
1
1
1
No memory lock features enabled.
2
1
0
Further programming of the flash and EEPROM is disabled in parallel and serial
programming mode. The fuse bits are locked in both serial and parallel
programming mode(1).
1.
Further programming and verification of the flash and EEPROM is disabled in
parallel and serial programming mode. The Fuse bits are locked in both serial
and parallel programming mode(1).
Program the fuse bits before programming the LB1 and LB2.
2.
“1” means unprogrammed, “0” means programmed.
3
Notes:
222
Protection Type
0
0
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4.22.2 Fuse Bit
The Atmel® ATtiny87/167 has three fuse bytes. Table 4-69, Table 4-70 & Table 4-71 describe briefly the functionality of all the
fuses and how they are mapped into the fuse bytes.
The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed (“0”), otherwise it is disabled.
Note that the fuses are read as logical zero, “0”, if they are programmed.
Table 4-69. Extended Fuse Byte
Fuse Extended Byte
Bit No
Description
Default Value
–
7
–
1 (unprogrammed)
–
6
–
1 (unprogrammed)
–
5
–
1 (unprogrammed)
–
4
–
1 (unprogrammed)
–
3
–
1 (unprogrammed)
–
2
–
1 (unprogrammed)
–
1
–
1 (unprogrammed)
SELFPRGEN
0
Self Programming Enable
1 (unprogrammed)
Bit No
Description
Default Value
Table 4-70. Fuse High Byte
Fuse High Byte
RSTDISBL
(1)
7
External reset disable
1 (unprogrammed)
DWEN
6
DebugWIRE enable
1 (unprogrammed)
SPIEN(2)
5
Enable serial program
and data downloading
0 (programmed,
SPI programming enabled)
WDTON(3)
4
Watchdog timer always on
1 (unprogrammed)
3
EEPROM memory is preserved
through the chip erase
1 (unprogrammed,
EEPROM not preserved)
BODLEVEL2(4)
2
Brown-out detector trigger level
1 (unprogrammed)
(4)
1
Brown-out detector trigger level
1 (unprogrammed)
EESAVE
BODLEVEL1
BODLEVEL0(4)
0
Brown-out detector trigger level
1 (unprogrammed)
Notes: 1. See Section 4.10.3.4 “Alternate Functions of Port B” on page 97 for description of RSTDISBL fuse.
2.
The SPIEN fuse is not accessible in serial programming mode.
3.
See Section 4.7.3.3 “Watchdog Timer Control Register - WDTCR” on page 74 for details.
4.
See Table 4-85 on page 240 for BODLEVEL fuse coding.
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Table 4-71. Fuse Low Byte
Fuse Low Byte
Bit No
Description
Default Value
(4)
7
Divide clock by 8
0 (programmed)
(3)
6
Clock output
1 (unprogrammed)
SUT1
5
Select start-up time
1 (unprogrammed)(1)
SUT0
4
Select start-up time
0 (programmed)(1)
CKSEL3
3
Select clock source
0 (programmed)(2)
CKSEL2
2
Select clock source
0 (programmed)(2)
CKSEL1
1
Select clock source
1 (unprogrammed)(2)
CKDIV8
CKOUT
CKSEL0
Notes: 1.
0
Select clock source
0 (programmed)(2)
The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 4-8 on
page 48 for details.
2.
The default setting of CKSEL3..0 results in internal RC oscillator at 8MHz. See Table 4-7 on page 48 for
details.
3.
The CKOUT fuse allows the system clock to be output on PORTB5. See Section 4.5.2.7 “Clock Output Buffer”
on page 52 for details.
4.
See Section 4.5.4 “System Clock Prescaler” on page 58 for details.
4.22.2.1 Latching of Fuses
The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect
until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is
programmed. The fuses are also latched on Power-up in normal mode.
4.22.3 Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial
and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
Table 4-72. Signature Bytes
Device
ATtiny167
Address
Value
Signature Byte Description
0
0x1E
Indicates manufactured by Atmel
1
0x94
Indicates 16Kb flash memory
2
0x87
Indicates ATtiny167 device when address 1 contains 0x94
4.22.4 Calibration Byte
The Atmel® ATtiny87/167 has a byte calibration value for the internal RC oscillator. This byte resides in the high byte of
address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL register to
ensure correct frequency of the calibrated RC oscillator.
224
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4.22.5 Page Size
Table 4-73. Number of Words in a Page and No. of Pages in the Flash
Device
Flash Size
Page Size
PCWORD
No. of Pages
PCPAGE
PCMSB
ATtiny87
4K words
64 words
PC[5:0]
64
PC[11:6]
11
ATtiny167
8K words
64 words
PC[5:0]
128
PC[12:6]
12
Table 4-74. Number of Words in a Page and No. of Pages in the EEPROM
Device
EEPROM Size
Page Size
PCWORD
No. of Pages
PCPAGE
EEAMSB
ATtiny87
ATtiny167
512bytes
4bytes
EEA[1:0]
128
EEA[8:2]
8
4.22.6 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify flash program memory, EEPROM data memory, memory lock bits,
and fuse bits in the Atmel® ATtiny87/167. Pulses are assumed to be at least 250ns unless otherwise noted.
4.22.6.1 Signal Names
In this section, some pins of the Atmel ATtiny87/167 are referenced by signal names describing their functionality during
parallel programming, see Figure 4-97 and Figure 4-98. Pins not described in the following table are referenced by pin
names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in
Figure 4-76.
When pulsing WR or OE, the command loaded determines the action executed. The different commands are shown in
Figure 4-77.
Figure 4-97. Parallel Programming
+4.5 to +5.5V
WR
PB0
XA0
PB1
XA1/ BS2
PB2
PAGEL/ BS1
PB3
VCC
+4.5 to +5.5V
AVCC
XTAL1/ PB4
OE
PB5
RDY/ BSY
PB6
+12V
PB7 to PB0
DATA
RESET/ PB7
GND
Note:
VCC – 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 to 5.5V
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Figure 4-98. Pin Name Mapping
Signal Name in
Programming Mode
Pin Name
I/O
WR
PB0
I
Write pulse (Active low).
XA0
PB1
I
XTAL1 action bit 0
XA1 / BS2
PB2
I
- XTAL1 action bit 1
- Byte select 2
(“0” selects low byte, “1” selects 2’nd high byte)
PAGEL / BS1
PB3
I
- Program memory and EEPROM data page load
- Byte select 1
(0” selects low byte, “1” selects high byte)
PB4
I
XTAL1 (clock input)
OE
PB5
I
Output enable (active low).
RDY / BSY
PB6
O
0: Device is busy programming,
1: Device is ready for new command.
+12V
PB7
I
- Reset (active low)
- Parallel programming mode (+12V).
DATA
PA7-PA0
I/O
Function
Bi-directional data bus (output when OE is low).
Table 4-75. Pin Values Used to Enter Programming Mode
Pin
Symbol
Value
PAGEL / BS1
Prog_enable[3]
0
XA1 / BS2
Prog_enable[2]
0
XA0
Prog_enable[1]
0
WR
Prog_enable[0]
0
Table 4-76. XA1 and XA0 Coding
XA1
XA0
Action when XTAL1 is Pulsed
0
0
Load flash or EEPROM address (high or low address byte determined by BS1).
0
1
Load data (high or low data byte for flash determined by BS1).
1
0
Load command
1
1
No action, idle
Table 4-77. Command Byte Bit Coding
Command Byte
226
Command Executed
1000 0000 b
Chip erase
0100 0000 b
Write fuse bits
0010 0000 b
Write lock bits
0001 0000 b
Write flash
0001 0001 b
Write EEPROM
0000 1000 b
Read signature bytes and calibration byte
0000 0100 b
Read fuse and lock bits
0000 0010 b
Read flash
0000 0011 b
Read EEPROM
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4.22.7 Parallel Programming
4.22.7.1 Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply 4.5 - 5.5V between VCC and GND.
2.
Set RESET to “0” and toggle XTAL1 at least six times.
3.
Set the Prog_enable pins listed in Table 4-75 on page 226 to “0000b” and wait at least 100ns.
4.
Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100ns after +12V has been applied to
RESET, will cause the device to fail entering programming mode.
5.
Wait at least 50µs before sending a new command.
4.22.7.2 Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For efficient programming, the following
should be considered.
● The command needs only be loaded once when writing or reading multiple memory locations.
●
Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE fuse is programmed)
and flash after a chip erase.
●
Address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte
EEPROM. This consideration also applies to signature bytes reading.
4.22.7.3 Chip Erase
The chip erase will erase the flash and EEPROM(1) memories plus lock bits. The lock bits are not reset until the program
memory has been completely erased. The fuse bits are not changed. A chip erase must be performed before the flash
and/or EEPROM are reprogrammed.
Note:
1.
The EEPRPOM memory is preserved during chip erase if the EESAVE fuse is programmed.
Load Command “Chip Erase”
1.
Set XA1, XA0 to “1,0 ”. This enables command loading.
2.
Set BS1 to “0”.
3.
Set DATA to “1000 0000 b”. This is the command for chip erase.
4.
Give XTAL1 a positive pulse. This loads the command.
5.
Give WR a negative pulse. This starts the chip erase. RDY/BSY goes low.
6.
Wait until RDY/BSY goes high before loading a new command.
4.22.7.4 Programming the Flash
The flash is organized in pages, see Table 4-73 on page 225. When programming the flash, the program data is latched into
a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes
how to program the entire Flash memory:
A. Load Command “Write Flash”
1. Set XA1, XA0 to “1,0”. This enables command loading.
2.
Set BS1 to “0”.
3.
Set DATA to “0001 0000 b”. This is the command for write flash.
Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte
1. Set XA1, XA0 to “00”. This enables address loading.
2.
Set BS1 to “0”. This selects low address.
3.
Set DATA = Address low byte (0x00 - 0xFF).
4.
Give XTAL1 a positive pulse. This loads the address low byte.
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C. Load Data Low Byte
1. Set XA1, XA0 to “0,1”. This enables data loading.
2.
Set DATA = Data low byte (0x00 - 0xFF).
3.
Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte.
2.
Set XA1, XA0 to “0,1”. This enables data loading.
3.
Set DATA = Data high byte (0x00 - 0xFF).
4.
Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte.
2.
Give PAGEL a positive pulse. This latches the data bytes. (See Figure 4-100 for signal waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the
FLASH. This is illustrated in Figure 4-99 on page 228. Note that if less than eight bits are required to address words in the
page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a
page write.
G. Load Address High byte
1. Set XA1, XA0 to “0,0”. This enables address loading.
2.
Set BS1 to “1”. This selects high address.
3.
Set DATA = Address high byte (0x00 - 0xFF).
4.
Give XTAL1 a positive pulse. This loads the address high byte.
H. Program Page
1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.
2.
Wait until RDY/BSY goes high (See Figure 4-100 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been programmed.
J. End Page Programming
1. Set XA1, XA0 to “1,0”. This enables command loading.
2.
Set DATA to “0000 0000b”. This is the command for no operation.
3.
Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.
Figure 4-99. Addressing the Flash Which is Organized in Pages
PCMSB
PROGRAM COUNTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PCWORD
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
INSTRUCTION WORD
PCWORD [PAGEMSB:0]
00
01
02
PAGEEND
228
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Figure 4-100. Programming the Flash Waveforms(1)
F
DATA
A
B
C
D
E
B
C
D
E
G
0x10
ADDR. LOW
DATA LOW
DATA HIGH
XX
ADDR. LOW
DATA LOW
DATA HIGH
XX
ADDR. HIGH
H
XX
XA1/ BS2
XA0
PAGEL/ BS1
XTAL1
WR
RDY/ BSY
RESET +12V
OE
Note:
1.
“XX” is don’t care. The letters refer to the programming description above.
4.22.7.5 Programming the EEPROM
The EEPROM is organized in pages, see Table 4-74 on page 225. When programming the EEPROM, the program data is
latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for
the EEPROM data memory is as follows (refer to Section 4.22.7.4 “Programming the Flash” on page 227 for details on
command, address and data loading):
A: Load Command “0001 0001b”.
G: Load Address High Byte (0x00 - 0xFF).
B: Load Address Low Byte (0x00 - 0xFF).
C: Load Data (0x00 - 0xFF).
E: Latch data (give PAGEL a positive pulse).
K: Repeat A through E until the entire buffer is filled.
L: Program EEPROM page
1. Set BS1 to “0”.
2.
Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.
3.
Wait until to RDY/BSY goes high before programming the next page (See Figure 4-101 for signal waveforms).
Figure 4-101. Programming the EEPROM Waveforms
K
DATA
A
G
B
C
E
B
C
E
0x11
ADDR. HIGH
ADDR. LOW
DATA
XX
ADDR. LOW
DATA
XX
L
XA1/ BS2
XA0
PAGEL/ BS1
XTAL
WR
RDY/ BSY
RESET +12V
OE
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4.22.7.6 Reading the Flash
The algorithm for reading the flash memory is as follows (refer to Section 4.22.7.4 “Programming the Flash” on page 227 for
details on command and address loading):
1. A: Load Command “0000 0010b”.
2.
G: Load Address High Byte (0x00 - 0xFF).
3.
B: Load Address Low Byte (0x00 - 0xFF).
4.
Set OE to “0”, and BS1 to “0”. The flash word low byte can now be read at DATA.
5.
Set BS1 to “1”. The flash word high byte can now be read at DATA.
6.
Set OE to “1”.
4.22.7.7 Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to Section 4.22.7.4 “Programming the Flash” on page
227 for details on command and address loading):
1. A: Load Command “0000 0011 b”.
2.
G: Load Address High Byte (0x00 - 0xFF).
3.
B: Load Address Low Byte (0x00 - 0xFF).
4.
Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
5.
Set OE to “1”.
4.22.7.8 Programming the Fuse Low Bits
The algorithm for programming the fuse low bits is as follows (refer to Section 4.22.7.4 “Programming the Flash” on page
227 for details on command and data loading):
1. A: Load Command “0100 0000 b”.
2.
C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the fuse bit.
3.
Give WR a negative pulse and wait for RDY/BSY to go high.
4.22.7.9 Programming the Fuse High Bits
The algorithm for programming the fuse high bits is as follows (refer to Section 4.22.7.4 “Programming the Flash” on page
227 for details on command and data loading):
1. A: Load Command “0100 0000 b”.
2.
C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the fuse bit.
3.
Set BS1 to “1” and BS2 to “0”. This selects high data byte.
4.
Give WR a negative pulse and wait for RDY/BSY to go high.
5.
Set BS1 to “0”. This selects low data byte.
4.22.7.10 Programming the Extended Fuse Bits
The algorithm for programming the extended fuse bits is as follows (refer to Section 4.22.7.4 “Programming the Flash” on
page 227 for details on Command and Data loading):
1. A: Load Command “0100 0000 b”.
2.
230
C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3.
Set BS1 to “0” and BS2 to “1”. This selects extended data byte.
4.
Give WR a negative pulse and wait for RDY/BSY to go high.
5.
Set BS2 to “0”. This selects low data byte.
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Figure 4-102. Programming the FUSES Waveforms
Write Fuse Low Byte
DATA
A
C
0x40
DATA
XX
Write Fuse High Byte
A
C
0x40
DATA
XX
Write Extended Fuse Byte
A
C
0x40
DATA
XX
XA1/ BS2
XA0
PAGEL/ BS1
XTAL1
WR
RDY/ BSY
RESET +12V
OE
4.22.7.11 Programming the Lock Bits
The algorithm for programming the lock bits is as follows (refer to Section 4.22.7.4 “Programming the Flash” on page 227 for
details on command and data loading):
1. A: Load Command “0010 0000 b”.
2.
C: Load Data Low Byte. Bit n = “0” programs the lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to re-program the lock bits by any external programming mode.
3.
Give WR a negative pulse and wait for RDY/BSY to go high.
4.
The lock bits can only be cleared by executing chip erase.
4.22.7.12 Reading the Fuse and Lock Bits
The algorithm for reading the fuse and lock bits is as follows (refer to Section 4.22.7.4 “Programming the Flash” on page 227
for details on command loading):
1. A: Load Command “0000 0100 b”.
2.
Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the fuse low bits can now be read at DATA (“0” means
programmed).
3.
Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the fuse high bits can now be read at DATA (“0” means
programmed).
4.
Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the extended fuse bits can now be read at DATA (“0”
means programmed).
5.
Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the lock bits can now be read at DATA (“0” means
programmed).
6.
Set OE to “1”.
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Figure 4-103. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
Fuse Low Byte
0
Extended Fuse Byte
1
0
DATA
BS2
Lock Bits
0
Fuse High Byte
1
1
BS1
BS2
4.22.7.13 Reading the Signature Bytes
The algorithm for reading the signature bytes is as follows (refer to Section 4.22.7.4 “Programming the Flash” on page 227
for details on command and address loading):
1. A: Load Command “0000 1000 b”.
2.
B: Load Address Low Byte (0x00 - 0x02).
3.
Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA.
4.
Set OE to “1”.
4.22.7.14 Reading the 8MHz RC Oscillator Calibration Byte
The algorithm for reading the 8MHz RC oscillator calibration byte is as follows (refer to Section 4.22.7.4 “Programming the
Flash” on page 227 for details on command and address loading):
1. A: Load Command “0000 1000 b”.
2.
B: Load Address Low Byte, 0x00.
3.
Set OE to “0”, and BS1 to “1”. The 8MHz RC oscillator calibration byte can now be read at DATA.
4.
Set OE to “1”.
4.22.7.15 Reading the Temperature Sensor Parameter Bytes
The algorithm for reading the temperature sensor parameter bytes is as follows (refer to Section 4.22.7.4 “Programming the
Flash” on page 227 for details on command and address loading):
1. A: Load Command “0000 1000 b”.
232
2.
B: Load Address Low Byte, 0x0003 or 0x0005.
3.
Set OE to “0”, and BS1 to “1”. The temperature sensor parameter byte can now be read at DATA.
4.
Set OE to “1”.
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4.22.8 Serial Downloading
Both the flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND.
The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the programming enable
instruction needs to be executed first before program/erase operations can be executed.
Note:
In Table 4-78, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the
internal SPI interface.
Figure 4-104. Serial Programming and Verify(1)
+2.7 to +5.5V
VCC
MOSI
PA4
MISO
PA2
SCK
PA5
RESET/ PB7
GND
Note:
1.
If the device is clocked by the internal oscillator, it is no need to connect a clock source to the XTAL1 pin.
Table 4-78. Pin Mapping Serial Programming
Symbol
Pin Name
I/O
Function
MOSI
PA4
I
Serial data in
MISO
PA2
O
Serial data out
SCK
PA5
I
Serial clock
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode
ONLY) and there is no need to first execute the chip erase instruction. The chip erase operation turns the content of every
memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK)
input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck ≥ 12MHz
High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck ≥ 12MHz
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4.22.8.1 Serial Programming Algorithm
When writing serial data to the Atmel® ATtiny87/167, data is clocked on the rising edge of SCK.
When reading data from the Atmel ATtiny87/167, data is clocked on the falling edge of SCK. See Figure 4-104 and
Figure 4-105 for timing details.
To program and verify the Atmel ATtiny87/167 in the serial programming mode, the following sequence is recommended
(see four byte instruction formats in Table 4-80 on page 235):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can
not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at
least two CPU clock cycles duration after SCK has been set to “0”.
2.
Wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin
MOSI.
3.
The serial programming instructions will not work if the communication is out of synchronization. When in sync.
the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. Whether
the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new programming enable command.
4.
The flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the
5LSB of the address and data together with the load program memory page instruction. To ensure correct loading
of the page, the data low byte must be loaded before data high byte is applied for a given address. The program
memory page is stored by loading the write program memory page instruction with the 6MSB of the address. If
polling (RDY/BSY) is not used, the user must wait at least t WD_FLASH before issuing the next page (see
Table 4-79). Accessing the serial programming interface before the flash write operation completes can result in
incorrect programming.
5.
A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least t WD_EEPROM before issuing the next byte (see
Table 4-79). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 2LSB of the address and data together with the load EEPROM memory page instruction. The EEPROM
memory page is stored by loading the write EEPROM memory page instruction with the 6MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM memory page instruction
is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at
least t WD_EEPROM before issuing the next page (see Table 4-74). In a chip erased device, no 0xFF in the data file(s)
need to be programmed.
6.
Any memory location can be verified by using the read instruction which returns the content at the selected
address at serial output MISO.
7.
At the end of the programming session, RESET can be set high to commence normal operation.
8.
Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
Table 4-79. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
234
Symbol
Minimum Wait Delay
t WD_FLASH
4.5ms
t WD_EEPROM
4.0ms
t WD_ERASE
4.0ms
t WD_FUSE
4.5ms
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4.22.8.2 Serial Programming Instruction set
Table 4-80 on page 235 and Figure 4-105 on page 236 describes the Instruction set
Table 4-80. Serial Programming Instruction Set
Instruction Format
Instruction/Operation
Byte 1
Byte 2
Byte 3
Byte4
Programming enable
0xAC
0x53
0x00
0x00
Chip erase (program memory/EEPROM)
0xAC
0x80
0x00
0x00
Poll RDY/BSY
0xF0
0x00
0x00
data byte out
Load extended address byte(1)
0x4D
0x00
Extended add.
0x00
Load program memory page, high byte
0x48
add. MSB
add. LSB
high data byte in
Load program memory page, low byte
0x40
add. MSB
add. LSB
low data byte in
Load EEPROM memory page (page access)
0xC1
0x00
0000 000aa b
data byte in
Read program memory, high byte
0x28
add. MSB
add. LSB
high data byte out
Read program memory, low byte
0x20
add. MSB
add. LSB
low data byte out
Read EEPROM memory
0xA0
0x00
00aa aaaa
data byte out
Read lock bits
0x58
0x00
0x00
data byte out
Read signature byte
0x30
0x00
0000 000aa
data byte out
Read fuse bits
0x50
0x00
0x00
data byte out
Read fuse high bits
0x58
0x08
0x00
data byte out
Read extended fuse bits
0x50
0x08
0x00
data byte out
Read calibration byte
0x38
0x00
0x00
data byte out
Write program memory page
0x4C
add. MSB
add. LSB
0x00
Write EEPROM memory
0xC0
0x00
00aa aaaa b
data byte in
Write EEPROM memory page (page access)
0xC2
0x00
00aa aa00 b
0x00
Write lock bits
0xAC
0xE0
0x00
data byte in
Write fuse bits
0xAC
0xA0
0x00
data byte in
Write fuse high bits
0xAC
0xA8
0x00
data byte in
Write extended fuse bits
0xAC
Notes: 1. Not all instructions are applicable for all parts.
0xA4
0x00
data byte in
Load Instructions
Read Instructions
Write Instructions
(6)
2.
a = address
3.
Bits are programmed ‘0’, unprogrammed ‘1’.
4.
To ensure future compatibility, unused fuses and lock bits should be unprogrammed (‘1’).
5.
Refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size.
6.
Instructions accessing program memory use a word address. This address may be random within the page range.
7.
See http://www.atmel.com/avr for Application Notes regarding programming and programmers.
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If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the
next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 4-105.
Figure 4-105. Serial Programming Instruction Example
Serial Programming Instruction
Load Program Memory Page (High/Low Byte)
Load EEPROM Memory Page (page access)
Byte 1
Byte 2
Byte 3
Addr MSB
Addr LSB
Bit 15 B
Write Program Memory Page/
Write EEPROM Memory Page
Byte 1
Byte 4
0
Page Offset
Byte 2
Byte 3
Addr MSB
Addr LSB
Bit 15 B
Byte 4
0
Page Buffer
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory/
EEPROM Memory
4.22.9 Serial Programming Characteristics
Figure 4-106. Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)
MSB
LSB
SERIAL DATA OUTPUT
(MISO)
MSB
LSB
SERIAL CLOCK INPUT
(SCK)
SAMPLE
For characteristics of the SPI module, see Section 4.23.8 “SPI Timing Characteristics” on page 245.
236
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4.23
Electrical Characteristics
Note:
All characteristics contained in this data sheet are based on simulation and characterization of Atmel®
ATtiny87/167 AVR® microcontrollers manufactured in a typical process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual Automotive silicon.
4.23.1 DC Characteristics
TA = –40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Parameters
Input low voltage
Test Conditions
Min.
Typ.(1)
Max.
Unit
VCC(2)
V
Except XTAL1 and RESET pins
VIL
–0.5
0.2
XTAL1 pin - External clock
selected
VIL1
–0.5
0.1 VCC(2)
V
RESET pin
VIL2
–0.5
0.2 VCC(2)
V
–0.5
VCC(2)
V
VCC(3)
VCC + 0.5
V
RESET pin as I/O
Input high voltage
Symbol
VIL3
0.2
Except XTAL1 and RESET pins
VIH
0.7
XTAL1 pin - External clock
selected
VIH1
0.8 VCC(3)
VCC + 0.5
V
RESET pin
VIH2
0.9 VCC(3)
VCC + 0.5
V
VIH3
VCC(3)
VCC + 0.5
V
0.6
0.5
V
RESET pin as I/O
0.7
Output low voltage(4)
(Ports A, B,)
IOL = 10mA, VCC = 5V
IOL = 5mA, VCC = 3V
VOL
Output high voltage(5)
(Ports A, B)
IOH = –10mA, VCC = 5V
IOH = –5mA, VCC = 3V
VOH
Input leakage current I/O pin
VCC = 5.5V, pin low
(absolute value)
IIL
< 0.05
1
µA
Input leakage current I/O pin
VCC = 5.5V, pin high
(absolute value)
IIH
< 0.05
1
µA
60
k
Reset pull-up resistor
RRST
4.3
2.5
30
V
I/O pin pull-up resistor
Rpu
20
50
Notes: 1. “Typ.”, typical values at 25°C. Maximum values are characterized values and not test limits in production.
k
2. “Max.” means the highest value where the pin is guaranteed to be read as low.
3. “Min.” means the lowest value where the pin is guaranteed to be read as high.
4. Although each I/O port can sink more than the test conditions (10mA at VCC = 5V, 5mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
The sum of all IOL, for all ports, should not exceed 120mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test condition.
5. Although each I/O port can source more than the test conditions (10mA at VCC = 5V, 5mA at VCC = 3V) under steady
state conditions (non-transient), the following must be observed:
The sum of all IOH, for all ports, should not exceed 120mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
6. Values using methods described in Section 4.6.8 “Minimizing Power Consumption” on page 64. Power reduction is
enabled (PRR = 0xFF) and there is no I/O drive.
7. BOD disabled.
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4.23.1 DC Characteristics (Continued)
TA = –40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Parameters
Test Conditions
Power supply current(6)
Active mode
(external clock)
Power supply current(6)
Idle mode
(external clock)
Symbol
Min.
Power supply current
Power-down mode
Max.
Unit
16MHz, VCC = 5V
10
13
mA
8MHz, VCC = 5V
5.5
7.0
mA
8MHz, VCC = 3V
2.8
3.5
mA
4MHz, VCC = 3V
1.8
2.5
mA
16MHz, VCC = 5V
3.5
5.0
mA
8MHz, VCC = 5V
1.8
2.5
mA
1
1.5
mA
0.5
0.8
mA
WDT enabled, VCC = 5V
7
100
µA
WDT disabled, VCC = 5V
0.18
70
µA
WDT enabled, VCC = 3V
5
70
µA
WDT disabled, VCC = 3V
0.15
45
µA
+10
+40
mV
+50
nA
8MHz, VCC = 3V
ICC
4MHz, VCC = 3V
(7)
Typ.(1)
Analog comparator
Input offset voltage
VCC = 5V
Vin = VCC/2
VACIO
–10
Analog comparator
Input leakage current
VCC = 5V
Vin = VCC/2
IACLK
–50
170
Analog comparator propagation VCC = 2.7V
tACID
Delay common mode VCC/2
VCC = 5.0V
180
Notes: 1. “Typ.”, typical values at 25°C. Maximum values are characterized values and not test limits in production.
ns
ns
2. “Max.” means the highest value where the pin is guaranteed to be read as low.
3. “Min.” means the lowest value where the pin is guaranteed to be read as high.
4. Although each I/O port can sink more than the test conditions (10mA at VCC = 5V, 5mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
The sum of all IOL, for all ports, should not exceed 120mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test condition.
5. Although each I/O port can source more than the test conditions (10mA at VCC = 5V, 5mA at VCC = 3V) under steady
state conditions (non-transient), the following must be observed:
The sum of all IOH, for all ports, should not exceed 120mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
6. Values using methods described in Section 4.6.8 “Minimizing Power Consumption” on page 64. Power reduction is
enabled (PRR = 0xFF) and there is no I/O drive.
7. BOD disabled.
Figure 4-107. Maximum Frequency versus VCC, Atmel ATtiny87/167
Frequency
16MHz
8MHz
Safe Operating Area
Voltage
2.7V
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4.5V
5.5V
4.23.2 Clock Characteristics
4.23.2.1 Calibrated Internal RC Oscillator Accuracy
Table 4-81. Calibration and Accuracy of Internal RC Oscillator
Frequency
VCC
Temperature
Accuracy
8.0MHz
5V
25°C
±2%
Factory
Calibration
4.23.2.2 External Clock Drive Waveforms
Figure 4-108. External Clock Drive Waveforms
tCHCX
tCLCH
tCHCX
tCHCL
VIH1
VIL1
tCLCX
tCLCL
4.23.2.3 External Clock Drive
Table 4-82. External Clock Drive
Parameter
Symbol
Oscillator frequency
VCC = 2.7 to 5.5V
VCC = 4.5 to 5.5V
Min.
Max.
Min.
Max.
Unit
8
0
16
MHz
1/tCLCL
0
Clock period
tCLCL
125
62.5
ns
High time
tCHCX
50
25
ns
Low time
tCLCX
50
25
ns
Rise time
tCLCH
1.6
0.5
ms
Fall time
tCHCL
1.6
0.5
ms
2
2
%
Change in period from one clock cycle to the next
tCLCL
4.23.3 RESET Characteristics
Table 4-83. External Reset Characteristics
Parameter
Condition
Symbol
Min
RESET pin threshold voltage
VCC = 5V
VRST
0.1 VCC
Minimum pulse width on RESET Pin
VCC = 5V
tRST
Bandgap reference voltage
VCC = 2.7V, TA = 25°C
VBG
Max
Unit
0.9 VCC
V
2.5
µs
1.1
1.2
V
Bandgap reference start-up time
VCC = 2.7V, TA = 25°C
Bandgap reference current
consumption
tBG
40
70
µs
VCC = 2.7V, TA = 25°C
IBG
15
1.0
Typ
µA
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Table 4-84. Power On Reset Characteristics
Parameter
Symbol
Power-on reset threshold voltage (rising)
Min
VPOT
(1)
Power-on reset threshold voltage (falling)
VCC maximum start voltage to ensure internal power-on reset
signal
VPORMAX
VCC minimum start voltage to ensure internal power-on reset
signal
VPORMIN
–0.1
VCCRR
0.01
VCC rise rate to ensure power-on reset
Typ
Max
Unit
1.0
1.4
V
0.9
1.3
V
0.4
V
V
V/ms
RESET pin threshold voltage
VRST
0.1 VCC
Note:
1. Before rising, the supply has to be between VPORMIN and VPORMAX to ensure a reset.
0.9 VCC
V
Table 4-85. BODLEVEL Fuse Coding
BODLEVEL 2:0 Fuses
Min. VBOT(1)
Typ. VBOT
1 1 1b
Max. VBOT
Unit
BOD Disabled
1 1 0b
1.7
1.8
2.0
1 0 1b
2.5
2.7
2.9
1 0 0b
4.1
4.3
4.5
0 1 1b
V
0 1 0b
Reserved
0 0 1b
Note:
1.
0 0 0b
VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case,
the device is tested down to VCC = VBOT during the production test. This guarantees that a brown-out reset will
occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.
The test is performed using BODLEVEL = 101 for low operating voltage and BODLEVEL = 100 for high operating voltage.
Table 4-86. Brown-out Characteristics
Parameter
Symbol
Brown-out detector hysteresis
Min pulse width on brown-out reset
Min.
Typ.
Max.
Unit
VHYST
80
mV
tBOD
2
µs
4.23.4 Internal Voltage Characteristics
Table 4-87. Internal Voltage Reference Characteristics
Parameter
Condition
Symbol
Min.
Typ.
Max.
Unit
Bandgap reference voltage
VCC = 4.5
TA = 25°C
VBG
1.0
1.1
1.2
V
Bandgap reference start-up time
VCC = 4.5
TA = 25°C
tBG
40
70
µs
Bandgap reference current consumption
VCC = 4.5
TA = 25°C
IBG
10
240
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µA
4.23.5 Current Source Characteristics
Table 4-88. Current Source Characteristics
Parameter
Condition
Symbol
Min.
Current
VCC = 2.7 V / 5.5 V
T = -40°C / +125°C
IISRC
94
Current source start-up time
VCC = 4.5
TA = 25°C
tISRC
Typ.
Max.
Unit
106
µA
60
µs
4.23.6 ADC Characteristics
Table 4-89. ADC Characteristics, Single Ended Channels (-40°C/+125°C)
Parameter
Condition
Resolution
Single ended conversion
Absolute accuracy
VCC = 4V, VREF = 4V,
ADC clock = 200kHz
TUE
2.0
3.5
LSB
Integral Non Linearity
VCC = 4V, VREF = 4V,
ADC clock = 200kHz
INL
0.6
2.0
LSB
Differential Non Linearity
VCC = 4V, VREF = 4V,
ADC clock = 200kHz
DNL
0.3
0.8
LSB
Gain error
VCC = 4V, VREF = 4V,
ADC clock = 200kHz
–6.0
–2.5
2.0
LSB
Offset error
VCC = 4V, VREF = 4V,
ADC clock = 200kHz
–3.5
1.5
3.5
LSB
AVCC
V
Ref voltage
Symbol
Min
Typ
Max
10
VREF
2.56
Input bandwidth
Bits
38.5
2.4
2.56
Unit
kHz
Internal voltage
VINT
Reference input resistance
RREF
32
2.7
k
V
Analog input resistance
RAIN
100
M
Table 4-90. ADC Characteristics, Differential Channels (–40°C/+125°C)
Parameter
Condition
Resolution
Differential conversion
Absolute accuracy
Symbol
Min
Typ
Max
8
Gain = 8x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
1.0
3.0
Gain = 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
1.5
3.5
Gain = 8x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Unit
TUE
LSB
2.0
4.5
2.0
6.0
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Table 4-90. ADC Characteristics, Differential Channels (–40°C/+125°C) (Continued)
Parameter
Integral Non Linearity
Differential Non Linearity
Condition
Typ
Max
Gain = 8x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
0.2
1.0
Gain = 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
0.4
1.5
Gain = 8x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Symbol
Min
INL
LSB
0.5
2.0
Gain = 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
1.6
5.0
Gain = 8x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
0.3
0.8
Gain = 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
0.3
0.8
Gain = 8x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
DNL
LSB
Gain = 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain error
Offset error
0.6
1.6
1.0
3.0
Gain = 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
–4.0
1.5
4.0
Gain = 8x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
–5.0
–2.5
0.0
Gain = 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
–4.0
–0.5
4.0
Gain = 8x or 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
–2.0
0.5
2.0
Gain = 8x or 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
–2.0
Analog supply voltage
Differential conversion
LSB
LSB
0.5
2.0
VREF
2.56
AVCC – 0.5
V
VDIFF
–VREF/Gain
+VREF/Gain
V
AVCC
VCC – 0.3
VCC + 0.3
V
0
AVCC
V
–511
+511
LSB
VIN
ADC conversion output
Input bandwidth
0.8
–3.0
Input differential voltage
Input voltage
0.4
Gain = 8x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Reference voltage
Unit
Differential conversion
4
VINT
Reference input resistance
RREF
32
k
Analog input resistance
RAIN
100
M
242
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
2.4
2.56
kHz
Internal voltage reference
2.7
V
4.23.7 Parallel Programming Characteristics
Figure 4-109. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
XTAL1
tXHXL
tDVXH
tXLDX
tBVPH
tPLBX
Data and Control
(DATA, XA0,
XA1/ BS2,
PAGEL/ BS1)
tWLBX
tBVWL
tWLWH
WR
tPLWL
tRLRH
RDY/ BSY
tWLRH
Figure 4-110. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
Load Address
(Low Byte)
Load Data
(Low Byte)
Load Data
(High Byte)
Load Address
(Low Byte)
tXLXH
XTAL1
PAGEL/ BS1
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1/ BS2
Note:
1.
The timing requirements shown in Figure 4-109 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
ATA6616C/ATA6617C [DATASHEET]
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243
Figure 4-111. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing
Requirements(1)
Load Address
(Low Byte)
Load Data
(Low Byte)
Read Data
(High Byte)
Load Address
(Low Byte)
tXLOL
XTAL1
tBVDV
PAGEL/ BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1/ BS2
Note:
1.
The timing requirements shown in Figure 4-109 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
Table 4-91. Parallel Programming Characteristics, VCC = 5V ±10%
Parameter
Programming enable voltage
Programming enable current
Symbol
Min
VPP
11.5
Typ
IPP
Max
Unit
12.5
V
250
µA
Data and control valid before XTAL1 high
tDVXH
67
ns
XTAL1 low to XTAL1 high
tXLXH
200
ns
XTAL1 pulse width high
tXHXL
150
ns
Data and control hold after XTAL1 low
tXLDX
67
ns
XTAL1 low to WR low
tXLWL
0
ns
BS1 valid before PAGEL high
tBVPH
67
ns
BS1 hold after PAGEL low
tPLBX
67
ns
BS2/1 hold after WR low
tWLBX
67
ns
PAGEL low to WR low
tPLWL
67
ns
BS1 valid to WR low
tBVWL
67
ns
WR pulse width low
tWLWH
150
ns
WR low to RDY/BSY low
tWLRL
0
1
µs
WR low to RDY/BSY high(1)
tWLRH
3.7
4.5
ms
tWLRH_CE
7.5
9
ms
XTAL1 low to OE low
tXLOL
0
BS1 valid to DATA valid
tBVDV
0
OE low to DATA valid
tOLDV
WR low to RDY/BSY high for chip erase(2)
OE high to DATA Tri-stated
tOHDZ
Notes: 1. tWLRH is valid for the write flash, write EEPROM, write fuse bits and write lock bits commands.
2.
244
tWLRH_CE is valid for the chip erase command.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
ns
250
ns
250
ns
250
ns
4.23.8 SPI Timing Characteristics
See Figure 4-112 and Figure 4-113 for details.
Table 4-92. SPI Timing Parameters
No.
Description
Mode
1
SCK period
Master
See Table 4-43
2
SCK high/low
Master
50% duty cycle
3
Rise/fall time
Master
3.6
4
Setup
Master
10
5
Hold
Master
10
6
Out to SCK
Master
0.5 • tsck
7
SCK to out
Master
10
8
SCK to out high
Master
10
9
SS low to out
Slave
15
10
SCK period
Slave
4 tck
Slave
2 tck
11
SCK high/low
(1)
Min.
Max.
Rise/Fall time
Slave
13
Setup
Slave
10
14
Hold
Slave
tck
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
Unit
ns
1.6
12
18
Note:
Typ.
15
µs
ns
20
10
SS low to SCK
Slave
2 tck
In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12MHz
- 3 tCLCL for fCK >12MHz
Figure 4-112. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
4
MISO
(Data Input)
5
3
...
MSB
LSB
8
7
MOSI
(Data Output)
MSB
...
LSB
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
245
Figure 4-113. SPI Interface Timing Requirements (Slave Mode)
18
SS
16
10
9
SCK
(CPOL = 0)
11
11
SCK
(CPOL = 1)
13
MOSI
(Data Input)
14
12
...
MSB
LSB
17
15
MISO
(Data Output)
4.24
...
MSB
LSB
Decoupling Capacitors
The operating frequency (i.e. system clock) of the processor determines in 95% of cases the value needed for
microcontroller decoupling capacitors.
The hypotheses used as first evaluation for decoupling capacitors are:
● The operating frequency (fop) supplies itself the maximum peak levels of noise. The main peaks are located at fop and
2 fop.
●
An SMC capacitor connected to 2 micro-vias on a PCB has the following characteristics:
●
1.5 nH from the connection of the capacitor to the PCB,
●
1.5 nH from the capacitor intrinsic inductance.
Figure 4-114. Capacitor Description
1.5nH
0.75nH
Capacitor
0.75nH
PCB
According to the operating frequency of the product, the decoupling capacitances are chosen considering the frequencies to
filter, fop and 2 fop.
The relation between frequencies to cut and decoupling characteristics are defined by:
1
1
and
fop = --------------------2 fop = --------------------2 LC 1
2 LC 2
where:
●
●
246
L: the inductance equivalent to the global inductance on the VCC/GND lines.
C1 & C2: decoupling capacitors (C1 = 4 C2).
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Then, in normalized value range, the decoupling capacitors become:
Table 4-93. Decoupling Capacitors versus Frequency
fop, Operating Frequency
C1
C2
16MHz
33nF
10nF
12MHz
56nF
15nF
10MHz
82nF
22nF
8MHz
120nF
33nF
6MHz
220nF
56nF
4MHz
560nF
120nF
These decoupling capacitors must to be implemented as close as possible to each pair of power supply pins:
● 16-17 for logic sub-system,
●
5-6 for analogical sub-system.
Nevertheless, a bulk capacitor of 10-47µF is also needed on the power distribution network of the PCB, near the power
source.
For further information, please refer to Application Notes AVR040 “EMC Design Considerations” and AVR042 “Hardware
Design Considerations” on the Atmel web site.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
247
4.25
Typical Characteristics
The data contained in this section is largely based on simulations and characterization of similar devices in the same
process and design methods. Thus, the data should be treated as indications of how the part will behave.
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption
measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator
with rail-to-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins,
switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and
frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL VCC f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.
The difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with
watchdog timer disabled represents the differential current drawn by the watchdog timer.
4.25.1 Active Supply Current
Figure 4-115. Active Supply Current versus Low Frequency (0.1 - 1.0MHz)
1.4
6.0
1.2
5.5
1.0
5.0
ICC (mA)
4.5
0.8
4.0
3.6
0.6
3.3
0.4
3.0
2.7
0.2
2.4
2.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
2.0
1.8
1.6
Figure 4-116. Active Supply Current versus Frequency (≥ 1MHz)
16
14
ICC (mA)
12
6.0
5.5
10
5.0
8
4.5
6
4.5
3.6
4
3.3
2
3.0
2.7
0
0
2
4
6
8
10
12
Frequency (MHz)
248
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
14
16
18
20
2.4
Figure 4-117. Active Supply Current versus VCC (Internal RC Oscillator, 8MHz)
9
8
ICC (mA)
7
6
150
5
125
85
4
25
3
-40
2
1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 4-118. Active Supply Current versus VCC (Internal RC Oscillator, 128kHz)
0.20
0.18
ICC (mA)
0.16
0.14
150
0.12
125
0.10
85
25
0.08
-40
0.06
0.04
0.02
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
4.25.2 Idle Supply Current
Figure 4-119. Idle Supply Current versus Frequency (≥ 1MHz)
10
9
8
6.0
ICC (mA)
7
5.5
6
5.0
5
4.5
4
4.0
3
3.6
2
3.3
1
3.0
2.7
0
0
2
4
6
8
10
12
14
16
18
20
2.4
Frequency (MHz)
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
249
Figure 4-120. Idle Supply Current versus VCC (Internal RC Oscillator, 8MHz)
3
2.5
150
ICC (mA)
2
125
1.5
85
1
-40
25
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 4-121. Idle Supply Current versus 5VCC (Internal RC Oscillator, 128kHz)
0.08
0.07
ICC (mA)
0.06
150
0.05
125
0.04
85
25
0.03
-40
0.02
0.01
0
1.5
2
2.5
3
3.5
VCC (V)
250
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
4
4.5
5
5.5
4.25.3 Supply Current of I/O Modules
The table below can be used to calculate the additional current consumption for the different I/O modules idle mode. The
enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See Section 4.6.9.3 “PRR – Power
Reduction Register” on page 66 for details.
Table 4-94. Additional Current Consumption for the Different I/O Modules (Absolute Values)
VCC = 5.0V
Freq. = 16MHz
VCC = 5.0V
Freq. = 8MHz
VCC = 3.0V
Freq. = 8MHz
VCC = 3.0V
Freq. = 4MHz
Unit
LIN/UART
0.77
0.37
0.20
0.10
mA
SPI
0.31
0.14
0.08
0.04
mA
TIMER-1
0.28
0.13
0.08
0.04
mA
TIMER-0
0.41
0.20
0.10
0.05
mA
USI
0.14
0.05
0.04
0.02
mA
ADC
0.48
0.22
0.10
0.05
mA
Module
4.25.4 Power-down Supply Current
Figure 4-122. Power-down Supply Current versus VCC (Watchdog Timer Disabled)
30
25
150
ICC (µA)
20
125
15
85
10
-40
25
5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 4-123. Power-down Supply Current versus VCC (Watchdog Timer Enabled)
40
35
ICC (µA)
30
150
25
125
20
85
25
15
-40
10
5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
251
4.25.5 Pin Pull-up
Figure 4-124. I/O Pin Pull-up Resistor Current versus Input Voltage (VCC = 2.7V)
90
80
70
IOP (µA)
60
150
50
125
40
85
30
25
20
-40
10
0
0
0.5
1
1.5
2
2.5
3
-10
VOP (V)
Figure 4-125. I/O Pin pull-up Resistor Current versus Input Voltage (VCC = 5V)
160
140
120
150
80
125
IOP (µA)
100
85
60
25
40
-40
20
0
0
1
2
3
4
5
6
-20
VOP (V)
Figure 4-126. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 2.7V)
70
60
IRESET (µA)
50
150
40
125
85
30
25
20
-40
10
0
0
0.5
1
1.5
-10
VRESET (V)
252
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
2
2.5
3
Figure 4-127. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 5V)
120
100
IRESET (µA)
80
150
125
60
85
25
40
-40
20
0
0
1
2
3
4
5
6
-20
VRESET (V)
4.25.6 Pin Driver Strength
Figure 4-128. I/O Pin Output Voltage versus Sink Current (VCC = 3V)
2.0
1.8
1.6
150
VOL (V)
1.4
125
1.2
85
1.0
25
0.8
-40
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
IOL (mA)
Figure 4-129. I/O Pin Output Voltage versus Sink Current (VCC = 5V)
1.2
1.0
150
VOL (V)
0.8
125
85
0.6
25
-40
0.4
0.2
0
0
5
10
15
20
25
IOL (mA)
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
253
Figure 4-130. I/O Pin Output Voltage versus Source Current (VCC = 3V)
3.0
2.5
150
125
VOH (V)
2.0
85
25
1.5
-40
1.0
0.5
0
0
2
4
6
8
10
12
14
16
18
20
IOH (mA)
Figure 4-131. I/O Pin Output Voltage versus Source Current (VCC = 5V)
5.1
4.9
150
VOH (V)
4.7
125
85
4.5
25
4.3
-40
4.1
3.9
3.7
0
2
4
6
8
10
12
14
IOH (mA)
4.25.7 Internal Oscillator Speed
Figure 4-132. Calibrated 8.0MHz RC Oscillator Frequency versus VCC
254
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
16
18
20
Figure 4-133. Calibrated 8.0MHz RC Oscillator Frequency versus OSCCAL Value
4.25.8 Current Consumption in Reset
Figure 4-134. Reset Supply Current versus VCC, Frequencies 0.1 - 1.0MHz
(Excluding Current Through the Reset Pull-up)
0.30
6.0
0.25
5.5
5.0
ICC (mA)
0.20
4.5
4.0
0.15
3.6
3.3
0.10
3.0
0.05
2.7
2.4
0
2.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (MHz)
0.7
0.8
0.9
1
2.0
1.8
1.6
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
255
Figure 4-135. Reset Supply Current versus VCC, Frequencies ≥ 1MHz
(Excluding Current Through the Reset Pull-up)
4.5
4.0
6.0
3.5
5.5
5.0
ICC (mA)
3.0
4.5
2.5
4.0
2.0
3.6
1.5
3.3
1.0
3.0
2.7
0.5
2.4
0
2.1
0
2
4
6
8
10
12
14
16
18
20
2.0
Frequency (MHz)
1.8
1.6
4.26
Register Summary
Address
Name
(0xFF)
Reserved
(0xFE)
Reserved
(0xFD)
Reserved
(0xFC)
Reserved
(0xFB)
Reserved
(0xFA)
Reserved
(0xF9)
Reserved
(0xF8)
Reserved
(0xF7)
Reserved
(0xF6)
Reserved
(0xF5)
Reserved
(0xF4)
Reserved
(0xF3)
Reserved
(0xF2)
Reserved
(0xF1)
Reserved
(0xF0)
Reserved
(0xEF)
Reserved
(0xEE)
Reserved
Notes:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
1. Address bits exceeding EEAMSB (Table 4-74 on page 225) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
3. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR®s, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel®
ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
256
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
4.26
Register Summary (Continued)
Address
Name
(0xED)
Reserved
(0xEC)
Reserved
(0xEB)
Reserved
(0xEA)
Reserved
(0xE9)
Reserved
(0xE8)
Reserved
(0xE7)
Reserved
(0xE6)
Reserved
(0xE5)
Reserved
(0xE4)
Reserved
(0xE3)
Reserved
(0xE2)
Reserved
(0xE1)
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xE0)
Reserved
(0xDF)
Reserved
(0xDE)
Reserved
(0xDD)
Reserved
(0xDC)
Reserved
(0xDB)
Reserved
(0xDA)
Reserved
(0xD9)
Reserved
(0xD8)
Reserved
(0xD7)
Reserved
(0xD6)
Reserved
(0xD5)
Reserved
(0xD4)
Reserved
(0xD3)
Reserved
(0xD2)
LINDAT
LDATA7
LDATA6
LDATA5
LDATA4
LDATA3
LDATA2
LDATA1
LDATA0
187
(0xD1)
LINSEL
–
–
–
–
/ LAINC
LINDX2
LINDX1
LINDX0
187
(0xD0)
LINIDR
LP1
LP0
LID3
LID2
LID1
LID0
186
(0xCF)
LINDLR
LTXDL3
LTXDL2
LID5/LDL1 LID4/LDL0
LTXDL1
LTXDL0
LRXDL3
LRXDL2
LRXDL1
LRXDL0
186
(0xCE)
LINBRRH
–
–
–
–
LDIV11
LDIV10
LDIV9
LDIV8
185
(0xCD)
LINBRRL
LDIV7
LDIV6
LDIV5
LDIV4
LDIV3
LDIV2
LDIV1
LDIV0
185
185
(0xCC)
LINBTR
LDISR
–
LBT5
LBT4
LBT3
LBT2
LBT1
LBT0
(0xCB)
LINERR
LABORT
LTOERR
LOVERR
LFERR
LSERR
LPERR
LCERR
LBERR
184
(0xCA)
LINENIR
–
–
–
–
LENERR
LENIDOK
LENTXOK
LENRXOK
184
Notes:
1. Address bits exceeding EEAMSB (Table 4-74 on page 225) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
3. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR®s, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel®
ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
257
4.26
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xC9)
LINSIR
LIDST2
LIDST1
LIDST0
LBUSY
LERR
LIDOK
LTXOK
LRXOK
183
(0xC8)
LINCR
LSWRES
LIN13
LCONF1
LCONF0
LENA
LCMD2
LCMD1
LCMD0
182
(0xC7)
Reserved
(0xC6)
Reserved
(0xC5)
Reserved
(0xC4)
Reserved
(0xC3)
Reserved
(0xC2)
Reserved
(0xC1)
Reserved
(0xC0)
Reserved
(0xBF)
Reserved
(0xBE)
Reserved
(0xBD)
Reserved
(0xBC)
USIPP
USIPOS
165
(0xBB)
USIBR
USIB7
USIB6
USIB5
USIB4
USIB3
USIB2
USIB1
USIB0
161
(0xBA)
USIDR
USID7
USID6
USID5
USID4
USID3
USID2
USID1
USID0
161
(0xB9)
USISR
USISIF
USIOIF
USIPF
USIDC
USICNT3
USICNT2
USICNT1
USICNT0
162
(0xB8)
USICR
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
163
(0xB7)
Reserved
–
EXCLK
AS0
TCN0UB
OCR0AUB
–
TCR0AUB
TCR0BUB
116
(0xB6)
ASSR
(0xB5)
Reserved
(0xB4)
Reserved
(0xB3)
Reserved
(0xB2)
Reserved
(0xB1)
Reserved
(0xB0)
Reserved
(0xAF)
Reserved
(0xAE)
Reserved
(0xAD)
Reserved
(0xAC)
Reserved
(0xAB)
Reserved
(0xAA)
Reserved
(0xA9)
Reserved
(0xA8)
Reserved
(0xA7)
Reserved
(0xA6)
Reserved
Notes:
1. Address bits exceeding EEAMSB (Table 4-74 on page 225) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
3. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR®s, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel®
ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
258
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
4.26
Register Summary (Continued)
Address
Name
(0xA5)
Reserved
(0xA4)
Reserved
(0xA3)
Reserved
(0xA2)
Reserved
(0xA1)
Reserved
(0xA0)
Reserved
(0x9F)
Reserved
(0x9E)
Reserved
(0x9D)
Reserved
(0x9C)
Reserved
(0x9B)
Reserved
(0x9A)
Reserved
(0x99)
Reserved
(0x98)
Reserved
(0x97)
Reserved
(0x96)
Reserved
(0x95)
Reserved
(0x94)
Reserved
(0x93)
Reserved
(0x92)
Reserved
(0x91)
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x90)
Reserved
(0x8F)
Reserved
(0x8E)
Reserved
(0x8D)
Reserved
(0x8C)
Reserved
(0x8B)
OCR1BH
OCR1B15 OCR1B14
OCR1B13
OCR1B12
OCR1B11
OCR1B10
OCR1B9
OCR1B8
145
(0x8A)
OCR1BL
OCR1B7
OCR1B6
OCR1B5
OCR1B4
OCR1B3
OCR1B2
OCR1B1
OCR1B0
145
(0x89)
OCR1AH
OCR1A15 OCR1A14
OCR1A13
OCR1A12
OCR1A11
OCR1A10
OCR1A9
OCR1A8
145
(0x88)
OCR1AL
OCR1A7
OCR1A6
OCR1A5
OCR1A4
OCR1A3
OCR1A2
OCR1A1
OCR1A0
145
(0x87)
ICR1H
ICR115
ICR114
ICR113
ICR112
ICR111
ICR110
ICR19
ICR18
145
(0x86)
ICR1L
ICR17
ICR16
ICR15
ICR14
ICR13
ICR12
ICR11
ICR10
145
(0x85)
TCNT1H
TCNT115
TCNT114
TCNT113
TCNT112
TCNT111
TCNT110
TCNT19
TCNT18
144
(0x84)
TCNT1L
TCNT17
TCNT16
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
144
(0x83)
TCCR1D
OC1BX
OC1BW
OC1BV
OC1BU
OC1AX
OC1AW
OC1AV
OC1AU
144
(0x82)
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
144
Notes:
1. Address bits exceeding EEAMSB (Table 4-74 on page 225) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
3. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR®s, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel®
ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
259
4.26
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x81)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
143
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
141
(0x7F)
DIDR1
–
–
–
–
–
ADC10D
ADC9D
ADC8D
207
(0x7E)
DIDR0
ADC7D /
AIN1D
ADC6D /
AIN0D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
207,
211
(0x7D)
Reserved
(0x7C)
ADMUX
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
203
(0x7B)
ADCSRB
BIN
ACME
ACIR1
ACIR0
–
ADTS2
ADTS1
ADTS0
206,
210
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
205
ADC8 /
ADC2
206
(0x79)
ADCH
- / ADC9
- / ADC8
- / ADC7
- / ADC6
- / ADC5
- / ADC4
ADC9 /
ADC3
(0x78)
ADCL
ADC7 /
ADC1
ADC6 /
ADC0
ADC5 / -
ADC4 / -
ADC3 / -
ADC2 / -
ADC1 / -
ADC0 / -
206
(0x77)
AMISCR
–
–
–
–
–
AREFEN
XREFEN
ISRCEN
190
(0x76)
Reserved
(0x75)
Reserved
(0x74)
Reserved
(0x73)
Reserved
(0x72)
Reserved
(0x71)
Reserved
(0x70)
Reserved
(0x6F)
TIMSK1
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
145
(0x6E)
TIMSK0
–
–
–
–
–
–
OCIE0A
TOIE0
117
(0x6D)
Reserved
(0x6C)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
82
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
82
(0x6A)
Reserved
(0x69)
EICRA
–
–
–
–
ISC11
ISC10
ISC01
ISC00
80
(0x68)
PCICR
–
–
–
–
–
–
PCIE1
PCIE0
81
(0x67)
Reserved
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
58
(0x66)
OSCCAL
(0x65)
Reserved
(0x64)
PRR
–
–
PRLIN
PRSPI
PRTIM1
PRTIM0
PRUSI
PRADC
66
(0x63)
CLKSELR
–
COUT
CSUT1
CSUT0
CSEL3
CSEL2
CSEL1
CSEL0
61
(0x62)
CLKCSR
CLKCCE
–
–
CLKRDY
CLKC3
CLKC2
CLKC1
CLKC0
59
(0x61)
CLKPR
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
59
Notes:
1. Address bits exceeding EEAMSB (Table 4-74 on page 225) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
3. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR®s, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel®
ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
260
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
4.26
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x60)
WDTCR
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
74
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
32
0x3E (0x5E)
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
32
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
32
0x3C (0x5C)
Reserved
0x3B (0x5B)
Reserved
0x3A (0x5A)
Reserved
0x39 (0x59)
Reserved
0x38 (0x58)
Reserved
217
0x37 (0x57)
SPMCSR
–
RWWSB
SIGRD
CTPB
RFLB
PGWRT
PGERS
SPMEN
0x36 (0x56)
Reserved
–
–
–
–
–
–
–
–
0x35 (0x55)
MCUCR
–
BODS
BODSE
PUD
–
–
–
–
65, 90
0x34 (0x54)
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
70
–
–
–
–
–
SM1
SM0
SE
65
0x33 (0x53)
SMCR
0x32 (0x52)
Reserved
0x31 (0x51)
DWDR
DWDR7
DWDR6
DWDR5
DWDR4
DWDR3
DWDR2
DWDR1
DWDR0
214
0x30 (0x50)
ACSR
ACD
ACIRS
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
210
0x2F (0x4F)
Reserved
0x2E (0x4E)
SPDR
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
153
0x2D (0x4D)
SPSR
SPIF
WCOL
–
–
–
–
–
SPI2X
153
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
151
0x2B (0x4B)
GPIOR2
GPIOR27
GPIOR26
GPIOR25
GPIOR24
GPIOR23
GPIOR22
GPIOR21
GPIOR20
45
0x2A (0x4A)
GPIOR1
GPIOR17
GPIOR16
GPIOR15
GPIOR14
GPIOR13
GPIOR12
GPIOR11
GPIOR10
45
0x29 (0x49)
Reserved
0x28 (0x48)
OCR0A
OCR0A7
OCR0A6
OCR0A5
OCR0A4
OCR0A3
OCR0A2
OCR0A1
OCR0A0
116
0x27 (0x47)
TCNT0
TCNT07
TCNT06
TCNT05
TCNT04
TCNT03
TCNT02
TCNT01
TCNT00
115
0x26 (0x46)
TCCR0B
FOC0A
–
–
–
–
CS02
CS01
CS00
115
0x25 (0x45)
TCCR0A
COM0A1
COM0A0
–
–
–
–
WGM01
WGM00
113
0x24 (0x44)
Reserved
0x23 (0x43)
GTCCR
TSM
–
–
–
–
–
PSR0
PSR1
118, 119
0x22 (0x42)
EEARH(1)
–
–
–
–
–
–
–
EEAR8
43
0x21 (0x41)
EEARL
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
43
0x20 (0x40)
EEDR
EEDR7
EEDR6
EEDR5
EEDR4
EEDR3
EEDR2
EEDR1
EEDR0
44
44
0x1F (0x3F)
EECR
–
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
0x1E (0x3E)
GPIOR0
GPIOR07
GPIOR06
GPIOR05
GPIOR04
GPIOR03
GPIOR02
GPIOR01
GPIOR00
45
0x1D (0x3D)
EIMSK
–
–
–
–
–
–
INT1
INT0
80
Notes:
1. Address bits exceeding EEAMSB (Table 4-74 on page 225) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
3. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR®s, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel®
ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
261
4.26
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1C (0x3C)
EIFR
–
–
–
–
–
–
INTF1
INTF0
81
0x1B (0x3B)
PCIFR
–
–
–
–
–
–
PCIF1
PCIF0
82
0x1A (0x3A)
Reserved
0x19 (0x39)
Reserved
0x18 (0x38)
Reserved
0x17 (0x37)
Reserved
0x16 (0x36)
TIFR1
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
117
0x15 (0x35)
TIFR0
–
–
–
–
–
–
OCF0A
TOV0
117
0x14 (0x34)
Reserved
0x13 (0x33)
Reserved
–
–
BBMB
BBMA
–
–
PUDB
PUDA
91
0x12 (0x32)
PORTCR
0x11 (0x31)
Reserved
0x10 (0x30)
Reserved
0x0F (0x2F)
Reserved
0x0E (0x2E)
Reserved
0x0D (0x2D)
Reserved
0x0C (0x2C)
Reserved
0x0B (0x2B)
Reserved
0x0A (0x2A)
Reserved
0x09 (0x29)
Reserved
0x08 (0x28)
Reserved
0x07 (0x27)
Reserved
0x06 (0x26)
Reserved
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
101
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
101
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
101
0x02 (0x22)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
101
0x01 (0x21)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
101
0x00 (0x20)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
101
Notes:
1. Address bits exceeding EEAMSB (Table 4-74 on page 225) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
3. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR®s, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel®
ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
262
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
4.27
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
Rd, Rr
Add two registers
Rd Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with carry two registers
Rd Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl, K
Add immediate to word
Rdh:Rdl Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two registers
Rd Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract constant from register
Rd Rd – K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with carry two registers
Rd Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with carry constant from register
Rd Rd – K – C
Z,C,N,V,H
1
SBIW
Rdl, K
Subtract immediate from word
Rdh:Rdl Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND registers
Rd Rd Rr
Z,N,V
1
ANDI
Rd, K
Logical AND register and constant
Rd Rd K
Z,N,V
1
OR
Rd, Rr
Logical OR registers
Rd Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR register and constant
Rd Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR registers
Rd Rd Rr
Z,N,V
1
COM
Rd
One’s complement
Rd 0xFF Rd
Z,C,N,V
1
NEG
Rd
Two’s complement
Rd 0x00 Rd
Z,C,N,V,H
1
SBR
Rd, K
Set Bit(s) in register
Rd Rd v K
Z,N,V
1
CBR
Rd, K
Clear Bit(s) in register
Rd Rd (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd Rd – 1
Z,N,V
1
TST
Rd
Test for zero or minus
Rd Rd Rd
Z,N,V
1
CLR
Rd
Clear register
Rd Rd Rd
Z,N,V
1
SER
Rd
Set register
Rd 0xFF
None
1
k
Relative jump
PC PC + k + 1
None
2
Branch Instructions
RJMP
Indirect jump to (Z)
PC Z
None
2
JMP
k
Direct jump
PC k
None
3
RCALL
k
Relative subroutine call
PC PC + k + 1
None
3
Indirect call to (Z)
PC Z
None
3
Direct subroutine call
PC k
None
4
Subroutine return
PC STACK
None
4
IJMP
ICALL
CALL
k
RET
RETI
CPSE
Rd, Rr
Interrupt return
PC STACK
I
4
Compare, skip if equal
if (Rd = Rr) PC PC + 2 or 3
None
1/2/3
CP
Rd, Rr
Compare
Rd – Rr
Z, N,V,C,H
1
CPC
Rd, Rr
Compare with carry
Rd – Rr – C
Z, N,V,C,H
1
CPI
Rd, K
Compare register with immediate
Rd K
Z, N,V,C,H
1
SBRC
Rr, b
Skip if Bit in register cleared
if (Rr(b)=0) PC PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in register is set
if (Rr(b)=1) PC PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O register is set
if (P(b)=1) PC PC + 2 or 3
None
1/2/3
None
1/2
BRBS
s, k
Branch if status flag set
if (SREG(s) = 1) then PC
PC + k + 1
BRBC
s, k
Branch if status flag cleared
if (SREG(s) = 0) then PC
PC + k + 1
None
1/2
BREQ
k
Branch if equal
if (Z = 1) then PC PC + k + 1
None
1/2
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
263
4.27
Instruction Set Summary (Continued)
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRNE
k
BRCS
k
Branch if not equal
if (Z = 0) then PC PC + k + 1
None
1/2
Branch if carry set
if (C = 1) then PC PC + k + 1
None
1/2
BRCC
BRSH
k
Branch if carry cleared
if (C = 0) then PC PC + k + 1
None
1/2
k
Branch if same or higher
if (C = 0) then PC PC + k + 1
None
1/2
BRLO
BRMI
k
Branch if lower
if (C = 1) then PC PC + k + 1
None
1/2
k
Branch if minus
if (N = 1) then PC PC + k + 1
None
1/2
BRPL
k
Branch if plus
if (N = 0) then PC PC + k + 1
None
1/2
BRGE
k
Branch if greater or equal, signed
if (N V= 0) then PC PC + k + 1
None
1/2
BRLT
k
Branch if less than zero, signed
if (N V= 1) then PC PC + k + 1
None
1/2
BRHS
k
Branch if half carry flag set
if (H = 1) then PC PC + k + 1
None
1/2
BRHC
k
Branch if half carry flag cleared
if (H = 0) then PC PC + k + 1
None
1/2
BRTS
k
Branch if T flag set
if (T = 1) then PC PC + k + 1
None
1/2
BRTC
k
Branch if T flag cleared
if (T = 0) then PC PC + k + 1
None
1/2
BRVS
k
Branch if overflow flag is set
if (V = 1) then PC PC + k + 1
None
1/2
BRVC
k
Branch if overflow flag is cleared
if (V = 0) then PC PC + k + 1
None
1/2
BRIE
k
Branch if interrupt enabled
if (I = 1) then PC PC + k + 1
None
1/2
BRID
k
Branch if interrupt disabled
if (I = 0) then PC PC + k + 1
None
1/2
Bit and Bit-test Instructions
SBI
P,b
Set Bit in I/O register
I/O(P,b) 1
None
2
CBI
P,b
Clear Bit in I/O register
I/O(P,b) 0
None
2
LSL
Rd
Logical shift left
Rd(n+1) Rd(n), Rd(0) 0
Z,C,N,V
1
LSR
Rd
Logical shift right
Rd(n) Rd(n+1), Rd(7) 0
Z,C,N,V
1
ROL
Rd
Rotate left through carry
Rd(0) C,Rd(n+1) Rd(n),C
Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate right through carry
Rd(7) C,Rd(n) Rd(n+1),C
Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic shift right
Rd(n) Rd(n+1), n=0..6
Z,C,N,V
1
None
1
SWAP
Rd
Swap nibbles
Rd(3..0) Rd(7..4),Rd(7..4)
Rd(3..0)
BSET
s
Flag set
SREG(s) 1
SREG(s)
1
BCLR
s
Flag clear
SREG(s) 0
SREG(s)
1
BST
Rr, b
Bit store from register to T
T Rr(b)
T
1
BLD
Rd, b
Bit load from T to register
Rd(b) T
None
1
Set carry
C1
C
1
SEC
264
CLC
Clear carry
C0
C
1
SEN
Set negative flag
N1
N
1
CLN
Clear negative flag
N0
N
1
SEZ
Set zero flag
Z1
Z
1
CLZ
Clear zero flag
Z0
Z
1
SEI
Global interrupt enable
I1
I
1
CLI
Global interrupt disable
I 0
I
1
SES
Set signed test flag
S1
S
1
CLS
Clear signed test flag
S0
S
1
SEV
Set twos complement overflow.
V1
V
1
CLV
Clear twos complement overflow
V0
V
1
SET
Set T in SREG
T1
T
1
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
4.27
Instruction Set Summary (Continued)
Mnemonics
Operands
Description
Operation
Flags
#Clocks
CLT
Clear T in SREG
T0
T
1
SEH
Set half carry flag in SREG
H1
H
1
CLH
Clear half carry flag in SREG
H0
H
1
Data Transfer Instructions
MOV
Rd, Rr
Move between registers
Rd Rr
None
1
MOVW
Rd, Rr
Copy register word
Rd+1:Rd Rr+1:Rr
None
1
LDI
Rd, K
Load immediate
Rd K
None
1
LD
Rd, X
Load indirect
Rd (X)
None
2
LD
Rd, X+
Load indirect and post-inc.
Rd (X), X X + 1
None
2
LD
Rd, –X
Load indirect and pre-dec.
X X - 1, Rd (X)
None
2
LD
Rd, Y
Load indirect
Rd (Y)
None
2
LD
Rd, Y+
Load indirect and post-inc.
Rd (Y), Y Y + 1
None
2
LD
Rd, –Y
Load indirect and pre-dec.
Y Y - 1, Rd (Y)
None
2
LDD
Rd, Y+q
Load indirect with displacement
Rd (Y + q)
None
2
LD
Rd, Z
Load indirect
Rd (Z)
None
2
LD
Rd, Z+
Load indirect and post-inc.
Rd (Z), Z Z+1
None
2
LD
Rd,–Z
Load indirect and pre-dec.
Z Z - 1, Rd (Z)
None
2
LDD
Rd, Z+q
Load indirect with displacement
Rd (Z + q)
None
2
LDS
Rd, k
Load direct from SRAM
Rd (k)
None
2
ST
X, Rr
Store indirect
(X) Rr
None
2
ST
X+, Rr
Store indirect and post-inc.
(X) Rr, X X + 1
None
2
ST
–X, Rr
Store indirect and pre-dec.
X X - 1, (X) Rr
None
2
ST
Y, Rr
Store indirect
(Y) Rr
None
2
ST
Y+, Rr
Store indirect and post-inc.
(Y) Rr, Y Y + 1
None
2
ST
– Y, Rr
Store indirect and pre-dec.
Y Y – 1, (Y) Rr
None
2
STD
Y+q,Rr
Store indirect with displacement
(Y + q) Rr
None
2
ST
Z, Rr
Store indirect
(Z) Rr
None
2
ST
Z+, Rr
Store indirect and post-inc.
(Z) Rr, Z Z + 1
None
2
ST
–Z, Rr
Store indirect and pre-dec.
Z Z – 1, (Z) Rr
None
2
STD
Z+q,Rr
Store indirect with displacement
(Z + q) Rr
None
2
STS
k, Rr
Store direct to SRAM
(k) Rr
None
2
Load program memory
R0 (Z)
None
3
LPM
LPM
Rd, Z
Load program memory
Rd (Z)
None
3
LPM
Rd, Z+
Load program memory and post-inc
Rd (Z), Z Z+1
None
3
Store program memory
(Z) R1:R0
None
-
In port
Rd P
None
1
SPM
IN
Rd, P
OUT
P, Rr
Out port
P Rr
None
1
PUSH
Rr
Push register on stack
STACK Rr
None
2
POP
Rd
Pop register from stack
Rd STACK
None
2
MCU Control Instructions
NOP
No operation
None
1
SLEEP
Sleep
(see specific descr. for sleep function)
None
1
WDR
Watchdog reset
(see specific descr. for WDR/timer)
None
1
BREAK
Break
For on-chip debug only
None
N/A
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
265
5.
Application
Figure 5-1. Typical LIN Slave Application
PVCC
100nF
C2
LIN
220pF
PB7
PA3
PA4
33kΩ
PB4
PVCC
GND
LIN
GND
PA3
ATMEL
ATA6616C/ATA6617C
GND
1
WD_OSC
NRES
TXD
INH
RXD
PA2
PA1
PA0
PB0
PB1
PB3
PB2
19
10kΩ
PA3
VS
VBAT
+
VCC
+
GND
100nF
KL15
MODE
TM
VS
PA4
PVCC
GND
38
WAKE
NTRIG
EN
MCUVCC
100nF
C1
MCUAVCC
PA4
AGND
PA5
PA6
PB6
PB5
PA7
32
WAKE
20
PB7
31
100nF
22μF
10μF
13
10kΩ
12
PB7
PA2
PA2
1
47kΩ
PB7
KL15
MODE
PVCC
PA5
PA4
INH
47kΩ
100nF
10kΩ*
PB7
ISP
* The MODE pin can be connected directly to GND, if it is not needed to disable the Watchdog
Note:
266
All open pins of the SiP can be used for application-specific purposes.
AVR®: Internal clock, TXD, RXD, NRES, EN and NTRIG connected for LIN slave. The software must be appropriately programmed for the connection between the LIN-SBC and the AVR.
SBC: LIN slave operation with watchdog enabled, 5V regulator and KL15 wake up
RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the
microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure
5-1.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Figure 5-2. Typical LIN Master Application
PVCC
100nF
22pF
C2
LIN
560pF
PA5 PA4
PB7
PA3
PB4
PVCC
LIN
GND
PA3
MCUVCC
100nF
GND
GND
Atmel
ATA6616C/ATA6617C
NRES
TXD
INH
RXD
PA2
PA1
PA0
PB0
PB3
PB2
PB1
GND
38
WAKE
NTRIG
19
1
10kΩ
PA3
VS
VS
VBAT
+
VCC
+
PVCC
GND
100nF
KL15
MODE
TM
LIN
Master
pull-up
PA4
EN
WD_OSC
C1
MCUAVCC
PA4
AGND
PA5
20
PA6
PB6
PB5
PA7
32
PB7
31
22pF
1kΩ
WAKE
33kΩ
XTAL
100nF
22μF
10μF
13
10kΩ
12
PB7
PB7
47kΩ
PA2
PA2
1
KL15
MODE*
PVCC
PA5
PA4
INH
51kΩ
100nF
10kΩ*
PB7
ISP
* The MODE pin can be connected directly to GND, if it is not needed to disable the Watchdog
Note:
All open pins of the SiP can be used for application-specific purposes.
AVR®: TXD, RXD, NRES and EN connected for LIN master. The software must be appropriately programmed
for the connection between the LIN-SBC and the AVR. System clock controlled by external crystal.
LIN-SBC: Master application, 1k Master resistance connected via diode to VS, local wake up via pin WAKE;
watchdog is enabled.
RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the
microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure
5-2.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
267
Figure 5-3. Typical LIN Master Application
1k LIN Master Pull-up Switched Off during Sleep and Silent Mode
PVCC
100nF
22pF
C2
LIN
560pF
PB7
PA3
PA5 PA4
33kΩ
XTAL
PB4
PVCC
GND
LIN
GND
PA3
Atmel
ATA6616C/ATA6617C
NRES
TXD
INH
RXD
PA2
PA1
PA0
PB3
PB2
PB0
38
PB1
GND
1
WD_OSC
GND
WAKE
NTRIG
19
10kΩ
PA3
VS
VBAT
+
VCC
+
PVCC
GND
100nF
KL15
MODE
TM
VS
PA4
EN
MCUVCC
100nF
C1
MCUAVCC
PA4
AGND
PA5
PB6
PB5
PA6
32
PA7
22pF
10kΩ
20
PB7
31
WAKE
100nF
10μF
13
22μF
1kΩ
10kΩ
12
LIN
Master
pull-up
PB7
PB7
47kΩ
KL15
PA2
PA2
1
MODE*
PVCC
PA5
PA4
47kΩ
100nF
10kΩ*
PB7
ISP
* The MODE pin can be connected directly to GND, if it is not needed to disable the Watchdog
Note:
268
All open pins of the SiP can be used for application-specific purposes.
AVR®: TXD, RXD, NRES and EN connected for LIN master. The software must be appropriately programmed
for the connection between the LIN-SBC and the AVR. System clock controlled by external crystal.
LIN-SBC: Master application, 10k Master resistance connected via diode to VS, 1k master resistance will be
switched off via pin INH during sleep mode, local wake up via pin WAKE; watchdog is enabled.
RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the
microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure
5-3.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Figure 5-4. LIN Slave Application with Minimum External Components
100nF
C2
PB7
LIN
PA5 PA4
220pF
PB4
PVCC
GND
LIN
GND
PA3
GND
1
PA2
1
PVCC
WD_OSC
NRES
TXD
INH
RXD
PA2
PA1
PA0
PB0
PB1
PB3
PB2
19
VS
PA4
VBAT
VS
VCC
+
PVCC
GND
38
WAKE
NTRIG
EN
Atmel
ATA6616C/ATA6617C
MCUVCC
100nF
C1
MCUAVCC
PA4
AGND
PA5
PA6
20
PA7
PB6
PB5
PB7
31
32
100nF
KL15
MODE
TM
+
PVCC
GND
22μF
10μF
13
10kΩ
12
PA2
PB7
PA4
PA5
PB7
ISP
Note:
All open pins of the SiP can be used for application-specific purposes.
AVR®: Internal clock, TXD, RXD, NRES and EN connected for LIN Slave. The software must be appropriately
programmed for the connection between the LIN-SBC and the AVR.
SBC: LIN slave operation with 5V regulator, watchdog disabled.
RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the
microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure
5-4.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
269
Figure 5-5. 3 3 LIN Slave Switch Module Matrix Decoder with the Atmel ATA6616C/ATA6617C
Optional resistors
for higher switch
currents
1
PA2
PVCC
PA5
PA4
PB7
ISP
VCC
PVCC
100nF
C2
LIN
220pF
PA3
PB7
100nF
GND
LIN
Atmel
ATA6616C/ATA6617C
S4
S5
S6
NRES
TXD
INH
RXD
PA2
PA1
PA0
PB0
PB1
GND
PB3
PB2
WAKE
(if needed)
WAKE
NTRIG
19
1
VS
10kΩ
PA3
PA4
EN
MCUVCC
GND
38
GND
PA3
MCUAVCC
PA4
AGND
PB4
WD_OSC
C1
PB6
PB5
PA5
32
PVCC
PA6
S3
PA7
S2
20
PB7
S1
33kΩ
31
VS
+
PVCC
GND
100nF
KL15
MODE
TM
VBAT
+
VCC
100nF
22μF
10μF
13
10kΩ
12
PB7
PB0
PB7
KL15
MODE*
47kΩ
S7
S8
100nF
47kΩ
10kΩ*
S9
* The MODE pin can be connected directly to GND, if it is not needed to disable the Watchdog
Note:
270
Note: All open pins of the SiP can be used for application-specific purposes.
AVR®: TXD, RXD, NRES and EN connected for LIN master. The software must be appropriately programmed
for the connection between the LIN-SBC and the AVR. PA7 and PA2 are used as analog inputs. In addition, the
application supports a 3 x 3 switch matrix. PA4, 5, 6 are used as PWM outputs to control the brightness of light
emitting diodes. System clock controlled by external crystal.
LIN-SBC: LIN slave application, local wake up via pin WAKE; watchdog is enabled.
RF emissions: best results for RF emissions will be achieved by connecting the blocking capacitors of the
microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line.
See also Figure 5-5.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
6.
Ordering Information
Extended Type Number
Program Memory
Package
MOQ
ATA6616C-P3QW-1
8-kB flash
QFN38, 57
4,000 pieces
ATA6617C-P3QW-1
16-kB flash
QFN38, 57
4,000 pieces
Package Information
Top View
D
38
1
technical drawings
according to DIN
specifications
E
PIN 1 ID
A
Side View
A3
A1
Dimensions in mm
Bottom View
D2
13
19
20
E2
12
COMMON DIMENSIONS
(Unit of Measure = mm)
1
31
32
38
e
Z
Z 10:1
L
7.
b
Symbol
MIN
NOM
MAX
A
0.8
0.85
0.9
A1
A3
0
0.16
0.035
0.21
0.05
0.26
D
4.9
5
5.1
D2
3.5
3.6
3.7
E
6.9
7
7.1
E2
5.5
5.6
5.7
L
0.35
0.4
0.45
b
e
0.2
0.25
0.5
0.3
NOTE
05/20/14
TITLE
Package Drawing Contact:
[email protected]
Package: QFN_5x7_38L
Exposed pad 3.6x5.6
GPC
DRAWING NO.
REV.
6.543-5187.03-4
1
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
271
8.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
9132J-AUTO-01/15
9132I-AUTO-06/14
9132H-AUTO-04/13
History
Section 6 “Ordering Information” on page 271 updated
Section 7 “Package Information” on page 271 updated
Put datasheet in the latest template
Section 2 “Atmel ATA6616C/ATA6617C LIN System in Package Solution (SIP)” on pages 2
to 3 updated
Section 3 “Absolute Maximum Ratings” on pages 4 to 5 added
Section 6 “Application” on pages 298 to 302 updated
9132G-AUTO-11/12
General Features on page 1 updated
General Features on page 1 updated
Section 2.2 “Absolute Maximum Ratings” on page 3 updated
9132F-AUTO-02/12
Section 3 “LIN System-basis-chip Block” on pages 4 to 16 updated
Section 3.7 “Absolute Maximum Ratings” on page 19 updated
Section 3.8 “Electrical Characteristics” on pages 20 to 25 updated
Section 5 “Application” on pages 299 to 303 updated
9132E-AUTO-05/11
Table 4-81 “Calibration and Accuracy of Internal RC Oscillator” on page 269 updated
Section 4.5.2.2 “Calibrated Internal RC Oscillator” on page 50 updated
Section 3.1 “Features” on page 4 updated
Section 3.2 “Description” on page 4 updated
Section 3.3.3 “Ground Pin” on page 6 updated
9132D-AUTO-12/10
Section 3.3.12 “Mode Input Pin (Mode)” on page 7 updated
Figure 3.2 “Modes of Operation” on page 10 updated
Section 3.4.4 “Fail-safe Mode” on page 12 updated
Section 3.5.6 “Voltage Regulator” on pages 15 to 16 updated
Section 3.8 “Electrical Characteristics” on pages 20 to 25 updated
272
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
9.
Table of Contents
General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.
Atmel ATA6616C/ATA6617C LIN System in Package Solution (SIP) . . . . . . . . . . . . . . 3
1.1
2.
3.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LIN System-basis-chip Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4.
Pinning Atmel ATA6616C/ATA6617C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Wake-up Scenarios from Silent or Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Atmel ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616C/ATA6617C . . . 26
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
4.26
4.27
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AVR CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AVR Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
System Clock and Clock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O-Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8-bit Timer/Counter0 and Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timer/Counter1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
16-bit Timer/Counter1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
USI – Universal Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
LIN/UART - Local Interconnect Network Controller or UART . . . . . . . . . . . . . . . . . . . . . . . 166
ISRC - Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
ADC – Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
AnaComp - Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
DebugWIRE On-chip Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Decoupling Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
6.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
7.
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
8.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
9.
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
273
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