Features • 3.0V to 5.5V Operating Range • Advanced, High-speed, Electrically-erasable Programmable Logic Device • • • • • • • • • • • • • • – Superset of 22V10 – Enhanced Logic Flexibility – Architecturally Compatible with ATV750B and ATV750 Software and Hardware D- or T-type Flip-flop Product Term or Direct Input Pin Clocking 10 ns Maximum Pin-to-pin Delay with 5V Operation 15 ns Maximum Pin-to-pin Delay with 3V Operation Highest Density Programmable Logic Available in 24-pin Package – Advanced Electrically-erasable Technology – Reprogrammable – 100% Tested Increased Logic Flexibility – 42 Array Inputs, 20 Sum Terms and 20 Flip-flops Enhanced Output Logic Flexibility – All 20 Flip-flops Feed Back Internally – 10 Flip-flops are also Available as Outputs Programmable Pin-keeper Circuits Dual-in-line and Surface Mount Package in Standard Pinouts Commercial and Industrial Temperature Ranges 20-year Data Retention 2000V ESD Protection 1000 Erase/Write Cycles Green Package Options (Pb/Halide-free/RoHS Compliant) Available High-speed Complex Programmable Logic Device ATF750LVC 1. Block Diagram (OE PRODUCT TERMS) 12 INPUT PINS PROGRAMMABLE INTERCONNECT AND COMBINATORIAL LOGIC ARRAY 4 TO 8 PRODUCT TERMS LOGIC OPTION (UP T0 20 FLIP-FLOPS) OUTPUT OPTION 10 I/O PINS (CLOCK PIN) 2. Description The Atmel® “750” architecture is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance. The ATF750LVC is a highperformance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. 1447F–PLD–11/08 3. Pin Configurations Pin Name Function CLK Clock IN Logic Inputs I/O Bi-directional Buffers GND Ground VCC 3V to 5.5V Supply PLCC 3.2 25 24 23 22 21 20 19 12 13 14 15 16 17 18 5 6 7 8 9 10 11 I/O I/O I/O GND(1) I/O I/O I/O IN IN GND GND(1) IN I/O I/O IN IN IN GND(1) IN IN IN 4 3 2 1 28 27 26 IN IN CLK/IN VCC(1) VCC I/O I/O 3.1 Note: DIP/SOIC/TSSOP CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN 1. For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. Each of the ATF750LVC’s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flipflop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. 2 ATF750LVC 1447F–PLD–11/08 ATF750LVC 4. Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ............................................-2.0V to +7V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7V for pulses of less than 20 ns with VCC at VCC max. 5. DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient) 0°C - 70°C -40°C - +85°C VCC Power Supply 3.0 - 5.25V 3.0 - 5.5V 6. Clock Mux CKMUX CKi CLOCK PRODUCT TERM CLK PIN TO LOGIC CELL SELECT 7. Output Options 3 1447F–PLD–11/08 8. Bus-friendly Pin-keeper Input and I/Os All input and I/O pins on the ATF750LVC have programmable “pin-keeper” circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. Please refer to the software compiler table for more details. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os. Table 1. Software Compiler Mode Selection Synario WinCupl Pin-keeper Circuit ATF750LVC V750C Disabled ATF750LVC (PPK) V750CPPK Enabled 9. Input Diagram VCC INPUT 100K ESD PROTECTION CIRCUIT PROGRAMMABLE OPTION 10. I/O Diagram VCC OE DATA I/O VCC 100K PROGRAMMABLE OPTION 4 ATF750LVC 1447F–PLD–11/08 ATF750LVC 11. DC Characteristics Symbol Parameter Condition Min Typ Max Units 3.0 3.3 3.6 V Com. 4.75 5.0 5.25 V Ind. 4.5 5.0 5.5 V 3V Operation VCC Power Supply Voltage 5V Operation ILI Input Load Current VIN = -0.1V to VCC + 1V 10 µA ILO Output Leakage Current VOUT = -0.1V to VCC + 0.1V 10 µA ICC Power Supply Current, Standby VCC = 3.6V VIN = 3.6V Outputs Open C-15 ICC Power Supply Current, Standby VCC = 5.25V VIN = 5.25V Outputs Open C-15 IOS(1)(2) Output Short Circuit Current VOUT = 0.5V VIL Input Low Voltage Min ≤ VCC ≤ Max VIH Input High Voltage VOL Output Low Voltage VOH Notes: Output High Voltage VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min Com. 65 90 mA Ind. 70 100 mA Com. 100 180 mA Ind. 110 190 mA -120 mA -0.6 0.8 V 2.0 VCC + 0.75 V IOL = 16 mA Com., Ind. 0.5 V IOL = 12 mA Mil. 0.5 V IOL = 24 mA Com. 0.8 V IOH = -100 µA VCC - 0.3V V IOH = -2.0 mA 2.4 V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. This test is performed at initial characterisation only. 12. Input Test Waveforms and Measurement Levels tR, tF < 3 ns (10% to 90%) 13. Output Test Load VCC 316 Ω 348 Ω 5 1447F–PLD–11/08 14. AC Waveforms, Product Term Clock(1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. 15. AC Characteristics, Product Term Clock(1) -15 (5V Operation) Max Units 10 15 ns Input to Output Enable 10 15 ns tER Input to Output Disable 10 15 ns tCO Clock to Output 4 10 5 12 ns tCF Clock to Feedback 4 7.5 5 9 ns tS Input Setup Time 4 8 ns tSF Feedback Setup Time 4 7 ns tH Hold Time 2 5 ns tP Clock Period 11 14 ns tW Clock Width 5.5 7 ns Symbol Parameter tPD Input or Feedback to Non-registered Output tEA fMAX Min Max -15 (3V Operation) Min External Feedback 1/(tS + tCO) 71 50 MHz Internal Feedback 1/(tSF + tCF) 86 62 MHz No Feedback 1/(tP) 90 71 MHz tAW Asynchronous Reset Width 10 15 ns tAR Asynchronous Reset Recovery Time 10 15 ns tAP Asynchronous Reset to Registered Output Reset tSP Setup Time, Synchronous Preset Note: 6 12 7 15 8 ns ns 1. See ordering information for valid part numbers. ATF750LVC 1447F–PLD–11/08 ATF750LVC 16. AC Waveforms, Input Pin Clock(1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. 17. AC Characteristics, Input Pin Clock -15 (5V Operation) Max Units 10 15 ns Input to Output Enable 10 15 ns tER Input to Output Disable 10 15 ns tCOS Clock to Output 0 7 0 10 ns tCFS Clock to Feedback 0 5 0 5.5 ns tSS Input Setup Time 5 8 ns tSFS Feedback Setup Time 5 7 ns tHS Hold Time 0 5 ns tPS Clock Period 10 14 ns tWS Clock Width 5 7 ns Symbol Parameter tPD Input or Feedback to Non-registered Output tEA fMAXS Min Max -15 (3V Operation) Min External Feedback 1/tSS + tCOS 83 55 MHz Internal Feedback 1/tSFS + tCFS 100 80 MHz No Feedback 1/tPS 100 83 MHz tAW Asynchronous Reset Width 10 15 ns tARS Asynchronous Reset Recovery Time 10 15 ns tAP Asynchronous Reset to Registered Output Reset tSPS Setup Time, Synchronous Preset 10 5 15 11 ns ns 7 1447F–PLD–11/08 18. Functional Logic Diagram ATF750LVC, Upper Half 8 ATF750LVC 1447F–PLD–11/08 ATF750LVC 19. Functional Logic Diagram ATF750LVC, Lower Half 9 1447F–PLD–11/08 20. Using the ATF750LVC’s Many Advanced Features The ATF750LVC’s advanced flexibility packs more usable gates into 24-pins than any other logic device. The ATF750LVCs start with the popular 22V10 architecture, and add several enhanced features: • Selectable D- and T-type Registers Each ATF750LVC flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. • Selectable Asynchronous Clocks Each of the ATF750LVC’s flip-flops may be clocked by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. • A Full Bank of Ten More Registers The ATF750LVC provides two flip-flops per output logic cell for a total of 20. Each register has its own sum term, its own reset term and its own clock term. • Independent I/O Pin and Feedback Paths Each I/O pin on the ATF750LVC has a dedicated input path. Each of the 20 registers has its own feedback terms into the array as well. This feature, combined with individual product terms for each I/O’s output enable, facilitates true bi-directional I/O design. 21. Synchronous Preset and Asynchronous Reset One synchronous preset line is provided for all 20 registers in the ATF750LVC. The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flip-flops are reset when the input signals received force the internal resets high. 22. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF750LVC fuse patterns. Once the security fuse is programmed, all fuses will appear programmed during verify. The security fuse should be programmed last, as its effect is immediate. 10 ATF750LVC 1447F–PLD–11/08 ATF750LVC ATF750LVC OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE(VOH = 2.4V) ATF75LVC OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE(VOL = 0.5V) 0 45 -10 40 IOL (mA) IOH (mA) -20 -30 -40 35 30 25 -50 20 -60 15 -70 3 3.25 3.3 3.5 3.6 4 4.25 4.5 4.75 5 5.25 5.5 3 6 3.3 3.6 4 4.25 4.5 4.75 5 5.25 5.5 6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) ATF750LVC INPUT CLAMP CURRENT o VS. INPUT VOLTAGE (TA = 25 C) ATF75LVC INPUT CURRENT VS. INPUT VOLTAGE o 0 AT VCC=3.3V ATVCC=5.0V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 INPUT CURRENT (mA) INPUT CURRENT (uA) (TA = 25 C) WITH PIN KEEPER 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -10 -20 -30 -40 -50 AT VCC=3.3V -60 AT VCC=5.0V -70 -80 -90 -100 INPUT VOLTAGE (V) 0 -0.2 -0.4 -0.6 -0.8 -1 INPUT VOLTAGE (V) ATF750LVC SUPPLY CURRENT o VS. SUPPLY VOLTAGE (TA = 25 C) 150 ICC (mA) 130 110 90 70 50 30 3 3.3 3.6 4 4.25 4.5 5 5.25 5.5 5.75 6 SUPPLY VOLTAGE (V) 11 1447F–PLD–11/08 ATF750LVC OUTPUT SOURCE CURRENT o VS. OUTPUT VOLTAGE (TA = 25 C) ATF750LVC OUTPUT SINK CURRENT VS. o OUTPUT VOLTAGE (TA = 25 C) 0 140 120 ioh@vcc=3.3V -40 ioh@Vcc=5.0V -60 IOL (mA) IOH (mA) -20 100 Iol AT Vcc=3.3V 80 IOL at VCC=5.0V 60 40 20 -80 0 0 -100 0.2 0.5 1 1.5 2 2.5 3 3.3 4 4.5 5 VOL (V) -120 0 0.5 1 1.5 2 2.5 3 3.3 4 4.5 5 VOH (V) 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 NORMALIZED SUPPLY CURRENT OVER TEMPERATURE (AT VCC = 3.3V & 5.0V) AT VCC=3.3V At VCC=5.0V Normalized Value ICC (mA) ATF750LVC SUPPLY CURRENT o VS. INPUT FREQUENCY (TA = 25 C) 0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -40 0 5 10 15 20 50 75 100 0 25 75 Temperature Frequency (MHz) 12 ATF750LVC 1447F–PLD–11/08 ATF750LVC 23. ATF750LVC Ordering Information 23.1 ATF750LVC Green Package Options (Pb/Halide-free/RoHS Compliant) tPD (ns) tCOS (ns) 15 Note: 10 Ext. fMAXS (MHz) 55 Ordering Code ATF750LVC-15JU ATF750LVC-15PU ATF750LVC-15SU ATF750LVC-15XU(1) Package 28J 24P3 24S 24X Operation Range Industrial (-40°C to 85°C) 1. Special order only; TSSOP package requires special thermal management. Package Type 28J 28-Lead, Plastic J-leaded Chip Carrier (PLCC) 24P3 24-lead, 0.300’ Wide, Plastic Dual Inline Package (PDIP) 24S 24-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC) 24X* 24-lead, 0.173” Wide, Thin Shrink Small Outline (TSSOP) 13 1447F–PLD–11/08 24. Package Information 24.1 28J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 E D2/E2 B1 B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 12.319 – 12.573 D1 11.430 – 11.582 E 12.319 – 12.573 E1 11.430 – 11.582 D2/E2 9.906 – 10.922 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 14 2325 Orchard Parkway San Jose, CA 95131 TITLE 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 28J B ATF750LVC 1447F–PLD–11/08 ATF750LVC 24.2 24P3 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. 2. This package conforms to JEDEC reference MS-001, Variation AF. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 31.623 – 32.131 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.651 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e NOTE Note 2 Note 2 2.540 TYP 6/1/04 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 24P3 REV. D 15 1447F–PLD–11/08 24.3 24S – SOIC B D1 D PIN 1 ID PIN 1 e E A COMMON DIMENSIONS (Unit of Measure = mm) A1 0º ~ 8º L1 L SYMBOL MIN NOM MAX A – – 2.65 A1 0.10 – 0.30 D 10.00 – 10.65 D1 7.40 – 7.60 E 15.20 – 15.60 B 0.33 – 0.51 L 0.40 – 1.27 L1 0.23 – 0.32 e NOTE 1.27 BSC 06/17/2002 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. REV. 24S B ATF750LVC 1447F–PLD–11/08 ATF750LVC 24.4 24X – TSSOP Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters 0.30(0.012) 0.19(0.007) 4.48(0.176) 6.50(0.256) 4.30(0.169) 6.25(0.246) PIN 1 0.65(0.0256)BSC 7.90(0.311) 1.20(0.047)MAX 7.70(0.303) 0.15(0.006) 0.05(0.002) 0.20(0.008) 0º ~ 8º 0.09(0.004) 0.75(0.030) 0.45(0.018) 04/11/2001 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. REV. 24X A 17 1447F–PLD–11/08 25. Revision History 18 Revision Level – Release Date History F – November 2008 Updated datasheet with extended voltage range offering. Removed the leaded parts offering. ATF750LVC 1447F–PLD–11/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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