ATF16V8B, ATF16V8BQ*, and ATF16V8BQL High-performance EE PLD DATASHEET Features Industry-standard Architecture Emulates Many 20-pin PALs® Low-cost Easy-to-use Software Tools ̶ ̶ High-speed Electrically-erasable Programmable Logic Devices Automatic 5mA Standby for ATF16V8BQL CMOS and TTL Compatible Inputs and Outputs Advanced Flash Technology ̶ ̶ 10ns Maximum Pin-to-pin Delay ̶ Input and I/O Pull-up Resistors Reprogrammable 100% Tested ̶ High-reliability CMOS Process ̶ ̶ ̶ ̶ 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200mA Latchup Immunity Industrial Temperature Range Dual-in-line and Surface Mount Packages in Standard Pinouts PCI-compliant Green Package Options (Pb/Halide-free/RoHS Compliant) Description The Atmel® ATF16V8B(QL) is a high-performance CMOS Electrically-Erasable Programmable Logic Device (EE PLD) that utilizes the Atmel proven electrically-erasable Flash memory technology. All speed ranges are specified over the full 5.0V 10% range for industrial temperature range. The ATF16V8BQL provides edge-sensing low-power PLD solution with low standby power consumption (5mA typical). The ATF16V8BQL powers down automatically to the low-power mode through the Input Transition Detection (ITD) circuitry when the device is idle. *The ATF16V8BQ is Replaced by ATF16V8B and ATF16V8BQL The ATF16V8B(QL) incorporate a super set of the generic architectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized. Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 Pin Configurations and Pinouts Table 1-1. Pin Configurations Pin Name Function CLK Clock GND Ground I Logic Inputs I/O Bi-directional Buffers OE Output Enable VCC +5V Power Supply Figure 1-1. Pinouts 20-lead TSSOP (Top View) (Top View) I/CLK 1 20 VCC I/CLK 1 20 VCC I1 2 19 I/O I1 2 19 I/O I2 3 18 I/O I2 3 18 I/O I3 4 17 I/O I3 4 17 I/O I/O I4 5 16 I/O I5 6 15 I/O I6 7 14 I/O I7 8 13 I/O I8 9 12 I/O 10 11 I9/OE 16 6 15 I/O I6 7 I7 8 13 I/O I8 9 12 I/O 10 11 I9/OE GND I/O 18 I/O I3 4 17 I/O I4 5 16 I5 6 I6 VCC 19 3 I/O 2 I2 19 I1 I/CLK VCC 20 20 I1 1 1 I/CLK I2 (Top View) 2 20-lead PLCC (Top View) 3 20-lead PDIP 6 16 I/O 15 I/O I6 7 15 I/O 7 14 I/O I7 8 14 I/O I7 8 13 I/O I8 9 12 I/O 10 11 I9/OE Drawings are not to scale. ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 13 I5 I/O I/O I/O 12 I/O 17 I/O 18 5 11 4 I4 I9/OE I3 GND Note: I/O 10 GND 14 9 I5 5 I8 I4 2 20-lead SOIC GND 1. 2. Block Diagram Figure 2-1. 10 Input Pins Block Diagram Programmable Interconnect and Combinatorial Logic Array Logic Option 8 I/O Pins Up to 8 Flip-Flops ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 3 3. Electrical Characteristics 3.1 Absolute Maximum Ratings* Temperature Under Bias . . . . . . . . . . . . . . . . . -55oC to +125oC Storage Temperature . . . . . . . . . . . . . . . . . . . . -65oC to +150oC Voltage on Any Pin with Respect to Ground . . . . . . . . . . . . . . . . . . . . . . -2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming . . . . . . . . . . . . . -2.0V to +14.0V(1) Programming Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . -2.0V to +14.0V(1) Note: 3.2 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20ns. Pin Capacitance Table 3-1. Pin Capacitance (f = 1MHz, T = 25°C(1)) Typ Max Units Conditions CIN 5 8 pF VIN = 0V COUT 6 8 pF VOUT = 0V Note: 3.3 *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. DC and AC Operating Conditions Table 3-2. DC and AC Operating Conditions Industrial Operating Temperature (Ambient) VCC Power Supply 4 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 -40oC to +85oC 5.0V 10% 3.4 DC Characteristics Table 3-3. DC Characteristics Symbol Parameter Condition IIL Input or I/O Low Leakage Current 0 VIN VIL(Max) IIH Input or I/O High Leakage Current 3.5 VIN VCC Power Supply Current, Standby ICC Clocked Power Supply Current ICC2 IOS(1) Output Short Circuit Current VIL Input Low Voltage VIH Input High Voltage VOL Output High Voltage VOH Output High Voltage Note: 1. VCC = Max VIN = Max, Outputs Open VCC = Max, Outputs Open f = 15MHz Min VCC = Min VIN = VIH or VIL VCC = Min Max Units -35 -100 μA 10 μA B-10 55 95 B-15 50 80 BQL-15 5 15 B-10 60 100 B-15 55 95 BQL-15 20 40 VOUT = 0.5 V VIN = VIH or VIL Typ mA -130 mA -0.5 0.8 V 2.0 VCC + 0.75 V 0.5 V IOL = 24mA IOH = -4.0 mA mA 2.4 V Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30s. ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 5 3.5 AC Characteristics AC Characteristics(1) Table 3-4. -10 Symbol Parameter tPD Input or Feedback to Non-Registered Output tCF Clock to Feedback tCO Clock to Output tS Input or Feedback Setup Time tH 8 outputs switching -15 Min Max Min Max Units 3 10 3 15 ns 8 ns 10 ns 6 2 7 2 7.5 12 ns Hold Time 0 0 ns tP Clock Period 12 16 ns tW Clock Width 6 8 ns fMAX External Feedback 1/(tS + tCO) 68 45 Internal Feedback 1/(tS + tCF) 74 50 No Feedback 1/(tP) 83 62 tEA Input to Output Enable — Product Term 3 10 3 15 ns tER Input to Output Disable — Product Term 2 10 2 15 ns tPZX OE pin to Output Enable 2 10 2 15 ns tPXZ OE pin to Output Disable 1.5 10 1.5 15 ns Note: 1. See ordering information for valid part numbers and speed grades. Figure 3-1. AC Waveforms(3.6) Inputs, I/O Reg. Feedback tH tS tW CLK tW tP tER, tPXZ tCO Registered Outputs Combinatorial Outputs tEA, tPZX HIGH Z Output Valid tPD tEA, tPZX tER, tPXZ Output Valid Output Valid Output Valid HIGH Z Output Valid Note 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified. 6 MHz ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 3.6 Input Test Waveforms 3.6.1 Input Test Waveforms and Measurement Levels Figure 3-2. Input Test Waveforms and Measurement Levels 3.0V AC Driving Levels 1.5V AC Measurement Level 0.0V tR, tF < 5ns (10% to 90%) 3.6.2 Output Test Loads (Commercial) Figure 3-3. Output Test Loads CL includes Test fixture and Probe capacitance 3.7 Power-up Reset The registers in the ATF16V8B(QL) are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during tPR. Figure 3-4. Power Power-up Reset Waveforms VRST tPR Registered Outputs tS tW Clock ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 7 Table 3-5. 3.8 Power-up Reset Parameters Parameter Description Typ Max Units tPR Power-up Reset Time 600 1,000 ns VRST Power-up Reset Voltage 3.8 4.5 V Preload of Registered Outputs The ATF16V8B(QL) device registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. 4. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF16V8B(QL) fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. 5. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. 6. Programming/Erasing Programming/erasing is performed using standard PLD programmers. 7. Input and I/O Pull-ups All ATF16V8B(QL) family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to VCC. This ensures that all logic array inputs are at known states. These are relatively weak active pull-ups that can easily be over driven by TTL-compatible drivers (see input and I/O diagrams below). Figure 7-1. Input Diagram VCC R > 50KΩ Input ESD Protection Circuit 8 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 VCC Figure 7-2. I/O Diagram VCC VCC OE R > 50KΩ I/O Data Feedback 8. Functional Logic Diagram Description The logic option and functional diagrams describe the ATF16V8B(QL) architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF16V8B(QL) can be configured in one of three different modes. Each mode makes the ATF16V8B(QL) look like a different device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control. The ATF16V8B(QL) universal architecture can be programmed to emulate many 20-pin PAL devices. These architectural subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF16V8B(QL) can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the content of the ATF16V8B(QL). Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the security fuse. 9. Software Support Atmel WinCUPL is a free tool, available on Atmel’s web site and can be used to design in all members of the ATF16V8B(QL) family of SPLDs. The below table lists the Atmel WinCUPL device mnemonics for the different macrocell configuration modes. Table 9-1. Compiler Mode Selection CUPL, Atmel WinCUPL Registered Complex Simple Auto Select G16V8MS G16V8MA G16V8AS G16V8 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 9 10. Macrocell Configuration Software compilers support the three different OMC modes as different device types. Most compilers have the ability to automatically select the device type, generally based on the register usage and Output Enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode: 10.1 Registered Mode Pin 1 and pin 11 are permanently configured as clock and output enable respectively. These pins cannot be configured as dedicated inputs in the registered mode. Complex Mode Pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. Simple Mode All feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. ATF16V8B(QL) Registered Mode PAL Device Emulation/PAL Replacement. The registered mode is used if one or more registers are required. Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently disabled. Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode: 10 16R8 16RP8 16R6 16RP6 16R4 16RP4 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 Figure 10-1. Registered Configuration for Registered Mode(1)(2) CLK D XOR Q Q OE Notes: 1. 2. Figure 10-2. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the registered outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE. The development software configures all the architecture control bits and checks for proper pin usage automatically. Combinatorial Configuration for Registered Mode(1)(2) XOR Notes: 1. 2. Pin 1 and Pin 11 are permanently configured as CLK and OE. The development software configures all the architecture control bits and checks for proper pin usage automatically. ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 11 Figure 10-3. Registered Mode Logic Diagram CLK 1 Input Lines 0 4 8 12 16 20 24 28 Output Logic 19 Output Logic 18 Output Logic 17 Output Logic 16 Output Logic 15 Output Logic 14 Output Logic 13 Output Logic 12 2 3 4 5 6 7 8 9 11 12 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 10.2 ATF16V8B(QL) Complex Mode PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output. Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode: 16L8 16H8 16P8 Figure 10-4. Complex Mode Option 0 1 7 XOR Pins 12 and 19 do not have this feedback path. ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 13 Figure 10-5. Complex Mode Logic Diagram 1 Input Lines 0 4 8 12 16 20 24 28 Output Logic 19 Output Logic 18 Output Logic 17 Output Logic 16 Output Logic 15 Output Logic 14 Output Logic 13 Output Logic 12 2 3 4 5 6 7 8 9 11 14 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 10.3 ATF16V8B(QL) Simple Mode PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs. The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs can be emulated using this mode: 10L8 10H8 10P8 12L6 12H6 12P6 14L4 14H4 14P4 16L2 16H2 16P2 Figure 10-6. Simple Mode Option VCC 0 S1* 1 0 7 XOR Pins 15 and 16 do not have this feedback path. * Pins 15 and 16 are always enabled. ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 15 Figure 10-7. Simple Mode Logic Diagram 1 Input Lines 0 4 8 12 16 20 24 28 Output Logic 19 Output Logic 18 Output Logic 17 Output Logic 16 Output Logic 15 Output Logic 14 Output Logic 13 Output Logic 12 2 3 4 5 6 7 8 9 16 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 11 Test Characterization Data Supply Current vs Input Frequency Supply Current vs Input Frequency ATF16V8B/BQ (VCC = 5V, TA = 25°C) ATF16V8BL/BQL (VCC = 5V, TA = 25°C) 75 75 ATF16V8B ATF16V8B ATF16V8BQ 50 ICC (mA) ICC (mA) 50 ATF16V8BQL 25 25 0 0 0 25 50 75 100 0 20 40 Frequency (MHz) 60 80 100 Frequency (MHz) Supply Current vs Supply Voltage Supply Current vs Supply Voltage ATF16V8B/BQ (TA = 25°C) ATF16V8BL/BQL (TA = 25°C) 65 6.0 ATF16V8B 5.5 ATF16V8BQ 45 ICC (mA) ICC (mA) 55 35 5.0 4.5 25 4.50 4.75 5.00 5.25 4.0 4.50 5.50 4.75 Supply Voltage (V) 5.50 ATF16V8BL/BQL (VCC = 5.0V) 70 5.6 60 5.2 ICC (mA) ICC (mA) 5.25 Supply Current vs Ambient Temperature ATF16V8B/BQ (VCC = 5.0V) 50 5.00 Supply Voltage (V) Supply Current vs Ambient Temperature ATF16V8B 40 4.8 4.4 ATF16V8BQ 30 4.0 -55 -10 35 80 125 -55 Ambient Temperature (C) -10 35 80 125 Ambient Temperature (C) Output Source Current vs Supply Current Output Sink Current vs Supply Current TA = 25°C TA = 25°C -10 34.5 -12 34.0 IOL (mA) -14 IOH (mA) 11. -16 -18 33.5 33.0 -20 32.5 -22 -24 4.5 4.7 4.9 5.1 Supply Voltage (V) 5.3 5.5 32.0 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 17 Output Source Current vs Outpute Voltage Output Sink Current vs Output Voltage (VCC = 5.0V, TA = 25°C) (VCC = 5.0V, TA = 25°C) 0.0 70 -0.5 60 50 IOL (mA) IOH (mA) -1.0 -1.5 -2.0 40 30 -2.5 20 -3.0 10 -3.5 -4.0 0 3.5 3.8 4.1 4.4 4.7 5.0 0.0 0.2 0.4 Output Voltage (V) 0.6 0.8 1.0 Output Voltage (V) Output Source Current vs Output Voltage Output Sink Current vs Output Voltage (VCC = 5.0V, TA = 25°C) (VCC = 5.0V, TA = 25°C) 0 140 120 100 IOL (mA) IOH (mA) -10 -20 80 60 40 -30 20 -40 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 Output Voltage (V) Normalized TPD vs Supply Voltage 1.30 1.15 ATF16VB/BQ 1.00 ATF16VB/BQL 0.85 0.70 4.50 Normalized TPD Normalized TPD 5 (VCC = 5.0V) 1.30 1.15 1.00 0.85 0.70 4.75 5.00 5.25 5.50 -55 Supply Voltage (V) -25 5 65 95 125 Normalized TCO vs Ambient Temperature (TA = 25°C) (VCC = 5.0V) 1.30 1.15 ATF16V8B/BQ 1.00 ATF16V8B/BQL 0.85 Normalized TCO 1.30 0.70 4.50 35 Ambient Temperature (C) Normalized TCO vs Supply Voltage Normalized TCO 4 Normalized TPD vs Ambient Temperature (TA = 25°C) 1.15 1.00 0.85 0.70 4.75 5.00 Supply Voltage (V) 18 3 Output Voltage (V) ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 5.25 5.50 -55 -10 35 80 Ambient Temperature (C) 125 Normalized TS vs Supply Voltage Normalized TS vs Ambient Temperature (TA = 25°C) (VCC = 5.0V) 1.30 Normalized TS Normalized TS 1.30 1.15 1.00 0.85 1.15 1.00 0.85 0.70 0.70 -55 -10 35 80 125 -55 -10 Supply Voltage (V) Delta TPD vs Output Loading 6 Delta TCO (ns) Delta TPD (ns) 125 (VCC = 5V, TA = 25°C) 6 4 2 0 4 2 0 -2 -2 0 50 100 150 200 250 300 0 50 100 Output Loading (pF) 150 200 250 300 Output Loading (pF) Delta TPD vs # Output Switching Delta TCO vs # Output Switching (VCC = 5.0V, TA = 25°C) (VCC = 5.0V, TA = 25°C) 0.0 0.0 -0.1 -0.1 Delta TCO (ns) Delta TPD (ns) 80 Delta TCO vs Output Loading (VCC = 5.0V, TA = 25°C) -0.2 -0.3 -0.4 -0.2 -0.3 -0.4 -0.5 -0.5 1 2 3 4 5 6 7 8 1 2 3 # of Output Switching 4 5 6 7 8 # of Output Switching Input Current vs Input Voltage Input Clamp Current vs Input Voltage (VCC = 5.0V, TA = 25°C) (VCC = 5.0V, TA = 25°C) 20 Input Current mA 40 Input Current μA 35 Ambient Temperature (C) 20 0 -20 0 -20 -40 -60 -80 -40 1 2 3 4 5 Input Voltage (V) 6 7 8 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 Input Voltage (V) ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 19 12. Ordering Information tPD (ns) tS (ns) tCO (ns) Ordering Code Package 10 7.5 7 ATF16V8B-10JU 20J ATF16V8B-15SU 20S2 ATF16V8B-15XU 20X ATF16V8B-15PU 20P3 ATF16V8B-15JU 20J 15 15 12 12 10 10 ATF16V8BQL-15SU 20S2 ATF16V8BQL-15XU 20X ATF16V8BQL-15PU 20P3 ATF16V8BQL-15JU 20J Package Type 20S2 20-lead, 0.300" wide, Plastic Gull-wing Small Outline (SOIC) 20X 20-lead, 4.4mm wide, Plastic Thin Shrink Small Outline (TSSOP) 20P3 20-lead, 0.300" wide, Plastic Dual Inline Package (PDIP) 20J 20 20-lead, Plastic J-leaded Chip Carrier (PLCC) ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 Operation Range Industrial (Pb/Halide-free/RoHS Compliant) (-40C to +85C) Industrial (Pb/Halide-free/RoHS Compliant) (-40C to +85C) 13. Packaging Information 13.1 20S2 — 20-lead SOIC C 1 10 E1 E 11 E1 20 TOP VIEW e L A2 b END VIEW A1 A D Notes: 1. 2. 3. 4. 5. 6. SIDE VIEW This drawing is for general information only. Refer to JEDEC Drawing MS-013, Variation AC, for proper dimensions, tolerances, datums, etc. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrustions or gate burrs shall not exceed 0.15 mm per end. Diminsion E1 does not include interlead flash or protursion. Interlead flash or protrusion shall not exceed 0.25 mm per side. The package top may be smaller than the package bottom. Dimensions D and E1 are determinded at the outermost extremes of the plastic body exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. The dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. Dimension ‘b’ does not include the dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of the ‘b’ dimension at maximum material condition. The dambar may not be located on the lower radius of the foot. ‘A1’ is defined as the vertical distance from the seating plane to the lowest point on the package body excluding the lid or thermal enhancement on the cavity down package configuration. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN D NOM MAX NOTE 12.80 BSC 2,3 E1 7.50 BSC 2,3 E 10.30 BSC A - - 2.65 A1 0.10 - 0.30 A2 2.05 - - e 6 1.27 BSC b 0.31 - 0.51 L 0.40 - 1.27 C 0.20 - 0.33 4,5 4 7/1/14 TITLE Package Drawing Contact: [email protected] 20S2, 20-lead, 0.300” Wide Body, Plastic Gull Wing Small Outline Package (SOIC) GPC DRAWING NO. REV. SRJ 20S2 E ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 21 20X — 20-lead TSSOP 0º~ 8º 13.2 b L L1 E E1 End View e COMMON DIMENSIONS (Unit of Measure = mm) Top View SYMBOL D 6.40 E D A MIN A2 E1 Notes: MAX NOTE 6.50 6.60 2, 5 4.50 3, 5 6.40 BSC 4.30 4.40 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 e Side View NOM L 4 0.65 BSC 0.45 L1 0.60 0.75 1.00 REF 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 09/26/11 Package Drawing Contact: [email protected] 22 TITLE 20X, 20-lead 4.4 x 6.5 mm Body, 0.65 mm Lead Pitch, Thin Shrink Small Outline Package (TSSOP) ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 GPC DRAWING NO. REV. TLN 20X D 20P3 — 20-lead PDIP 20 11 E1 1 10 D E e See Lead Detail A2 A BASE PLANE -CSEATING PLANE C L A1 b GAGE PLANE eA L b2 .015 j 0.10 m C Z Z 13.3 c eB COMMON DIMENSIONS (UNIT OF MEASURE=MM) eC Lead Detail Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). Symbol A A1 A2 b b2 c D E E1 L e eA eB eC Min. 0.381 2.921 0.356 1.143 0.203 24.892 7.620 6.096 2.921 0.000 Nom. 3.302 0.457 1.524 0.254 26.162 7.874 6.350 3.302 2.54 BSC 7.62 BSC - Max. 5.334 4.953 0.588 1.778 0.356 26.924 8.255 7.112 3.810 Note Note 2 Note 2 10.922 1.524 1/6/12 Package Drawing Contact: [email protected] TITLE 20P3, 20-lead, 0.300”/7.62 mm Wide Plastic Dual Inline Package (PDIP) GPC DRAWING NO. PQD 20P3 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 REV. F 23 13.4 20J — 20-lead PLCC PIN NO. 1 1.14(0.045) X 45° 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) IDENTIFIER e E1 E D2/E2 B1 B A2 D1 A1 D A 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102mm) maximum SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 9.779 – 10.033 D1 8.890 – 9.042 E 9.779 – 10.033 E1 8.890 – 9.042 D2/E2 7.366 – 8.382 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 Package Drawing Contact: [email protected] 24 ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 20J B 14. Revision History Doc. Rev. 0364K Date 07/2014 Comments Removed ATF16V8BQ device and commercial options due to becoming obsolete. Updated package drawings to most current versions and the 20S to 20S2 package drawing. Updated template, Atmel logos, disclaimer page. 0364J 07/2005 1999 Green Package options added in 2005. ATF16V8B-25 JC/PC/SC/XC/JI/PI/SI/XI and ATF16V8BQL-25 JC/PC/SC/XC/JI/PI/SI/XI were obsoleted in August 1999 and removed from the datasheet. ATF196V8B(Q)(QL) [DATASHEET] Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014 25 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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