AT91EB42 Evaluation Board .............................................................................................. User Guide Table of Contents Section 1 Overview ............................................................................................... 1-1 1.1 1.2 1.3 Scope ........................................................................................................1-1 Deliverables ..............................................................................................1-1 The AT91EB42 Evaluation Board .............................................................1-1 Section 2 Setting Up the AT91EB42 Evaluation Board ................................................................ 2-1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Electrostatic Warning ................................................................................2-1 Requirements............................................................................................2-1 Layout .......................................................................................................2-1 Jumper Settings ........................................................................................2-2 Powering Up the Board .............................................................................2-2 Measuring Current Consumption on the AT91M42800A ..........................2-2 Testing the AT91EB42 Evaluation Board..................................................2-3 Section 3 The On-board Software ........................................................................ 3-1 3.1 3.2 3.3 3.4 3.5 3.6 3.7 AT91EB42 Evaluation Board ....................................................................3-1 Boot Software Program.............................................................................3-1 Programmed Default Memory Mapping ....................................................3-2 Flash Uploader..........................................................................................3-2 Power-down Demonstration......................................................................3-3 Angel Debug Monitor ................................................................................3-3 Programmed Default Speed......................................................................3-3 Section 4 Circuit Description................................................................................. 4-1 4.1 4.2 4.2.1 I/O Expansion Connector ...................................................................4-1 4.2.2 EBI Expansion Connector ..................................................................4-1 4.2.3 JTAG Interface ...................................................................................4-1 4.3 4.4 4.5 4.6 4.7 AT91EB42 Evaluation Board User Guide AT91M42800A Processor .........................................................................4-1 Expansion Connectors and JTAG Interface..............................................4-1 Memories ..................................................................................................4-2 Analog-to-digital Converter .......................................................................4-2 Power and Crystal Quartz .........................................................................4-2 Push-buttons, LEDs, Reset and Serial Interfaces.....................................4-3 Layout Drawing .........................................................................................4-3 i 1708C–ATARM–12-May-05 Table of Contents Section 5 Appendix A – Configuration Straps....................................................... 5-1 5.1 5.2 5.3 5.4 5.5 Functional Pin Assignment .......................................................................5-1 Configuration Straps (CB1 - 23, JP1 - 8) ..................................................5-2 Power Consumption Measurement Strap (JP5) .......................................5-7 Ground Links (JP6) ...................................................................................5-7 Increasing Memory Size ...........................................................................5-7 Section 6 Appendix B – Schematics..................................................................... 6-1 6.1 Schematics ...............................................................................................6-1 Section 7 Appendix C – Bill of Materials............................................................... 7-1 Section 8 Appendix D – Flash Memory Mapping .................................................................................. 8-1 ii 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Section 1 Overview 1.1 Scope The AT91EB42 Evaluation Board enables real-time code development and evaluation. It supports the AT91M42800A. This user guide focuses on the AT91EB42 Evaluation Board as an evaluation and demonstration platform. ! Section 1 provides an overview. ! Section 2 describes how to set up the evaluation board. ! Section 3 details the on-board software. ! Section 4 contains a description of the circuit board. ! Section 5 and Section 6 are two appendixes covering configuration straps and schematics, including pin connectors. 1.2 Deliverables The evaluation board is delivered with a DB9 plug-to-DB9 socket straight-through serial cable to connect the target evaluation board to a PC. A bare power lead with a 2.1 mm jack on one end for connection to a bench power supply is also delivered. The evaluation board is also delivered with a CD-ROM that contains an evaluation version of the software development toolkit, the documentation that outlines the AT91 microcontroller family and the AT91 C Library. The evaluation board is capable of supporting different kinds of debugging systems, using an ICE interface or the on-board Angel™ Debug Monitor. 1.3 The AT91EB42 The board consists of an AT91M42800A together with several peripherals: Evaluation Board ! Two serial ports ! Reset push-button ! An indicator that memorizes a reset event ! Four user-defined push-buttons ! Eight LEDs ! A 256K bytes 16-bit SRAM (upgradeable to 1M byte) AT91EB42 Evaluation Board User Guide 1-1 Rev. 1708C–ATARM–12-May-05 Overview ! A 2M bytes 16-bit Flash (of which 1M byte is available for user software) ! A 4M bytes Serial DataFlash ! An analog-to-digital converter with SPI access ! 2 x 32-pin EBI expansion connectors ! 2 x 32-pin I/O expansion connectors ! 20-pin JTAG interface connector If required, user-defined peripherals can also be added to the board. See Section 5 for details. Figure 1-1. AT91EB42 Evaluation Board Block Diagram AT91M42800A Reset Controller JTAG ICE Connector 8K Bytes RAM SRAM ARM7TDMI Processor ASB 32.768 kHz Crystal Push-buttons Clock Generator Watchdog Flash AMBA Bridge Interrupt Controller System Timer Reset Controller EBI Expansion Connector EBI LEDs PIO APB I/O Expansion Connector Timer Counters Serial DataFlash Reset SPI 10-bit ADC 4 Channels PIO 2.1 mm DC Power Socket Power Supply Fast-charge Controller 1-2 1708C–ATARM–12-May-05 Serial Ports RS232 Transceivers DB9 Serial Connectors Battery Connector AT91EB42 Evaluation Board User Guide Section 2 Setting Up the AT91EB42 Evaluation Board 2.1 Electrostatic Warning The AT91EB42 Evaluation Board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. 2.2 Requirements In order to set up the AT91EB42 Evaluation Board, the following requirements are needed: ! The AT91EB42 Evaluation Board itself ! The DC power supply capable of supplying 7V to 12V at 1A (not supplied) 2.3 Layout Figure 2-1 shows the layout of the AT91EB42 Evaluation Board. Figure 2-1. Layout of the AT91EB42 Evaluation Board AT91EB42 Evaluation Board User Guide 2-1 Rev. 1708C–ATARM–12-May-05 Setting Up the AT91EB42 Evaluation Board 2.4 Jumper Settings JP1 is used to boot standard or user programs. For standard operations, set it in the STD position. JP8 is used to select the core power supply of the AT91M42800A. Operations at 2V are not supported on the current silicon. For more information about jumpers and other straps, see Section 5. 2.5 Powering Up the Board DC power is supplied to the board via the 2.1 mm socket (J1) shown in Figure 2-2. The polarity of the power supply is not critical. The minimum voltage required is 7V. A battery is supplied on the AT91EB42. It supplies all on-board devices in the same way that the external DC power operates. A battery fast-charge controller is provided onboard with a fast-charge indicator (D28), as shown in Figure 2-1. Figure 2-2. 2.1 mm Socket positive (+) or negative (-) 2.1 mm Connector The board has a voltage regulator providing +3.3V. The regulator allows the input voltage to range from 7V to 12V. When you switch the power on, the red LED marked POWER lights up. If it does not, switch off and check the power supply connections. 2.6 Measuring Current Consumption on the AT91M42800A 2-2 1708C–ATARM–12-May-05 The board is designed to generate the power for the AT91 product, and only the AT91 product, through the jumpers JP5 (VDDIO) and JP8 (VDDCORE). This feature enables measurements of the consumption of the AT91 product to be made. See Section 5 for further details. AT91EB42 Evaluation Board User Guide Setting Up the AT91EB42 Evaluation Board 2.7 Testing the To test the AT91EB42 Evaluation Board, perform the following procedure: AT91EB42 1. Hold down the SW1 button and power-up the board, or generate a reset and wait for the light sequence on each LED to complete. All the LEDs light. Evaluation Board 2. Release the SW1 button. The LEDs D1 to D8 light up in sequential order. If all the LEDs light up twice, this indicates an error. The LEDs represent the following test functions: ! D1 for the internal SRAM ! D2 for the external SRAM ! D3 for the external Flash ! D4 reserved ! D5 for the SPI DataFlash® ! D6 reserved ! D7 for the USART ! D8 for ADC with SPI access During a complete test cycle, each LED flashes once to inform the user that the corresponding function has been successfully tested. If an error is detected, all the LEDs will light up twice. After a complete test cycle, the embedded self-test software called Functional Test Software (FTS) restarts a new cycle. AT91EB42 Evaluation Board User Guide 2-3 1708C–ATARM–12-May-05 Setting Up the AT91EB42 Evaluation Board 2-4 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Section 3 The On-board Software 3.1 AT91EB42 The AT91EB42 Evaluation Board embeds an AT49BV162A Flash memory device proEvaluation Board grammed with default software. Only the lowest 8 x 8 KB sectors are used. The remaining sectors are user definable, and can be programmed using one of the Flash downloader “Flash_16x4” solutions offered in the AT91 Library. When delivered, the Flash memory device contains: ! the Boot Software Program ! the Functional Test Software (FTS) ! the Flash Uploader ! the power-down function ! the Angel Debug Monitor ! a default user boot with a default application (LED Swing Application) The Boot Software Program and Functional Test Software (FTS) are in sectors 0 and 1 of the Flash. These sectors are not locked in order to provide an easy on-board upgrade. The user must avoid overwriting these sectors. 3.2 Boot Software Program The Boot Software Program configures the AT91M42800A, and thus controls the memory and other board components. The Boot Software Program is started at reset if JP1 is in the STD position. If JP1 is in the USER position, the AT91M42800A boots from address 0x01100000 in the Flash, which must have a user-defined boot. The Boot Software Program first initializes the master clock frequency at 32.768 MHz. The EBI then executes the REMAP procedure and checks the state of the buttons as described below. ! When the SW1 button is pressed: – All the LEDs light up together. – The D1 LED remains lit when SW1 is released. – The Functional Test Software (FTS) is started. AT91EB42 Evaluation Board User Guide 3-1 Rev. 1708C–ATARM–12-May-05 The On-board Software ! When the SW2 button is pressed: – Reserved ! When the SW3 button is pressed: – All the LEDs light up together. – The D3 LED remains lit when SW3 is released. – The Flash uploader is activated. ! When the SW4 button is pressed: – All the LEDs light up together. – The D4 LED remains lit when SW4 is released. – The power-down function is activated. ! When no buttons are pressed: – Branch at address 0x01006000. – The Angel Debug Monitor starts from this address by recopying itself in external SRAM. 3.3 Programmed Default Memory Mapping Table 3-1 defines the mapping defined by the boot program. Table 3-1. Memory Map Part Name Start Address End Address Size Device U1 0x01000000 0x011FFFFF 2M Bytes Flash AT49BV162A U2 - U3 0x02000000 0x0203FFFF 256K Bytes SRAM The Boot Software Program, Functional Test Software (FTS), Flash Uploader and the power-down demonstration are in sectors 0 and 1 of the Flash device. Sectors 3 to 8 support the Angel Debug Monitor. Sector 24 at address 0x0110 0000 can be programmed with a user application to be debugged. This sector is mapped at address 0x0100 0000 (or 0x0 after a reset) when the jumper JP1 is in the USER position. 3.4 Flash Uploader The Flash Uploader included in the EB42 Boot Software is the same Flash Uploader factory-programmed in the Flash-based AT91 devices, the AT91FR4042 and the AT91FR40162/S. The Flash Uploader allows programming to Sector 24 of Flash through a serial port. Either of the on-chip USARTs can be used by the Flash Uploader. To boot from the application downloaded in Sector 24, the downloading address must be 0x01100000. The boot starts the Flash Uploader if the SW3 button is pressed at reset. The procedure is as follows: 1. Connect the Serial A or B port of the AT91EB42 Evaluation Board to a host PC Serial port using the straight serial cable provided. 2. Start the AT91Loader.exe program available in the AT91 Library on the host computer. The AT91 Loader must be configured beforehand. See the “Readme.pdf” file in folder <CDROM>\ToolBox\host_tools\Dev PC windev\AT91Loader\Doc. 3-2 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide The On-board Software 3. Check JP1 is in STD position. Power-on or press RESET, holding down the SW3 button simultaneously. Wait for all LEDs to light up together and then release SW3. LED3 remains lit. If the AT91Loader is configured in automatic mode, the download starts. Wait for the download to end. 4. Put JP1 in USER position and press RESET button. The application downloaded starts. For further details, see the application note “Crystal Oscillator and PLL Considerations for AT91M42800A and AT91M55800A”, literature number 1740A. A PLL Filter Calculator Tool is also available. See “Automatic_calculation_xls.zip”. 3.5 Power-down Demonstration The AT91EB42 Evaluation Board is delivered with a battery unit to supply the board when the main power supply is removed. The aim of the power-down demonstration is to save the battery unit. When the power-down function is started, the main clock of the AT91M42800A is switched to the slow clock oscillator at 32.768 kHz. The processor is put in IDLE mode and all peripheral clocks are turned off. The power-down mode is indicated by LED4 flashing every 10 seconds. The boot starts the power-down demonstration if the SW4 button is pressed at reset. The procedure is as follows: 1. Power-on or press RESET, holding down the SW4 button simultaneously. 2. Wait for all LEDs to light up and then release SW4. LED4 remains lit for 3 seconds and light off. Then LED4 flashes every 10 seconds. 3. Press SW4 or the reset button to re-start the board. When SW4 is pressed, the power-down demonstration re-configures the AT91M42800A to run at 32.768 MHz and branches to Angel. 3.6 Angel Debug Monitor The Angel Debug Monitor is located in the Flash from 0x01006000 up to 0x01011FFF. The boot program starts it if no button is pressed at reset. When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used by Angel is from 0x02020000 to 0x0203FFFF, i.e., the highest half part of the SRAM. The Angel on the AT91EB42 Evaluation Board can be upgraded regardless of the version programmed on it. Note that if the debugger is started through ICE while the Angel monitor is on, the Advanced Interrupt Controller (AIC) and the USART channel are enabled. 3.7 Programmed Default Speed As the speed of the AT91M42800A is programmable, the Boot Software Program initializes the device to run as fast as possible, i.e., at 32.768 MHz. The Boot Software Program and the Functional Test Software are run at this speed. When Angel is started, it also runs at 32.786 MHz and the user should not modify this frequency without reprogramming the speed of the USARTs. AT91EB42 Evaluation Board User Guide 3-3 1708C–ATARM–12-May-05 The On-board Software 3-4 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Section 4 Circuit Description 4.1 AT91M42800A Processor Figure 6-1 on page 6-2 shows the AT91M42800A. The footprint is for a 144-pin TQFP package. Strap CB20 enables the user to choose between the standard ICE debug mode and the JTAG boundary scan mode of operation. The operating mode is defined by the state of the JTAGSEL input detected at reset. Jumper JP5 (see Figure 6-8 on page 6-9 in Section 6, “Appendix B – Schematics”) can be removed by the user to allow measurement of the consumption of the whole microcontroller (V DDIO and V DDCORE ). Jumper JP8 can be removed to measure the core microcontroller consumption (VDDCORE). 4.2 Expansion Connectors and JTAG Interface The two expansion connectors, I/O expansion connector and EBI expansion connector, and the JTAG interface are described below. 4.2.1 I/O Expansion Connector The I/O expansion connector makes the general-purpose I/O (GPIO) lines, VCC3V3 and Ground, available to the user. Configuration straps CB2, CB3, CB4, CB11, CB13, CB14, CB15, CB17, CB18 and CB19 are used to select between the I/O lines being used by the evaluation board or by the user via the I/O expansion connector. 4.2.2 EBI Expansion Connector The schematic (see Figure 6-4 on page 6-5 in Section 6, “Appendix B – Schematics”) also shows the bus expansion connector. The 32 x 2 connector allows the user to access the data bus, all control bus signals and oscillator output. VCC3V3 and ground are also available on this connector. The I/O and EBI expansion connectors’ pinout and position are compatible with other AT91 evaluation boards (except the I/O expansion connector pinout and position of the EB40) so that users can connect their prototype daughter boards to any of these evaluation boards. Configuration strap CB1, when open, allows the user to connect the EBI expansion connector to the MPI expansion connector of an AT91EB63 evaluation board without any conflict. 4.2.3 JTAG Interface An ARM®-standard 20-pin box header (P5) is provided to enable connection of an ICE interface to the JTAG inputs on the AT91. This allows code to be developed on the board without using system resources such as memory and serial ports. AT91EB42 Evaluation Board User Guide 4-1 Rev. 1708C–ATARM–12-May-05 Circuit Description 4.3 Memories The schematic (see Figure 6-3 on page 6-4 in Section 6, “Appendix B – Schematics”) shows one AT49BV162A 2M bytes 16-bit Flash, one AT45DB321 4M bytes serial DataFlash, one AT24C512 64K bytes EEPROM, one AT25256 32K Bytes EEPROM and two 128K/512K x 8 SRAM devices. Note: The AT24C512 64K byte EEPROM and the AT25256 32K byte EEPROM are not mounted. 4.4 Analog-to-digital Converter An on-board 4-channel, 10-bit ADC device (TLV1504 by Texas Instruments) is featured on the AT91EB42. This device is interfaced to the AT91M42800A via the SPIA peripheral and embeds its voltage reference equal to 2V. Four channels are used on the AT91EB42 for the following measurements: ! Channel 0 is used to measure the temperature near the 32.768 kHz crystal. ! Channel 1 is dedicated to supervise the External Power Supply. ! Channel 2 is dedicated to supervise the Battery Power Supply. ! Channel 3 is dedicated to supervise the VDDCORE. Each ADC channel is fitted on the I/O extension connector and can be used in other applications. For this reason, each ADC input can be taken away from its function by its appropriate jumper. 4.5 Power and Crystal Quartz The AT91M42800A master clock is derived from a 32.768 kHz crystal. The on-chip lowpower oscillator together with two PLL-based frequency multipliers and the prescaler results in a programmable master clock between 500 Hz and 33 MHz. A temperature sensor has been placed near the 32.768 kHz crystal and the analog signal output has been fitted to Channel 0 of the on-board ADC. Two sets of components for the PLL filters are fitted by default on the board (see Figure 6-6 on page 6-7 in Section 6, “Appendix B – Schematics”). They are calculated to provide a 16.77 MHz (PLLA: multiplier factor of 512 and settling time of 600 µs) or a 32.768 MHz (PLLB: multiplier factor of 1000 and settling time of 6 ms) master clock frequency. For further details, see the application note “Crystal Oscillator and PLL Considerations for AT91M42800A and AT91M55800A”, literature number 1740A. A PLL Filter Calculator Tool is also available. See “Automatic_calculation_xls.zip”. The voltage regulator provides 3.3V to the board and will light the red POWER LED (D11) when operating. Power can be applied via the 2.1 mm connector to the regulator in either polarity because of the diode-rectifying circuit. Another regulator allows the user to power the AT91M42800A core with 3.3V or 1.8V by means of the JP8 jumper. All functions can be supplied by the on-board battery. A connector permits the user to disconnect the battery. The type of battery and connection to be used are shown in Section 6 of this user guide. This type of battery will ensure the power supply of the board for approximately one hour. A battery fast-charge controller is provided on-board to charge it and maintains the full charge. The user is warned while the fast-charge is started via the on-board indicator (D28) or a logical signal on I/O port PB18. 4-2 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Circuit Description 4.6 Push-buttons, LEDs, Reset and Serial Interfaces The IRQ0, TIOA0, PB6 and PB21 switches are debounced and buffered. A supervisory circuit has been included in the design to detect and consequently reset the board when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be changed depending on the board production series. The supervisory circuit also provides a debounced reset signal. This device can also generate the reset signal in case of watchdog timeout as the pin NWDOVF of the AT91M42800A is connected to its input MR. The assertion of this reset signal will light up the red RESET LED (D10). By pressing the CLEAR RESET push-button (S1), the LED can be turned off. Another supervisory circuit initializes separately the microcontroller-embedded JTAG/ICE interface when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be changed, depending on the board production series. These separated reset lines allow the user to reset the board without resetting the JTAG/ICE interface while debugging. The schematic (see Figure 6-5 on page 6-6 in Section 6, “Appendix B – Schematics”) also shows eight general-purpose LEDs connected to Port B PIO pins (PB8 to PB15). Two 9-way D-type connectors (P3/4) are provided for serial port connection. Serial Port A (P3) is used primarily for host PC communication and is a DB9 female connector. TXD and RXD are swapped so that a straight-through cable can be used. CTS and RTS are connected together, as are DCD, DSR and DTR. Serial Port B (P4) is a DB9 male connector with TXD and RXD obeying the standard RS-232 pinout. Apart from TXD, RXD and ground, the other pins are not connected. LEDs are connected to the TX and RX signals of both serial ports and show activity on these serial links. A MAX3223 device (U10) and associated bulk storage capacitors provide RS-232 level conversion. 4.7 Layout Drawing The layout diagram (see Figure 6-1 on page 6-2 in Section 6, “Appendix B – Schematics”) shows an approximate floor plan for the board. This has been designed to give the lowest board area, while still providing access to all test points, jumpers and switches on the board. The board is provided with four mounting holes, one at each corner, into which feet are attached. The board has two signal layers and two power planes. AT91EB42 Evaluation Board User Guide 4-3 1708C–ATARM–12-May-05 Circuit Description 4-4 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Section 5 Appendix A – Configuration Straps 5.1 Functional Pin Assignment The following table provides a list of each peripheral used on the AT91EB42 Evaluation Board. Table 5-1. Functional Pin Assignment Pin Designation Function Used on the AT91EB42 NCS0 Chip Select signal for the Flash Memory (AT49BV162A) NCS1 Chip Select signal for the Static RAMs PB7/TIOA0 General I/O input line for the User Interface Push-button (SW1) PA0/IRQ0 General I/O input line for the User Interface Push-button (SW2) PB6/TCLK0 General I/O input line for the User Interface Push-button (SW3) PB21/TCLK5 General I/O input line for the User Interface Push-button (SW4) PB8/TIOB0 General I/O output line for the User Interface Light Indicator (Led D1) PB9/TCLK1 General I/O output line for the User Interface Light Indicator (Led D2) PB10/TIOA1 General I/O output line for the User Interface Light Indicator (Led D3) PB11/TIOB1 General I/O output line for the User Interface Light Indicator (Led D4) PB12/TCLK2 General I/O output line for the User Interface Light Indicator (Led D5) PB13/TIOA2 General I/O output line for the User Interface Light Indicator (Led D6) PB14/TIOB2 General I/O output line for the User Interface Light Indicator (Led D7) PB15/TCLK3 General I/O output line for the User Interface Light Indicator (Led D8) PA6/TXD0 To the RS232 Transceiver device and dedicated for the Serial A socket PA7/RXD0 To the RS232 Transceiver device and dedicated for the Serial A socket PA9/TXD1/NTRI To the RS232 Transceiver device and dedicated for the Serial B socket PA10/RXD1 To the RS232 Transceiver device and dedicated for the Serial B socket PB18/TCLK4 General I/O input line to detect the fast-charge mode for the battery PB16/TIOA3 General I/O output line to generate SCL signal dedicated for a two wire bus access AT91EB42 Evaluation Board User Guide 5-1 Rev. 1708C–ATARM–12-May-05 Appendix A – Configuration Straps Table 5-1. Functional Pin Assignment (Continued) 5.2 Configuration Straps (CB1 - 23, JP1 - 8) Pin Designation Function Used on the AT91EB42 PB17/TIOB3 General I/O input/output line to generate SDA signal dedicated for a two wire bus access PA13/MOSIA To generate SPI bus Access to the DataFlash, EEPROM and ADC devices PA12/MISOA To generate SPI bus Access to the DataFlash, EEPROM and ADC devices PA11/SPCKA To generate SPI bus Access to the DataFlash, EEPROM and ADC devices PA14/NPCSA0/NSSA Chip Select signal for the SPI device: DataFlash PA15/NPCSA1 Chip Select signal for the SPI device: EEPROM PA16/NPCSA2 Chip Select signal for the SPI device: ADC PA3/IRQ3 Interrupt line from the ADC device By adding the I/O and EBI expansion connectors, users can connect their own peripherals to the evaluation board. These peripherals may require more I/O lines than available while the board is in its default state. Extra I/O lines can be made available by disabling some of the on-board peripherals or features. This is done using the configuration straps detailed below. Some of these straps present a default wire (notified by the default mention) that must be cut before soldering the strap. CB1 Closed On-board PB5/A23/CS4 Signal (1) Open Note: AT91 PB5/A23/CS4 signal is not connected to the EBI expansion connector (P1-B21). This authorizes users to connect the EBI expansion connector of this board to the MPI expansion connector of an AT91EB63 Evaluation Board without conflicting problems. 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB3 Closed Open Note: 5-2 1708C–ATARM–12-May-05 AT91 PB5/A23/CS4 signal is connected to the EBI expansion connector (P1-B21). On-board IRQ3 Signal (1) AT91 IRQ3 signal is connected to the external ADC (U20 pin 4). AT91 IRQ3 signal is not connected to the external ADC (U20 pin 4). This authorizes the user to use this signal for other applications via the I/O Expansion connector (P2 - A8). 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. AT91EB42 Evaluation Board User Guide Appendix A – Configuration Straps CB4 Closed ADC Chip Select Line (1) Open Note: ADC (U20) control lines disabled. This authorizes users to connect the corresponding chip select line to their own resources via the I/O expansion connector. 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB5 Closed Standard Power Supply Supervisory Enabling (1) Open Note: 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. VDDCORE Voltage Monitoring (1) Open Note: 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. Battery Power Supply Supervisory Enabling (1) Open Note: Open Note: AT91EB42 Evaluation Board User Guide Battery power supply is supervised by the ADC (U20) channel 2 via a resistor bridge. The ratio is set to 0.24 so that the battery voltage range can be supervised (5.5V to 6.2V). Battery power supply is not connected to the ADC (U20) channel 2. This authorizes the user to connect the corresponding ADC channel to their own resources via the I/O expansion connector. 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB8 Closed The ADC channel 3 is connected at the VDDCORE power supply. This allows the user to tune the frequency clock according to the core voltage. The ADC channel 3 is not connected and it is available on the I/O expansion connector for user application. CB7 Closed Standard power supply is supervised by the ADC (U20) channel 1 via a resistor bridge. The ratio is set to 0.1013 so that the standard power supply can be supervised up to 15V. Standard power supply is not connected to the ADC (U20) channel 1. This allows the user to connect the corresponding ADC channel to their own resources via the I/O expansion connector. CB6 Closed ADC (U20) control lines enabled. Ambient Temperature Monitoring (1) The ADC channel 0 is connected to a temperature sensor near the 32.768 kHz crystal. This allows the user to evaluate the frequency drift according to the ambient temperature. The ADC channel 0 is not connected and it is available on the I/O expansion connector for the user application. 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. 5-3 1708C–ATARM–12-May-05 Appendix A – Configuration Straps CB9 On-board Boot Chip Select Closed (1) Open AT91 NCS0 select signal is not connected to the Flash memory. This authorizes the user to connect the corresponding select signal to their own resources via the EBI expansion connector. Note: 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB10 Closed Flash Reset (1) Open 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB12 Boot Mode Strap Configuration (1) BMS AT91 input pin is set for the microcontroller to boot on an external 16-bit memory at reset. Closed BMS AT91 input pin is set for the microcontroller to boot on an external 8-bit memory at reset. Open Note: 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB13, CB14 Closed (1) Open Two-wire Interface EEPROM Enabling EEPROM communication enabled. EEPROM communication disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. Note: 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB15 Closed Serial DataFlash Enabling (1) Open AT91 NPCSA0 select signal is connected to the serial DataFlash memory. AT91 NPCSA0 select signal is not connected to the serial DataFlash memory. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. Note: 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB16 Control Line for the Internal Oscillator Closed Disables the internal low frequency oscillator. Open Note: 1708C–ATARM–12-May-05 The on-board reset signal is connected to the Flash NRESET input. The on-board reset signal is not connected to the Flash NRESET input. Note: 5-4 AT91 NCS0 select signal is connected to the Flash memory. (1) Enables the internal oscillator. 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. AT91EB42 Evaluation Board User Guide Appendix A – Configuration Straps CB17 Closed SPI EEPROM Enabling (1) EEPROM communication enabled. Open Note: EEPROM communication disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB18 R(eturn) TCK ICE Signal Synchronization 1 - 2(1) The TCK and RTCK ICE signals are not synchronized with MCKO. 2-3 The TCK signal from the JTAG interface can be synchronized with the MCKO signal and returns to the JTAG interface (RTCK). Note: 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB19 Closed PB18 End of Fast Charge Signal (1) AT91 PB18 signal is connected to the battery charger (U16), NFASTCHG output pin. Open Note: AT91 PB18 signal is not connected to the battery charger (U16), NFASTCHG output pin. This authorizes users to connect the corresponding signal to their own resources via the I/O expansion connector. 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB20 1-2 JTAGSEL (1) AT91 standard ICE debug feature enabled 2-3 Note: IEEE 1149.1 JTAG boundary scan feature enabled 1. Hardwired default position: To cancel this default configuration, the user should cut the wire on the board. CB21, CB22, CB23 Charger Device (U16): Programming the Battery Number of Cells Number of Cells CB21 CB22 CB23 1 Open Closed Closed 2 Open Open Closed 4 Closed Open Closed 5(1) Open Closed Open 6 Open Open Open 8 Closed Open Open AT91EB42 Evaluation Board User Guide 5-5 1708C–ATARM–12-May-05 Appendix A – Configuration Straps 5-6 1708C–ATARM–12-May-05 JP1 User or Standard Boot Selection 2-3 The first half part of the Flash memory is accessible at its base address. 1-2 The second half part of the Flash memory is accessible at its base address. This authorizes users to download their own application software in this part and to boot on it. JP2 Push Button Enabling Open SW1-4 inputs to the AT91 are valid. Closed SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. JP3 User or Standard Boot Selection Open The RS-232 transceivers are enabled. Closed The RS-232 transceivers are disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. JP4 PME Function (Protect Mode Enable) Closed The AT91M42800A is in Protect Mode. Open This is the default mode on the AT91EB42. The AT91M42800A internal registers are accessible in all processor modes. JP8 Core Power Supply Selection 2-3 The AT91 core is powered by 3.3V power supply. 1-2 Not supported on the current microcontroller revision. AT91EB42 Evaluation Board User Guide Appendix A – Configuration Straps 5.3 Power Consumption Measurement Strap (JP5) The JP5 strap enables connection of an ammeter to measure the AT91M42800A global consumption (VDDCORE and VDDIO) when VDDCORE power supply is derived from VDDIO (JP8 in 3V3 position). Core consumption can be measured by connecting another ammeter between JP8 1 - 2 or 2 - 3, depending on the power supply used to power the core. 5.4 Ground Links (JP6) The JP6 strap allows the user to connect the electrical and mechanical grounds. 5.5 Increasing Memory Size The AT91EB42 Evaluation Board is supplied with two 128K x 8 SRAM memories. If, however, the user needs more than 256K bytes of memory, the devices can be replaced with two 512K x 8 3.3V 10/15 ns SRAMs, giving a total of 1024K bytes. The following references for the 512K x 8 SRAM are available. Manufacturer Reference Samsung KM68V4002BJ-15 in 36-SOJ-400 package IDT 71V424-15 in 36-pin 400-mil SOJ package (SO36-1) AT91EB42 Evaluation Board User Guide 5-7 1708C–ATARM–12-May-05 Appendix A – Configuration Straps 5-8 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Section 6 Appendix B – Schematics 6.1 Schematics The following schematics are appended: ! Figure 6-1 – PCB Layout ! Figure 6-2 – AT91EB42 Blocks Overview ! Figure 6-3 – EBI Memories ! Figure 6-4 – I/O and EBI Expansion Connectors ! Figure 6-5 – Push-buttons, LEDs and Serial Interface ! Figure 6-6 – AT91M42800A ! Figure 6-7 – Reset and JTAG Interface ! Figure 6-8 – Power Supply and Battery Charger ! Figure 6-9 – SPI Memories, Two-wire Interface Memories and SPI ADC The pin connectors are indicated on the schematics: ! P1 = EBI Expansion Connector (Figure 6-4) ! P2 = I/O Expansion Connector (Figure 6-4) ! P3 = Serial A (Figure 6-5) ! P4 = Serial B (Figure 6-5) ! P5 = JTAG Interface (Figure 6-7) AT91EB42 Evaluation Board User Guide 6-1 Rev. 1708C–ATARM–12-May-05 Appendix B – Schematics Figure 6-1. PCB Layout 6-2 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide AT91EB42 Evaluation Board User Guide power supply / battery SUPPLY and RTC SA VE micro / Rst / Wchdog / JTAG co. MICROCONTROLLE R memories connected on EBI EBI MEMORIES PB18 EBI_[0..42] IOB_[0..53] PB22 A20 EBI_[0..42] IOB_48 IOB_[0..57] EBI_[0..42 ] IOB_[0..57] IOB_[0..57] EBI_[0..42 ] IOB_[0..53] IOB_52 IOB_32 EBI_[0..42 ] IOB_[0..57] IOB_[0..57] IOB_0 IOB_[9..10] IOB_[6..7] VIN[1..4] NPCSA2 NPCSA1 NPCSA0 MOSIA MISOA SPCKA IRQ3 PB19 PB20 PB16 PB17 NRST Extension Connectors EBI_[0..42] IOB_[0..57] SERIAL MEMOR IES INPUT / OUTPUT ON BOARD EXTENSIONS CONNECTORS Serial Connectors / P.B. / LED PA0 PA[9..10] PA[6..7] PB[6..15] SERIAL MEMORIES IOB_[54..57] EBI_41 IOB_[36..45] IOB_16 IOB_15 IOB_14 IOB_13 IOB_12 IOB_11 IOB_3 IOB_49 IOB_50 IOB_46 IOB_47 IOB_[0..57] EBI_[0..42 ] Appendix B – Schematics Figure 6-2. AT91EB42 Blocks Overview 6-3 1708C–ATARM–12-May-05 6-4 1708C–ATARM–12-May-05 1 1 NRST CB9 2 CB10 CB24 1 2 VCC3V3 100k 9 10 14 13 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 12 NCS0_126 11 28 NRST_1 2 R2 2 2 100k R1 VCC3V3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 1 NCS0 NWE NOE A20B 1 A[0..19] AT49BV162A RESET CE WE OE NC NC NC NC / Vpp A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 U1 GND GND VCCQ VCC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 2Mbytes FLASH ME MORY 46 27 47 37 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 12 11 9 8 U6D U6C 7 C89 10 74LVC02AD 100nF 1 VCC3V3 13 74LVC02AD 1 C5 100nF VCC3V3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D[0..15] NWR0 VCC3V3 NCS1 C1 100nF VCC3V3 NWR0 VCC3V3 NCS1 A19 D2 D3 D0 D1 A18 A19 D2 D3 D0 D1 A18 A5 A6 A7 A8 A1 A2 A3 A4 A5 A6 A7 A8 A1 A2 A3 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 128k 512k 36 NC 35 A18 34 A17 33 A16 32 A15 31 OE 30 D7 29 D6 28 GND 27 VCC 26 D5 25 D4 24 A14 23 A13 22 A12 21 A11 20 A10 19 NC 128k 512k 44 NC 43 NC 42 NC 41 A18 40 A17 39 A16 38 A15 37 OE 36 D7 35 D6 34 GND 33 VCC 32 D5 31 D4 30 A14 29 A13 28 A12 27 A11 26 A10 25 NC 24 NC 23 NC A20 IDT71424S10PH NC NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC NC U4 IDT71V424S10Y A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 U2 A13 A12 A11 A10 A9 A17 A16 A15 A14 A13 A12 A11 A10 A9 A17 A16 A15 A14 D5 D4 D7 D6 D5 D4 D7 D6 VCC3V3 VCC3V3 C3 100nF VCC3V3 NWR1 NCS1 IOB_32 3 2 74LVC02 1 NWR1 GND NCS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 1 36 NC 35 A18 34 A17 33 A16 32 A15 31 OE 30 D7 29 D6 28 GND 27 VCC 26 D5 25 D4 24 A14 23 A13 22 A12 21 A11 20 A10 19 NC 128k 512k A20B CTL6 CTL4 CTL5 NRD NCS1 NCS0 VCC3V3 NOE NUB NWE VCC3V3 C4 100nF VCC3V3 NRD NRST NRD CTL2 NWR0 D13 D12 D15 D14 D13 D12 D15 D14 NWR1 A13 A12 A11 A10 A9 A17 A16 A15 A14 A13 A12 A11 A10 A9 A17 A16 A15 A14 CTL1 CTL0 44 NC 43 NC 42 NC 41 A18 40 A17 39 A16 38 A15 37 OE 36 D7 35 D6 34 GND 33 VCC 32 D5 31 D4 30 A14 29 A13 28 A12 27 A11 26 A10 25 NC 24 NC 23 NC IDT71424S10PH NC NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC NC U5 USER BOOT 2 128k 512k IDT71V424S10Y A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 U3 STD BOOT D[0..15] EBI_[0..15] JP1 jumper_3P A[0..19] 3 A5 A6 A7 A8 A1 A2 A3 A4 A5 A6 A7 A8 A1 A2 A3 A4 CTL[0..6] A19 D10 D11 D8 D9 A18 A19 D10 D11 D8 D9 A18 EBI_[16..35] EBI_[36..42] VCC3V3 U6A VCC3V3 EBI_[0..42 ] NRD layout for TSSOP 400mil. C2 100nF VCC3V3 NRD layout for SOJ 400mil. 1Mbytes ( two 512kX8 ) SRAM with two footprints or 256kbytes ( two 128kX8 ) SRAM with two footprints. Appendix B – Schematics Figure 6-3. EBI Memories 14 AT91EB42 Evaluation Board User Guide I/O Extension Connector PA[0..29] CTL[0..6] P1A P1B P2A P2B PB[0..23] CTL4 NCS0 VCC3V3 A0 A2 A4 A6 A[0..19] PB[0..23] NCS2 A8 A10 A12 A14 VCC3V3 A16 A18 PB2 PB4 CS7 CS5 D0 D2 D4 D6 VCC3V3 D8 D10 D12 D14 GND NWR0 / NWE NRD / NOE PA25 / MCK0 NCS0 PB0 / NCS2 VCC3V3 A0 / NLB A2 A4 A6 GND A8 A10 A12 A14 VCC3V3 A16 A18 PB2 / A20 / CS7 PB4 / A22 / CS5 GND D0 D2 D4 D6 VCC3V3 D8 D10 D12 D14 GND EBI Ext. Con. GND NWR1 / NUB NWAIT NCS1 PB1 / NCS3 NRST A1 A3 A5 A7 GND A9 A11 A13 A15 VCC3V3 A17 A19 PB3 / A21 / CS6 PB5 / A23 / CS4 GND D1 D3 D5 D7 VCC3V3 D9 D11 D13 D15 GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 CTL1 CTL3 VCC3V3 PA0 PA1 NCS1 CTL6 CTL5 A1 A3 A5 A7 NCS3 PB1 PA2 PA3 PB[0..23] PA25 PB0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A[0..19] CTL0 CTL2 A9 A11 A13 A15 CB1 VCC3V3 PA28 PA29 VCC3V3 PA26 VCC3V3 A17 A19 CS4_1 1 VCC3V3 PA4 VIN[1..4] CS6 2CS4 PB3 PB5 PA18 PA19 PA20 PA21 PA27 D1 D3 D5 D7 VCC3V3 D9 D11 D13 D15 PA17 PA16 VCC3V3 EBI Ext. Con. VIN1 VIN2 VIN3 VIN4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 GND VCC3V3 PA0 / IRQ0 PA1 / IRQ1 GND PA2 / IRQ2 VCC3V3 PA3 / IRQ3 GND PA4 / FIQ VCC3V3 PA28 / HOLDA PA29 / HOLD VCC3V3 PA26 GND VIN1 VIN2 VIN3 VIN4 GND PA18 / SPCKB PA19 / MISOB PA20 / MOSIB PA21 / NPCSB0 / NSSB PA27 / BMS GND PA17 / NPCSA3 PA16 / NPCSA2 GND VCC3V3 GND I/O Ext. Conn. PB6 / TCLK0 PB7 / TIOA0 PB8 / TIOB0 PB9 / TCLK1 PB10 / TIOA1 PB11 / TIOB1 PB12 / TCLK2 PB13 / TIOA2 PB14 / TIOB2 PB15 / TCLK3 PB16 / TIOA3 PB17 / TIOB3 PB18 / TCLK4 PB19 / TIOA4 PB20 / TIOB4 PB21 / TCLK5 PB22 / TIOA5 PB23 / TIOB5 PA5 / SCK0 PA6 / TXD0 PA7 / RXD0 PA8 / SCK1 PA9 / TXD1 / NTRI PA10 / RXD1 PA22 / NPCSB1 PA23 / NPCSB2 PA24 / NPCSB3 PA12 / MISOA PA13 / MOSIA PA11 / SPCKA PA14 / NPCSA0 / NSSA PA15 / NPCSA1 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PA5 PA6 PA7 PA8 PA9 PA10 PA22 PA23 PA24 PA12 PA13 PA11 PA14 PA15 I/O Ext. Conn. D[0..15] EBI_[0..15] PA[0..29] IOB_[0..29] A[0..19] EBI_[16..35] PB[0..23] IOB_[30..53] CTL[0..6] EBI_[36..42] VIN[1..4] IOB_[54..57] EBI_[0..42] B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 Figure 6-4. I/O and EBI Expansion Connectors AT91EB42 Evaluation Board User Guide EBI Extension Connector IOB_[0..57] Appendix B – Schematics 6-5 1708C–ATARM–12-May-05 SW3 1 2 TP 33 VAL_RS232 PA7 PA10 VCC3V3 D31 R75 100R VCC3V3 D32 R76 100R 100R R74 D30 PB6 PB21 8 11 RXD0 RXD1 TX D0 TX D1 C22 100nF C18 100nF VCC3V3 PB7 6 TCLK5 TCLK0 TIOA0 IRQ0 14 1 15 10 13 12 6 5 4 2 INVALID R1IN R2IN T1OUT T2OUT V- V+ PB21 FORCEOFF 100nF C16 R44 100k MAX3223EC AP U10 FORCEON EN R1OUT R2OUT T1IN T2IN C2- C2+ C1- C1+ R45 100k 100k 100k GND R17 100K jumper_NO JP3 VCC3V3 PA[9..10] PA6 PA9 100R VCC3V3 100nF 2 PA0 3 R43 R42 VCC3V3 VCC VALID RS232on IOB PA[9..10] PA[6..7] R73 100k D29 R16 VCC3V3 1 C12 EN 74LV125D R5 100k jumper_NO JP2 18 PA7 47nF C15 VCC3V3 13 12 10 9 4 5 1 2 U9 1 2 19 PA[6..7] PA0 SW4 R15 100K VCC3V3 C11 47nF VALBP VALBP 7 C14 47nF SW2 100K R4 VCC3V3 14 100K R14 VCC3V3 C10 47nF 100K R3 VCC3V3 20 11 16 9 17 8 7 3 VCC3V3 VCC3V3 4 6 8 PB9 PB10 PB11 100nF 100nF VCC3V3 C19 C17 17 PB15 22pF C26 22pF C27 100nF C13 GND SIGNAL EN EN U8 74LV244D 15 13 PB13 PB14 11 PB12 19 2 1 PB8 VALBP 20 PA0 SW1 TP 33 1708C–ATARM–12-May-05 TP 33 6-6 TP 33 VCC3V3 VCC3V3 3 5 7 9 12 14 16 18 R10 R11 R12 R13 D5 D6 D7 D8 TX1 RX1 22pF C23 RX0 22pF C24 R9 D4 22pF R8 D3 TX0 R7 D2 C20 DTR0 DCD0 DSR0 R6 D1 VCC3V3 Red LED PB[6..15] C21 22pF CTS0 RTS0 100R 100R 100R 100R 100R 100R 100R 100R 1 6 2 7 3 8 4 9 5 1 6 2 7 3 8 4 9 5 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 Sub D 9b M P4 10nF C25 Sub D 9b F P3 PB[6..15] Usart 1: SERIAL B Usart 0: SERIAL A Appendix B – Schematics Figure 6-5. Push-buttons, LEDs and Serial Interface 10 AT91EB42 Evaluation Board User Guide 1 CB12 PA27 VCC3V3 AT91EB42 Evaluation Board User Guide 61 60 59 58 57 56 55 54 53 D15 D14 D13 52 51 50 GND VDDIO 49 48 D12 D11 D10 D9 D8 D7 D6 D5 D4 PB0 / NCS2 PB1 / NCS3 GND GND D[0..15] GND VDDIO A[0..19] PB12 / TCLK2 PB11 / TIOB1 PB10 / TIOA1 PB9 / TCLK1 PB8 / TIOB0 PB7 / TIOA0 PB6 / TCLK0 EBI_[0..15] 70 69 68 67 66 65 64 63 62 EBI_[16..35] PB21 / TCLK5 PB20 / TIOB4 PB19 / TIOA4 PB18 / TCLK4 PB17 / TIOB3 PB16 / TIOA3 PB15 / TCLK3 PB14 / TIOB2 PB13 / TIOA2 100nF VDDIO VDDCORE CTL[0..6 ] VDDIO GND 74 73 76 75 83 82 81 80 79 78 77 72 71 PB[0..23] PB23 PB22 VDDIO VDDCORE C51 100nF PA6 PA5 PA4 PA3 PA2 PA1 PA0 PA10 PA9 PA8 PA7 89 88 87 86 85 84 PA16 PA15 PA14 PA13 PA12 PA11 95 94 93 92 91 90 VDDIO PA17 VDDIO 98 97 96 VDDIO VDDCORE GND GND PB23 / TIOB5 PB22 / TIOA5 PA6 / TXD0 PA5 / SCK0 PA4 / FIQ PA3 / IRQ3 PA2 / IRQ2 PA1 / IRQ1 PA0 / IRQ0 GND VDDIO PA10 / RXD1 PA9 / TXD1 / NTRI PA8 / SCK1 PA7 / RXD0 PA16 / NPCSA2 PA15 / NPCSA1 PA14 / NPCSA0 / NSSA PA13 / MOSIA PA12 / MISOA PA11 / SPCKA GND VDDIO PA17 / NPCSA3 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 105 104 103 102 101 100 99 106 PB[0..23] PA[0..29] XOUT VT CB16 JTAGSEL NWDOVF NRST IOB_[30..53] IOB_[0..29] 100nF 10% C47 100nF 10% C46 IOB_[0..53] C48 1µF 10% R20 R21 680R 1% 120R 1% 1 2 1 2 PLL filter B 10nF 10% C45 2 PLL filter A C44 1 2 Y1 32,768kHz C43 1 100K R48 R18 R19 1K50 1% 100R 1% 1 2 1 2 JTAGSEL NWDOVF CTL5 Guard ring PLLRCB Guard ring PLLRCA XIN Guard ring VCC3V3 2 EBI_[36..42] C50 PA25 / MCKO PA24 / NPCSB3 PA23 / NPCSB2 PA22 / NPCSB1 PA21 / NPCSB0 / NSSB PA20 / MOSIB PA19 / MISOB PA18 / SPCKB 108 107 100nF VDDCORE EBI_[0..42 ] NWDOVF PA27 / BMS C49 100nF PLLRCA VDDPLL PLLRCB VDDPLL VDDCORE VDDIO GND XIN XOUT GND 35 36 VDDCORE VDDIO D0 D1 D2 D3 NWAIT NOE / NRD NWE / NWR0 NUB / NWR1 NCS0 NCS1 31 32 33 34 143 144 D0 D1 D2 D3 141 142 CS7 CS6 CS5 CS4 PB0 PB1 135 136 137 138 139 140 / / / / CTL3 CTL2 CTL0 CTL1 CTL4 CTL6 PA29 / PME A20 A21 A22 A23 134 VDDIO GND / / / / VDDIO 132 133 NRST PA28 VDDIO GND PA29 130 131 A19 PB2 PB3 PB4 PB5 CTL5 2 PB2 PB3 PB4 PB5 PA28 JTAGSEL TMS TDI TDO TCK NTRST 24 25 124 125 126 127 128 129 1 26 27 28 29 30 JTAGSEL JTAG2 JTAG1 JTAG4 JTAG3 JTAG0 VDDIO PA27 122 123 1 A19 120 VDDIO 121 TQFP 144 NWDOVF A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 116 117 118 119 VDDIO VDDCORE 100nF C29 C28 VDDIO 14 15 16 17 18 19 20 21 22 23 VDDPLL AT91M42800A PLLRCB U11 PLLRCA 2 VDDIO GND 112 113 114 115 GND GND 1 12 13 VT XIN XOUT PA26 VDDIO GND GND 111 NLB / A0 A1 A2 A3 A4 A5 A6 A7 A8 PA26 1 2 PA[0..29] 109 110 3 4 5 6 7 8 9 10 11 CTL[0..6 ] JTAG[0..4] 100K R71 1 2 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A0 A1 A2 A3 A4 A5 A6 A7 A8 CTL3 PB[0..23] JTAG[0..4] NWAIT 2 1 VDDIO C30 100nF 100K R46 JP4 PA29 2 VDDCORE VCC3V3 VCC3V3 1 1 PB[0..23] A[0..19] 2 BMS 2 Default boot Mode : 16 Bits 100K R41 Appendix B – Schematics Figure 6-6. AT91M42800A PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 VDDIO D15 D14 D13 47 46 45 44 43 42 41 40 39 VDDIO D12 D11 D10 D9 D8 D7 D6 D5 D4 38 37 VDDCORE 6-7 1708C–ATARM–12-May-05 Appendix B – Schematics 6-8 1708C–ATARM–12-May-05 2 4 8 20 18 16 14 12 10 6 3 5 7 9 19 17 15 13 11 JTAG Connector (Front View) 1 Figure 6-7. Reset and JTAG Interface AT91EB42 Evaluation Board User Guide AT91EB42 Evaluation Board User Guide C61 1µF 10% 1 2 5 2 LT1503CS8-1.8 SHDN/SS C1- C1+ GND C2- C2+ Vout 7 8 6 1 C62 1µF 10% 10µF / 16V + C63 C103 10nF 11 Vin U17 TLO Temp CC 3 10nF 6 THI GND Vbatt- 1K R58 1K 7 5 Vlimit REF FASTCHG V+ Batt- 12 4 3 10 9 Vbatt+ Vbatt+ Vbatt- R62 2R49 / 1% JUMPER_NO 2 v+ 2 1 CB22 1 CB23 2 Vbatt- 1 CB21 JUMPER_NO 5 cel. NiCd Timeout 264mn 1µF 10% C64 PGM1 PGM0 PGM3 PGM2 Batt+ 2 U16 MAX 712/713 VCC1V8 VDDIO 1K R79 1 3 2 JP8 jumper_3P VDDCORE=3.3V Rth1 Rth2 D26 1N4001 VDDCORE=1.8V D25 1N4001 7 3 10µH L1 4 R61 10K CTN 6V / 300mAH BT1 1N5817 D15 100nF C54 I Vddcore C60 3,3nF / 10% SENSE 2 4 T˚C C102 1 R60 Rth2 R59 1K 1 16 8 15 150R DRV 1µF 10% C101 2 Rth1 V+ R30 Q1 2N6109 SYNC SHTDN 3 U15 LT1507CS8-3.3 1 VCC3V3 1 2 1µF 10% C100 C99 10µF / 25V 10nF C98 14 CB19 VIN 10MQ100N 10MQ100N C57 10µF / 25V 5 4 VSW 8 100R D28 2 jumper_NO JP6 D19 D18 1N4001 VIN 6 PB18 VCC3V3 R29 1 SMT6T15CA D17 10MQ100N D16 10MQ100N 2 GND R77 680R D14 VIN_1 1N914 VC C59 22pF / 25V VINplug2 1000m A/30V VIN D12 BOOST Jack Dia.2.1mm J1 22pF / 25V VIN1F D24 1 C55 VINplug1 F1 Vps VDDIO VDDA VDDPLL VDDCORE TP3 Test Point Corner 3 Test Point Corner 2 TP4 Test Point Corner 4 TP2 I Vddio Test Point Corner 1 + 1 2 TP1 100µF / 10V C58 JP5 jumper_NO VCC3V3 Appendix B – Schematics Figure 6-8. Power Supply and Battery Charger 13 6-9 1708C–ATARM–12-May-05 6-10 1708C–ATARM–12-May-05 C6 1µF GND C7 1µF LM61BIM3 Vout 3 1 2 R69 750-1% R70 2.37K1% VBATT+ CB14 VCC3V3 C110 100nF 1 CB13 11 12 3 4 5 6 7 8 9 1 2 GND NC NC NC NC NC NC WP VCC AT24C512W1-10SC-2.7 TWD TWCK NC NC NC NC NC NC NC A0 A1 U19 10 18 17 16 15 14 13 19 20 VIN3 VIN2 VIN1 IRQ3 MOSIA 1 CB3 VIN3 VIN2 VIN1 8 7 6 5 4 3 2 SPCKA 1 MISOA 2 NPCSA2 CB4 TLV1504 A2 A1 A0 VCC IOC(INT) SCLK SDI SDO U20 1 2 Serial EEPROM memory on PIO Not Mounted VIN[1..4] IOB_54 IOB_55 IOB_56 2 1 2 CB5 1 CB7 1 C105 100nF 2 CB8 2 R31 100k VCC3V3 A3 CSTART GND PWDN FS REFM REFP CS C67 100nF VCC3V3 9 10 11 12 13 14 15 16 VIN4 + VIN4 IOB_57 1µF C106 CB6 VCC3V3 C104 10µF / 16V R65 100K VCC3V3 IOB_14 MOSIA MISOA SPCKA NRST 2 R67 750-1% TWD TWCK VCC U23 R68 6.65K-1% VPS 2 1 VCC3V3 PB16 PB17 R51 100K VCC3V3 CB15 R81 7.5K1% 9.09K1% R80 VDDCORE NPCSA1 C90 100nF 1 2 1 CB17 2 9 10 11 12 4 5 6 5 2 6 1 VCC GND HOLD WP 4 7 3 8 AT25256W-10SC-2.7 SI SO SCK CS U21 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 7 R52 100K GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC Data Flash Memory AT45DB321-TC NC NC NC NC NC NC NC CS SI SO SCK RDY/BUSY RESET WP U18 Not Mounted Serial EEPROM memory on SPIA R66 100k VCC3V3 NPCSA1_1 MOSIA MISOA SPCKA VCC3V3 100k R40 MOSIA MISOA SPCKA 13 15 16 14 NRST NPCSA0 R32 100k 1 2 3 R34 100k VCC3V3 R53 100K 100nF C70 VCC3V3 VCC3V3 C65 100nF VCC3V3 Appendix B – Schematics Figure 6-9. SPI Memories, Two-wire Interface Memories and SPI ADC 1 AT91EB42 Evaluation Board User Guide Section 7 Appendix C – Bill of Materials Figure 7-1. Bill of Materials for AT91EB42 Item Qty. Reference Part Designation Manufacturer 1 1 BT1 6V battery NiCd pack battery 6V – 300 mAh Saft 2 2 JP1, JP8 3-point jumper Jumper 3 2 JP4, JP5 2-point Jumper CB24(*) 2-point strap Soft-soldering jumper 4 5 30 C1, C2, C3, C4, C5, C12, C13, C16, C17, C18, C19, C22, C28, C29, C30, C49, C50, C51, C52, C53, C54, C65, C67, C70, C89, C90, C94, C96, C105, C110 100 nF Ceramic Y5 10V AVX 6 3 C6, C7, C106 1 µF Ceramic Y5V 10V AVX 7 4 C10, C11, C14, C15 47 nF Ceramic X7R 10V AVX 8 5 C20, C21, C23, C24, C26, C27 22 pF Ceramic NPO 10V AVX 9 14 C25, C71, C72, C73, C74, C75, C76, C77, C82, C83, C86, C98, C102, C103 10 nF Ceramic X7R 16V AVX 10 7 C43, C78, C79, C80, C81, C84, C85 10 pF Ceramic NPO 10V 5% AVX 11 1 C44 4 - 25 pF Varicap. serie TZBX4 MURATA 12 1 C45 10 nF CeramicX7R 10V 10% AVX 13 2 C46, C47 100 nF CeramicX7R 10V 10% AVX 14 3 C48, C100, C101 1 µF CeramicX7R 10V 10% AVX 15 2 C55, C59 22 pF CeramicX7R 25V AVX 16 2 C57, C99 10 µF Tantalum (TPS ou OS-CON) 25V ESR < 0.5Ω AVX 18 1 C58 100 µF Tantalum (TPS ou 593D) 10V ESR < 0.5Ω AVX 20 1 C60 3.3 nF Ceramic X7R/25V/10% SIEMENS 21 3 C61, C62, C64 1 µF CeramicX7R 10V 10% AVX 22 2 C104, C63 10 µF Tantalum 16V 10% TAJ AVX 23 9 D1, D2, D3, D4, D5, D6, D7, D8, D11 Red LED Red LED H.R. 3mm T1 7mcd 60° HP AT91EB42 Evaluation Board User Guide 7-1 Rev. 1708C–ATARM–12-May-05 Appendix C – Bill of Materials Figure 7-1. Bill of Materials for AT91EB42 (Continued) Item Qty. Reference Part Designation Manufacturer 24 2 D10, D28 Red LED Red CMS LED HP 25 2 D30, D29 Orange LED SMT Orange LED HP 26 2 D32, D31 Green LED SMT Green LED HP 27 1 D12 1N914 Diode Fairchild 28 1 D14 SMT6T15CA Transil 12.8V/600W/VBRmin. 14.3V ST 29 1 D15 1N5817 Schottky 1A/0.45V ST 30 7 D16, D17, D18, D19, D24, D25, D26 10MQ100N Rectifier diode 0.62V/0.77A I.R. 31 1 F1 1000 mA/30V Fuse rarm 1000 mA/30V Polyswitch 32 1 J1 Jack diam. 2.1mm Jack socket diam. 2.1 mm LUMBERG 33 1 L1 10 µH Self 10 µH @ 1A and 500 kHz COILCRAFT 34 1 P3 Sub D 9b F Sub D 9b F, female socket, right angle, mechanical strength, locking ETEC 35 1 P4 Sub D 9b M Sub D 9b M, male socket, right angle, mechanical strength, locking ETEC 36 1 P5 HE10 2x10 HE10 2 x 10, low-profile T&B 37 1 Q1 MJD45H11 Transistor PNP MOTOROLA 38 29 R1, R2, R3, R4, R5, R14, R15, R16, R17, R25, R27, R31, R32, R34, R40, R41, R42, R43, R44, R45, R46, R48, R51, R52, R53, R65, R66, R71, R78 100K Resistors @ 5% Vishay 39 15 R6, R7, R8, R9, R10, R11, R12, R13, R23, R24, R29, R73, R74, R75, R76 100R Resistor @ 5% Vishay 40 1 R18 1K50 1% Resistor @ 1%, 125 mW Vishay 41 1 R19 100R 1% Resistor @ 1%, 125 mW Vishay 42 1 R20 680R 1% Resistor @ 1%, 125 mW Vishay 43 1 R21 120R 1% Resistor @ 1%, 125 mW Vishay 44 1 R30 150R Resistor @ 1%, 125 mW Vishay 45 1 R58 10K Resistor @ 1%, 125 mW Vishay 46 1 R59, R60, R79 1k Resistor @ 1%, 125 mW Vishay 47 1 R61 10K CTN Therm. CTN 10k @ 25°C, B = 3730°K SIEMENS 48 4 R62d, R62c, R62b, R62a (****) 10R Resistor 0.25W 5% RC01 49 1 R67 7.5K1% Resistor @ 1%, 125 mW Vishay 50 1 R68 66.5K1% Resistor @ 1%, 125 mW Vishay 51 1 R69 31.6K1% Resistor @ 1%, 125 mW Vishay 52 1 R70 100K1% Resistor @ 1%, 125 mW Vishay 53 1 R77 (****) 6R8 Resistor @ 1%, 125 mW Vishay 54 1 R80 90.9K1% Resistor @ 1%, 125 mW Vishay 55 1 R81 75K1% Resistor @ 1%, 125 mW Vishay 56 4 SW1, SW2, SW3, SW4 TP 33 Push-button with black cap APEM 7-2 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Appendix C – Bill of Materials Figure 7-1. Bill of Materials for AT91EB42 (Continued) Item Qty. Reference Part Designation Manufacturer 57 1 SW5 TP 33 Push-button with red cap APEM 58 1 S1 B.P. SMT Push-button J.RENAUD 59 4 TP1, TP2, TP3, TP4 Test Point Corner SMT Test point 60 1 U1 (1) AT49BV162A-70TI 2-Mbyte x 16-bit Flash Atmel (2) IDT71V424S10Y Static memory: 128K x 8 - 15 ns/36-pin 400 mil SOJ IDT 61 2 U3, U2 62 2 U5, U4(2) IDT71424S10PH Static memory: 128K x 8 - 15 ns/44-pin TSOP Type II IDT 63 1 U6 74LVC02AD QUAD 2-INPUT NOR Gate TI Philips 64 1 U8 74LV244D Buffer TI Philips 65 1 U9 74LV125D Tri-state buffer TI Philips 66 1 U10 MAX3223ECAP Driver RS232 + ESD “E” MAXIM 67 1 U11 AT91M42800A 32-bit Arm/Thumb Microcontroller Atmel 68 1 U12 74LVC74AD D flip-flop (LVC Serial) TI Philips 69 2 U13, U14 MAX6315US30D4-T Circuit LVD-reset Maxim 70 1 U15 LT1507CS8-3.3 Voltage Regulator DC/DC Linear Technology 71 1 U16 MAX 712/713 NiCd/NiMH Battery Fast-charge Controllers MAXIM 72 1 U17 LTC 1503CS8-2 Voltage Regulator DC/DC Linear Technology AT45DB321-TC Serial DataFlash Atmel (3) 73 1 U18 75 1 U20 TLV1504 4 analog-to-digital converter with SPI protocol (D package) TI 77 1 U23 LM61BIM3 2.7V, SOT-23 Temperature Sensor NS 78 1 U30 74LCX74 D flip-flop (LCX serie) TI Philips 79 1 Y1 32,768kHz Crystal 32.768 kHz/50 ppm MICRO CRYSTAL 80 2 P1, P2 2 x 32 male HE10 Header 2.54 mm FCI 81 4 R62d, R62c, R62b, R62a 14R7 Resistor 0.25W 5% RC01 82 1 R77 680 Resistor 0.25W 5% RC01 Vishay 83 2 P1, P2 2 x 32-point, male HE13 Header 2.54 mm FCI 84 4 R62d, R62c, R62b, R62a 14R7 Resistor 0.25W 5% RC01 4-point socket, male 2.54 mm pitch KK® vertical friction lock header, series 6410/7395 Molex 4-point connector, female 2.54 mm pitch KK crimp terminal housing, series 6471 Molex (4) 85 1 Socket to be bonded to BT1 86 1 Connector to supply battery(1) Notes: 1. The AT91EB42 board is equipped with SRAM U2/U3 or U4/U5. The difference is in the type of case used. The selection is made based on availability. 2. U18 is wired according to availability. 3. Cannot be seen in Figure 6-1. AT91EB42 Evaluation Board User Guide 7-3 1708C–ATARM–12-May-05 Appendix C – Bill of Materials 7-4 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Section 8 Appendix D – Flash Memory Mapping Figure 8-1 shows the embedded software mapping after the remap. It describes the location of the different programs in the AT49BV162A Flash memory and the division into sectors. Figure 8-1. EB42 Flash Memory Software Mapping 0x011FFFFF Not Used 15 Sectors (64K Bytes/Sector) 1M Byte User Mode 0x01100000 LED Swing Application (Example) Not Used 14 Sectors (64K Bytes/Sector) Not Used 1 Sector (64K Bytes/Sector) Angel Debug Monitor 5 Sectors (8K Bytes/Sector) + 1 Sector (64K Bytes/Sector) Free Sector for Boot Upgrade 1 Sector (8K Bytes/Sector) Flash Uploader Functional Test Software Boot Program 2 Sectors (8K Bytes/Sector) 0x01011FFF 0x01006000 0x01005FFF 1M Byte Standard Mode 0x01004000 0x01000000 AT91EB42 Evaluation Board User Guide 8-1 Rev. 1708C–ATARM–12-May-05 Appendix D – Flash Memory Mapping 8-2 1708C–ATARM–12-May-05 AT91EB42 Evaluation Board User Guide Document Details Title AT91EB42 Evaluation Board User Guide Literature Number 1708 Revision History Version C Publication Date: 12-May-05 Revisions since last issue All pages Removed all references to SRAM Downloader Removed all references to two-wire interface Changed all occurrences of AT49B1604(A) or AT49BV1614(A) or AT49BV16x4 to AT49BV162A. Section 1.3 Removed references to: 64K bytes of EEPROM with two-wire access 32K bytes of SPI EEPROM Fig.1-1 Removed the 2 "SERIAL EEPROM" boxes Section 2.7 Changed - D4 for the EEPROM with two-wire access to D4 reserved - D6 for the SPI EEPROM to D6 reserved Section 3.2 Replaced the description of "When SW2 button is pressed" by Reserved Section 3.4 Removed Section 3.5 Replaced AT91F40816 and AT91FR4081 by AT91FR4042 and AT91FR40162/S Section 4.3 Added note: The AT24C512 64K byte EEPROM and the AT25256 32K byte EEPROM are not mounted. Appendix A Removed the table describing CB24 Figure 6-3 EBI Memories Changed AT49BV16X4-90TC to AT49BV162A for U1 part. Figure 6-9 Changed figure names into SPI and TWI Memories. For U19 & U21 part: Add note NOT MOUNTED Table 7-1 Removed items 74 & 76 Item 60 / "Part" Column --> changed to AT49BV162A-70TI 1 1708C–ATARM–12-May-05 Figure 8-1 Updated with new memory sizes 2 1708C–ATARM–12-May-05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are ® and others are registered trademarks, and others are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 1708C–ATARM–12-May-05