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AT91EB55 Evaluation Board
..............................................................................................
User Guide
Table of Contents
Section 1
Overview ............................................................................................... 1-1
1.1
1.2
1.3
Scope ........................................................................................................1-1
Deliverables ..............................................................................................1-1
The AT91EB55 Evaluation Board .............................................................1-1
Section 2
Setting Up the AT91EB55
Evaluation Board .................................................................................. 2-1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Electrostatic Warning ................................................................................2-1
Requirements............................................................................................2-1
Layout .......................................................................................................2-1
Jumper Settings ........................................................................................2-2
Powering Up the Board .............................................................................2-2
Measuring Current Consumption on the AT91M55800A ..........................2-2
Testing the AT91EB55 Evaluation Board..................................................2-2
Section 3
The On-board Software ........................................................................ 3-1
3.1
3.2
3.3
3.4
AT91EB55 Evaluation Board ....................................................................3-1
The Boot Software Program......................................................................3-1
Programmed Default Memory Mapping ....................................................3-2
The Angel Debug Monitor .........................................................................3-2
Section 4
Circuit Description................................................................................. 4-1
4.1
4.2
AT91M55800A Processor .........................................................................4-1
Expansion Connectors and JTAG Interface..............................................4-1
4.2.1
I/O Expansion Connector ...................................................................4-1
4.2.2
EBI Expansion Connector ..................................................................4-1
4.2.3
JTAG Interface ...................................................................................4-2
4.3
4.4
4.5
4.6
4.7
Memories ..................................................................................................4-2
ADC and DAC Peripheral Connections.....................................................4-2
Power and Crystal Quartz .........................................................................4-2
Push Buttons, LEDs, Reset and Serial Interface ......................................4-3
Layout Drawing .........................................................................................4-4
Section 5
Appendix A – Configuration Straps....................................................... 5-1
5.1
AT91EB55 Evaluation Board User Guide
Configuration Straps (CB1 – 15, JP1 – 9).................................................5-1
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Table of Contents
5.2
5.3
5.4
Power Consumption Measurement Straps (JP5, JP9) .............................5-4
Ground Links (JP6) ...................................................................................5-4
Increasing Memory Size ...........................................................................5-4
Section 6
Appendix B – Schematics..................................................................... 6-1
6.1
Schematics ...............................................................................................6-1
Section 7
Appendix C – Bill of Material ................................................................ 7-1
Section 8
Appendix D – Flash Memory ................................................................ 8-1
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AT91EB55 Evaluation Board User Guide
Section 1
Overview
1.1
Scope
The AT91EB55 Evaluation Board enables real-time code development and evaluation.
It supports the AT91M55800A.
This user guide focuses on the AT91 Evaluation Board as an evaluation and demonstration platform:
! Section 1 provides an overview.
! Section 2 describes how to setup the evaluation board.
! Section 3 describes the on-board software.
! Section 4 contains a description of the circuit board.
Appendixes A and B cover configuration straps and schematics including pin
connectors.
1.2
Deliverables
The evaluation board is supplied with a DB9 plug to DB9 socket straight through serial
cable to connect the target evaluation board to a PC. There is also a bare power lead
with a 2.1 mm jack on one end for connection to a bench power supply.
The evaluation board is also delivered with a CD-ROM that contains an evaluation version of Software Development Toolkit and the documentation that outlines the AT91
microcontroller family.
The evaluation board is capable of supporting different kinds of debugging systems
using an ICE interface or the on-board Angel Debug Monitor. Refer to the EB55 “Getting
Started” tutorial documents for recommendations on using the evaluation board in a full
debugging environment.
1.3
The AT91EB55
The board consists of an AT91M55800A, together with several peripherals:
Evaluation Board ! Two serial ports
! Reset push button
! An indicator which memorizes a reset appearance
! Memory clear for the reset indicator
! Four user-defined push buttons
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Overview
! Eight LEDs
! 256K byte of 16-bit SRAM (upgradable to 1 MB)
! 2M bytes of 16-bit Flash (of which 1 MB is available for user software)
! 4M bytes of Serial Data Flash (upgradeable to 16 MB)
! 2 x 32 pin EBI expansion connector
! 3 x 32 pin I/O expansion connector
! 20-pin JTAG interface connector
If required, user-defined peripherals can also be added to the board. See “Appendix A”
for details.
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AT91EB55 Evaluation Board User Guide
Overview
Figure 1-1. AT91EB55 Block Diagram
AT91M55800
SRAM
Flash
8K byte
RAM
Reset
Controller
ARM7TDMI
Processor
EBI
Expansion
Connector
EBI
JTAG-ICE
Connector
ASB
16 MHz
XTAL
Clock
Generator
AMBA
Bridge
LEDs
APB
Push
Buttons
Reset
Controller
Interrupt
Controller
PIO
Watchdog
Timer
Timer
Counters
Reset
SPI
I/O
Expansion
Connector
Temperature
Sensor
Wake Up
Push
Button
VDDIO and
VDDCORE
Power
Supply
Serial
Data Flash
APMC
VDDCORE
2
ADC
DAC
32.768 kHz
XTAL
RTC
Battery
Power
Supply
AT91EB55 Evaluation Board User Guide
Serial
Ports
RS232
Transceivers
DB9
Serial
Connectors
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Overview
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AT91EB55 Evaluation Board User Guide
Section 2
Setting Up the AT91EB55
Evaluation Board
2.1
Electrostatic
Warning
The AT91EB55 Evaluation Board is shipped in protective anti-static packaging. The
board must not be subjected to high electrostatic potentials. A grounding strap or similar
protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element.
2.2
Requirements
Requirements in order to set up the AT91EB55 Evaluation Board are:
! The AT91EB55 Evaluation Board itself
! DC power supply capable of supplying 7V to 12V @ 1 A (not supplied)
2.3
Layout
Figure 2-1 shows the layout of the AT91EB55 Evaluation Board.
Figure 2-1. Layout of the AT91EB55 Evaluation Board
128K x 8
512K x 8
128K x 8
AT91M55800A
33 AI
512K x 8
AT91EB55 Evaluation Board User Guide
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Rev. 1709C–ATARM–28-Apr-05
Setting Up the AT91EB55 Evaluation Board
2.4
Jumper Settings
JP1 is used to boot on standard or user programs. For standard operations, set it in the
STD position.
JP8 is used to select the core power supply of the AT91M55800A. Operations at 2V are
not supported on the current silicon.
For more information about jumpers and other straps, see Appendix A.
2.5
Powering Up the
Board
DC power is supplied to the board via the 2.1 mm socket (J1) shown below in Figure 22. The polarity of the power supply is not critical. The minimum voltage required is 7V.
Figure 2-2. 2.1 mm Socket
positive (+)
or
negative (-)
2.1 mm connector
The board has a voltage regulator providing +3.3V. The regulator allows the input voltage to be from 7V to 12V. When you switch the power on, the red LED marked
“POWER” will light up. If it does not, switch off and check the power supply connections.
The battery BT1 provides a 3V power supply to the Advanced Power Management Controller and the Real Time Clock (VDDBU). In order to power up this module, the user must
first close the JP9 jumper.
2.6
Measuring
Current
Consumption on
the
AT91M55800A
2.7
Testing the
In order to test the AT91EB55 Evaluation board, the following procedure should be
performed:
AT91EB55
Evaluation Board 1. Hold down the SW1 button and power up the board or generate a reset and wait
The board is designed to generate the power for the AT91 product only through the
jumpers JP5 (VDDIO), JP8 (VDDCORE) and JP9 (VDDBU). This feature enables measurements to be made on the current consumption of the AT91 product. See Appendix A for
further details.
for the light sequence on each LED to complete. All the LEDs light once and the
D1 LED remains lit.
2. Release the SW1 button. The LEDs D1 to D7 light up in sequential order. If an
error is detected, all the LEDs will light up twice.
The LEDs represent the following devices:
! D1 for the internal SRAM
! D2 for the external SRAM
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AT91EB55 Evaluation Board User Guide
Setting Up the AT91EB55 Evaluation Board
! D3 for the external Flash
! D4 reserved
! D5 for the SPI data flash
! D6 reserved
! D7 for the USART
! D8 for the ADC and DAC
If a test is not carried out, the corresponding LED remains unlit and the test sequence
restarts.
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Setting Up the AT91EB55 Evaluation Board
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AT91EB55 Evaluation Board User Guide
Section 3
The On-board Software
3.1
AT91EB55
The AT91EB55 Evaluation Board contains an AT49BV162A Flash device programmed
Evaluation Board with default software. Only the lowest eight 8-Kbyte sectors are used. The remaining
sectors are user-definable and can be programmed using one of the Flash downloader
solutions offered in the AT91 library.
When delivered, the Flash device contains:
! The Boot Software Program
! The Functional Test Software
! The Angel Debug Monitor
! A Default User Boot with a Default Application
The boot and FTS and are in sectors 0 and 1 of the Flash. These sectors are not locked
for an easy on-board upgrade. The user must avoid overwriting this sector.
3.2
The Boot
Software
Program
The Boot Software Program configures the AT91M55800A and thus controls the memory and other board devices.
The Boot Software Program is started at reset if JP1 is in the STD position. If JP1 is in
the USER position, the AT91M55800A boots from address 0x01010000 in the Flash,
which must have a user-defined boot.
The Boot Software Program first initializes the master clock frequency at 32 MHz, the
EBI, then executes the REMAP and checks the state of the buttons as described below.
As long as the SW1 button is pressed:
! All the LEDs light together
! The D1 LED remains lit until SW1 is released
! The Functional Test Software (FTS) is started
When the SW2 button is pressed:
! Reserved
! When the SW4 button is pressed:
! The shutdown function from AT91M55800A is activated. The power-up can be
achieved by pressing the S1 push button only (Wake-up function)
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The On-board Software
When no buttons are pressed:
! Branch at address 0x01006000
! The Angel Debug Monitor starts from this address by recopying itself in external
SRAM
3.3
Programmed
Default Memory
Mapping
The following table defines the mapping defined by the boot program.
Table 3-1. Memory Map
Part Name
Start Address
End Address
Size
Device
U1
0x01000000
0x011FFFFF
2-Mbyte
Flash AT49BV162A
U2 - U3
0x02000000
0x0203FFFF
256-Kbyte
SRAM
The Boot Software Program and FTS and are in sectors 0 and 1 of the Flash device.
Sectors 3 to 7 support the Angel Debug Monitor
Sector 24 at address 0x01100000 must be programmed with a boot sequence to be
debugged. This sector can be mapped at address 0x01000000 (or 0x0 after a reset)
when the jumper JP1 is in the USER position.
3.4
The Angel Debug The Angel Debug Monitor is located in the flash from 0x01006000 up to 0x0100FFFF.
The boot program starts it if no button is pressed.
Monitor
When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used by
Angel is from 0x02020000 to 0x0203FFFF, i.e., the highest half part of the SRAM.
The Angel on the AT91EB55 can be upgraded regardless of the version programmed on
it.
Note: If the debugger is started through ICE while the Angel monitor is on, the
Advanced Interrupt Controller (AIC) and the USART channel are enabled.
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AT91EB55 Evaluation Board User Guide
Section 4
Circuit Description
4.1
AT91M55800A
Processor
Figure 6-1 in “Appendix B – Schematics” shows the AT91M55800A. The footprint is for
a 176-pin TQFP package.
Strap CB15 enables the user to choose between the standard ICE debug mode and the
JTAG boundary scan mode of operation.
The operating mode is defined by the state of the JTAGSEL input detected at reset.
Jumper JP5 can be removed by the user to allow measurement of the current demand
by the whole microcontroller (VDDIO and VDDCORE). Jumper JP8 can be removed to measure the core microcontroller consumption (VDDCORE). See Figure 6-8. in “Appendix B –
Schematics.”
Jumper JP9 can be removed by the user to allow measurement of the current demand
by the APMC and RTC microcontroller modules (VDDBU). See Figure 6-8. in “Appendix B
– Schematics.”
4.2
Expansion
Connectors and
JTAG Interface
The two expansion connectors (I/O expansion connector and EBI expansion connector)
and the JTAG Interface are described below.
4.2.1
I/O Expansion
Connector
The I/O expansion connector makes the general purpose I/O (GPIO) lines, VCC3V3 and
Ground available to the user. Configuration straps CB2, CB3, CB4, CB5, CB6, CB13,
CB14 and CB17 are used to select between the I/O lines being used by the evaluation
board or by the user via the I/O expansion connector. The connector is not fitted at the
factory; however, the user can fit any 32 x 3 connector on a 0.1" (2.54 mm) pitch.
4.2.2
EBI Expansion
Connector
The schematic illustrated in Figure 6-4 in "Appendix B - Schematics" also shows the Bus
expansion connector, which, like the I/O expansion connector, is not fitted at the factory.
The user can fit any 32 x 2 connector on a 0.1" (2.54 mm) pitch to gain access to the
data, address, chip select, read/write, oscillator output and wait request pins. VCC3V3
and Ground are also available on this connector. Configuration strap CB1, when open,
allows the user to connect the EBI expansion connector to the MPI expansion connector
of an AT91EB63 evaluation board without fearing any conflict problem.
The I/O and EBI expansion connectors pin-outs and positions are compatible with the
other evaluation boards (except for the I/O expansion connector pin-out and position of
the EB40) so that users can connect their prototype daughter boards to any of these
evaluation boards. For the I/O expansion connector, rows A and B are position and
pinout compatible.
AT91EB55 Evaluation Board User Guide
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Rev. 1709C–ATARM–28-Apr-05
Circuit Description
4.2.3
JTAG Interface
An ARM-standard 20-pin box header (P5) is provided to enable connection of an ICE to
the JTAG inputs on the AT91. This allows code to be developed on the board without
using system resources such as memory and serial ports.
4.3
Memories
The schematics in Figure 6-3 and Figure 6-9 in "Appendix B – Schematics" show one
AT49BV162A 2-Mbyte 16-bit Flash, one AT24C512 64-Kbyte EEPROM, one AT25256
32-Kbyte EEPROM, two 128K/512K x 8 SRAM devices and four AT45DB321 4-Mbyte
serial data Flash devices.
The SPI devices are accessible through a 4 to 16 line decoder and by using the Chip
Select Decode feature of the AT91 SPI peripheral (PCSDEC bit of the SPI Mode
Register).
Note:
The AT91EB55 is fitted with two 128K x 8 SRAM devices and one AT45DB321 serial
DataFlash device (U21)AT24C512. The AT24C512 64-Kbyte EEPROM, and AT25256
32-Kbyte EEPROM are not fitted.
Strap JP1 shown on the schematic is used to select which part of 1-Mbyte of the flash is
to be accessed. This is to enable users to flash download their application in the second
part of the flash and to boot on it.
4.4
ADC and DAC
Peripheral
Connections
Two of the ADC and DAC channels are loop-backed together: DA0 on AD4 and DA1 on
AD0.
Two 2.5V voltage reference devices are fitted on the board and connected to the
DAVREF and ADVREF inputs, See Figure 6-6 in "Appendix B – Schematics". The user
can fit other voltage reference value devices from this family (REF19x from Analog
Devices) as the footprints are compatible.
A temperature sensor (LM61: Figure 6-6 in "Appendix B – Schematics") is connected to
the AD1 input and is placed near the 32.768 kHz crystal quartz. It enables the user to
take into account the frequency drift due to temperature evolutions using a software
program.
The VDDCORE with a resistor bridge (10 kΩ) provides the following value:
VDDCORE
------------------------------ c
2
This voltage can be measured by AD2 input and allows the user to select the running
clock accordingly.
4.5
Power and
Crystal Quartz
The board features two quartz crystals: a 32.768 kHz one connected to the RTC lowpower oscillator of the AT91M55800A and a 16 MHz one connected to the main
oscillator.
The AT91M55800A Master Clock can be derived from the 32.768 kHz crystal quartz or
the 16 MHz crystal quartz depending on the programming of the APMC registers. The
on-chip oscillators together with one PLL-based frequency multiplier and the prescaler
results in a programmable Master Clock between 500 Hz and 33 MHz.
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AT91EB55 Evaluation Board User Guide
Circuit Description
Components for the PLL filter are fitted by default on the board (Figure 6-6 in "Appendix
B – Schematics"). They are calculated to provide a 32 MHz (multiplier factor of 2 and
settling time of 160 µs) Master Clock frequency.
The Voltage Regulator provides 3.3V to the board and will light the red POWER LED
(D11) when operating.
This Voltage Regulator can be turned off by using the APMC shutdown feature when the
JP7 jumper is closed. See Figure 6-8 in "Appendix B – Schematics." A wake-up push
button (S1) is provided to exit this mode. Alternatively, the user can program a RTC
alarm to awake the voltage regulator.
Power can be applied via the 2.1 mm connector to the regulator in either polarity
because of the diode rectifying circuit. Another regulator allows the user to power the
AT91M55800A core with 3.3V or 2V by the mean of the JP8 jumper.
A 3V battery is provided on-board (Figure 6-8 in "Appendix B – Schematics") to power
the RTC and APMC (V DDBU ). It has been provided to ensure the power supply for
approximately 1 year.
4.6
Push Buttons,
LEDs, Reset and
Serial Interface
The IRQ0, TIOA0, PB17 and PB19 switches are debounced and buffered.
A supervisory circuit has been included in the design to detect and, consequently, reset
the board when the 3.3V supply voltage drops below a typical 3.0V threshold. Note that
the threshold can change, depending on the board production series. The supervisory
circuit also provides a debounced reset signal. This device can also generate the reset
signal in case of watchdog timeout as the pin NWDOVF of the AT91M55800A is connected on its input MR.
The assertion of this reset signal will light the red RESET LED D10 and if the CLEAR
RESET push button is pressed the LED D10 will unlight.
Another supervisory circuit separately initializes the microcontroller embedded
JTAG/ICE interface when the 3.3V supply voltage drops below a typical 3.0V threshold.
Note that this voltage can change depending on the board production series. The separated reset lines allow the user to reset the board without resetting the JTAG/ICE
interface while debugging. bill
An RC device has been fitted on-board to ensure a correct power-on reset for the battery power supply modules (V D D B U ) first power up or when V D D B U has been
disconnected. This RC network has been calculated to generate a valid 300 ms minimum pulse width NRSTBU signal.
The schematic, Figure 6-5 in "Appendix B - Schematics" also shows eight general-purpose LEDs connected to Port B PIO pins PB8 to PB15.
Two 9-way D-type connectors P3/4 are provided for serial port connection.
Serial Port A (P3) is used primarily for host PC communication and is a DB9 female connector. TXD and RXD are swapped so that a straight through cable can be used. CTS
and RTS are connected together as are DCD, DSR and DTR.
Serial Port B (P4) is a DB9 male connector with TXD and RXD obeying the standard
RS-232 pin-out. Apart from TXD, RXD and Ground, the other pins are not connected.
A MAX3223 device U10 and associated bulk storage capacitors provide RS-232 level
conversion.
AT91EB55 Evaluation Board User Guide
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Circuit Description
4.7
Layout Drawing
The layout diagram schematic shows an approximate floorplan for the board. This has
been designed to give the lowest board area, while still providing access to all test
points, jumpers and switches on the board. See Figure 6-1 in “Appendix B –
Schematics.”
The board is provided with four mounting holes, one at each corner, into which feet are
attached. The board has two signal layers and two power planes.
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AT91EB55 Evaluation Board User Guide
Section 5
Appendix A – Configuration Straps
5.1
Configuration
By adding the I/O and EBI expansion connectors, users can connect their own peripherStraps (CB1 – 15, als to the evaluation board. These peripherals may require more I/O lines than available
while the board is in its default state. Extra I/O lines can be made available by disabling
JP1 – 9)
some of the on-board peripherals or features. This is done using the configuration straps
detailed below. Some of these straps present a default wire (notified by the default mention) that must be cut before soldering the strap.
CB1
On-board NCS4 Signal
(1)
Closed
NCS4 signal is connected to the EBI expansion connector (P1 – B21)
Open
NCS4 signal is not connected to the EBI expansion connector (P1 – B21).
This authorizes users to connect the EBI expansion connector of this board to
the MPI expansion connector of an AT91EB63 evaluation board without
conflict problems.
CB2
ADC0 Trigger Input Command
(1)
Closed
ADC0 trigger input (AD0TRIG) is controlled by the PA4 PIO line.
Open
ADC0 trigger input (AD0TRIG) is not connected to the PA4 PIO line. This
authorizes users to connect the corresponding lines to their own resources via
the I/O expansion connector.
CB3
ADC1 Trigger Input Command
Closed(1)
ADC1 trigger input (AD1TRIG) is controlled by the PA7 PIO line.
Open
ADC1 trigger input (AD1TRIG) is not connected to the PA7 PIO line. This
authorizes users to connect the corresponding lines to their own resources via
the I/O expansion connector.
AT91EB55 Evaluation Board User Guide
5-1
Rev. 1709C–ATARM–28-Apr-05
Appendix A – Configuration Straps
CB4
Temperature Sensor Enabling
(1)
Closed
The temperature sensor device is connected to the ADC channel 1 (AD1)
input.
Open
The temperature sensor device is not connected to the ADC channel 1 (AD1)
input. This authorizes users to connect the corresponding ADC channel to their
own resources via the I/O expansion connector.
CB5
Analog Converter Peripherals Loopback
(1)
Closed
DAC Channel 0 is connected to ADC Channel 4 for test purposes.
Open
DAC Channel 0 is not connected to ADC Channel 4. This authorizes users to
connect the corresponding Analog Channels to their own resources via the I/O
expansion connector.
CB6
Analog Converters Peripherals Loopback
(1)
Closed
DAC Channel 1 is connected to ADC Channel 0 for test purposes.
Open
DAC Channel 1 is not connected to ADC Channel 0. This authorizes users to
connect the corresponding Analog Channels to their own resources via the I/O
expansion connector.
CB9
On-board Boot Chip Select
(1)
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1709C–ATARM–28-Apr-05
Closed
NCS0 select signal is connected to the Flash memory.
Open
NCS0 select signal is not connected to the Flash memory. This authorizes
users to connect the corresponding select signal to their own resources via the
EBI expansion connector.
CB10
Flash Reset
Closed(1)
The on-board reset signal is connected to the Flash RESET input.
Open
The on-board reset signal is not connected to the Flash RESET input.
CB11
Boot Mode Strap Configuration
(1)
Open
The BMS MCU input pin is set for the microcontroller to boot on an external
16-bit memory at reset.
Closed
The BMS MCU input pin is set for the microcontroller to boot on an external
8-bit memory at reset.
AT91EB55 Evaluation Board User Guide
Appendix A – Configuration Straps
CB13, CB14
(1)
I2C EEPROM Enabling
Closed
E2PROM communication is enabled.
Open
E2PROM communication is disabled. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
CB15
JTAGSEL
(1)
1–2
The MCU standard ICE debug feature is enabled.
2–3
IEEE 1149.1 JTAG boundary scan feature is enabled.
CB16
R(eturn) TCK ICE Signal Synchronization
1–2
The TCK signal from the JTAG interface can be synchronized with MCKO
signal and returns to the JTAG interface. (RTCK)
2 – 3(1)
The TCK and RTCK ICE signals are not synchronized with MCKO.
VDDCORE Voltage Measurement
CB17
(1)
Closed
The VDDCORE power supply is connected to the ADC Channel 2 (AD2) input
through a resistor bridge (divisor ratio 1/2).
Open
The VDDCORE power supply is not connected to the ADC Channel 2 (AD2) input.
This authorizes users to connect the corresponding ADC Channel to their own
resources via the I/O expansion connector.
CB18
Flash Configuration
Open
Should be open when an AT49BV162A is fitted on the board.
Closed
Should not be closed when an AT49BV162A is fitted on the board.
JP1
User or Standard Boot Selection
2–3
The first half of the Flash memory is accessible at its base address.
1–2
The second half of the Flash memory is accessible at its base address. This
authorizes users to download their own application software in this part and to
boot on it.
JP2
Push Button Enabling
Open
SW1-4 inputs to the AT91 are valid.
Closed
SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
AT91EB55 Evaluation Board User Guide
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1709C–ATARM–28-Apr-05
Appendix A – Configuration Straps
JP3
RS-232 Driver Enabled
Open
The RS-232 transceivers are enabled.
Closed
The RS-232 transceivers are disabled. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
JP7
Power Shut-down Feature
Open
The power supply shut-down feature is disabled.
Closed
The power supply shut-down feature is enabled. The user may shut-down the
board main power supply by using the APMC shut-down feature. The system
may be awakened by pushing the S1 Wake-Up push button or by programming
an alarm in the RTC module.
JP8
Core Power Supply Selection
2–3
The MCU core is powered by a 3.3V power supply.
1–2
Not supported on the current microcontroller revision.
Note:
5.2
Power
Consumption
Measurement
Straps (JP5, JP9)
1. Hardwired default position: To cancel this default configuration, cut (or place) the wire
(a jumper) on the board.
The JP5 strap enables the user to connect an ammeter to measure the AT91M55800A
global consumption (VDDCORE and VDDIO) when VDDCORE power supply is derived from
VDDIO (JP8 in 3V3 position). The user can measure the core consumption by connecting
another ammeter between JP8 1 – 2 or 2 – 3 depending on the power supply used to
power the core.
The JP9 strap enables the user to connect an ammeter to measure the AT91M55800A
APMC and RTC modules battery backup consumption (VDDBU).
5.3
Ground Links
(JP6)
The JP6 strap allows the user to connect the electrical and mechanical ground.
5.4
Increasing
Memory Size
The AT91EB55 evaluation board is supplied with two 128K bytes x 8 SRAM memories.
If, however, the user needs more than 256K bytes of memory, the devices can be
replaced with two 512K x 8, 3.3V, 10/15 ns SRAMs, giving in total 1024K bytes.
The AT91EB55 evaluation board is supplied with one 4-MB Serial Data Flash. If the
user needs more storage memory, 3 additional footprints are provided to fit AT45DB321
devices giving a total of 16M bytes.
5-4
1709C–ATARM–28-Apr-05
AT91EB55 Evaluation Board User Guide
Section 6
Appendix B – Schematics
6.1
Schematics
The following schematics are appended:
! Figure 6-1 PCB Layout
! Figure 6-2 AT91EB55 Blocks Synopsis
! Figure 6-3 EBI Memories
! Figure 6-4 I/O and EBI Expansion Connectors
! Figure 6-5 Push Buttons, LEDs and Serial Interface
! Figure 6-6 AT91M55800A
! Figure 6-7 Reset and JTAG Interface
! Figure 6-8 Power Supply
! Figure 6-9 SPI and I2C Memories
The pin connectors are indicated on the schematics:
! P1 = EBI Expansion – External Bus Interface (Figure 6-4)
! P2 = I/O Expansion Connector (Figure 6-4)
! P3 = Serial A - Serial Interface (Figure 6-5)
! P4 = Serial B– Serial Interface (Figure 6-5)
! P5 = JTAG Interface (Figure 6-7)
AT91EB55 Evaluation Board User Guide
6-1
Rev. 1709C–ATARM–28-Apr-05
Appendix B – Schematics
Figure 6-1. PCB Layout
128K x 8
512K x 8
128K x 8
AT91M55800A
33 AI
512K x 8
6-2
1709C–ATARM–28-Apr-05
AT91EB55 Evaluation Board User Guide
AT91EB55 Evaluation Board User Guide
power supply / battery
SUPPLY and RTC SAVE
micro / Rst / Wchdog / JTAG co.
MICRCONTROLLOR
MICROCONTROLLER
memories connected on EBI
MOSI
MISO
SPCK
IOB_54
SHDN
SHDN
EBI_[0..49]
IOB_[0..67]
NPCS[0..3]
SDA
SCL
EBI MEMORIES
EBI_[0..49]
SHDN
SHDN
IOB_[0..67]
SDA
SCL
IOB_54
EBI_[0..49]
IOB_[0..71]
NPCS[0..3]
EBI_[0..49]
IOB_[0..71]
SDA
SCL
MOSI
MISO
SPCK
EBI_[0..49]
IOB_[0..71]
IOB_[0..71]
NPCS[0..3]
IOB_[0..71]
EBI_[0..49]
IOB_[0..53]
IOB_[68..71]
EBI_41
Extension Connectors
EBI_[0..49]
IOB_[0..71]
SERIAL MEMORIES
INPUT / OUTPUT ON BOARD
Extension Connectors
Serial Connectors / P.B. / LED
IOB_[0..53]
SERIAL MEMORIES
SDA
SCL
MOSI
MISO
SPCK
NPCS[0..3]
IOB_[68..71]
EBI_41
Appendix B – Schematics
Figure 6-2. AT91EB55 Blocks Synopsis
6-3
1709C–ATARM–28-Apr-05
MOSI
MISO
SPCK
1
EBI_[0..49]
IOB_54
NRST
1
NCS0
NWR0/NWE
NRD/NOE
A20B
VCC3V3
CB18
CB10
CB9
1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
2
2
2
R1
100k
1
2
1
R2
100k
IOB_54
VCC3V3
2
1709C–ATARM–28-Apr-05
12
26
11
28
9
10
14
13
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
15
NCS[0..7]
A[0..19]
CTL[0..5]
EBI_[36..41]
EBI_[42..49]
D[0..15]
2
EBI_[0..15]
74LVC04AD
1
GND
GND
46
27
47
37
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
NRD/NOE
NCS0
NCS1
NRST
NWR1/NUB
CTL2
CTL5
NWR0/NWE
CTL1
D[0..15]
CTL0
USER BOOT
A20B
C5
100nF
VCC3V3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
STD BOOT
2
EBI_[16..35]
1
U6A
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
(A-1) / I/O15
(BYTE) / VCCQ
VCC
JP1
jumper_3P
AE20
AT49BV162A
RESET
CE
WE
OE
NC / (A19)
NC
NC
NC / Vpp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19 / (RDY / BUSY)
U1
3
6-4
1
A[0..19]
NWR0/NWE
VCC3V3
NCS1
C1
100nF
VCC3V3
NWR0/NWE
VCC3V3
NCS1
A19
D2
D3
D0
D1
A18
A19
D2
D3
D0
D1
A18
A5
A6
A7
A8
A1
A2
A3
A4
A5
A6
A7
A8
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
128k
512k
NC
A18
A17
A16
A15
OE
D7
D6
GND
VCC
D5
D4
A14
A13
A12
A11
A10
NC
NC
NC
128k N C
A18
A17
A16
A15
OE
D7
D6
GND
VCC
D5
D4
A14
A13
A12
A11
A10
NC
NC
NC
512k
IDT71424S10PH
NC
NC
A0
A1
A2
A3
A4
CS
D0
D1
VCC
GND
D2
D3
WE
A5
A6
A7
A8
A9
NC
NC
U4
IDT71V424S10Y
A0
A1
A2
A3
A4
CS
D0
D1
VCC
GND
D2
D3
WE
A5
A6
A7
A8
A9
U2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A13
A12
A11
A10
A9
A17
A16
A15
A14
A13
A12
A11
A10
A9
A17
A16
A15
A14
D5
D4
D7
D6
D5
D4
D7
D6
VCC3V3
VCC3V3
C3
100nF
VCC3V3
NWR1/NUB
NCS1
NRD/NOE
VCC3V3
VCC3V3
NWR1/NUB
NCS1
layout for TSSOP 400mil.
C2
100nF
VCC3V3
NRD/NOE
layout for SOJ 400mil.
A19
D10
D11
D8
D9
A18
A19
D10
D11
D8
D9
A18
A5
A6
A7
A8
A1
A2
A3
A4
A5
A6
A7
A8
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
128k
512k
NC
A18
A17
A16
A15
OE
D7
D6
GND
VCC
D5
D4
A14
A13
A12
A11
A10
NC
NC
NC
128k N C
A18
A17
A16
A15
OE
D7
D6
GND
VCC
D5
D4
A14
A13
A12
A11
A10
NC
NC
NC
512k
IDT71424S10PH
NC
NC
A0
A1
A2
A3
A4
CS
D0
D1
VCC
GND
D2
D3
WE
A5
A6
A7
A8
A9
NC
NC
U5
IDT71V424S10Y
A0
A1
A2
A3
A4
CS
D0
D1
VCC
GND
D2
D3
WE
A5
A6
A7
A8
A9
U3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A13
A12
A11
A10
A9
A17
A16
A15
A14
A13
A12
A11
A10
A9
A17
A16
A15
A14
D13
D12
D15
D14
D13
D12
D15
D14
VCC3V3
NRD/NOE
C4
100nF
VCC3V3
VCC3V3
NRD/NOE
Appendix B – Schematics
Figure 6-3. EBI Memories
AT91EB55 Evaluation Board User Guide
AT91EB55 Evaluation Board User Guide
A8
A10
A12
A14
A0
A2
A4
A6
A16
A18
NCS7
NCS5
NCS0
NCS2
D8 VCC3V3
D10
D12
D14
D0
D2
D4
D6
VCC3V3
VCC3V3
CTL0
CTL2
CTL4
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
EBI Ext. Con.
GND
NWR0 / NWE
NRD / NOE
MCK0
NCS0
NCS2
VCC3V3
A0 / NLB
A2
A4
A6
GND
A8
A10
A12
A14
VCC3V3
A16
A18
NCS7
NCS5
GND
D0
D2
D4
D6
VCC3V3
D8
D10
D12
D14
GND
P1A
EBI Ext. Con.
GND
NWR1 / NUB
NWAIT
NCS1
NCS3
NRST
A1
A3
A5
A7
GND
A9
A11
A13
A15
VCC3V3
A17
A19
NCS6
NCS4
GND
D1
D3
D5
D7
VCC3V3
D9
D11
D13
D15
GND
P1B
NCS4
EBI_[36..41]
EBI_[42..49]
CTL[0..5]
NCS[0..7]
EBI_[16..35]
NCS6
2
A[0..19]
D9
D11
D13
D15
D1
D3
D5
D7
CB1
A17
A19
A9
A11
A13
A15
A1
A3
A5
A7
NCS1
NCS3
EBI_[0..15]
VCC3V3
NSC4_1 1
VCC3V3
CTL5
CTL1
CTL3
D[0..15]
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
CTL[0..5]
NCS[0..7]
EBI Extension Connector
I/O Ext. Conn.
GND
VCC3V3
PA9 / IRQ0
PA10 / IRQ1
GND
PA11 / IRQ2
VCC3V3
PA12 / IRQ3
GND
PA13 / FIQ
VCC3V3
PB3 / IRQ4
PB4 / IRQ5
GND
PB5 / IRQ6
PB0
GND
PB1
PB2
PB8
PB9
VCC3V3
PB10
PB11
PB12
PB18 / BMS
GND
NSPICS8
NSPICS7
GND
VCC3V3
GND
P2A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
VCC3V3
VCC3V3
VCC3V3
VCC3V3
EBI_[0..49]
VCC3V3
NSPICS8
NSPICS7
PA13
PA12
PA11
PA9
PA10
PB10
PB11
PB12
PB18
PB1
PB2
PB8
PB9
PB5
PB0
PB3
PB4
I/O Ext. Conn.
PB19 / TCLK0
PB20 / TIOA0
PB21 / TIOB0
PB22 / TCLK1
PB23 / TIOA1
PB24 / TIOB1
PB25 / TCLK2
PB26 / TIOA2
PB27 / TIOB2
PA0 / TCLK3
PA1 / TIOA3
PA2 / TIOB3
PA3 / TCLK4
PA4 / TIOA4
PA5 / TIOB4
PA6 / TCLK5
PA7 / TIOA5
PA8 / TIOB5
PA14 / SCK0
PA15 / TXD0
PA16 / RXD0
PA17 / SCK1
PA18 / TXD1 / NTRI
PA19 / RXD1
PA20 / SCK2
PA21 / TXD2
PA22 / RXD2
PA24 / MISO
PA25 / MOSI
PA23 / SPCK
NSPICS5
NSPICS6
P2B
NSPICS5
NSPICS6
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA24
PA25
PA23
IOB_[26..53]
IOB_[0..25]
PA[0..25]
IOB_[54..57]
IOB_[58..59]
IOB_[60..67]
IOB_[68..71]
I/O Ext. Conn.
GND
VCC3V3
PB13
PB14
PB15
PB16
PB17
VCC3V3
GND
A20
A21
A22
A23
GND
DA0
GND
DA1
GND
PB6 / AD0TRIG
GND
AD0
AD1
AD2
AD3
GND
AD4
AD5
AD6
AD7
GND
PB7 / AD1TRIG
GND
P2C
PB[0..27]
AE[20..23]
DA[0..1]
AD[0..7]
NSPICS[5..8]
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
I/O Extension Connector
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
VCC3V3
VCC3V3
PB7
PB6
AE20
AE21
AE22
AE23
PB13
PB14
PB15
PB16
PB17
AD[0..7
DA[0..1]
IOB_[0..71]
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
DA1
DA0
AE[20..23
PB[0..27]
PA[0..25]
Appendix B – Schematics
Figure 6-4. I/O and EBI Expansion Connectors
6-5
1709C–ATARM–28-Apr-05
SW1
SW3
TP 33
TP 33
C14
47nF
R14
100K
VCC3V3
C10
47nF
C11
47nF
PA[0..25]
C15
47nF
R15
100K
VCC3V3
SW4
TP 33
SW2
R17
100K
JP3
jumper_NO
VCC3V3
PA9
PB20
PB17
PB19
6
8
11
TXD0
TXD1
RXD0
RXD1
PA16
PA19
C22
100nF
C18
100nF
VCC3V3
PA9
3
74LV125D
R5
100k
JP2
jumper_NO
PA15
PA18
R16
100k
100nF
2
1
C12
EN
VCC3V3
13
12
10
9
4
5
1
2
U9
VALBP
7
R4
100K
1
14
R3
100K
2
VCC3V3
TIOA0
IRQ0
14
1
15
10
13
12
6
5
4
2
100nF
C16
R45
100k
R43
100k
FORCEON
EN
R1OUT
R2OUT
T1IN
T2IN
C2-
C2+
C1-
C1+
INVALID
R1IN
R2IN
T1OUT
T2OUT
V-
V+
VCC3V3
FORCEOFF
MAX3223ECAP
U10
R44
100k
R42
100k
VCC3V3
18
GND
VCC3V3
2
1
19
1709C–ATARM–28-Apr-05
VCC
6-6
20
11
16
9
17
8
7
3
VCC3V3
4
6
8
PB9
PB10
PB11
15
17
PB14
PB15
100nF
100nF
VCC3V3
C19
C17
13
PB13
22pF
C26
20
22pF
C27
100nF
C13
GND SIGNAL
EN
EN
U8
74LV244D
11
PB12
19
2
1
PB8
VALBP
10
VCC3V3
VCC3V3
3
5
7
9
12
14
16
18
22pF
R10
R11
R12
R13
D5
D6
D7
D8
TX1
RX1
C23
22pF
RX0
C24
22pF
R9
D4
TX0
R8
D3
C20
DTR0
DCD0
DSR0
R7
D2
VCC3V3
R6
D1
C21
22pF
CTS0
RTS0
100R
100R
100R
100R
100R
100R
100R
100R
IOB_[26..53]
PB[0..27]
Red LED
IOB_[0..25]
PA[0..25]
1
6
2
7
3
8
4
9
5
1
6
2
7
3
8
4
9
5
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
Sub D 9b M
P4
10nF
C25
Sub D 9b F
P3
Usart 1:
SERIAL B
Usart 0:
SERIAL A
IOB_[0..53]
Appendix B – Schematics
Figure 6-5. Push Buttons, LEDs and Serial Interface
AT91EB55 Evaluation Board User Guide
TP 33
AE20
AE21
AE22
AE23
AE[20..23]
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A0
A1
A2
A3
A4
A5
A6
A7
100k
RR1
VCC3V3
VDDIO
VDDIO
100k
RR2
35
36
37
38
39
40
41
42
31
32
33
34
29
30
17
18
19
20
21
22
23
24
25
26
27
28
15
16
7
8
9
10
11
12
13
14
3
4
5
6
1
2
C30
100nF
100k
100k
8
7
6
5
8
7
6
5
100nF
U12
AT91M55800A - 33AI
PB27
PB26
PB25
PB24
PB23
VDDIO
PB22
PB21
PB20
PB19
PB[0..27]
PB[0..27]
SCL
SDA
PA18
PA17
PA16
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7
RR4
1 RR3
2
3
4
1
2
3
4
100nF
C50
C49
VDDCORE
VDDIO
D0
D1
D2
D3
D4
D5
D6
D7
A20
A21
A22
A23
VDDIO
GND
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
VDDIO
GND
A0/NLB
A1
A2
A3
A4
A5
A6
A7
NCS0
NCS1
NCS2
NCS3
GND
GND
VDDIO
VDDCORE
VDDCORE
43
44
VDDIO
D0
D1
D2
D3
D4
D5
D6
D7
NCS0
NCS1
NCS2
NCS3
VDDCORE
D[0..15]
VCC3V3
VDDIO
VDDCORE
NCS[0..7]
A[0..19]
Default
boot Mode :
16 Bits
VCC3V3
176
175
VDDIO
VDDCORE
GND
GND
45
46
2
174
173
172
171
170
NUB / NWR1
NWE / NWRO
NOE / NRD
NWAIT
NRST
D8
D9
D10
D11
D12
D13
D14
D15
47
48
49
50
51
52
53
54
1 CB11
CTL[0..5]
169
168
167
166
165
164
NTRST
TCK
TDO
TDI
TMS
JTAGSEL
TCLK0
TIOA0
TIOB0
TCLK1
/
/
/
/
PB19
PB20
PB21
PB22
55
56
57
58
R41
100K
JTAG[0..4]
59
60
JTAG[0..4]
162
161
VDDIO
GND
8
7
6
5
8
7
6
5
160
MCKO
GND
VDDIO
/
/
/
/
/
1
2
3
4
1
2
3
4
163
PB18 / BMS
159
NWDOVF
TIOA1
TIOB1
TCLK2
TIOA2
TIOB2
PB23
PB24
PB25
PB26
PB27
61
62
63
64
65
CTL3
R46
NCS[0..7]
NWAIT
GND
GND
RXD2
TXD2
SCK2
RXD1
PA[0..25]
100nF
VCC3V3
C51
100nF
PA22
PA21
PA20
PA19
94
93
92
91
90
89
PA25
PA24
PA23
VDDIO
XOUT
XIN
PA[0..25]
VDDCORE
VDDIO
C32
C42
100nF
GNDBU
C46
TIOA5
PA7
vt
MOSI
MISO
SPCK
NPCS[0..3]
1
680pF 10%
VDDA
2
2
1
CB8
CB7
REF192GS
OUT
NC/ENABLE
OUT
NC/ENABLE
GNDBU
IOB_[26..53]
IOB_[0..25]
PA[0..25]
IOB_[58..59]
IOB_[60..67]
IOB_[54..57]
DA[0..1]
3
Y3
Osc 16MHZ
3
8
7
6
5
8
7
6
5
IOB_[0..67]
100nF
VDDPLL
R21
100k
C93
1
100nF
VDDBU
R19
100k
C92
C4
+
1µF / 16
GNDA
100nF C39
ADVREF
REF 2.5V
1
+
1µF / 16
GNDA
100nF C36
DAVREF
C3
GNDA
100nF
REF 2.5V
3
C91
EBI_[0..49]
GND
LM61BIM3
Vout
PB[0..27]
DA0
DA1
2
2
GNDBU
2
VCC
U13
TP
NC
Vs
NC
SLEEP O U T P U T
GND
TP
REF192GS
U15
Y1
osc 32,768KHz
1
2
3
4
2
1
TP
NC
Vs
NC
SLEEP O U T P U T
GND
TP
AD[0..7]
C38
1
2
3
4
U14
CB4
VDDA
AE[20..23]
CB17 2
1
C31
GNDBU
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VDDCORE
C48
1
R57
100K
1
2
Y4
Qtz 16MHz
C47
1
C44
1
2
R48 100k
GNDA
VDDA
100nF
Y2
Qtz 32,768kHz
C43
1
R56
100K
CB12
VCC3V3
GNDA
GNDA
VDDA
100nF
GNDA
AD1
TIOA4
PA4
EBI_[42..49]
NCS[0..7]
2
EBI_[36..41]
EBI_[16..35]
A[0..19]
CTL[0..5]
EBI_[0..15]
D[0..15]
2
GNDA
CB3
CB2
MCKO
JTAGSEL
NWDOVF
NRST
C33 1µF / 16V
VDDBU
100nF
R20
287R 1%
1
2
270K
R18
68pF 10%
C45
NPCS3
NPCS2
NPCS1
NPCS0
VDDPLL
101
100
99
98
97
96
95
103
102
C41
VDDA
CB6
XOUT32
XIN32
GNDPLL
PLLRC
108
107
106
105
104
CB5
WAKEUP
NRSTBU
112
111
110
109
114
113
116
115
vt
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
125
124
123
122
121
120
119
118
S H D N 10µF / 16V
DAVREF
ADVREF
127
126
117
DA1
DA0
AD1TRIG 1
AD0TRIG 1
CTL4
JTAGSEL
NWDOVF
CTL5
GNDA
PB7
PB6
VDDIO
VDDCORE
129
128
130
132
131
100nF
VDDCORE
VDDIO
PA22 /
PA21 /
PA20 /
PA19 /
PA29 / NPCS3
PA28 / NPCS2
PA27 / NPCS1
PA26 / NPCS0 / NSS
PA25 / MOSI
PA24 / MISO
PA23 / SPCK
GND
VDDIO
GNDPLL
XOUT
XIN
VDDPLL
PLLRC
NRSTBU
XOUT32
XIN32
VDDBU
WAKEUP
GND
GNDBU
SHDN
VDDA
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
DAVREF
ADVREF
DA1
DA0
GNDA
VDDIO
VDDCORE
C28
C29
100k
VDDCORE
PB18
VDDIO
158
157
156
155
154
153
152
151
150
149
TCLK3
TIOA3
TIOB3
TCLK4
TIOA4
TIOB4
TCLK5
/
/
/
/
/
/
/
PA0
PA1
PA2
PA3
PA4
PA5
PA6
148
147
GND
VDDIO
73
74
146
145
144
143
142
141
140
139
PB7 / AD1TRIG
PB6 / AD0TRIG
PB5 / IRQ6
PB4 / IRQ5
PB3 / IRQ4
PB2
PB1
PB0
VDDIO
GND
138
137
136
135
NCS7
NCS6
NCS5
NCS4
75
76
77
78
79
80
81
82
83
84
85
86
134
133
PA7 / TIOA5
PA8 / TIOB5
PA9 / IRQ0
PA10 / IRQ1
PA11 / IRQ2
PA12 / IRQ3
PA13 / FIQ
PA14 / SCK0
PA15 / TXD0
PA16 / RXD0
PA17 / SCK1
PA18 / TXD1 / NTRI
2
1
GND
GND
VDDCORE
VDDIO
PB17
PB16
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
66
67
68
69
70
71
72
VDDIO
87
88
2
1
1
2
1
2
2
1
2
1
2
AT91EB55 Evaluation Board User Guide
1
CTL5
CTL3
CTL2
CTL0
CTL1
GND
JTAGSEL
JTAG2
JTAG1
JTAG4
JTAG3
JTAG0
VCC
VDDIO
2
PB18
4
CTL4
GND
NWDOVF
VCC
VDDIO
2
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
4
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
+
NCS4
NCS5
NCS6
NCS7
+
BMS
Appendix B – Schematics
Figure 6-6. AT91M55800A
VDDIO
PA6
PA5
PA4
PA3
PA2
PA1
PA0
D15
D14
D13
D12
D11
D10
D9
D8
6-7
1709C–ATARM–28-Apr-05
NRST
JTAG[0..4]
RESET
CLEAR
RESET LED
SW5
TP 33
2
1
C84
10pF
JTAG4
MR
VCC
100nF
C94
NRST
C85
10pF
C79
10pF
JTAG1
C80
10pF
JTAG2
3
4
VCC3V3
R54
100k
CLKRSTLED
CLRSTLED
4
MAX6315US27D1-T
RST
GND
U18
PBRST
C78
10pF
JTAG0
1
74LVC04AD
S2
B.P.
U6B
3
3
4
NRST
G2
G1
C74
10nF
C72
10nF
G4
G3
13
JTAG4
C82
10nF
RSTLED
G6
G5
R25
100k
C75
10nF
C73
10nF
GND
GND
GND
GND
GND
GND
GND
GND
20
18
16
14
12
10
8
6
4
2
VCC3V3
CTL5
VCC
PBRST
JTAG G N D
HE10 2x10
NC
NC
NRST
TDO
TCK
TCK
TMS
TDI
NTRST
VCC
P5
VCC3V3
VCC3V3
BAS216
D9
C76
10nF
19
17
15
11
9
7
JTAG3
JTAG2
5
1
JTAG1
TCK
R27
100k
VCC3V3
3
C81
10pF
JTAG3
MR
VCC
100nF
MAX6315US27D1-T
RST
GND
U17
C53
100nF
C52
74LVC74AD
9
8
5
6
JTAG0
2
1
10
11
12
13
S
C1
1D
R
U16
7
4
3
2
1
14
CTL6
G9
G8
G7
G6
G5
G4
G3
G2
G1
10nF
C71
G9
G8
G7
JTAGSEL
NRST
RESET
100R
R23
C86
10nF
C83
10nF
C77
10nF
JTAGSEL
MCKO
ICE
2
IEEE
D10
Red LED
3
CB15
TCK
1
NWDOVF
4
3
2
1
10
11
12
13
VCC3V3
S
C1
1D
R
U30
VCC3V3
C96
100nF
9
8
5
6
VCC3V3
D11
Red LED
R24
100R
VCC3V3
74LVC74AD
3V3 SUPPLY
7
R22
100k
14
RTCK
TCK
3
1
1709C–ATARM–28-Apr-05
2
CB16
JTAG3
WAKEUP
C95
5
9
11
13
GNDBU
1
1
1
1
U6C
74LVC04AD
74LVC04AD
U6D
74LVC04AD
U6E
74LVC04AD
U6F
S1
B.P.
R26
100k
VDDBU
7
6-8
6
8
VCC3V3
10
12
WAKEUP
100nF
14
VCC3V3
Appendix B – Schematics
Figure 6-7. Reset and JTAG Interface
AT91EB55 Evaluation Board User Guide
SH1
OR
R29
C59
22pF / 25V
RTC SAVE
R30
not use
C61
1µF 10%
1000m A/30V
1
R50
Radj
2
5
2
3
4
GND
C2-
C2+
Vout
7
8
6
2
jumper_NO
JP9
Vddbu=1V84 with R30=620k R29=330k
Vddbu=3V with R29=0R and R30 off
1
C62
1µF 10%
GNDBU
VDDBU
+ C63
SHDN
10µF / 16V
D19
10MQ100N
D18
10MQ100N
1
D17
10MQ100N
D16
10MQ100N
I Vddbu
LT1503CS8-2
SHDN/SS
C1-
C1+
Vin
U20
jumper_NO
JP6
SMT6T15CA
VSAVE=3V
D14
C64
1µF 10%
C57B
10µF / 25V
2
GNDBU
SHDN
1
JP7
jumper_NO
C57
10µF / 25V
5
4
2
GNDA
SENSE
VSW
C60
3,3nF / 10%
7
3
U19
LT1507CS8-3.3
VDDCORE=2.0V
2
JP8
jumper_3P
VDDCORE=3.3V
SYNC
SHTDN
VIN
GNDPLL
VCC1V8
VDDIO
SHDN_1
R55
100K 5%
SHDN_2
1N914
GND
6
C55
22pF / 25V
BT1
3V Button Pile
VCC3V3
shield
Jack Dia.2.1mm
J1
1
1
1
BOOST
VC
8
D12
3
AT91EB55 Evaluation Board User Guide
1
I Vddcore
D15
1N5817
C54
100nF
10µH
L1
+
+
TP2
Test Point Corner 2
TP3
Test Point Corner 3
TP4
Test Point Corner 4
100µF / 10V
C58
I Vddio
TP1
Test Point Corner 1
100µF / 10V
C58B
JP5
jumper_NO
2
1
F1
VDDCORE
VDDIO
VDDA
VDDPLL
VCC3V3
Appendix B – Schematics
Figure 6-8. Power Supply
6-9
1709C–ATARM–28-Apr-05
NPCS[0..3]
SCL
SDA
1
2
NPCS3
NPCS0
NPCS1
NPCS2
CB14
1
2
VCC3V3
R40
100k
VCC3V3
6
4
5
1
2
3
6
4
5
1
2
3
SDA1
SCL1
R31
100k
R51
100k
CB13
VCC3V3
EN
&
EN
BIN/OCT
74LV138D
1
2
4
U29
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
15
14
13
12
11
10
9
7
15
14
13
12
11
10
9
7
VCC3V3
BIN/OCT
&
GND
NC
NC
NC
NC
NC
NC
WP
VCC
C90
100nF
NSPICS0
NSPICS1
NSPICS2
NSPICS3
NSPICS4
NSPICS5
NSPICS6
NSPICS7
10
18
17
16
15
14
13
19
20
100nF
NSPICS8
VCC3V3
C89
AT24C512W1-10SC-2.7
SDA
SCL
NC
NC
NC
NC
NC
NC
NC
A0
A1
74LV138D
1
2
4
U27
11
12
3
4
5
6
7
8
9
1
2
U23
16
8
1709C–ATARM–28-Apr-05
16
6-10
Not Mounted
8
VCC3V3
EBI_41
VCC3V3
NSPICS[5..8]
C67
100nF
VCC3V3
EBI_41
100k
100k
100k
100k
R38
NRST
NSPICS2
IOB_[68..71]
MOSI
MISO
SPCK
NRST
NSPICS0
R36
MOSI
MISO
SPCK
R34
R32
VCC3V3
VCC3V3
9
10
11
12
4
5
6
13
15
16
14
1
2
3
9
10
11
12
4
5
6
13
15
16
14
1
2
3
AT45DB321-TC
NC
NC
NC
NC
NC
NC
NC
CS
SI
SO
SCK
RDY/BUSY
RESET
WP
U25
AT45DB321-TC
NC
NC
NC
NC
NC
NC
NC
CS
SI
SO
SCK
RDY/BUSY
RESET
WP
U21
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
7
MOSI
MISO
SPCK
C68
100nF
VCC3V3
C65
100nF
VCC3V3
MOSI
MISO
SPCK
VCC3V3
VCC3V3
100k
100k
100k
100k
NSPICS4
MOSI
MISO
SPCK
R39
R37
MOSI
MISO
SPCK
R35
R33
5
2
6
1
GND
HOLD
WP
VCC
9
10
11
12
4
5
6
13
15
16
14
1
2
3
9
10
11
12
4
5
6
13
15
16
14
4
7
3
8
R52
100K
AT45DB321-TC
NC
NC
NC
NC
NC
NC
NC
CS
SI
SO
SCK
RDY/BUSY
RESET
WP
U26
AT45DB321-TC
NC
NC
NC
NC
NC
NC
NC
CS
SI
SO
SCK
RDY/BUSY
RESET
WP
U22
AT25256W-10SC-2.7
SI
SO
SCK
CS
U28
NSPICS3
NRST
NSPICS1
NRST
1
2
3
R53
100K
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
7
C70
100nF
VCC3V3
VCC3V3
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
C69
100nF
VCC3V3
C66
100nF
VCC3V3
Appendix B – Schematics
Figure 6-9. SPI and TWI Memories
Not Mounted
AT91EB55 Evaluation Board User Guide
Section 7
Appendix C – Bill of Material
Table 7-1. Bill of Material
Item
Qty
Reference
Part
Designation
1
1
BT1
3V Button Pile
Li/MnO2 3V 180 mAH pile UL:
MH13654(N)
2
2
CB16
3
3
CB18
CB_NO
4
41
C1, C2, C3, C4, C5,
C12, C13, C16, C17,
C18, C19, C22, C28,
C29, C30, C31, C32,
C36, C38, C39, C42,
C49, C50, C51, C52,
C53, C54, C65, C66,
C67, C68, C69, C70,
C89, C90, C91, C94,
C95, C96
100 nF
Ceramic X7R/10V
5
4
C10, C11, C14, C15
47 nF
Ceramic X7R/10V
6
6
C20, C21, C23, C24,
C26, C27
22 pF
Ceramic NPO/10V
7
11
C25, C71, C72, C73,
C74, C75, C76, C77,
C82, C83, C86
10 nF
Ceramic X7R/16V
8
3
C33, C37, C40
1 µF/16V
Tantalum 16V/10%/TAJ
9
2
C41, C63
10 µF/16V
Tantalum 16V/10%/TAJ
10
3
C43, C47, C48
10 pF
Ceramic NPO/10V/5%
11
1
C44
4 - 25 pF
Adjustable Capacitor, serial
TZBX4
12
1
C45
68 pF/10%
Ceramic X7R/10V/10%
13
1
C46
680 pF/10%
Ceramic X7R/10V/10%
14
2
C55, C59
22 pF/25V
Ceramic X7R/25V
15
1
C57
10 µF/25V
25V ESR < 0.5Ω/0.5Arms
16
1
C58
100 µF/10V
Tantalum 10V ESR < 0.5Ω
AT91EB55 Evaluation Board User Guide
3 position jumper (jumper
between 2-3)
7-1
Rev. 1709C–ATARM–28-Apr-05
Appendix C – Bill of Material
Table 7-1. Bill of Material (Continued)
7-2
1709C–ATARM–28-Apr-05
Item
Qty
Reference
Part
Designation
17
1
C60
3.3 nF/10%
Ceramic X7R/25V/10%
18
3
C61, C62, C64
1 µF/10%
Ceramic X7R/10V/10%
19
6
C78, C79, C80, C81,
C84, C85
10 pF
Ceramic X7R/16V
20
10
D1, D2, D3, D4, D5,
Red LED
D6, D7, D8, D10, D11
Red LED H.R. 3mm/ T1/ 7mcd
60°
21
1
D9
BAS32L
Diode signal
22
1
D12
1N914
Diode signal
23
1
D14
SMT6T15CA
Transil 12.8V/600W/
VBRmini/14.3V
24
1
D15
1N5817
Schottky diode 1A/0.45V
25
4
D16,D17,D18,D19
10MQ060N
Diode rectifying 0.62V/0.77A
26
1
F1
1000 mA
Fuse rarm. 1000 mA/30V
27
3
JP1,JP8
jumper_3P
3 point jumper
28
6
JP5,JP7,JP9
jumper_NO
2 point jumper
29
1
J1
Jack Diameter 2.1mm Jack socket 2.1mm
30
1
L1
10 µH
Self 10 µH at 1A and 500 kHz
31
1
P3
Sub D 9b F
Sub D 9b Female socket, right
angle, mechanical strength,
locking
32
1
P4
Sub D 9b M
Sub D 9b Male socket, right
angle, mechanical strength,
locking
33
1
P5
HE10 2x10
HE10 2x10 socket, low profile,
right angle
34
27
R3, R4, R5, R14, R15,
R16, R17, R25, R26,
R27, R31, R32, R33,
100K
R34, R35, R36, R37,
R38, R39, R40, R41,
R51, R55
Resistor 5%
35
2
R56, R57
10K
Resistor 5%
36
10
R6, R7, R8, R9, R10,
R11, R12, R13, R23,
R24
100R
Resistor 5%
37
1
R18
270K
Resistor 5%
38
1
R20
287R 1% E48
Resistor 1%
39
4
RR1, RR2, RR3, RR4 100K
Resistance network (4 resistors
with 1 common point)
40
1
R29
0R
Shunt OR
41
16
R22, R42, R43, R44,
R45, R46, R48, R52,
R53, R54
100K
Resistor 5%
AT91EB55 Evaluation Board User Guide
Appendix C – Bill of Material
Table 7-1. Bill of Material (Continued)
Item
Qty
Reference
Part
Designation
42
4
SW1, SW2, SW3,
SW4
TP 33
Push button with black
cabochon
43
1
SW5
TP 33
Push button with red cabochon
44
2
S1, S2
Push Button
CMS Push button
45
4
TP1, TP2, TP3, TP4
Test Point Corner
CMS Test point
46
1
U1
AT49BV162A-70TI
Flash 2M bytes x 16-bits
47(1)
1
U4, U5
IDT71V124SA15PH
Static memory: 128k x 8-15 ns
(double implantation)
48
1
U6
74LVC04AD
Reverser (LVC serial)
49
1
U8
74LV244D
Buffer
50
1
U9
74LV125D
Tri-state buffer
51
1
U10
MAX3223ECAP
Driver RS232 + ESD "E"
52
1
U12
AT91M55800A
Microcontroller
53
1
U13
LM61BIM3
Temperature sensor
54
2
U14, U15
REF192GS
Reference of voltage 2V5 ±0.5%
55
1
U16
74LVC74AD
D flip flop (LVC serial)
56
1
U30
74LCX74
D Flip Flop (LCX serial)
57
2
U17, U18
MAX6315US27D1-T
Circuit LVD-reset. (Threshold
2.7V; Timeout = 1 ms)
58
1
U19
LT 1507CS8-3.3
Voltage Regulator DC/DC
59
1
U20
LTC 1503CS8-2
Voltage Regulator DC/DC
60
4
U21
AT45DB321-TC
Serial DataFlash (wired
according to availability)
61
1
U23
AT24C512W1-10SCEEPROM 64K bytes
2.7
62
2
U27, U29
74LV138D
63
1
U28
AT25256W-10SC-2.7 EEPROM 32K bytes
64
1
Y2
Crystal 32768 kHz
Crystal 32768 kHz, ±20 ppm at
25° C
65
1
Y4
Crystal 16 MHz
Crystal 16 MHz, ±30ppm at
25° c
66
4
PS1, PS2, PS3, PS4
Board Support
Plastic bases H > 10mm
Note:
AT91EB55 Evaluation Board User Guide
Decoder (3 to 8)
1. The EB55 is equipped with SRAM U2/U3 or U4/U5 (the difference lies in case type
only). The choice is made according to availability.
7-3
1709C–ATARM–28-Apr-05
Appendix C – Bill of Material
7-4
1709C–ATARM–28-Apr-05
AT91EB55 Evaluation Board User Guide
Section 8
Appendix D – Flash Memory
The Figure 8-1 shows the embedded software mapping after the remap. It describes the
location for the different programs in the AT49BV162A flash memory and the division
into sectors.
AT91EB55 Evaluation Board User Guide
8-1
Rev. 1709C–ATARM–28-Apr-05
Appendix D – Flash Memory
Figure 8-1. EB55 Flash Memory Software Location
0x011FFFFF
Not Used
15 Sectors
(64K byte/sector)
1MB
User Mode
Led Swing Application
(example)
0x01100000
Not Used
0x01011FFF
Angel Debug
Monitor
0x01006000
0x01005FFF
0x01004000
0x01000000
8-2
1709C–ATARM–28-Apr-05
15 Sectors
(64K Byte/sector)
1MB
Standard Mode
1 Sector
(64K Byte/sector)
5 Sectors
(8K Byte/sector)
Free Sector
for
Boot Upgrade
Flash Uploader
Functional Test Software
Boot Program
2 Sectors
(8K Byte/sector)
AT91EB55 Evaluation Board User Guide
Revision History
Doc. Rev
Date
Comments
1709A
June 2001
First Issue
1709B
04-Aug-02
Pg. 5-2, Default positiion of CB11 changed from closed to open
1709C
28-Apr-05
Global: Most Flash references read as AT49BV162V
Change Request Ref.
CSR 05-199
Figure 1-1, and global, reference to I2C E2PROM and SPI E2PROM
removed or modified.
Global: Reference to SRAM downloader removed.
Section 3.2, SW2 button usage changed to reserved.
Section 3.4, 0x1004000 changed to 0x1006000.
Section 4.3, changes to information and note
Figure 6-3, AT49BV162A associated to U1
Table 6-9, name changed. U23 and U28 shown as “Not Mounted”.
Table 7-1, item 46, parts column shows AT49BV162A-70TI
Figure 8-1, illustration replaced
AT91EB55 Evaluation Board User Guide
1709C–ATARM–28-Apr-05
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