4 2 P2[7:0] P2.3 C P2.7 EA# EXT_ACCESS[3:0] RST FILT PVDD PVSS X1 X2 B3 C2 C3 C4 C5 D5 C6 D6 A8 B8 B9 C9 C10 C8 D10 D9 E10 B1 A1 G10 F4 F3 G2 H3 H4 TST# SDA SCL P3.1 P3.0 P3.3 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 EA# PSEN#/ISP# ALE RST FILT PVDD PVSS X2 X1 nc nc MCLK MCMD MDAT DCLK DSEL DOUT SCLK AUDRST# CBP LPHN HPN HPP PAINN PAINP MONON MONOP AUXP AUXN LINER LINEL HSL HSR nc nc VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDIG nc AUDVDD AUDVSS AUDVSS AUDVSS AUDVBAT ESDVSS AUDVREF HSVSS HSVDD AUDVCM INGND nc P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 D DD+ UVDD UVSS P4.3/SS# P4.2/SCK P4.1/MOSI P4.0/MISO P3.7/RD# P3.6/WR# P3.5/T1 P3.4/T0 P3.3/INT1# P3.2/INT0# P3.1/TXD P3.0/RXD nc nc nc nc nc TST# SDA SCL KIN0 U1 P0[7:0] TWI[2:0] J3 J2 K2 K1 C7 B6 A7 B7 J6 J5 H6 G6 K4 F7 F6 G5 D4 D3 D2 C1 F8 H5 E5 E3 B2 DD+ USB[1:0] 1 TST# P3.7 P3.6 P3.5 P3[7:0] D 3 UVDD UVSS SND2_IRQ_Controller 5 VDD MMC[2:0] MCLK MCMD MDAT VDD TST# AUDIO[18:0] AUDRST# CBP LPHN HPN HPP PAINN PAINP MONON MONOP AUXP AUXN LINER LINEL HSL HSR EA# TEST[5:0] EXT_ACCESS[3:0] C A10 J4 H9 F5 E9 A5 A6 E8 E6 K3 J10 B10 A9 E1 J9 K5 H1 K7 E7 E4 G1 F1 J1 H2 A4 CLOCK[2:0] D1 H10 D8 F10 F9 H7 G7 H8 G8 G9 J8 J7 K6 K8 K9 K10 B5 B4 A3 A2 G4 G3 E2 F2 D7 B B INGND HSVSS HSVDD VDD AUDVDD VSS AUDVBAT ESDVSS AT83SND2MP3_CTBGA100 C1 C2 C3 100n 10u 10u VDD C4 C5 C6 1n 1n 1n C7 C8 C9 1n 1n 1n VSS PVDD VDD A C10 C11 C12 C13 C14 C15 100n 100n 100n 100n 100n 100n Connection to Remote Controller ############################### # UART RX and TX # VSS # Reset # Optionnal SND2_IRQ_Controller (snd2 output) #### AUDVSS AUDVDD C17 C18 C19 C20 C21 100n 1n 100n 1n 100n 1n PLL Decoupling CPU decoupling HSVDD C16 PVSS VSS UVDD UVSS C22 1n HSVSS USB Decoupling C23 AUDVSS Audio Decoupling A 100n Title Size A4 Date: 5 4 3 2 Processor Document Number AT83SND2MP3 - Reference board Friday, November 25, 2005 Rev 3.2 Sheet 1 1 of 6 5 4 3 2 1 D D J14 1 2 CP1 Configuration Pad CP2 PVDD POWER SELECTOR D1 VCC5 (5V to 9V) VIN ADJ 3 CONNECTOR SIP2 DC POWER SUPPLY 5V to 9V LM317-EMP 1 2 1 C Configuration Pad CP3 UVDD 1N4002 Configuration Pad CP4 AUDVDD U2 J1 VOUT VOUT VCC3 2 4 R2 680 100u TANTAL 1N4002 Configuration Pad CP5 AUDVBAT R3 C Configuration Pad CP6 HSVDD 68 D2 C24 + VDD Configuration Pad C25 + 100u TANTAL C26 + 100n VSS D3 POWER-ON LED PWR RED R4 470 PVSS UVSS AUDVSS ESDVSS B B HSVSS Warning: 1. To prevent system malfunctions during periods of insufficient power supply voltage, AT8xC51SND2C voltage supply shall be monitored by a voltage supervisor. 2. During USB operation, AT8xC51SND2C voltage supply shall be 3.0 V to 3.6V to comply USB specification. 3. AUDVBAT (Audio power amplifier supply) shall be connected to Battery supply (at least 3.2V). A A Title Size A Date: 5 4 3 Power supply Document Number AT83SND2MP3 - Reference board Friday, November 25, 2005 2 Rev 3.2 Sheet 2 of 1 6 5 4 3 CPU RESET D EXT_ACCESS[3:0] RST PUSHBUTTON R5 10K C TWI[1:0] D AUDIO[18:0] C27 1u SW2 RESET VDD 1 AUDIO RESET VDD + 2 R7 SDA AUDRST 0 D4 C 1N4148 CLOCK[2:0] FILT VSS R6 100 VSS C30 2.2n Reset pin shall be connected to remote controller. Refer to Hardware guide FAQ for how to connect it. C31 10n B PVSS C32 B PLL filter X1 VSS Y1 16 MHz 33p C33 CLOCK[2:0] X2 VSS 33p CPU CLOCK A A Title Size A Date: 5 4 3 Clock & Reset Document Number AT83SND2MP3 - Reference board Friday, November 25, 2005 2 Rev 3.2 Sheet 3 of 1 6 5 4 3 2 1 VDD R9 100k P3.3 D D 1 J3 Q-BC860 Q2 MMC[2:0] 3 R27 100K VDD P3[7:0] 2 R26 10K R10 10k VSS VDD VSS 1 2 3 4 5 6 7 8 9 MCMD VSS VDD MCLK VSS MDAT VSS MMC / SD Interface VSS MMC_CON 2 UVDD C34 100n VSS J13 USB Hardware condition C 1 Q1 R8 1.5k 2 3 1 mini USB B 1 2 3 4 5 C P3.5 Q-BC860 P3[7:0] R11 1.5K J10 VBUS UDUD+ UVSS R12 R13 UVSS 27 27 1 2 3 DD+ VSS Rx Tx R15 R14 27 27 P3.0 P3.1 P3[7:0] CONNECTOR SIP3 RS232 USB[1:0] J2 B UART interface USB interface B During USB operation, AT8xC51SND2C voltage supply shall be 3.0 V to 3.6V to comply USB specification. A A Title Size A4 Date: 5 4 3 2 Standard Interfaces Document Number AT83SND2MP3 - Reference board Friday, November 25, 2005 Rev 3.2 Sheet 4 1 of 6 5 4 3 2 1 AUDIO OUPUTS D J6 AUDIO STEREO JACK C36 4 3 2 1 D HSR 100u TANTAL HSL C38 AUXN 100u TANTAL C45 470n C46 J16 4 3 2 1 AUXP AUDIO[18:0] AUDVSS 470n AUDIO STEREO JACK Head Set output AUDVSS AUXN C AUXP C36 and C38 can be replaced by 10u capacitors. This will decrease the frequency bandwith. Refer to Hardware guide FAQ for full desription. C AUDIO MONO JACK HPP 1 2 3 AUDIO[18:0] HPN J17 R18 200 Mono input LPHN PAINN C40 470n MONON PAINP J12 C41 470n MONOP B AUDIO MONO JACK AUDVBAT AUDVSS C42 22u AUDVSS C43 100n AUDVBAT 470n B LINER 3 2 1 CBP LINEL AUDVSS J15 AUDIO MONO JACK Speaker C47 3 2 1 C48 470n AUDIO[18:0] AUDVSS AUDIO[18:0] Line inputs (stereo) A A Title Size A4 Date: 5 4 3 2 Audio Interfaces Document Number AT83SND2MP3 - Reference board Friday, November 25, 2005 Rev 3.2 Sheet 5 1 of 6 5 4 3 2 1 P0[7:0] D D VDD P3[7:0] TWI[1:0] 12 13 37 VCC IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 29 30 31 32 41 42 43 44 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 C NandFlash 512b page size P2.3 SCL R16 47K P2[7:0] C CLE ALE /CE /RE /WE /WP RDY/B 100nF VSS VCC P2[7:0] 16 17 9 8 18 19 7 VSS U8 P2.0 P2.1 P2.7 P3.7 P3.6 36 VSS C37 VSS C35 100nF VDD B Nand Flash connection : P3.6 : WR# P3.7 : RD# P2.0 : CLE P2.1 : ALE SCL: WP#. NandFlash WP# pin signal shall be pull down (47K ohms) and connected to AT8xC51SND2C SCL (from TWI[1:0] bus). P2.3 : RDY/BUSY P2.7 : CE# B Changes ####### # v3.2.0, 25 Nov, 2005 - Clarify cpu non connected pins # v3.1.0, 27 May, 2005 - First Release of AT83SND2MP3 schematics based on AT89RFD-08 reference board. #### A TIPS #### # For debugging purpose, it is recommend to add testpoints on the following signals: # - ALE # - RST # - UART RX and TX # - PSEN # Refer to Hardware Guide for Layout Rules #### A Title Size A4 Date: 5 4 3 2 NandFlash Document Number AT83SND2MP3 - Reference board Friday, November 25, 2005 Rev 3.2 Sheet 6 1 of 6