TLV320DAC3202 www.ti.com SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 LOW POWER HIGH FIDELITY I2S INPUT HEADSET IC Check for Samples: TLV320DAC3202 FEATURES 1 • Ground Referenced Click-Pop Free Class-G Stereo Headset Driver Capable of Driving 1 VRMS at the Headset Driver Output, Per Channel, in Phase 100-dB(A) Channel SNR With 6.5-mW of Quiescent Power Dissipation Built In Short-Circuit Protection for Preventing Supply Rails Overload Supports 8-, 11.025-, 12-, 16-, 24-, 32-, 44.1and 48-kHz Sample Rates I2C Interface for Digital Control Supports 16-, 20-, 24- and 32-Bit Data Width Supports Standard I2S, PCM, Left and Right Justified Formats Supports Data Mixing With Gain Options • • • • • • • • • • • • 32-Step Volume Control from 4 to -59 dB Clocking: Internal Clock Derived from I2S BCLK Package: WCSP, 0.5 mm Pitch, 2 mm x 2.5 mm Power Supply: Direct Battery and IO Supply APPLICATIONS • • • • • • Smart Phones and Music Phones Portable Navigation Personal Media Players PDAs Portable Game Consoles HDD and Flash-Based Portable Audio Players DESCRIPTION The TLV320DAC3202 is a high fidelity and low power headphone amplifier with integrated DAC and power rails. The small solution size and highly efficient operation maximizes battery life and performance. The digital audio interface supports industry standard formats such as I2S and PCM. Many features of this device such as volume setting, data width and sampling rate are configurable for optimum flexibility and efficiency. The headset power control automatically adjusts the rail voltage based on the input signal to maximize efficiency and performance. The control interface uses an industry standard I2C controller for ease of operation and reduction in device pin count. Table 1. ORDERING INFORMATION (1) PACKAGE (2) TA –30ºC to 85ºC (1) (2) YZJ ORDERABLE PART NUMBER Tape and reel of 250 TLV320DAC3202CYZJT Tape and reel of 3000 TLV320DAC3202CYZJR For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. While this part number includes the YZJ package designator, it does not conform to the standard YZJ footprint. Only the drawings below should be used for system design and not the YZJ drawing available from the TI Packaging website. Bottom View Top View 1 2 3 4 5 5 A A B B C C D D 4 3 2 1 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM REG FLT DIGMIXL SCL SDA Gain HSLDRV DAC L SD Class G HSLDAC DIN HSOUTG HSL I2S FLT HSR DIGMIXR WCLK HSLOUT Gain BCLK DAC R SD Class G HSROUT HSRDRV HSRDAC Internal Clocks VANAG CP VANA DVSS HSVSS CFLYN HSVDD CFLYP AVDD VANA VPOW AVSS VREF DVDD VPOW REFSYS PLL PIN ASSIGNMENTS Table 2. PIN ASSIGNMENTS (TOP VIEW) 1 2 3 4 5 A AVSS B VREF VANAG VANA CFLYP CFLYN AVDD VPOW DVDD C DVSS SDA SCL HSOUTG HSVDD HSOUTL D BCLK WCLK DIN HSOUTR HSVSS Table 3. TERMINAL FUNCTIONS TERMINAL I/O VOLTAGE LEVEL (V) DESCRIPTION A1 Input 0 Analog ground A2 Input 0 Leave floating VANA A3 Output 1.55 Analog LDO output CFLYP A4 Input/Output 1.95 FLY cap "+" terminal CFLYN A5 Input/Output -1.95 FLY cap "-" terminal VREF B1 Output 0.75 Analog reference output AVDD B2 Input VBAT VPOW B3 Output 1.95 VPOW LDO output DVDD B4 Input VIO 1.8-V IO digital supply DVSS B5 Input 0 SDA C1 Input/Output VIO I2C Data SCL C2 Input VIO I2C CLK in HSOUTG C3 Input 0 HSVDD C4 Input/Output 1.95 HSOUTL C5 Output +/-1.5 BCLK D1 Input VIO I2S bit clock WCLK D2 Input VIO I2S word clock DIN D3 Input VIO I2S downlink data NAME NO. AVSS VANAG 2 2.3-V to 4.8-V battery input Digital ground Headset feedback ground Headset positive supply Headset output left Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 TLV320DAC3202 www.ti.com SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 Table 3. TERMINAL FUNCTIONS (continued) TERMINAL VOLTAGE LEVEL (V) I/O DESCRIPTION NAME NO. HSOUTR D4 Output ±1.5 Headset output right HSVSS D5 Input/Output -1.95 Headset negative supply ABSOLUTE MAXIMUM RATINGS (1) All voltages values are with respect to GND. Over operating free-air temperature range (unless otherwise noted). VALUE AVDD (VBAT) DC UNIT -0.3 to 5 V AC (2) -0.3 to 5.5 DC -0.3 to 2.1 AC (2) -0.3 to 2.2 TA Operating free air temperature -40 to 85 °C TJ Maximum junction temperature 125 °C Tstg Storage temperature -65 to 150 °C 115 °C DVDD (VIO) Lead temperature Human Body Model ESD rating (all pins) (1) (2) V -2000 to 2000 Charged Device Model V -500 to 500 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For spike duration of 1 ms, 10,000 times over 7 years (lifetime). RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TA Operating free air temperature -30 85 °C Tstg Storage temperature -55 150 °C ELECTRICAL CHARACTERISTICS AVDD = 3.7 V, DVDD = 1.8 V, TA = 25°C, unless otherwise specified. PARAMETER AVDD (VBAT) TEST CONDITIONS MIN TYP Functional only 2.3 4.8 Parametric performance 2.3 4.8 DVDD (VIO) 1.65 VIH, digital (1) 1.8 1.95 0.65 x VIO 0.35 x VIO HSOUTL/R Voltage Power consumption from all supplies with internal PLL (SNR = 100 dBA) Enabled UNIT V V V VIL, digital (1) (1) MAX -1.5 1.5 Disabled, HiZ 1.8 No load 6.5 0.1 mW/channel, 1 kHz, 32 Ω 9.7 V V mW CHIP_EN = 1, HSLEN = 1, HSREN = 1, active I2S, idle channel, amplifiers muted Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 3 TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD = 3.7 V, DVDD = 1.8 V, TA = 25°C, unless otherwise specified. PARAMETER TEST CONDITIONS TYP MAX 2 DVDD, GND mode (2) 2 AVDD, HiZ mode (3) 1 DVDD, HiZ mode (3) 1 AVDD, GND mode Shutdown current MIN (2) Startup time From CHIP_EN assertion to Florin reaching Standby state (clock and power supplies available) Wake up time From HSL/R_EN assertion to Florin reaching Active state, during which the system is completely powered up with headset drivers enabled UNIT µA 15.5 ms 3 ms AUDIO PATH ELECTRICAL PERFORMANCE Maximum amplitude at ball Amplitude across load Dynamic range 0-dB PCM, 1 kHz, THD = 1%, 32-Ω load, 4-dB gain 1.05 32-Ω load 0.7 16-Ω load 0.45 0.5 97 100 1 kHz, -60 dBFs, A-weighted POUT = 20 mW 1 kHz, 16-Ω load in series with 10 Ω (REMI) THD+N POUT = 12 mW 70 dB (A) POUT = 4 mW 74 dB 72 20 Hz to 20 kHz Channel separation 1 kHz, full scale input (4) 90 95 217 Hz, 500-mVpp ripple on AVDD 80 90 Pop noise specification (5) Vrms 68 Frequency response PSRR Vrms -0.25 0.25 dB dB dB Maximum DC value after power up 0.5 mV RECEIVE CHANNEL DIGITAL FILTER PERFORMANCE, Fs = 44.1 kHz or 48 kHz HPF -3 dB corner LPF pass band corner frequency 0.8 -10 dBFs LPF pass band ripple 5 0.42 Fs Hz -0.25 0.25 dB LPF -3 dB corner 0.48 Fs LPF interpolation multiplier 8 LPF magnitude response < 0.16 Fs LPF stop band corner frequency LPF stop band attenuation < 2 Fs Absolute delay Filter only, at 1 kHz, without HPF Excludes interface + compute latency Hz -0.05 Hz 0.05 dB 0.6 Fs Hz 70 dB 11/ Fs s AUDIO INTERFACE TIMING PARAMETERS Tbclk Audio clock period Variable BCLK 1/BCLK Tbclkh BCLK high duration 0.35 x BCLK period Tbclkl BCLK low duration 0.35 x BCLK period Tdv Data hold time following BCLK falling edge (2) (3) (4) (5) 4 ns 20 ns ns ns CHIP_EN = 0, HIZ_L = 0, HIZ_R = 0 CHIP_EN = 0, HIZ_L = 1, HIZ_R = 1 The maximum board resistance should be less than 250 mΩ between the HSOUTL/HSOUTR pins and the HSOUTG pin. Maximum slew rate (ΔV/Δt) < 5 V/s after A-weighting Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 TLV320DAC3202 www.ti.com SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD = 3.7 V, DVDD = 1.8 V, TA = 25°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TFS Sample clock setup time following BCLK falling edge Tds Data set time before BCLK rising edge 0.2 x BCLK period ns Tdh Data hold time after BCLK rising edge 0.2 x BCLK period ns Twclks Short frame sync pulse width 10 1/BCLK Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 ns ns 5 TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISITICS DAC TO HEADSET FFT AT -3 dBFS WITH 16-Ω HEADSET 0 0 -20 -20 -40 -40 Amplitude - dBr Amplitude - dBr DAC TO HEADSET FFT AT -3 dBFS WITH 32-Ω HEADSET -60 -80 -100 -120 -60 -80 -100 -120 -140 -140 0 5000 10000 15000 20000 0 Figure 1. Figure 2. 1 0.75 0.75 0.5 0.5 Amplitude - mV Amplitude - mV 1 0.25 0 -0.25 20000 0.25 0 -0.25 -0.5 -0.5 -0.75 -0.75 -1 -5 0 TIME - ms 5 -5 -10 10 0 5 10 TIME - ms Figure 4. TOTAL HARMONIC DISTORTION + NOISE vs HEADPHONE OUTPUT POWER WITH 32-Ω HEADSET TOTAL HARMONIC DISTORTION + NOISE vs HEADPHONE OUTPUT POWER WITH 16-Ω HEADSET 0 0 -10 -10 -20 -20 -30 -30 THDN -dB THDN -dB 15000 CLICK AND POP PERFORMANCE WITH 16-Ω HEADSET Figure 3. -40 -50 -40 -50 -60 -60 -70 -70 -80 -80 -90 -90 0 5 10 15 20 0 Headphone Output Power - mW Figure 5. 6 10000 f - Frequency - Hz CLICK AND POP PERFORMANCE WITH 32-Ω HEADSET -1 -10 5000 f - Frequency - Hz 5 10 15 20 Headphone Output Power - mW Figure 6. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 TLV320DAC3202 www.ti.com SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 FREQUENCY RESPONSE SAMPLING FREQUENCY = 48 kHz CHANNEL SEPARATION 0 0.5 0.4 Left Channel -20 0.3 Amplitude - dBr Amplitude - dB 0.2 0.1 0 -0.1 -0.2 -40 -60 -80 Right Channel -100 -0.3 -120 -0.4 -0.5 10 100 1000 f - Frequency - Hz 10000 100000 -140 500 700 900 1100 1300 1500 f - Frequency - Hz Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 7 TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 www.ti.com DIGITAL INTERFACE Audio Interface The audio interface for data communication with application processor or modem supports multiple formats such as I2S, left justified, right justified or the short frame sync PCM formats. The default interface format is I2S at 48kHz sampling rate and 16-bit data size. The clock input selection module within PLL block also supports multiple input frequency options. The input clock must be in standard square wave format; hence a clock squarer is not necessary. The following tables shows the details of audio interface configuration through I2C register controls. Table 4. Audio Interface Format Configuration Register INTF_MODE (1:0) INTERFACE FORMAT TYPE 0 0 Standard I2S 0 1 Left justified I2S 1 0 Right justified I2S 1 1 Short PCM Table 5. Audio Interface BCLK to WCLK Ratio Setting Register INTF_FRAME_SIZE (2:0) INTERFACE FRAME SIZE, BCLK/WCLK INTF_SIZE (1:0) 0 0 0 0 0 2 x 16 x Fs 0 0 1 0 1 2 x 20 x Fs 0 1 0 1 0 2 x 24 x Fs 0 1 1 1 1 2 x 32 x Fs 1 0 0 0 0 4 x 16 x Fs 1 0 1 0 1 4 x 20 x Fs 1 1 0 1 0 4 x 24 x Fs 1 1 1 1 1 4 x 32 x Fs Table 6. Audio Sampling Rate Setting Register CLK_MODE(3:0) INTERFACE SAMPLING RATE, WCLK (kHz) 0 0 0 0 8 0 0 0 1 11.025 0 0 1 0 12 0 0 1 1 NA 0 1 0 0 16 0 1 0 1 22.05 0 1 1 0 24 0 1 1 1 NA 1 0 0 0 32 1 0 0 1 44.1 1 0 1 0 48 1 0 1 1 NA 1 1 0 0 NA Table 7. Detailed Configuration of Interface Including PLL Setup Registers 8 BCLK/WCLK DATA SIZE Fs (WCLK) Fs x DATA BCLK/PLL INPUT 32 16 48.000 1536 1536 40 20 48.000 1920 1920 48 24 48.000 2304 2304 64 32 48.000 3072 3072 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 TLV320DAC3202 www.ti.com SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 Table 7. Detailed Configuration of Interface Including PLL Setup Registers (continued) BCLK/WCLK DATA SIZE Fs (WCLK) Fs x DATA BCLK/PLL INPUT 32 16 44.100 1411.2 1411.2 40 20 44.100 1764 1764 48 24 44.100 2116.8 2116.8 64 32 44.100 2822.4 2822.4 64 16 8.000 256 512 64 16 11.025 352.8 705.6 64 16 12.000 384 768 64 16 16.000 512 1024 64 16 22.050 705.6 1411.2 64 16 24.000 768 1536 64 16 32.000 1024 2048 64 16 44.100 1411.2 2822.4 64 16 48.000 1536 3072 80 20 8.000 320 640 80 20 11.025 441 882 80 20 12.000 480 960 80 20 16.000 640 1280 80 20 22.050 882 1764 80 20 24.000 960 1920 80 20 32.000 1280 2560 80 20 44.100 1764 3528 80 20 48.000 1920 3840 96 24 8.000 384 768 96 24 11.025 529.2 1058.4 96 24 12.000 576 1152 96 24 16.000 768 1536 96 24 22.050 1058.4 2116.8 96 24 24.000 1152 2304 96 24 32.000 1536 3072 96 24 44.100 2116.8 4233.6 96 24 48.000 2304 4608 128 32 8.000 512 1024 128 32 11.025 705.6 1411.2 128 32 12.000 768 1536 128 32 16.000 1024 2048 128 32 22.050 1411.2 2822.4 128 32 24.000 1536 3072 128 32 32.000 2048 4096 128 32 44.100 2822.4 5644.8 128 32 48.000 3072 6144 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 9 TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 WCLK www.ti.com RIGHT CHANNEL LEFT CHANNEL BCLK DIN MSB LSB LSB MSB Left Justified Mode RIGHT CHANNEL LEFT CHANNEL WCLK BCLK MSB DIN LSB LSB MSB Right Justified Mode LEFT CHANNEL WCLK RIGHT CHANNEL BCLK DIN MSB LSB MSB LSB I2S Mode WCLK BCLK DIN LSB MSB LEFT CHANNEL MSB LSB RIGHT CHANNEL PCM Short Frame Sync 1/fs Figure 9. Interface Format Supporting Four Different Options WCLK (short) Twclks WCLK (long) T FS Tbclk T bclkh T bclkl BCLK T dv T ds T dh DIN Figure 10. Interface Timing for I2S (Long) or PCM (Short) WCLK Options 10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 TLV320DAC3202 www.ti.com SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 AUDIO Channel Performance The receive channel of TLV320DAC3202 converts the digital signal to analog for the headset amplifier through a highly efficient low-power DAC. The signal in stereo I2S format with configurable data size drives the Class G amplifier after the conversion. The channel gain is implemented in two segments in digital and analog domains. In digital domain the gain steps have finer resolution whereas in the analog domain the amplifier gain steps are defined at 2-dB resolution. The detail of volume control is shown in the register map description. The mixing feature allows the left and right channels to be combined in digital domain prior to conversion and then routed to either channel. The audio signal can be disabled either by soft mute feature in the digital domain or by disabling the output amplifier. FLT Gain DIN WCLK DIGMIXL HSL HSLDRV DAC SD L Class G HSOUTL HSLDAC I2S BCLK FLT Gain HSOUTR DIGMIXR HSR DAC SD R Class G HSRDRV HSRDAC Figure 11. Audio Path Diagram Volume Control The volume control module is implemented with combination of digital and analog gain settings for optimum performance. The total gain range is from 4 dB to -59 dB with variable steps. The gain for the amplifiers is from 4 dB to -12 dB in 2-dB steps. Table 8. Volume Control Register Decoding REGISTER VALUE GAIN (dB) GAIN_ANALOG (dB) 31 4 4 GAIN_DIGITAL (dB) 0 30 3 4 -1 29 2 2 0 28 1 2 -1 27 0 0 0 26 -1 0 -1 25 -2 -2 0 24 -3 -2 -1 23 -4 -4 0 22 -5 -4 -1 21 -6 -6 0 20 -7 -6 -1 19 -8 -8 0 -1 18 -9 -8 17 -10 -10 0 16 -11 -10 -1 15 -13 -12 -1 14 -15 -12 -3 13 -17 -12 -5 12 -19 -12 -7 11 -21 -12 -9 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 11 TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 www.ti.com Table 8. Volume Control Register Decoding (continued) REGISTER VALUE GAIN (dB) GAIN_ANALOG (dB) GAIN_DIGITAL (dB) 10 -23 -12 -11 9 -25 -12 -13 8 -27 -12 -15 7 -31 -12 -19 6 -35 -12 -23 5 -39 -12 -27 4 -43 -12 -31 3 -47 -12 -35 2 -51 -12 -39 1 -55 -12 -43 0 -59 -12 -47 SYSTEM AND CONTROL Power-Up Sequence The power up sequence of the IC is initiated by asserting the CHIP_EN bit to logic ‘1’. It is expected that VBAT and VIO are powered up prior to assertion of this bit. The HSL/R amplifiers are then enabled by writing to their perspective control bits in register address 0x01. The I2S clock must be present prior to power up sequence and maintain its activity during active mode. The figure below shows the typical power up sequence of the IC. The IC power up state machine updates I2C register bits corresponding to enabled modules. I2C register control can subsequently be used to turn OFF unused circuits. The power down sequence is initiated by de-asserting the CHIP_EN bit in CODEC_EN register. It is expected that the CHIP_EN bit is de-asserted prior to turning OFF the VIO supply. The HS driver power on/off sequence is designed to be click-pop free. AVDD T1 > 0 DVDD (1.8V) 1ms CHIP_EN = 1 15.5ms Start up Time Standby State 3ms Wake up Time HSL/R_EN = 1 Active State Figure 12. Power-Up Sequence Timing 12 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 TLV320DAC3202 www.ti.com SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 Dual Supply Charge Pump The charge pump on TLV320DAC3202 has dual-supply capability module with automatic selection which can be either from VBAT or VIO depending on the input signal range and load current that is detected. Charge pump generates both the positive and negative rails for low and high headset rails. For typical listening range where the signal level is low, the supply is expected to be from VIO and headset rail is 0.9 V. For higher signal levels where higher current drains from VIO are not possible, the IC uses an automatic input voltage and load current threshold based algorithm to switch ON the VPOW regulator and use VPOW, which is powered from VBAT. It is designed to power the left and right headset drivers up to rated full scale output. The threshold point to transition between the low and high power range can be programmed through I2C interface. There are two threshold points controlled by register bits, one for each of left and right channels. The threshold monitor mechanisms for each channel can be independently enabled and programmed. The load current threshold settings can be 10.5 mA, 11.5 mA, 12.5 mA (default) or 13.5 mA per channel. Output Impedance In order to share the output connector between audio and other signals such as video output, a high impedance option is implemented that can be enabled through I2C controller. In this mode the output impedance is increased while the signal is muted. As shown in below table the output impedance is large enough to avoid an unwanted attenuation of other signal connected to the jack contact. Table 9. Output Impedance in Various Mode Settings CHIP_EN HiZ HS_EN IMPEDANCE MODE 0 0 0 150 Ω Shut down 0 0 1 150 Ω Shut down 8.5 Ω at 40 kHz 600 Ω at 6 MHz 0 1 0 HiZ 0 1 1 - Invalid 1 0 0 150 Ω Active, HS off 1 0 1 - Active 1 1 0 - Invalid 1 1 1 - Invalid 400 Ω at 13 MHz I2C INTERFACE The control interface for programming the registers on TLV320DAC3202 is done using a standard I2C interface with the IC operating in slave mode. The 2 modes of operation as defined in Ref [1,2] are (a) Standard-mode up to 100 kbit/s, and (b) Fast-mode up to 400 kbit/s. The IC defaults to fast-mode. A 7-bit slave addressing is used. The device I2C slave address is fixed to 0011010X, with 00110100 for master write cycle (TLV320DAC3202 reads) and 00110101 for master read cycle (TLV320DAC3202 writes). For data and clock lines, pull up resistors are required and are expected to be provided as defined in section 7 of Ref [1]. References [1] UM10204: I2C-Bus Specification and user manual Rev. 03 – 19 June 2007 [2] The I2C-BUS SPECIFICATION VER 2.1 January 2000 [3] I2S Bus specification, Phillips Semiconductors, June 1996 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 13 TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 www.ti.com Register Map Table 10. Register Map Designation for I2C Interface ADDRESS REGISTER D7 D6 D5 D4 - - D3 D2 D1 - - THERMAL D0 INITIAL VALUE ACCESS (R, W, WR) 0x00 14 0x01 EN HSL_EN HSR_EN 0x02 VOL_CTRL HSL_MUTE HSR_MUTE 0x03 HIZ_CTRL - - 0x04 ASICREV 0x05 I2CID 0x06 HS_LP2HP _SW1 HS_LP_MODE HS_BYPASS _CUR_SW 0x07 CODEC_EN HSL_DRV_EN HSR_DRV_EN CP_EN PLL_EN HSR_FIR_EN HSL_RAMP _DIS HSR_RAMP _DIS 0x08 CODEC_CTRL CHIP_EN 0x00 R - 0xC0 WR HIZ_R 0x00 WR 0x00 R 0x34 R 0x00 WR 0x00 W 0x00 WR VOLCTRL(4:0) SPARE SPARE - - HIZ_L ASICID(3:0) VERSION(3:0) I2CID(7:0) HSL_FIR_EN 0x09 INTF 0x0A FIR INTF_MODE(1:0) 0x0B CP CP_OPEN CP_HPMODE 0x0C REF - - - - HSL_CUR_THRD(1:0) REF_EN INTF_DATA_SIZE(1:0) HSR_CUR_THRD(1:0) - DACL_EN HSL_MIX_CTRL(1:0) - CLK_MODE(3:0) HSR_MIX_CTRL(1:0) INTF_FRAME_SIZE(2:0) - CP_ENCLAMP - INTERPOLATION(1:0) CP_FET_SIZE(2:0) - REF_CM_HIGH_SWING(1:0) - REF_CUR(3:0) 0x0D DAC DAC_INV_CLK OFFSET _CORR_EN 0x0E HS_LP2HP _SW2 HP_LOW _IBIAS HS_BYPASS _SHTDN 0x11 PM_EN REFSYS_EN - 0x12 PM_LDO - - 0x18 UNLOCK_PM - - - - - - - 0x19 PM_TEST1 TEST_REFSYS _SET_BG EEPROM _BYPASS SPARE TEST_VANA _HIZ - TEST_VPOW _HIZ EEPROM _PROGRAM 0x1A HS_TEST SPARE SPARE TEST_HSL _TM1 TEST_HSL _OCDIS TEST_DC2DAC TEST_ISUM _DETECT TEST_HSR _TM1 0x1B CODEC_TEST1 - - SPARE_W 0x1C CODEC_TEST2 0x1D CODEC_TEST3 SPARE 0x1E CODEC_TEST4 0x1F CODEC_TEST5 VANA_EN VPOW_OUT(1:0) CODEC_TEST_MUX(3:0) TEST_BYP _MOD DACR_SWING HS_SW_OVER_SPEED(1:0) DACL_SWING HS_AMP_SW_OVER(1:0) - VPOW_EN - - TEST_BYP_FIR TEST_BYP TEST_PLL_ _RANDOMIZER OVERRIDE_EN CP_TEST(1:0) DACR_EN DACR_LP HS_HIGHAMP_SW_OVER(1:0) - PLL_TEST_MODE_L(5:0) PLL_TEST_MODE_H(7:0) Submit Documentation Feedback - TEST_CP_CLK(2:0) WR WR 0x00 WR 0x00 WR 0x00 WR 0x80 WR 0x00 W 0x00 WR UNLOCK_PM 0x00 WR DIEID _PROGRAM 0X00 WR TEST_HSR _OCDIS 0x00 WR 0x00 WR 0x00 WR 0x00 WR 0x30 WR 0x00 WR VANA_OUT(1:0) PLL_PRE_DIV_OVR(4:0) PLL_FB_LOOP_OVR(6:0) DACL_LP 0x00 0xA3 Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 TLV320DAC3202 www.ti.com SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 PCB DEVELOPMENT The following table explains the PCB recommendations. In addition, it is recommended to split the ground plane into analog and digital segment for clean and noisy signals. They should be connected only in a single point to avoid ground loop. Table 11. PCB Recommendations BALL NAME DESCRIPTION AVSS Analog ground LAYOUT RECOMMENDATIONS VANAG Connected to VANA via capacitor Connect to output capacitor with < 10 mΩ. VANA Analog LDO output Connect to output capacitor with < 10 mΩ. DVDD IO/Digital supply CFLYP FLY capacitor "+" terminal Minimize the resistance path with adequate decoupling very close to the ball. Connect to positive side of output capacitor with < 10 mΩ. Connect to AVSS via output capacitor. The capacitor trace on the AVSS side of the capacitor should not be connected to GND plane directly but at the AVSS pin. See application diagram. VREF Analog reference output AVDD 2.3-V to 4.8-V battery input Minimize the resistance path with adequate decoupling very close to the ball. VPOW CP LDO output Minimize the resistance path with adequate decoupling very close to the ball. DVSS Digital ground Connect to separate GND plane for noisy signals, i.e. PLL and interfaces. Connect the two planes in a single point to avoid GND loop. CFLYN FLY capacitor "-" terminal Connect to negative side of output capacitor with < 10 mΩ. SDA I2C data Keep this away from clean quite signal paths over the digital GND plane. SCL I2C CLK in Keep this away from clean quite signal paths over the digital GND plane. HSOUTG HS feedback ground Trace impedance must be very small, < 60 mΩ. This is important for cross talk reduction. Connection to GND plane must be at IC ball. HSVDD HS positive supply HSOUTL HS output left DIN I2S downlink data Keep this trace away from quite GND/signal traces. WCLK I2S word clock Keep this trace away from quite GND/signal traces. BCLK I2S bit clock Keep this trace away from quite GND/signal traces. HROUTR HS output right HSVSS HS negative supply Decouple this path to DVSS with trace impedance of < 20 mΩ. Must be routed in differential pair with GNDHS to the connector. Match the impedances and as small as possible. Must be routed in differential pair with GNDHS to the connector. Match the impedances and as small as possible. Decouple this path to DVSS with trace impedance of < 20 mΩ. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 15 TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 www.ti.com TYPICAL CIRCUIT CONFIGURATION VIO 4.7kW 4.7kW Processor or MODEM 15Ω SCL HSOUTL SDA HSOUTG 10nF 10nF HSOUTR DIN 15Ω WCLK 2.2 μF BCLK CFLYP VANA CFLYN 2.2 μF HSVSS 1μF HSVDD VANAG VBAT 2.2 μF AVDD VPOW 2.2 μF DVSS VIO AVSS 2.2μF VREF DVDD 2.2μF 2.2μF Figure 13. Typical Circuit Table 12. External Component List (1) (1) 16 PIN NAME DESCRIPTION AVDD 2.2 µF, 6.3-V tolerance VPOW 2.2 µF, 6.3-V tolerance VREF 2.2 µF, 6.3-V tolerance VANA 1 µF, 6.3-V tolerance HSVDD 2.2 µF, 6.3-V tolerance HSVSS 2.2 µF, 6.3-V tolerance CFLYP/N 2.2 µF, 6.3-V tolerance DVDD 2.2 µF, 6.3-V tolerance The headset amplifiers output power and distortion are characterized using the nominal capacitance for the supply, ground, output loads, and the charge pump fly cap as shown in the above application diagram. To meet the stated performance with discrete component variations, it is recommended that the external components be chosen to account for manufacturing tolerance, voltage and temperature de-rating. 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