AN-17 DDR SDRAM Memory Termination AN-17 USING THE LX1672 AND LX1673 FOR DDR SDRAM MEMORY TERMINATION LX1672 Protected by US Patents: 6,285,571 & 6,292,378 I N T E G R A T E D Copyright © 2002 Revision 1.2b, 3/8/2006 P R O D U C T S Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 1 AN-17 DDR SDRAM Memory Termination TABLE OF CONTENTS 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 INTRODUCTION..................................................................................................................................................... 3 SDR vs DDR SDRAM ............................................................................................................................................. 4 TERMINATION METHODS .................................................................................................................................... 5 SSTL_2 TERMINATION ......................................................................................................................................... 5 SSTL_2 DRIVERS and RECEIVERS ..................................................................................................................... 7 SSTL_2 VOLTAGES............................................................................................................................................... 7 VTT and VREF ............................................................................................................................................................ 8 LX1672 CONTROLLER .......................................................................................................................................... 9 LX1673 CONTROLLER ........................................................................................................................................ 14 Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 2 AN-17 DDR SDRAM Memory Termination 1.0 INTRODUCTION The demand for higher memory speeds has resulted in evolution of the established PC100 / PC133 SDRAM to the newer Double Data Rate (DDR) SDRAM which clocks data on both positive and negative transitions of the clock, two data transfers per clock cycle result in a data rate of 266 MHz while the command and address lines only transition on the positive clock edges for a 133 MHz rate, speed grades for DDR allow for both 200 MHz and 266 MHz data transfer rates. At higher data rates it is necessary to terminate the bus accurately to manage ringing and reflections. Stub Series Terminated Logic (SSTL) has been developed to allow data rates of 266MHz as required for DDR SDRAMs. JEDEC has released a specification (EIA/JESD8-9A) that defines I/O levels and conditions for operation with SSTL_2 , for 2.5 volt levels vs. the 3.3 volts used in PC133. A new terminating voltage (VTT) is required as a supply for the terminating resistors and the line driver / receiver supply ( VDDQ) is a second new supply voltage required by DDR SDRAM. The LX167X family of synchronous buck controllers can supply the power required for the termination voltage. The three members of this family LX1671,72,73 have either three, two, or one PWM controllers and one linear regulator controller. Power requirements in addition to VTT can be met with the additional controllers. The LX1672 can supply both VDDQ and VTT using only one package, an example of a circuit using this part is shown in section 8.0. Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 3 AN-17 DDR SDRAM Memory Termination 2.0 SDR VS DDR SDRAM DDR memory systems are configured in the same way as the PC133 SDRAM with many similarities in the DIMM packaging and communication protocols, however significant differences exist. The internal addressing , command control interface, and refresh requirements are identical. Some key differences are the reduction in VDD and VDDQ voltages to 2.5 volts and the requirement for a terminating voltage (VTT), there is also a reference voltage (VREF) that is used on one side of the differential line receiver. The new voltages VREF and VTT must meet the JEDEC standard to insure proper data transmission. VTT has a unique feature in that it must source and sink current. PARAMETER SDR VDD and VDDQ The DDR clock is a differential signal and allows data transfer on both positive and negative transitions, all other lines are single ended, DDR also uses a new bi-directional data strobe. SDR memory employed a fixed voltage level for signal interface and while DDR data is still single ended the addition of VREF on the negative side of the line receiver allows symmetrical data transfer with superior noise immunity, lower voltage swings on the signal lines, and less jitter. Table 1 shows some of the key differences between SDR and DDR memory systems with emphasis on DC voltages since memory commands are not the focus of this document. DDR COMMENTS 3.3 V 2.5V Lower power requirements for DDR VREF N/A 1/2 VDDQ Used on line receiver negative input VTT N/A = VREF 1X Clock 2X Clock DDR has a Differential Clock LVTTL SSTL_2 DDR --- JEDEC standard EIA/JESD8-9A Data Rate Signal Interface Supply for terminating resistors Table 1 – SDR vs DDR Key Differences (Partial List) Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 4 AN-17 DDR SDRAM Memory Termination 3.0 TERMINATION METHODS Several methods shown in Figure 1 can be used to terminate a transmission line into its characteristic impedance to minimize ringing and reflections. From the power dissipation point of view there are significant differences that must be taken into account when a large number of lines are being terminated. VDD VDD RS (Fig 1a) Shows a simple resistor to ground with no power dissipation when data is low, dissipation is VDD2 / RT+RS) for a high signal. Although this works well for single ended lines power consumption is data dependant. The open circuit voltage is zero which will not work with the line receiver used for SSTL. RT VSS VSS a - Grounded Termination resistor VDD The second method (Fig 1b) uses two resistors on each line. The Thevenin equivalent is a terminating resistor of RTΩ and an open circuit voltage of VDD/2. For RS=RT power dissipation for both high and low signals is (3 VDD)2 / 8RT. If the data line is floating there is a constant power dissipation of VDD2/4RT. VDD VDD 2RT RS 2RT VSS A third method (Fig 1c) uses a single resistor connected to a terminating voltage VDD/2. For either a high or low signal the dissipation is (VDD/2)2 / (RT+RS). There is no power dissipated when the line is floating. This offers a three to one power dissipation advantage over the Thevenin termination with only one termination resistor and also has an open circuit voltage of VDD/2. VSS b - Thevinin Termination VDD VDD/2 VDD RT RS VSS VSS c - Termination Resistor Connected To VDD / 2 Figure 1 – Three Bus Termination Methods 4.0 SSTL_2 TERMINATION Some key differences between SSTL_2 and Figure 1c are the addition of a different supply voltage for the line driver (VDDQ), a termination voltage (VTT), and the reference voltage (VREF) on the negative input of the line receiver . Power dissipation in RT and RS is determined by the current output of the line driver which will determine the magnitude of the signal swing. With worst case conditions for a Class II line driver the maximum current in RT could be 31.8 mA ( see section 7.0). The SSTL_2 specification requires a minimum signal level, at the input of the line receiver, of 380 mV above and below VREF with the line driver Vout at its maximum high and low voltages. Two classes of termination (Class I and II), Figures 2 and 3, are specified and are intended for different line drivers There are several other termination methods allowed by the SSTL_2 specification that are not in wide spread use and are not shown here. Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 5 AN-17 DDR SDRAM Memory Termination VTT = VREF VDDQ RT 50Ω VDD + RS 25Ω - VREF VSS VSS Figure 2 – SSTL_2 Class I Termination VTT VTT = VREF = VREF VDDQ RT 50Ω RT 50Ω VDD + RS 25Ω VREF VSS VSS Figure 3 – SSTL _2 Class II Termination SSTL_2 Class I is used with line drivers having a minimum of 7.6 mA sink or source capability and Class II is used with line drivers having a minimum of 15.2 mA sink and source capability. A variation of Class II is to Copyright © 2002 Revision 1.2b, 3/8/2006 use a single 25Ω termination resistor at the line receiver. In either case the effective RT is 25Ω resulting in the same current demand on the VTT supply. Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 6 AN-17 DDR SDRAM Memory Termination 5.0 SSTL_2 DRIVERS AND RECEIVERS voltage for best noise margins, this gives very good performance since the two transistors are matched and the threshold voltage can be tightly controlled by VREF. Figure 4 shows the basic configuration for the driver and receiver used with SSTL_2. The driver in Fig 4a is not much different from line drivers used in PC133 but has greater drive capability. The receiver in Fig 4b has a differential input and a reference voltage on one side. The data is single ended but must be centered on the VREF VDDQ = 2.5V VDDQ VOUT OUT DATA INPUT VREF VSSQ Figure 4a VSS Figure 4B Figure 4 – SSTL_2 Line Driver and Receiver 6.0 SSTL_2 VOLTAGES JEDEC standard JESD8-9A contains values for the key voltages which are summarized in Table 2 SYMBOL PARAMETER VDD Device Supply Voltage VDDQ MIN NOMINAL MAX UNITS VDDQ Output Supply Voltage 2.3 2.5 2.7 V VREF Input Reference Voltage 1.15 1.25 1.35 V VTT Termination Voltage VREF -.04 VREF VREF +.04 V Table 2 Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 7 AN-17 DDR SDRAM Memory Termination Some points to keep in mind when working with these values. 1 2 VDD is not specified but must be greater than or equal to VDDQ (3.3 V is allowed although the DDR SDRAM specification JESD79 calls for a migration to 2.5 V) VREF is one half of VDDQ (plus or minus 8%) and must track it at all times. (The JEDEC specification allows deviation from VDDQ/2 but most designers will stay with nominal values.) 3 4 5 6 VTT must be within 3.2% of VREF. VTT must track any changes in VREF over all operating conditions. The peak to peak noise on the VREF line must not exceed +/-2% of the VREF DC value. This only allows 25mV of noise. There is no specification for noise on the VTT voltage. 7.0 VTT AND VREF VREF is only used as an input to devices with very low input current so does not need a low source impedance except for the requirement to keep noise within the 25mV limit. VREF can be supplied by the output of an operational amplifier with appropriate bypassing but this may cause stability problems with the amplifier. A simple and easy VREF source is to use a resistive divider from VDDQ and bypass it at a number of locations with capacitors to the VDDQ and VSSQ rails. The balanced bypassing helps to insure that VREF is kept midway between VDDQ and VSSQ even in the presence of transients. VDDQ 10K Ω VDDQ (VDDQ max-VTT min) / (RT+RS) = 31.8 mA of VTT current when high, or sink VTT max / (RT+ RS) = 27.8 mA when low. The assumption of a 0 Ω driver is made because SSTL-2 specifies only the minimum output driver current. VDDQMAX = 2.7V VDDQ .1 uF RT 25Ω .1 uF Line Driver .1 uF VTTMAX = 1.39V VTTMIN=1.11V 0Ω VREF 10K Ω A driver could source (Figure 10) .1 uF 0Ω VSSQ VSSQ VSSQ Figure 5 – VREF Divider and Bypassing RS 25Ω VSSQ = 0 The receiver uses VREF as one side of the its input so any noise or deviation in VREF voltage will result in timing errors and jitter. A number of bypass capacitors (ceramic multilayer) located at each DIMM will keep the noise within specification. As always good layout techniques are essential. Since VTT is used to supply current to the terminating resistors it must have a low source impedance and be able to supply enough current for the number of lines to be terminated. Figure10 – Worst Case RT current Under nominal conditions (VDDQ=2.5 V and VTT = 1.25 V) the line driver can source or sink 25 mA per line with a 0 Ω output impedance line driver. A bus with equal distribution of high and low signals would place no demand on the VTT supply, however a bus that had all high or all low signals could source or sink currents of several amperes, even with nominal values. VTT must be supplied by a low output impedance source to remain within specification as the loads change. Using worst case conditions (VDDQ max = 2.7V, VTT min = 1.11V, VTT max = 1.39 V and 0 Ω driver output resistance) but nominal 25 Ω RS and RT. Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 8 AN-17 DDR SDRAM Memory Termination 8.0 LX1672 CONTROLLER With a number of DIMMs operating from 2.5 volts and the need to generate VTT at a significant amount of current two new voltages are now required on the motherboard. The LX1672 is a dual PWM that can supply both voltages and output current can be scaled to suit the specific board requirements. The LX1671 with three PWMs and the LX1673 with one PWM can be substituted if applicable. The PWM controllers are nearly identical on all devices. The VTT voltage must track VREF and be able to source and sink current depending on the state of the data. A supply topology that meets this requirement is a synchronous buck regulator with an error amplifier input that can be connected to an external reference voltage. The LX1672 has one PWM with the error amplifier inputs pinned out. VREF can be connected directly to the positive error amplifier input to insure that VTT will be at one half of VDDQ and stay within tolerance over changes in the VDDQ voltage as required by the SSTL_2 specification. Due to the relatively high currents required for a large number of terminating resistors, 2A to 6 A, the VTT supply should be as close as possible to the terminating resistors Copyright © 2002 Revision 1.2b, 3/8/2006 and use wide etch in both the VTT and return paths, a number of bypass capacitors (.1uf ceramic multilayer) should located at the terminating resistors. Figures 6 and 7 are block diagrams showing the LX1672 developing both VTT and VDDQ from a 3.3 volt input, Figure 8 is a schematic of the same configuration showing the complete solution to develop both voltages. The LDO is not shown but could be connected if a third output is required. When an external reference is used the connection between the error amplifier positive input and the Soft Start pin is lost and Soft Start will not function. It is recommended that the external reference voltage have an R-C time constant that will be long enough to allow the output capacitor to charge slowly. For details on circuit operation, component selection , and other circuit configurations see the Microsemi LX1672 Data Sheet and LX1672 Product Design Guide or equivalent documents for the LX1671 and LX1673. Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 9 AN-17 DDR SDRAM Memory Termination RSET ISET +5V CS2 VIN CS Comp IRESET PWM + VTRIP VS2 ISET R Q S Q VC2 CIN HO2 L3 VTT ESR EO2 LO2 COUT PG2 +5V Error Comp + FB2 VCCL Hiccup - + Amplifier/ Compensation VREF RF2 20k 16V Ramp Oscillator VREF = 1/2 VDDQ UVLO +5V 16V UVLO VCC S F 5.5V FAULT S R S SS1 TEMP SS2 SS/ENABLE DIS 2 CSS Figure 6 – LX1672 VTT Supply Block Diagram Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 10 AN-17 DDR SDRAM Memory Termination RSET ISET CS1 +12V CS Comp IRESET PWM + VTRIP VS1 VIN(5V) ISET R Q S Q R2 VC1 CIN R1 HO1 VDDQ L1 ESR EO1 LO1 COUT PG1 +5V Error Comp + FB1 VCCL Hiccup - + Amplifier/ Compensation VREF 16V 20k Ramp Oscillator UVLO 16V +5V UVLO VCC S F FAULT S R S TEMP SS1 5.5V SS2 SS/ENABLE DIS1 PWGD (MLP Only) CSS Figure 7 – LX1672 VDDQ Supply Block Diagram Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 11 AN-17 DDR SDRAM Memory Termination +5V C11 CR1 CR2 C12 +5V +3.3V HO2 LO2 PG2 LDGD VC2 VC1 C7 + Q1 HO1 LO1 PG1 LDFB LDDIS VCCL DGND VCC C10 VREF =1/2 VDDQ R8 R7 R6 AGND DIS2 SS2 RF2 FB2 VS1 CS1 EO1 FB1 SS1 EO2 DIS1 CS2 VS2 VDDQ 2.5V L1 + Q2 C1 + C2 +5V C4 R5 R4 R3 R1 C5 R2 C6 +3.3V + Q3 C9 + L2 Q4 C8 VTT 1.25V + Figure 8 – Schematic LX1672 VTT and VDDQ supply Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 12 AN-17 DDR SDRAM Memory Termination MISCELLANEOUS COMPONENTS Line Item 1 2 3 4 Part Description PWM Controller MOSFET N Channel Schottky Diode, 1A 20V Inductor 5.0µH, 6.5A Manufacturer & Part # MICROSEMI LX1672-03CLQ VISHAY Si4842DY MICROSEMI UPS5817 COOPER CTX5-4A Case Reference Designators Qty MLP SO-8 PWRMITE SMD U1 Q1 – Q4 CR1, CR2 L1, L2 1 4 2 2 CAPACITORS Line Item 1 2 3 4 5 Part Description 180µF, 4V Polymer Electrolytic 270µF, 2V Polymer Electrolytic 0.1µF, 25V ±10% 0.22µF, 25V ±10% 4.7µF, 6.3V Ceramic Part Description Case Reference Designators Qty CDE ESRE181M04B CDE ESRE271M02B ROHM MCH182CN104KK ROHM MCH182CN224KK MURATA GMR219R60J475K D 7.3 x 4.3 0805 0805 0805 C1, C2, C6, C7 C8, C9 C5, C11, C12 C10 C4 4 2 3 1 1 Case Reference Designators Qty 0805 0805 0805 R2, R3, R5, R6, R8 R4, R7 R1 5 2 1 RESISTORS Line Item 1 2 3 Part Description 2K 1% 1/8W 200K 1% 1/8W 4.42K 1% 1/8W Part Description ROHM MCR10F2001 ROHM MCR10F2003 ROHM MCR10F4421 Table 3 – Bill Of Material for LX1672 VTT and VDDQ Supply Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 13 AN-17 DDR SDRAM Memory Termination 9.0 LX1673 CONTROLLER The LX1673 single phase PWM controller may be used to generate two output voltages if the internal LDO controller is used. Figure 10 is a block diagram of the LX1673 showing its use as a single output VTT supply. Figure 11 is a schematic of the LX1673 configured for a VTT supply with the LDO feature not being used. When an external reference is used the connection between the error amplifier positive input and the Soft Start pin is lost and Soft Start will not function. It is recommended that the external reference voltage have an R-C time constant that will be long enough to allow the output capacitor to charge slowly. RSET ISET +5V CS 3.3V CS Comp IRESET VS VTRIP PWM + R Q ISET S Q VC1 CIN TDRV L1 ESR EAO BDRV VTT 1.25V COUT PGND +5V Error Comp + EA- VREF =1/2 VDDQ VCCL Hiccup - + Amplifier/ Compensation VREF 16V 20k EA+ +5V 16V UVLO Ramp Oscillator UVLO VCC S F FAULT S R S TEMP 5.5V SS1 SS CSS DIS Figure10 – LX1673 VTT Supply Block Diagram Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 14 AN-17 DDR SDRAM Memory Termination V in 3 .3 V + C 1 ,C 2 1 80u F +5V Q1 S i4 82 4 CR1 U P S 5 81 7 C5 VT T 1.25 V L1 5u H .1u F Q2 S i4 82 4 + C 3 ,C 4 27 0u F 20 19 18 LDVCC PW GD 17 VC1 TDRV +5V 16 PGND 1 15 LD G D BDRV 2 C6 4.7 uF 14 LDFB VCCL U1 LX 1673 3 LD D IS 4 VCC VS AGND CS 5 6 SS 7 EA+ 8 EA9 R4 12 DGND D IS C 7 4.7u F 13 10 +5V 11 R1 EAO 4 .4 2K 10 R3 2 00 K R2 4.4 2K C8 .1u F V REF = 1/2 V D D Q Figure 11 – Schematic LX1673 VTT Supply (LDO not used) Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 15 AN-17 DDR SDRAM Memory Termination MISCELLANEOUS COMPONENTS Line Item 1 2 3 4 Part Description PWM Controller MOSFET N Channel Schottky Diode, 1A 20V Inductor 5.0µH, 6.5A Manufacturer & Part # MICROSEMI LX1672-03CLQ VISHAY Si4842DY MICROSEMI UPS5817 COOPER CTX5-4A Case Reference Designators Qty MLP SO-8 PWRMITE SMD U1 Q1 – Q2 CR1 L1 1 2 1 1 CAPACITORS Line Item 1 2 3 4 Part Description 180µF, 4V Polymer Electrolytic 270µF, 2V Polymer Electrolytic 0.1µF, 25V ±10% 4.7µF, 6.3V Ceramic Part Description Case Reference Designators Qty CDE ESRE181M04B CDE ESRE271M02B ROHM MCH182CN104KK MURATA GMR219R60J475K D 7.3 x 4.3 0805 0805 C1, C2 C3, C4 C5, C8 C6, C7 2 2 2 2 Case Reference Designators Qty 0805 0805 0805 R4 R3 R1, R2 1 1 2 RESISTORS Line Item 1 2 3 Part Description 10 Ohm, 1% 1/8W 200K 1% 1/8W 4.42K 1% 1/8W Part Description ROHM MCR10F10R0 ROHM MCR10F2003 ROHM MCR10F4421 Table 4 – Bill Of Material for LX1673 VTT Supply Copyright © 2002 Revision 1.2b, 3/8/2006 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax:: 714-893-2570 Page 16