M Section 25. LCD HIGHLIGHTS This section of the manual contains the following major topics: 25.1 Introduction ..................................................................................................................25-2 25.2 Control Register ...........................................................................................................25-3 25.3 LCD Timing ..................................................................................................................25-6 25.4 LCD Interrupts............................................................................................................25-12 25.5 Pixel Control...............................................................................................................25-13 25.6 Voltage Generation ....................................................................................................25-15 25.7 Operation During Sleep .............................................................................................25-16 25.8 Effects of a Reset.......................................................................................................25-17 25.9 Configuring the LCD Module......................................................................................25-17 25.10 Discrimination Ratio ...................................................................................................25-18 25.11 LCD Voltage Generation ............................................................................................25-20 25.12 Contrast .....................................................................................................................25-22 25.13 LCD Glass..................................................................................................................25-22 25.14 Initialization ................................................................................................................25-23 25.15 Design Tips ................................................................................................................25-24 25.16 Related Application Notes..........................................................................................25-25 25.17 Revision History .........................................................................................................25-26 25 LCD 1997 Microchip Technology Inc. DS31025A page 25-1 PICmicro MID-RANGE MCU FAMILY 25.1 Introduction The LCD module generates the timing control to drive a static or multiplexed LCD panel, with support for up to 32 segments multiplexed with up to four commons. It also provides control of the LCD pixel data. The interface to the module consists of three control registers (LCDCON, LCDSE, and LCDPS) used to define the timing requirements of the LCD panel and up to 16 LCD data registers (LCD00-LCD15) that represent the array of the pixel data. In normal operation, the control registers are configured to match the LCD panel being used. Primarily, the initialization information consists of selecting the number of commons and segments required by the LCD panel, and then specifying the LCD Frame clock rate to be used by the panel. Once the module is initialized for the LCD panel, the individual bits of the LCD data registers are cleared/set to represent a turned-on pixel respectively. Once the module is configured, the LCDEN bit (LCDCON<7>) is used to enable or disable the LCD module. The LCD panel can also operate during sleep by clearing the SLPEN bit (LCDCON<6>). Figure 25-1: LCD Module Block Diagram Data Bus LCD RAM 32 x 4 128 to SEG<31:0> TO I/O PADS 32 MUX Timing Control LCDCON COM3:COM0 LCDPS TO I/O PADS LCDSE Internal RC osc T1CKI Fosc/4 DS31025A-page 25-2 Clock Source Select and Divide 1997 Microchip Technology Inc. Section 25. LCD 25.2 Control Register Register 25-1: LCDCON Register R/W-0 LCDEN bit 7 R/W-0 SLPEN U-0 — R/W-0 VGEN R/W-0 CS1 R/W-0 CS0 R/W-0 LMUX1 bit 7 LCDEN: Module Drive Enable bit 1 = LCD drive enabled 0 = LCD drive disabled bit 6 SLPEN: LCD Display Sleep Enable bit 1 = LCD module will stop operating during SLEEP 0 = LCD module will continue to display during SLEEP bit 5 Unimplemented: Read as '0' bit 4 VGEN: Voltage Generator Enable bit 1 = Internal LCD Voltage Generator Enabled, (powered-up) 0 = Internal LCD Voltage Generator powered-down, voltage is expected to be provided externally bit 3:2 CS1:CS0: Clock Source Select bits 00 = Fosc/256 01 = T1CKI (Timer1) 1x = Internal RC oscillator bit 1:0 LMUX1:LMUX0: Common Selection bits Specifies the number of commons and the bias method LMUX1:LMUX0 00 01 10 11 MULTIPLEX Static 1/2 1/3 1/4 (COM0) (COM0, 1) (COM0, 1, 2) (COM0, 1, 2, 3) R/W-0 LMUX0 bit 0 BIAS Max # of Segments Static 1/3 1/3 1/3 32 31 30 29 Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-3 PICmicro MID-RANGE MCU FAMILY Register 25-2: LCDPS Register U-0 — bit 7 U-0 — U-0 — U-0 — bit 7:4 Unimplemented, read as '0' bit 3:0 LP3:LP0: Frame Clock Prescale Selection bits R/W-x LP3 R/W-x LP2 R/W-x LP1 LMUX1:LMUX0 Multiplex 00 Static Clock source / (128 * (LP3:LP0 + 1)) 01 1/2 Clock source / (128 * (LP3:LP0 + 1)) 10 1/3 Clock source / ( 96 * (LP3:LP0 + 1)) 11 1/4 Clock source / (128 * (LP3:LP0 + 1)) R/W-x LP0 bit 0 Frame Frequency = Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Register 25-3: - n = Value at POR reset Generic LCDD (Pixel Data) Register Layout R/W-x SEGs COMc bit 7 bit 7:0 R/W-x SEGs COMc R/W-x SEGs COMc R/W-x SEGs COMc R/W-x SEGs COMc R/W-x SEGs COMc R/W-x SEGs COMc R/W-x SEGs COMc bit 0 SEGsCOMc: Pixel Data bit for segment s and common c 1 = Pixel on (dark) 0 = Pixel off (clear) Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ DS31025A-page 25-4 - n = Value at POR reset 1997 Microchip Technology Inc. Section 25. LCD Register 25-4: LCDSE Register R/W-1 SE29 bit 7 bit 7 R/W-1 SE27 R/W-1 SE20 R/W-1 SE16 R/W-1 SE12 R/W-1 SE9 R/W-1 SE5 R/W-1 SE0 bit 0 SE29: Pin Function Select bits for COM1/SEG31 - COM3/SEG29 1 = pins have LCD segment driver function 0 = pins have digital Input function Note: The LMUX1:LMUX0 setting takes precedence over the SE29 bit, causing pins to become common drivers. bit 6 SE27: Pin Function Select for SEG28 and SEG27 1 = pins have LCD segment driver function 0 = pins have digital Input function bit 5 SE20: Pin Function Select bits for SEG26 - SEG20 1 = pins have LCD segment driver function 0 = pins have digital Input function bit 4 SE16: Pin Function Select bits for SEG19 - SEG16 1 = pins have LCD segment driver function 0 = pins have digital Input function bit 3 SE12: Pin Function Select bits for SEG15 - SEG12 1 = pins have LCD segment driver function 0 = pins have digital Input function bit 2 SE9: Pin Function Select bits for SEG11 - SEG09 1 = pins have LCD segment driver function 0 = pins have digital Input function bit 1 SE5: Pin Function Select bits for SEG08 - SEG05 1 = pins have LCD segment driver function 0 = pins have digital Input function bit 0 SE0: Pin Function Select bits for SEG04 - SEG00 1 = pins have LCD segment driver function 0 = pins have digital I/O function Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Note: - n = Value at POR reset On a Power-on Reset, the LCD pins are configured for LCD drive function. 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-5 PICmicro MID-RANGE MCU FAMILY 25.3 LCD Timing The LCD module has 3 possible clock source inputs and supports static, 1/2, 1/3, and 1/4 multiplexing. 25.3.1 Timing Clock Source Selection The clock sources for the LCD timing generation are: • Internal RC oscillator • Timer1 oscillator • System clock divided by 256 used for device low frequency or sleep operation used for device low frequency or sleep operation The first timing source is an internal RC oscillator which runs at a nominal frequency of 14 kHz. This oscillator provides a lower speed clock which may be used to continue running the LCD while the processor is in sleep. The RC oscillator will power-down when it is not selected or when the LCD module is disabled. The second source is the Timer1 external oscillator. This oscillator provides a lower speed clock which may be used to continue running the LCD while the processor is in sleep. It is assumed that the frequency provided on this oscillator will be 32 kHz. To use the Timer1 oscillator as a LCD module clock source, it is only necessary to set the T1OSCEN (T1CON<3>) bit. The third source is the system clock divided by 256. This divider ratio is chosen to provide about 32 kHz output when the external oscillator is 8 MHz. The divider is not programmable. Instead the LCDPS register is used to set the LCD frame clock rate. The clock sources are selected with bits CS1:CS0 (LCDCON<3:2>). Refer to Figure 25-1 for details of the register programming. TMR1 32 kHz crystal oscillator ÷4 Static ÷2 1/2 4-bit Programmable Prescaler ÷32 COM3 COM2 ÷256 COM1 FOSC LCD Clock Generation COM0 Figure 25-2: ÷1,2,3,4 Ring Counter 1/3 1/4 Internal RC oscillator Nominal FRC = 14 kHz LCDPS<3:0> CS1:CS0 LMUX1:LMUX0 LMUX1:LMUX0 internal data bus DS31025A-page 25-6 1997 Microchip Technology Inc. Section 25. LCD 25.3.2 Multiplex Timing Generation The timing generation circuitry will generate 1 to 4 common’s based on the display mode selected. The mode is specified by bits LMUX1:LMUX0 (LCDCON<1:0>). Table 25-1 shows the formulas for calculating the frame frequency. Table 25-1: Frame Frequency Formulas Multiplex Frame Frequency = Static Clock source / (128 * (LP3:LP0 + 1)) 1/2 Clock source / (128 * (LP3:LP0 + 1)) 1/3 Clock source / (96 * (LP3:LP0 + 1)) 1/4 Clock source / (128 * (LP3:LP0 + 1)) Table 25-2: Approximate Frame Frequency in Hz using Timer1 @ 32.768 kHz or Fosc @ 8 MHz LP3:LP0 Static 1/2 1/3 1/4 2 85 85 114 85 3 64 64 85 64 4 51 51 68 51 5 43 43 57 43 6 37 37 49 37 7 32 32 43 32 Table 25-3: Approximate Frame Frequency in Hz using internal RC osc @ 14 kHz LP3:LP0 Static 1/2 1/3 1/4 0 109 109 146 109 1 55 55 73 55 2 36 36 49 36 3 27 27 36 27 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-7 PICmicro MID-RANGE MCU FAMILY Figure 25-3: STATIC Waveforms Liquid Crystal Display and Terminal Connection V1 COM0 V0 V1 COM0 SEG0 V0 V1 SEG1 V0 SEG7 V1 COM0-SEG0 V0 (selected pixel waveform) SEG6 -V1 SEG5 COM0-SEG1 DS31025A-page 25-8 V0 1 Frame SEG4 SEG3 SEG2 SEG0 SEG1 (non-selected pixel waveform) 1997 Microchip Technology Inc. Section 25. LCD Figure 25-4: 1/2 MUX, 1/3 BIAS Waveform Liquid Crystal Display and Terminal Connection V3 COM0 V2 V1 V0 COM1 V3 V2 V1 COM0 COM1 V0 V3 V2 SEG3 V1 V0 V3 V2 SEG1 SEG3 SEG2 SEG1 SEG0 V1 V0 V3 V2 V1 COM0-SEG3 V0 (selected pixel waveform) -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 (non-selected pixel waveform) -V1 1 Frame -V2 25 -V3 LCD 1997 Microchip Technology Inc. DS31025A-page 25-9 PICmicro MID-RANGE MCU FAMILY Figure 25-5: 1/3 MUX, 1/3 BIAS Waveform V3 Liquid Crystal Display and Terminal Connection V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 SEG0 V1 V0 SEG0 SEG1 SEG2 V3 V2 SEG2 V1 V0 V3 V2 V1 COM0-SEG0 (non-selected pixel waveform) V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG2 V0 (selected pixel waveform) -V1 -V2 -V3 1 Frame DS31025A-page 25-10 1997 Microchip Technology Inc. Section 25. LCD Figure 25-6: 1/4 MUX, 1/3 BIAS Waveform Liquid Crystal Display and Terminal Connection COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM3 COM2 COM1 COM0 SEG0 SEG1 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 (selected pixel waveform) COM0-SEG0 (non-selected pixel waveform) 1 Frame V3 V2 V1 V0 -V1 -V2 -V3 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-11 PICmicro MID-RANGE MCU FAMILY 25.4 LCD Interrupts The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. Writing pixel data at the frame boundary allows a visually crisp transition of the image. This interrupt can also be used to synchronize external events to the LCD. For example, the interface to an external segment driver, such as a Microchip AY0438, can be synchronized for segment data update to the LCD frame. A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a certain fixed time before the frame boundary as shown in Figure 25-7. The LCD controller will begin to access data for the next frame within TFWR after the interrupt. Figure 25-7: Example Waveforms in 1/4 MUX Drive LCD Interrupt occurs Controller accesses next frame data V3 V2 V1 V0 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 1 Frame TFINT Frame Boundary TFWR Frame Boundary TFWR = TFRAME/(LMUX1:LMUX0 + 1) TFINT = (TFWR /2 - (2TCY + 40 ns)) → min. (TFWR /2 - (1TCY + 40 ns)) → max. DS31025A-page 25-12 1997 Microchip Technology Inc. Section 25. LCD 25.5 Pixel Control 25.5.1 LCDD (Pixel Data) Registers The pixel registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Table 25-4 shows the correlation of each bit in the LCDD registers to the respective common and segment signals. Any LCD pixel location not being used for display can be used as general purpose RAM. Table 25-4: LCDD Registers Name LCDD00 LCDD01 LCDD02 LCDD03 LCDD04 LCDD05 LCDD06 LCDD07 LCDD08 LCDD09 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 Note 1: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 COM1 (1) COM1 COM1 COM1 COM1 COM1 COM1 COM1 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 COM2 (1) COM2 (1) COM2 COM2 COM2 COM2 COM2 COM2 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 COM3 (1) COM3 (1) COM3 (1) COM30 COM3 COM30 COM3 COM3 These pixels do not display, but can be used as general purpose RAM. Value on POR, BOR Value on all other Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-13 PICmicro MID-RANGE MCU FAMILY 25.5.2 Segment Enables The LCDSE register is used to select the pin function for groups of pins. The selection allows each group of pins to operate as either LCD drivers or digital only pins. To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. If the pin is a digital input the corresponding TRIS bit controls the data direction. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. Note 1: On a Power-on Reset, the LCD pins are configured as LCD drivers. Note 2: The LMUX1:LMUX0 bits take precedence over the LCDSE bit settings for pins RD7, RD6 and RD5. Example 25-1: BCF BSF BCF BCF MOVLW MOVWF STATUS,RP0 STATUS,RP1 LCDCON,LMUX1 LCDCON,LMUX0 0xFF LCDSE Example 25-2: BCF BSF BSF BCF MOVLW MOVWF DS31025A-page 25-14 Static MUX with 32 Segments ; ; ; ; ; ; Select Bank2 Select Static MUX Make PortD,E,F,G LCD pins configure rest of LCD 1/3 MUX with 13 Segments STATUS,RP0 STATUS,RP1 LCDCON,LMUX1 LCDCON,LMUX0 0x87 LCDSE ; ; ; ; ; ; Select Bank2 Select 1/3 MUX Make PORTD<7:0> & PORTE<6:0> LCD pins configure rest of LCD 1997 Microchip Technology Inc. Section 25. LCD 25.6 Voltage Generation There are two methods for LCD voltage generation, internal charge pump, or external resistor ladder. 25.6.1 Charge Pump The LCD charge pump is shown in Figure 25-8. The 1.0V - 2.3V regulator will establish a stable base voltage from the varying battery voltage. This regulator is adjustable through the range by connecting a variable external resistor from VLCDADJ to ground. The potentiometer provides contrast adjustment for the LCD. This base voltage is connected to VLCD1 on the charge pump. The charge pump boosts VLCD1 into VLCD2 = 2 * VLCD1 and VLCD3 = 3 * VLCD1. When the charge pump is not operating, VLCD3 will be internally tied to VDD. See the Electrical Specifications section for charge pump capacitor and potentiometer values. 25.6.2 External R-Ladder The LCD module can also use an external resistor ladder (R-Ladder) to generate the LCD voltages. Figure 25-8 shows external connections for static and 1/3 bias. The VGEN (LCDCON<4>) bit must be cleared to use an external R-Ladder. Figure 25-8: Charge Pump and Resistor Ladder Block Diagram VDD 10 µA nominal LCDEN Charge Pump VLCD3 VLCDADJ 100k(2) VLCD2 VLCD1 0.47 µF(2) 0.47 µF(2) SLPEN C1 C2 0.47 µF(2) 130k(2) 0.47 µF(2) 10k* (1) 10k(2) (1) VDD 10k(2) (1) VDD 10k* External connections for internal charge pump, VGEN = 1. (1) 5k(2) External connections for external R-ladder, 1/3 Bias, VGEN = 0. 5k(2) External connections for external R-ladder, Static Bias, VGEN = 0. 1997 Microchip Technology Inc. DS31025A-page 25-15 LCD Note 1: Location of optional filter capacitor. 2: These values are provided for design guidance only and should be optimized to the application by the designer. 25 PICmicro MID-RANGE MCU FAMILY 25.7 Operation During Sleep The LCD module can operate during sleep. The selection is controlled by bit SLPEN (LCDCON<6>). Setting the SLPEN bit allows the LCD module to go to sleep. Clearing the SLPEN bit allows the module to continue to operate during sleep. If a SLEEP instruction is executed and SLPEN = '1', the LCD module will cease all functions and go into a very low current consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure 25-9 shows this operation. To ensure that the LCD completes the frame, the SLEEP instruction should be executed immediately after a LCD frame boundary. The LCD interrupt can be used to determine the frame boundary. See 25.4 “LCD Interrupts” for the formulas to calculate the delay. If a SLEEP instruction is executed and SLPEN = '0', the module will continue to display the current contents of the LCDD registers. To allow the module to continue operation while in sleep, the clock source must be either the internal RC oscillator or Timer1 external oscillator. While in sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode, however the overall consumption of the device will be lower due to shutdown of the core and other peripheral functions. Note: The internal RC oscillator or external Timer1 oscillator must be used to operate the LCD module during sleep. Figure 25-9:Sleep Entry/exit When SLPEN = 1 or CS1:CS0 = 00 3/3V Pin COM0 2/3V 1/3V 0/3V 3/3V Pin COM1 2/3V 1/3V 0/3V 3/3V 2/3V Pin COM3 1/3V 0/3V 3/3V 2/3V Pin SEG0 1/3V 0/3V interrupted frame SLEEP instruction execution DS31025A-page 25-16 Wake-up 1997 Microchip Technology Inc. Section 25. LCD 25.8 Effects of a Reset The LCD module is disabled, but the LCD pins are configured as LCD drivers. This ensures that the microcontroller does not damage the LCD glass by accidently having a DC voltage across a segment. 25.9 Configuring the LCD Module The following is the sequence of steps to follow to configure the LCD module. 1. 2. 3. 4. 5. 6. Select the frame clock prescale using the LP3:LP0 bits (LCDPS<3:0>). Configure the appropriate pins to function as segment drivers using the LCDSE register. Configure the LCD module for the following using the LCDCON register. Multiplex mode and Bias, selected by the LMUX1:LMUX0 bits Timing source, selected by the CS1:CS0 bits Voltage generation, enabled by the VGEN bit Sleep mode operation, enabled by the SLPEN bit Write initial values to pixel data registers, LCDD00 through LCDD15. Clear LCD interrupt flag bit, LCDIF, and if desired, enable the interrupt by setting the LCDIE bit. Enable the LCD module, by setting the LCDEN bit (LCDCON<7>). 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-17 PICmicro MID-RANGE MCU FAMILY 25.10 Discrimination Ratio Discrimination ratio is a way to calculate the contrast levels that a panel can achieve. The first example is a static waveform from Figure 25-3. The voltages V1 and V0 will be assigned values of 1 and 0. The next step is to construct an equation for one frame to help visualize the DC and RMS voltages present on an individual pixel that is ON and OFF. The rest of the following shows the calculation of the DC, RMS, and Discrimination Ratio. Example 25-3: Discrimination Ratio Calculation for Static MUX COMx - SEGx [ON] = 1 - 1, VDC = 0 COMx - SEGx [OFF] = 0 + 0, VDC = 0 VRMS [ON] = ∆V (1)2 + (-1)2 2 = 1∆V VRMS [OFF] = ∆V (0)2 + (0)2 2 = 0∆V D = VRMS [ON] VRMS [OFF] = 1∆V 0∆V = ∞ See Figure 25-3 for Static waveform. DS31025A-page 25-18 1997 Microchip Technology Inc. Section 25. LCD The next example is for Figure 25-6 which is a 1/4 MUX, 1/3 BIAS waveform. For this example, the values 3, 2, 1 and 0 will be assigned to V3, V2, V1, and V0 respectively. The frame equation, DC voltage, RMS voltage and discrimination ratio calculations are shown in Example 25-4. Example 25-4: COM0 - SEGx [ON] = COM0 - SEGx [OFF] = 3-3+1-1+1-1+1-1 1-1-1+1-1+1-1+1 VDC = 0 VDC = 0 VRMS [ON] = ∆V (3)2 + (-3)2 + (1)2 + (-1)2 + (1)2 + (-1)2 + (1)2 + (-1)2 8 = 3 ∆V VRMS [OFF] = ∆V (1)2 + (-1)2 + (-1)2 + (1)2 + (-1)2 + (1)2 + (-1)2 + (1)2 8 = ∆V D = VRMS [ON] VRMS [OFF] Note: Discrimination Ratio Calculation 1/4 MUX = 3 ∆V 1 ∆V = 1.732 Refer to Figure 25-6 As shown in these examples, static displays have excellent contrast. The higher the multiplex ratio of the LCD, the lower the discrimination ratio, and therefore, the lower the contrast of the display. Table 25-5 shows the VOFF, VON and discrimination ratios of the various combinations of MUX and BIAS. As the multiplex of the LCD panel increases, the discrimination ratio decreases. The contrast of the panel will also decrease, so to provide better contrast the LCD voltages must be increased to provide greater separation between each level. Table 25-5: Discrimination Ratio vs. MUX and Bias 1/3 BIAS VOFF VON D STATIC 0 1 ∞ 1/2 MUX 0.333 0.745 2.236 1/3 MUX 0.333 0.638 1.915 1/4 MUX 0.333 0.577 1.732 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-19 PICmicro MID-RANGE MCU FAMILY 25.11 LCD Voltage Generation Among the many ways to generate LCD voltage, two methods stand out above the crowd: • resistor ladder • charge pump. The resistor ladder method, shown in Figure 25-10, is most commonly used for higher VCC voltages. This method uses inexpensive resistors to create the multi-level LCD voltages. Regardless of the number of pixels that are energized the current remains constant. The voltage at point V3 is typically tied to VCC, either internally or externally. The resistance values are determined by two factors: display quality and power consumption. Display quality is a function of the LCD drive waveforms. Since the LCD panel is a capacitive load, the waveform is distorted due to the charging and discharging currents. This distortion can be reduced by decreasing the value of resistance. However, this change increases the power consumption due to the increased current now flowing through the resistors. As the LCD panel increases in size, the resistance value must be decreased to maintain the image quality of the display. Sometimes the addition of parallel capacitors to the resistance can reduce the distortion caused by charging/discharging currents. The capacitors act as charge storage to provide current as the display waveform transitions. In general, R is 1 kΩ to 50 kΩ and the potentiometer is 5 kΩ to 200 kΩ. Figure 25-10: Resistor Ladder V3 R V2 R V1 R V0 Figure 25-11: Resistor Ladder with Capacitors +5V V3 R C R C R C V2 V1 V0 DS31025A-page 25-20 1997 Microchip Technology Inc. Section 25. LCD A charge pump is ideal for low voltage battery operation because the VDD voltage can be boosted up to drive the LCD panel. The charge pump requires a charging capacitor and filter capacitor for each of the LCD voltages as seen in Figure 25-12. These capacitors are typically low leakage types such as polyester, polypropylene, or polystyrene material. Another feature that makes the charge pump ideal for battery applications is that the current consumption is proportional to the number of pixels that are energized. Figure 25-12: Charge Pump C1 C2 V3 V2 V1 V0 VADJ 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-21 PICmicro MID-RANGE MCU FAMILY 25.12 Contrast Although contrast is heavily dependent on the light source available and the multiplex mode, it also varies with the LCD voltage levels. As previously seen, a potentiometer is used to control the contrast of the LCD panel. The potentiometer sets the separation between each of the LCD voltages. The larger the separation, the better the contrast achievable. 25.13 LCD Glass The characteristics of the LCD glass vary depending on the materials used. Appendix B gives a list of some LCD manufacturers. Please contact them for the characteristics of your desired glass. DS31025A-page 25-22 1997 Microchip Technology Inc. Section 25. LCD 25.14 Initialization Example 25-5 shows the code for initializing the LCD module with all segments cleared. Example 25-5: BCF BCF BSF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF CLRF BSF BSF BCF LCD Initialization Code PIR1,LCDIF STATUS,RP0 STATUS,RP1 0x06 LCDPS 0xff LCDSE 0x17 LCDCON LCDD00 LCDD01 LCDD02 LCDD03 LCDD04 LCDD05 LCDD06 LCDD07 LCDD08 LCDD09 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 PIE1,LCDIE LCDCON,LCDEN STATUS,RP1 ; Clear LCD interrupt flag ; Go to Bank2 ; Set frame freq to ~37Hz ; Make all pin functions LCD drivers ; Drive during SLEEP, Charge pump enabled ; Timer1 clock source, 1/4 MUX ; Clear all data registers to turn ; all pixels off ; Enable LCD interrupts ; Enable LCD Module ; Go to Bank0 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-23 PICmicro MID-RANGE MCU FAMILY 25.15 Design Tips Question 1: I’m trying to use some of the LCD pins as inputs. Answer 1: Ensure that you have the control bits in the LCDSE properly configured, since these bits override the TRIS bits. Question 2: My LCD panel is flickering. Answer 2: Your frame frequency may be too low. The frame frequency can be changed in the LCDPS register. Question 3: The LCD segments are not very visible. Answer 3: This may be due to misadjusted LCD voltage, some possibilities include: 1. 2. DS31025A-page 25-24 If you are using the R-ladder, try different values of R, vary the R-ladder potentiometer. The VLCDADJ pin should be connected to ground. If you are using the charge pump, adjust the resistance value on the VLCDADJ pin. 1997 Microchip Technology Inc. Section 25. LCD 25.16 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Mid-Range MCU family (that is they may be written for the Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to the LCD drivers are: Title Application Note # Yet Another Clock Using the PIC16C92X AN649 LCD Fundamentals Using PIC16C92x Microcontrollers AN658 PICDEM3 Demo Board User’s Guide DS51079 25 LCD 1997 Microchip Technology Inc. DS31025A-page 25-25 PICmicro MID-RANGE MCU FAMILY 25.17 Revision History Revision A This is the initial released revision of the LCD module description. DS31025A-page 25-26 1997 Microchip Technology Inc.