MDT11P0122 1、General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 4K words of EPROM, and 176 bytes of static RAM. The application areas of this MDT11P0122 range from appliance motor control and high speed automotive to low power remote transmitters/receivers and telecommunications processors, such as Remote controller, small instruments, toy, automobile and keyboard … etc. 2、Features RISC CPU Fully static design 37 single word instructions 4K x 14 program memory. 176 bytes RAM for data 25 bi-directional I/O Eight level hardware stacks Watchdog timer with on-chip RC oscillator. Interrupt capability Timer0 : 8-bit timer with 8-bit prescaler Timer1 : 16-bit timer 16-bit Timer1 compare register. Sleep mode for power saving. PB with port change wake-up interrupt. LCD：29 Segments,4 commons.(27 x 4 at LQFP Package) 1/2,1/3,1/4 multiplex at 1/3,1/2 bias. 2 channel comparator 3. Applications This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.1 2007/11 VER 1.0 MDT11P0122 4. IC Diagram (1)Pin Diagram PD6/COM2 PD7/COM1 COM0 VDD PB6 PB7 PB5 PB4 /MCLR PB3 PB2 PA0/CMP0I PA1/CMP0R VSS PA2/CMPP1I PA3/CMP1R 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PA4/RTCC 1 48 PD5/COM3 PA5 2 47 PG6/SEG26 PB1 3 46 PG5/SEG25 PB0/IRQ 4 45 PG4/SEG24 PC3 5 44 PG3/SEG23 PC4 6 43 PG2/SEG22 PC5 7 42 PG1/SEG21 C1 8 C2 9 40 PF7/SEG19 Vlcd 2 10 39 PF6/SEG18 Vlcd 3 11 38 PF5/SEG17 VDD 12 37 PF4/SEG16 VSS 13 36 PF3/SEG15 OSCI 14 35 PF2/SEG14 OSCO 15 34 PF1/SEG13 PC0/T1OSCO 16 33 PF0/SEG12 MDT11P0122LQ11 41 PG0/SEG20 Device LCD dot Package MDT11P0122LQ11 4 X 27 64 PIN LQFP MDT11P0122 4 X 29 COB PE6/SEG11 PE5/SEG10 PE4/SEG9 PE3/SEG8 PE2/SEG7 PE1/SEG6 PE0/SEG5 PD4/SEG4 PD3/SEG3 PD2/SEG2 PD1/SEG1 PD0/SEG0 VLCD PC1/T1OSCI NC 23 24 25 26 27 28 29 30 31 32 PC2 17 18 19 20 21 22 Remark This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.2 2007/11 VER 1.0 MDT11P0122 (2)pad diagram IC substrate connect to VSS VDD (pad 14,55), VSS (pad 15, 65) must to be connect This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.3 2007/11 VER 1.0 MDT11P0122 (3)pad Coordinates PAD-No PAD Name X Y PAD-No PAD Name X Y 1 PA2 68.00 2278.00 34 PE6 1468.00 77.00 2 PA3 68.00 2178.00 35 PF0 1468.00 177.00 3 PA4 68.00 2078.00 36 PF1 1468.00 277.00 4 PA5 68.00 1978.00 37 PF2 1468.00 377.00 5 PB1 68.00 1878.00 38 PF3 1468.00 477.00 6 PB0 68.00 1778.00 39 PF4 1468.00 577.00 7 PC3 68.00 1678.00 40 PF5 1468.00 677.00 8 PC4 68.00 1578.00 41 PF6 1468.00 777.00 9 PC5 68.00 1478.00 42 PF7 1468.00 877.00 10 C1 68.00 1378.00 43 PG7 1468.00 977.00 11 C2 68.00 1278.00 44 PG0 1468.00 1077.00 12 VLCD2 68.00 1178.00 45 PG1 1468.00 1177.00 13 VLCD3 68.00 1078.00 46 PG2 1468.00 1277.00 14 VDD 68.00 978.00 47 PG3 1468.00 1377.00 15 VSS 68.00 878.00 48 PG4 1468.00 1477.00 16 OSC1 68.00 778.00 49 PG5 1468.00 1577.00 17 OSC2 68.00 678.00 50 PG6 1468.00 1677.00 18 PC0 68.00 578.00 51 PD5 1468.00 1777.00 19 PC1 68.00 478.00 52 PD6 1468.00 1877.00 20 PC2 68.00 378.00 53 PD7 1468.00 1977.00 21 VLCD 68.00 278.00 54 COM0 1468.00 2077.00 22 PD0 73.00 68.00 55 VDD 1357.80 2318.00 23 PD1 173.00 68.00 56 PB6 1257.80 2318.00 24 PD2 273.00 68.00 57 PB7 1157.80 2318.00 25 PD3 373.00 68.00 58 PB5 1057.80 2318.00 26 PD4 473.00 68.00 59 PB4 957.80 2318.00 27 PE7 573.00 68.00 60 MCLRB 831.80 2318.00 28 PE0 673.00 68.00 61 PB3 724.90 2318.00 29 PE1 773.00 68.00 62 PB2 624.90 2318.00 30 PE2 873.00 68.00 63 PA0 524.90 2318.00 31 PE3 973.00 68.00 64 PA1 424.90 2318.00 32 PE4 1073.00 68.00 65 VSS 324.90 2318.00 33 PE5 1173.00 68.00 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.4 2007/11 VER 1.0 MDT11P0122 5. Pin function description Pin name Type Buffer type Description OSC1 I Oscillator input OSC2 O Oscillator out /MCLR I ST PA0/CMP0I I/O TTL PA1/CMP0R I/O TTL PA2/CMP1I I/O TTL PA3/CMP1R I/O TTL PA4/RTCC I/O ST PA5 I/O TTL Reset input Bi-directional I/O port A. Port A can be software programmed for internal 50K ohm pull-up PA0 ~PA3 can use TTL level I/O or Comaparator input. Output_Lo sink current only 14mA Can be clock input to Timer0. Bi-directional I/O port B. Port B can be software programmed for internal 50K ohm pull-up on all pins. PB0-PB7 can generate interrupt on pin state change. PB0/IRQ can be the external interrupt pin. PB0/IRQ I/O ST/TTL PB1 I/O TTL PB2 I/O TTL PB3 I/O TTL PB4 I/O TTL PB5 I/O TTL PB6 I/O TTL PB7 I/O TTL Bi-directional I/O port C. Port C can be software programmed for internal 100K pull-up on all pins. PC0 I/O ST PC0 can be Timer1 oscillator output or Timer1 clock input. PC1 can be Timer1 oscillator input. PC1 I/O ST PC2 I/O ST PC3 I/O ST PC4 I/O ST PC5 I/O ST PD0/SEG00 I/O/L ST PD1/SEG01 I/O/L ST PD2/SEG02 I/O/L ST PD3/SEG03 I/O/L ST PD4/SEG04 I/O/L ST PC2 can be Timer1 compare output. Bi-directional I/O/LCD Driver port. PD0~PD4 are open drain I/O or LCD Segment driver This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.5 2007/11 VER 1.0 MDT11P0122 Pin name Type Buffer type PD5/COM3 I/L ST PD6/COM2 I/L ST PD7/COM1 I/L ST PE0/SEG05 PE1/SEG06 I/L I/L ST ST PE2/SEG07 I/L ST PE3/SEG08 I/L ST PE4/SEG09 I/L ST PE5/SEG10 I/L ST PE6/SEG11 I/L ST PE7/SEG27 I/L ST PF0/SEG12 PF1/SEG13 I/L I/L ST ST PF2/SEG14 I/L ST PF3/SEG15 I/L ST PF4/SEG16 I/L ST PF5/SEG17 I/L ST PF6/SEG18 I/L ST PF7/SEG19 I/L ST PG0/SEG20 PG1/SEG21 I/L I/L ST ST PG2/SEG22 I/L ST PG3/SEG23 I/L ST PG4/SEG24 I/L ST PG5/SEG25 I/L ST PG6/SEG26 I/L ST PG7/SEG28 I/L ST COM0 C1 C2 VLCD VLCD2 VLCD3 L - - LCD Common 0 LCD voltage charge pump pin 1 LCD voltage charge pump pin 2 LCD voltage input pin LCD voltage pin(1/2VDD) LCD voltage pin (3/2VDD) VDD - - Power input Vss - - Ground pin **note : I:input O:output Description PD5~PD7 are digital input or LCD Common driver Digital input or LCD Segment Driver port Digital input or LCD Segment Driver port Digital input or LCD Segment Driver port L:lcd This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.6 2007/11 VER 1.0 MDT11P0122 6. Memory Mapping 6.1 Program memory : 0000h Reset Vector 0001h 0002h 0003h 0004h Peripheral interrupt Vector 0005h Program memory (Page 0) 07FFh 0800h Program memory (Page 1) 0FFFh This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.7 2007/11 VER 1.0 MDT11P0122 6.2 Register file map 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h BANK 0 I. ADDR BANK 1 I. ADDR RTCC PCL STATUS MSR Port A Port B Port C Port D Port E PCHLAT INTS PIFB1 TMR PCL STATUS MSR COIO A COIO B COIO C COIO D COIO E PCHLAT INTS PIEB1 TMR1L TMR1H T1STA PSTA CMPPH CCP1L CCP1H CCPCTL General Purpose Register 70h General Purpose Register Access 7Fh 70h~7Fh BANK 2 I. ADDR BANK 3 I. ADDR RTCC PCL STATUS MSR TMR PCL STATUS MSR Port B Port F Port G COIO B COIO F COIO G PCHLAT INTS PCHLAT INTS 80h 100h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h F0h 17Fh Access Access 1F0h FFh 17Fh 70h~7Fh 70h~7Fh 1FFh LCDPFS LCDFS LCDCTL LCD00 LCD01 LCD02 LCD03 LCD04 LCD05 LCD06 LCD07 LCD08 LCD09 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h Unimplemented memory location. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.8 2007/11 VER 1.0 MDT11P0122 ‧ BANK 1 R00 IAR(Indirect addressing register) R01 RTCC (Real Time Counter/Counter Register) Timer0 register R02 PCL (Program Counter Low Byte) Low order 8 bits of the Program Counter (PC) R03 STATUS (Status register) Bit Symbol 0 C 1 HC 2 Z 3 /PF 4 TO 5 RBS0 6 RBS1 7 RBS2 Function Carry bit Half Carry bit Zero bit Power loss Flag bit WDT TIME OUT bit Register page select bit 0 0： 00/H --- 7F/H 0 1： 80/H --- FF/H 1 0：100/H --- 17F/H 1 1：180/H --- 1FF/H Register page select bit 0： 00/H--- FF/H 1：100/H---1FF/H R04H : MSR (Memory Select Register) Indirect data memory address pointer. R05H : Port A PortA PA7 PA6 PA5 PA0~PA5：portA I/O register. PA6~PA7：always read as 0. R06H : Port B PortB PB7 PB6 PB5 PA4 PA3 PA2 Always available PB4 PB3 Always available PB0~PB7：Have pin change interrupt PB2 PA1 PA0 PB1 PB0 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.9 2007/11 VER 1.0 MDT11P0122 R07H : Port C PortC PC7 PC6 PC5 PC4 PC0~PC5：portA I/O register. PC6~PC7：always read as 0. PC3 PC2 Always available PC1 PC0 R08H : Port D PortD PD7 PD6 PD5 PD4 PD3 Always available PD2 PD1 PD0 R09H : Port E PortE PE7 PE6 PE5 PE4 PE3 Always available PE2 PE1 PE0 PCH2 PCH1 PCH0 - TMR1IF R0AH : PCHLAT(Program counter high byte.) BIT 7~0 PCH4 Bit0~4：Hiht byte of PC. Bit5~7：always read as 0 PCH3 R0BH : INTS(Interrupt control register.) Bit Symbol Function 0 RBIF PORT B change interrupt flag. 1 INTF PB0/IRQ external interrupt flag bit. 2 TIF Timer0 overflow interrupt flag bit. 0 ： disable PB change interrupt 3 RBIE 1 ： enable PB change interrupt 0 ： disable INT interrupt 4 INTS 1 ： enable INT interrupt 0 ： disable TMR0 interrupt 5 TIS 1 ： enable TMR0 interrupt 0 ： disable all peripheral interrupt 6 PEIE 1 ： enable all peripheral interrupt 0 ： disable global interrupt 7 GIS 1 ： enable global interrupt R0CH : PIFB1(Peripheral interrupt flag register.) BIT 7~0 LCDIF Bit 0：Timer1 overflow interrupt flag bit Bit 7：LCD interrupt flag bit Bit1~6：always read as 0 - - This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.10 2007/11 VER 1.0 MDT11P0122 R0EH : TMR1L(Timer1 data register low byte.) ROFH : TMR1H(Timer1 data register high byte.) R10H : T1STA(Timer1 control register) Bit Symbol Function 0 ： Stop TMR1 0 TMR1ON 1 ： Enable TMR1 0 ： Internal clock (Fosc/4) 1 TMR1CLK 1 ： External clock from pin PC0 TMR1CLK = 1 0 ： Synchronize external clock ______ 1 ： Do not synchronize external clock 2 T1SYNC TMR1CLK = 0 This bit is ignored 0 ： TMR1 Oscillator is shut off 3 T1OSCEN 1 ： TMR1 Oscillator is enable 1 1 = 1：8 Prescale value T1CKPS1 1 0 = 1：4 Prescale value ~ 4~5 0 1 = 1：2 Prescale value T1CKPS0 0 0 = 1：1 Prescale value 6~7 - Unimplemented R15H : CCP1L(Timer1 compare LSB) R16H : CCP1H(Timer1 compare MSB) R17H : CCPCTL Bit Symbol 0 CCPM0 1~7 - Function 0 ： COMPARE off 1 ： COMPARE on Unimplemented. R20H~R7FH : General purpose register This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.11 2007/11 VER 1.0 MDT11P0122 ‧ BANK 1 R81H : TMR(Time Mode Register) Bit Symbol Function Prescaler Value RTCC rate WDT rate 1 ： 2 1 ： 1 000 001 1 ： 4 1 ： 2 010 1 ： 8 1 ： 4 011 1 ： 16 1 ： 8 0~2 PS0~2 100 1 ： 32 1 ： 16 101 1 ： 64 1 ： 32 101 1 ： 128 1 ： 64 111 1 ： 256 1 ： 128 Prescaler assignment bit 0 ： RTCC 3 PSC 1 ： Watchdog Timer RTCC signal edge ： 0 ： Increment on low-to-high transition on RTCC pin 4 TCE 1 ： Increment on high-to-low transition on RTCC pin RTCC signal set ： 0 ： Internal instruction cycle clock 5 TCS 1 ： Transition on RTCC pin Interrupt edge select 0 ： Interrupt on falling edge on PB0 6 IES 1 ： Interrupt on rising edge on PB0 PORTB pull-hi 0 ： PORTB pull-hi are enable 7 /PBPH 1 ： PORTB pull-hi are disable R85H : CPIO A (Control Port I/O Mode Register) 0： I/O pin in output mode; 1： I/O pin in input mode. R86H : CPIO B (Control Port I/O Mode Register) 0： I/O pin in output mode; 1： I/O pin in input mode. R87H : CPIO C (Control Port I/O Mode Register) 0： I/O pin in output mode; 1： I/O pin in input mode. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.12 2007/11 VER 1.0 MDT11P0122 R88H : CPIO D (Control Port I/O Mode Register) 0： I/O pin in output mode; 1： I/O pin in input mode. R89H : CPIO E (Control Port I/O Mode Register) 0： I/O pin in output mode; 1： I/O pin in input mode. R8CH : PIEB1 Bit Symbol 0 TMR1IE 1~6 - 7 R8EH : PSTA Bit LCDIE - 1 PORB 2~7 - 0 1 2~3 4 5 6~7 TMR1 interrupt enable bit 0 ： disable TMR1 interrupt 1 ： enable TMR1 interrupt Unimplemented. LCD interrupt enable bit 0 : disable LCD interrupt 1 : enable LCD interrupt Symbol 0 R90H:CMPPH Bit Function Function Unimplemented. 0:Power on Reset occurred 1:No Power on Reset occurred Unimplemented. Symbol Function 0:PA0,PA1 as TTL input CMPS0 1:PA0,PA1 as Comparaotr input 0:PA2,PA3 as TTL input CMPS1 1:PA2,PA3 as Comparaotr input 1 1 = PA1,PA3 select extrenal vrefence voltage 1 0 = PA1,PA3 select 3/4 VDD as vrefence voltage CMPRS0~1 0 1 = PA1,PA3 select 1/2 VDD as vrefence voltage 0 0 = PA1,PA3 select 1/4 VDD as vrefence voltage 0:Port A pull up enable PAHR 1:Port A pull up disable 0:Port C pull up enable PCHR 1:Port C pull up disable - - This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.13 2007/11 VER 1.0 MDT11P0122 ‧ BANK2 R107H : PortF PortF PF7 PF6 PF5 PF4 PF3 PF2 Always read available PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 Always read available PG1 PG0 FS1 FS0 108H : PortG PortG R10DH ：LCDPFS(Lcd pin function select) Bit Symbol 0 DL00 1 DL05 2 DL09 3 DL12 4 DL16 5 DL20 6 DL27 7 DL29 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： Function PD0~PD4 as digital input PD0~PD4 as LCD driver PE0~PE3 as digital input PE0~PE3 as LCD driver PE4~PE6 as digital input PE4~PE6 as LCD driver PF0~PF3 as digital input PF0~PF3 as LCD driver PF4~PF7 as digital input PF4~PF7 as LCD driver PG0~PG6 as digital input PG0~PG6 as LCD driver PG7,PE7 as digital input PG7,PE7 as LCD driver PD5~PD7 as digital input PD5,PD7 as LCD driver R10EH : LCDFS(LCD frame frequency select) BIT 7~0 - Common select 1/2 1/3 1/4 - - - FS3 FS2 Frame frequency Clock/[128 * (FS3:FS0+1)] Clock/[ 96 * (FS3:FS0+1)] Clock/[128 * (FS3:FS0+1)] This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.14 2007/11 VER 1.0 MDT11P0122 R10FH : LCDCTL(LCD control) Bit Symbol Function LCD Common select bits 0 0： -0~1 LCDS0~1 0 1： 1/2 (use COM 0,1) 1 0： 1/3 (use COM 0,1,2) 1 1： 1/4 (use COM 0,1,2,3) Clock select 0 0： sysclk/256 2~3 CLKS0~1 0 1： Timer1 clk (must enable T1 osc) 1 X： internal RC Cap mode and Resistor mode select 0 ： Resistor mode 4 CRS 1 ： Cap mode BIAS Select 0 ： Use 1/2 bias mode 5 BIASS 1 ： Use 1/3 bias mode LCD enabled in Sleep mode 0 ： LCD enable in sleep mode 6 SLPE 1 ： LCD disable in sleep mode LCD enable bit 0 ： LCD disable 7 LCDE 1 ： LCD enable This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.15 2007/11 VER 1.0 MDT11P0122 R110H~R11FH : LCD00~LCD15(LCD data register 00~15) Address Symbol R110H R111H R112H R113H R114H R115H R116H R117H R118H R119H R11AH R11BH R11CH R11DH R11EH R11FH LCD00 LCD01 LCD02 LCD03 LCD04 LCD05 LCD06 LCD07 LCD08 LCD09 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 *SEG31 *SEG30 *SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 *SEG31 *SEG30 *SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 *SEG31 *SEG30 *SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 *SEG31 *SEG30 *SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 * These bits don’t display, but can used as general ram. ‧ BANK3 R187H : CPIO F R188H : CPIO G This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.16 2007/11 VER 1.0 MDT11P0122 7.Reset Condition for all Registers Register Power-On Reset, Power range Address /MCLR or WDT Reset detector Reset Wake-up from SLEEP IAR 00h N/A N/A N/A RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000 0000 0000 0000 PC+1 STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h xxxx xxxx uuuu uuuu uuuu uuuu PORT A 05h --00 0000 --00 0000 --uu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu PORT C 07h --xx xxxx --uu uuuu --uu uuuu PORT D 08h 0000 0000 0000 0000 uuuu uuuu PORT E 09h 0000 0000 uuuu uuuu uuuu uuuu PCHLAT 0Ah ---- 0000 ---- 0000 ---- uuuu INS 0Bh 0000 000x 0000 000u uuuu uuuu PIFB1 0Ch ---- ---x ---- ---u ---- ---u TMR1L 0Eh xxxx xxxx uuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuu uuuu uuuu uuuu T1STA 10h --00 0000 --00 0000 --uu uuuu CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu CCPCTL 17h --1- ---0 --1- ---0 --u- ---u MTR 81h 1111 1111 1111 1111 uuuu uuuu CPIOA 85h --11 1111 --11 1111 --uu uuuu CPIOB 86h 1111 1111 1111 1111 uuuu uuuu CPIOC 87h --11 1111 --11 1111 --uu uuuu CPIOD 88h 1111 1111 1111 1111 uuuu uuuu CPIOE 89h 1111 1111 1111 1111 uuuu uuuu PIEB1 8Ch ---- ---0 ---- ---0 ---- ---u PWRCON 8Eh ---- --#- ---- --u- ---- --u- CMPPH 90h 0011 0000 0011 uuuu 00uu uuuu PORT F 107h 0000 0000 0000 0000 uuuu uuuu PORT G 108h 0000 0000 0000 0000 uuuu uuuu This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.17 2007/11 VER 1.0 MDT11P0122 Power-On Reset, Power range Address /MCLR or WDT Reset detector Reset Register Wake-up from SLEEP LCDPFS 10Dh 1111 1111 1111 1111 uuuu uuuu LCDFS 10Eh ---- 0000 ---- 0000 ---- uuuu LCDCTL 10Fh 0000 0000 0000 0000 uuuu uuuu Lcd00~15 110h xxxx xxxx uuuu uuuu uuuu uuuu CPIO F 186h 1111 1111 1111 1111 uuuu uuuu CPIO G 187h 1111 1111 1111 1111 uuuu uuuu Note ： u＝unchanged， x＝unknown， - ＝unimplemented， read as “0” #＝value depends on the condition of the following table Condition Status bit 4 Status bit 3 PWRCON bit 1 POWR ON RESET 1 1 0 /MCLR reset (not during SLEEP) u u u /MCLR reset during SLEEP 1 0 u WDT reset (not during SLEEP) 0 1 u WDT reset during SLEEP 0 0 u Interrupt Wake-up during SLEEP 1 0 u 8. Instruction Set Instruction Code Mnemonic Operands Function Operation Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode 0→WT, stop OSC TF, PF 010000 00000011 TMODE Load W to TMR register W→TMR None 010000 00000rrr CPIO Control I/O port register W→CPIO 010001 1rrrrrrr STWR Store W to register W→R 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3) (4~7)]→t None 011001 trrrrrrr INCR R + 1→t 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t (R+/W+1→t) C, HC, Z R R R, t Increment register r This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.18 2007/11 None None Z None VER 1.0 MDT11P0122 Instruction Code Mnemonic Operands Function R, t Decrement register Operation Status 011101 trrrrrrr DECR 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 110110 iiiiiiii XORWI i ♁ W→W Z 011111 trrrrrrr COMR /R→t Z 010110 trrrrrrr RRR R(n) →R(n-1), C i i i Exclu. OR W and immediate R, t Complement register R, t Z R ﹣1→t Rotate right register None C→R(7), R(0)→C 010101 trrrrrrr RLR R, t Rotate left register R(n)→r(n+1), C C→R(0), R(7)→C 010000 1xxxxxxx CLRW Clear working register 0→W Z 010001 0rrrrrrr CLRR Clear register 0→R Z 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None Long CALL subroutine n→PC, None R 100nnn nnnnnnnn LCALL n PC+1→Stack 101nnn nnnnnnnn LJUMP n Long JUMP to address n→PC 110001 iiiiiiii RTIW i Return, place immediate to W Stack→PC, i→W 110111 iiiiiiii ADDWI Add immediate to W PC+1→PC, None None C,HC,Z W+i→W 111000 iiiiiiii SUBWI Subtract W from immediate i-W→W 010000 00001001 RTFI Return from interrupt Stack→PC,1→GIS None 010000 00000100 RET Return from subroutine Stack→PC None Note : W WT TMODE CPIO : : : : TF PF : : Working register Watchdog timer TMODE mode register Control I/O port register ( PA, PB, PC Only ) Timer overflow flag Power loss flag b t : : 0 1 R : C : HC : C,HC,Z Bit position Target : Working register : General register General register address Carry flag Half carry This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.19 2007/11 VER 1.0 MDT11P0122 PC OSC Inclu. Exclu. AND : : : : : Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ Z / x i n : : : : : Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address 9. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Max Unit 2.5 6.3 V VDD=5V -0.6 1.0 V VDD=5V 2.0 VDD V PC, PD, PE, PF, PG RTCC, /MCLR VDD=5V 3.2 VDD V +/-1 µA VDD Operating voltage VIL Input Low Voltage Min Typ Input high Voltage VIH IIL PA, PB Input leakage current VDD=5V Output Low Voltage VDD=5V, IOL=20mA 0.4 V PA, PB, PC, PD VDD=5V, IOL=5mA 0.1 V Output High Voltage VDD=5V, IOH= -20mA 3.3 V PA, PB, PC VDD=5V, IOH= -5mA 4.5 V PortA pullhigh resister VDD=5V 50k Ω Rph PortB pullhigh resister VDD=5V 50K Ω PortC pullhigh resister VDD=5V 100K Sleep current (WDT disable) VDD＝2.3 ~ 6.3 V Ω μA Sleep current (WDT enable) VDD＝2.3 V 2 μA VDD＝3.0 V 5 μA VDD＝4.0 V 10 μA VDD＝5.0 V 18 μA VDD＝6.3 V 35 μA Sleep current Vdd=5.0 V 15 (LCD on at CAP MODE),no load Vdd=3.0 v 5.5 Sleep current Vdd=5.0 V 20 (LCD on at RES MODE),no load Vdd=3.0 v 7 VOL VOH Islp Islp Islp-L Vpr Power Edge-detector Reset Voltage 0.1 1.0 1.1 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.20 2007/11 μA μA 1.3 V VER 1.0 MDT11P0122 Sym Description Condition The basic WDT time-out cycle time Twdt TFLT /MCLR filter Vref Input reference voltage --- Lrc Unit mS VDD＝3.0 V 23.6 mS VDD＝4.0 V 20.1 mS VDD＝5.0 V 20.4 mS VDD＝6.3 V 16.4 mS VDD＝5.0 V VDD=2.5v ~6.3v 600 VDD VDD=5.0v , V- = Vref V+ = (PA0~PA3) Comparator Response time V-=VDD/4, V+=V- ± 0.2v Max 26.4 nS V 8 μS V-=VDD/2, V+=V- ± 0.2v 8 μS V-=VDD3/4, V+=V- ± 0.2v 8 μS V-=VDD-0.8,V+=V± 0.2v 8 μS Internal LCD RC VDD=5v Internal LCD resister current between vlcd pin and VDD VDD=3v 10. Typ VDD＝2.3 V VDD=5v Ires Min 15 - 1/3bias 10 1/2bias 30 1/3bias 0.1 1/2bias 4 35 kHz μA Equivalent Circuit Port A PA0,PA2 P u ll-h ig h 50K Q I/O C o n tro l L a tc h CK QB D I/O C o n tro l P u ll-H ig h c o n tro l P o r t I/O P in D W r ite D a ta O /P L a tc h G QB In p u t R e s is to r D a ta B u s 0 R ead D QB D a ta I/P L a tc h G T T L in p u t le v e l S 1 + c o m p a ra to r le v e l VREF C o m p a rto r C o n tro l This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.21 2007/11 VER 1.0 MDT11P0122 PA1,PA3 Q D P ull_H i 50K I/O C ontrol L atch I/O C ontrol QB CK Pull_H i C ontrol P ort I/O Pin D D ata O /P L atch W rite QB G Input R esistor D ata B us D ata I/P L atch R ead com parator enable D QB T T L Input L evel G 3 V ref S0 S1 2 3/4 V D D 1 1/2 V D D 0 1/4 V D D C M P R S0 C M P R S1 PA4,PA5 Q D P u ll_ H i 5 0 k I/O C o n tro l L a tc h I/O C o n tro l C K QB P u ll_ H i C o n tro l P o rt I/O P in D D a ta O /P L a tc h W rite G D a ta B u s QB In p u t R e s isto r T T L in p u t le v e l R ead This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.22 2007/11 VER 1.0 MDT11P0122 Port B Q D Pull_Hi 50K I/O Control Latch I/O Control QB CK Pull_Hi Control Port I/O Pin D Data O/P Latch Write QB G Data Bus D QB Data I/P Latch Read Input Resistor TTL Input Level G Port C D Q I/O Control Latch I/O Control CK Pull_Hi 100k QB Pull_Hi Control Port I/O Pin D Data O/P Latch Write G Data Bus QB Input Resistor SMI input level Read This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.23 2007/11 VER 1.0 MDT11P0122 Port D PD0~PD3 LCD SEG LCD SEG e n a b le D I/O C o n tro l L a tc h I/O C o n tro l QB CK P o rt I /O P in D D a ta O /P L a tc h W rite G QB D a ta B u s D QB D a ta I/P L a tc h R ead G S M I In p u t L e v e l In p u t R e s is to r PD5~PD7 LCD COM Port I/O Pin LCDPFS(N) Data Bus D QB Read Data I/P Latch G SMI Input Level Input Resistor VDD CPIO D This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.24 2007/11 VER 1.0 MDT11P0122 Port E、F、G LCD SEG LCDPFS(N) Port input/ LCD output Pin Input Resistor Data Bus SMI Input Level Read VDD CPIO MCLRB PIN R≒1K MCLRB Schmitt Trigger This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.25 2007/11 VER 1.0 MDT11P0122 11. External Capacitor Selection For Crystal Oscillator Osc. Type HF XT LF Resonator Freq. C1 C2 20 MHz 5 pF ~10 pF 10 pF ~30 pF 10 MHz 10 pF ~50 pF 20 pF ~100 pF 4 MHz 10 pF ~50 pF 20 pF ~100 pF 10 MHz 10 pF ~30 pF 10 pF ~50 pF 4 MHz 10 pF ~50 pF 20 pF ~100 pF 1 MHz 10 pF ~30 pF 20 pF ~50 pF 1 MHz 3 pF ~5 pF 3 pF ~5 pF 455 K 10 pF ~30 pF 20 pF ~50 pF 32 K 10 pF ~20 pF 15 pF ~30 pF MDT11P0122 OSC1 C1 OSC2 C2 To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.26 2007/11 VER 1.0 MDT11P0122 12. Timer1 comapre mode CCP1CTL Enable CCP1 Input 1/2 Output PC2 COMPARATOR PC2 OUTPUT ENABLE Clear TMR1L TMR1 PC2 13. Lcd application (1) LCD voltage generation at capacitance mode Input Output Default 13. LCD APPLICATION (1) LCD voltage generation at CAP mode 1/2 BIAS CAP MODE Vlcd Vlcd 3 Vlcd 2 *0.1u Vdd C1 C2 VLCD3 VDD VLCD2 1/2VDD 0 VSS *0.1u Vdd This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.27 2007/11 VER 1.0 MDT11P0122 1/3 BIAS CAP MODE VLCD3 VDD VLCD2 Vlcd Vlcd 3 Vlcd 2 *0.1u C1 3/2VDD VDD 1/2VDD C2 0 *0.1u VSS *0.1u Vdd *These value are adjusted to the application by designer (2) LCD voltage generation at resister mode 1/3 BIAS RES MODE Vlcd Vlcd 3 Vlcd 2 C1 1/2 BIAS VLCD VLCD 2/3VLCD 1/2VLCD 1/3VLCD VSS C2 VSS Vdd * Designer can adjust vlcd resister to change lcd voltage at resister mode. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.28 2007/11 VER 1.0 MDT11P0122 (3) LCD Interrupt ( in 1/3 bias, 1/4 duty ) VLCD3 VDD VLCD2 0 COM0 COM1 VLCD3 VDD VLCD2 0 COM2 VLCD3 VDD VLCD2 0 COM3 VLCD3 VDD VLCD2 0 LCDINT 1 Frame 1 Frame 1 Frame 1 Frame This interrupt can be used to write next frame data This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P.29 2007/11 VER 1.0