PIC18F2221/2321/4221/4321 PIC18F2221/2321/4221/4321 Family Silicon Errata and Data Sheet Clarification The PIC18F2221/2321/4221/4321 devices that you have received conform functionally to the current Device Data Sheet (DS39689F), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. 3. The errata described in this document will be addressed in future revisions of the PIC18F2221/2321/4221/4321 silicon. Note: 4. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (B3). 5. Data Sheet clarifications and corrections start on page 5, following the discussion of silicon issues. Note: The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: The DEVREV values for the various PIC18F2221/2321/ 4221/4321 silicon revisions are shown in Table 1. (1) Revision ID for Silicon Revision(2) Device ID PIC18F2221 216h PIC18F2321 212h PIC18F4221 214h PIC18F4321 210h 2: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. SILICON DEVREV VALUES Part Number Note 1: Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB IDE project. Configure the MPLAB IDE project for the appropriate device and hardware debugger. Based on the version of MPLAB IDE you are using, do one of the following: a) For MPLAB IDE 8, select Programmer > Reconnect. b) For MPLAB X IDE, select Window > Dashboard and click the Refresh Debug Tool Status icon ( ). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. B2 B3 2h 3h The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format “DEVID DEVREV”. Refer to the “PIC18F2XXX/4XXX Family Flash Microcontroller Programming Specification” (DS39622) for detailed information on Device and Revision IDs for your specific device. 2006-2014 Microchip Technology Inc. DS80000285D-page 1 PIC18F2221/2321/4221/4321 TABLE 2: SILICON ISSUE SUMMARY Module 10-Bit Analog-to-Digital Converter (A/D) Feature 2 TOSC or RC Item Number Affected Revisions(1) Issue Summary B2 B3 1. When the A/D clock source is set as 2 TOSC or RC, the Integral Linearity Error and Differential Linearity Error may exceed the data sheet specification, in extremely rare cases, at codes 511 and 512. X X X X X X Master Synchronous Serial Port (MSSP) I2C™ Slave Reception 2. When configured for I2C slave reception, the MSSP module may not receive the correct data if the SSPBUF register is not read within a window after an SSPIF interrupt occurs. Timer1/3 Interrupt 3. When the timer is operated in Asynchronous External Input mode, unexpected interrupt flag generation may occur. Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80000285D-page 2 2006-2014 Microchip Technology Inc. PIC18F2221/2321/4221/4321 3. Module: Timer1/3 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B3). 1. Module: 10-Bit Analog-to-Digital Converter (A/D) Work around When the AD clock source is selected as 2 TOSC or RC (when ADCS<2:0 = 000 or x11), in extremely rare cases, the EIL (Integral Linearity Error) and EDL (Differential Linearity Error) may exceed the data sheet specification at codes 511 and 512. Work around Select the AD clock source as 4 TOSC, 8 TOSC, 16 TOSC, 32 TOSC or 64 TOSC and avoid selecting 2 TOSC or RC. Affected Silicon Revisions B2 B3 X X When Timer1 or Timer3 is operated in Asynchronous External Input mode, unexpected interrupt flag generation may occur if an external clock edge arrives too soon following a firmware write to the TMRxH:TMRxL registers. An unexpected interrupt flag event may also occur when enabling the module or switching from Synchronous to Asynchronous mode. 2. Module: Master Synchronous Serial Port (MSSP) When configured for I2C™ slave reception, the MSSP module may not receive the correct data, in extremely rare cases. This occurs only if the Serial Receive/Transmit Buffer Register (SSPBUF) is not read within a window after the SSPIF interrupt (PIR1<3>) has occurred. Work around This issue only applies when operating the timer in Asynchronous mode. Whenever possible, operate the timer module in Synchronous mode to avoid spurious timer interrupts. If Asynchronous mode must be used in the application, potential strategies to mitigate the issue may include any of the following: • Design the firmware so it does not rely on the TMRxIF flag or keep the respective interrupt disabled. The timer still counts normally and does not reset to 0x0000 when the spurious interrupt flag event is generated. • Design the firmware so that it does not write to the TMRxH:TMRxL registers or does not periodically disable/enable the timer, or switch modes. Reading from the timer does not trigger the spurious interrupt flag events. • If the firmware must use the timer interrupts and must write to the timer (or disable/enable, or mode switch the timer), implement code to suppress the spurious interrupt event, should it occur. This can be achieved by following the process shown in Example 1. The issue can be resolved in either of these ways: • Prior to the I2C slave reception, enable the clock stretching feature. This is done by (SSPCON2<0>). setting the SEN bit • Each time the SSPIF is set, read the SSPBUF before the first rising clock edge of the next byte being received. Affected Silicon Revisions B2 B3 X X 2006-2014 Microchip Technology Inc. DS80000285D-page 3 PIC18F2221/2321/4221/4321 EXAMPLE 1: ASYNCHRONOUS TIMER MODE WORK AROUND TO AVOID SPURIOUS INTERRUPT //Timer1 update procedure in asynchronous mode //The code below uses Timer1 as example T1CONbits.TMR1ON = 0; PIE1bits.TMR1IE = 0; TMR1H = 0x00; TMR1L = 0x00; T1CONbits.TMR1ON = 1; //Stop timer from incrementing //Temporarily disable Timer1 interrupt vectoring //Update timer value //Turn on timer //Now wait at least two full T1CKI periods + 2TCY before re-enabling Timer1 interrupts. //Depending upon clock edge timing relative to TMR1H/TMR1L firmware write operation, //a spurious TMR1IF flag event may sometimes assert. If this happens, to suppress //the actual interrupt vectoring, the TMR1IE bit should be kept clear until //after the "window of opportunity" (for the spurious interrupt flag event has passed). //After the window is passed, no further spurious interrupts occur, at least //until the next timer write (or mode switch/enable event). while(TMR1L < 0x02); NOP(); NOP(); PIR1bits.TMR1IF = 0; PIE1bits.TMR1IE = 1; //Wait for 2 timer increments more than the Updated Timer //value (indicating more than 2 full T1CKI clock periods elapsed) //Wait two more instruction cycles //Clear TMR1IF flag, in case it was spuriously set //Now re-enable interrupt vectoring for timer 1 Affected Silicon Revisions B2 B3 X X DS80000285D-page 4 2006-2014 Microchip Technology Inc. PIC18F2221/2321/4221/4321 1. Module: Configuration Bits and Device IDs Data Sheet Clarifications Table 23-1: Configuration Bits and Device IDs, on Page 253, has been changed to designate Bit 3 of CONFIG4L as unimplemented. The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39689F): Note: The table is changed as shown. Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 300002h CONFIG2L — — — BORV1 BORV0 BOREN1 300003h CONFIG2H — — — Bit 1 Bit 0 FOSC1 FOSC0 BOREN0 PWRTEN WDTPS3 WDTPS2 WDTPS1 WDTPS0 LPT1OSC PBADEN Default/ Unprogrammed Value 00-- 0111 ---1 1111 WDTEN ---1 1111 CCP2MX 1--- -011 300005h CONFIG3H MCLRE — — — — 300006h CONFIG4L DEBUG XINST BBSIZ1 BBSIZ0 — LVP — STVREN 1000 -1-1 300008h CONFIG5L — — — — — — CP1 CP0 ---- --11 11-- ---- 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — — — WRT1 WRT0 ---- --11 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 ---- --11 30000Dh CONFIG7H -1-- ---- 3FFFFEh DEVID1(1) (1) — EBTRB — — — — — — DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100 3FFFFFh DEVID2 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Unimplemented in PIC18F2221/4221 devices; maintain these bits set. See Register 23-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. Note 1: 2: 2006-2014 Microchip Technology Inc. DS80000285D-page 5 PIC18F2221/2321/4221/4321 2. Module: CONFIG4L Register Register 23-5 CONFIG4L: Configuration Register 4 Low (Byte Address 300006h), on Page 258, has been changed to designate Bit 3 of CONFIG4L as unimplemented. The register is changed as shown. REGISTER 23-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST BBSIZ1 BBSIZ0 — LVP — STVREN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5-4 BBSIZ<1:0>: Boot Block Size Select bits Feature2 Devices: 1x = 1024 Words 01 = 512 Words 00 = 256 Words Feature1 Devices: 1x = 512 Words x1 = 512 Words 00 = 256 Words bit 3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP™ Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset DS80000285D-page 6 2006-2014 Microchip Technology Inc. PIC18F2221/2321/4221/4321 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (7/2006) First revision of this document. Silicon issue 1 (MSSP). Rev B Document (6/2007) Added silicon Converter). issue 2 (10-Bit Analog-to-Digital Rev C Document (5/2010) Converted existing silicon errata and data sheet errata documents to new, combined format. Removed issue 1 (MSSP), making former issue 2 (10-Bit A/D) issue 1. Added silicon issue 2 (MSSP) and removed data sheet clarifications 1-3 and 6-14. This document replaces these errata documents: • DS80285B, “PIC18F2221/2321/4221/4321 Rev. B2 Silicon Errata” – DS number assumed by this errata • DS80310G, “PIC18F2221/2321/4221/4321 Data Sheet Errata” – Document retired Rev D Document (7/2014) Updated errata to new format; Added MPLAB X IDE; Added Module 3, Timer1/3, to Silicon Errata Issues section. 2006-2014 Microchip Technology Inc. DS80000285D-page 7 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2006-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-446-1 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS80000285D-page 8 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2006-2014 Microchip Technology Inc. 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