PIC18(L)F23/24/43/44K22 PIC18(L)F23/24/43/44K22 Rev. A2 Silicon Errata and Data Sheet Clarification The PIC18(L)F23/24/43/44K22 family devices that you have received conform functionally to the current Device Data Sheet (DS41412F), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC18(L)F23/24/43/44K22 silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A2). Data Sheet clarifications and corrections start on page 6, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1. 2. 3. 4. 5. Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB IDE project. Configure the MPLAB IDE project for the appropriate device and hardware debugger. Based on the version of MPLAB IDE you are using, do one of the following: a) For MPLAB IDE 8, select Programmer > Reconnect. b) For MPLAB X IDE, select Window > Dashboard and click the Refresh Debug Tool Status icon ( ). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18(L)F23/24/ 43/44K22 silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Device ID(1) Revision ID for Silicon Revision(2) A1 A2 PIC18F43K22 0101 0111 000x xxxx 0 0001 0 0010 PIC18LF43K22 0101 0111 001x xxxx 0 0001 0 0010 PIC18F23K22 0101 0111 010x xxxx 0 0001 0 0010 PIC18LF23K22 0101 0111 011x xxxx 0 0001 0 0010 PIC18F44K22 0101 0110 000x xxxx 0 0001 0 0010 PIC18LF44K22 0101 0110 001x xxxx 0 0001 0 0010 PIC18F24K22 0101 0110 010x xxxx 0 0001 0 0010 PIC18LF24K22 0101 0110 011x xxxx 0 0001 0 0010 Note 1: 2: The Device ID is located in the last configuration memory space. Refer to the “PIC18(L)F2XK22/4XK22 Flash Memory Programming Specification” (DS41398) for detailed information on Device and Revision IDs for your specific device. 2010-2015 Microchip Technology Inc. DS80000512J-page 1 PIC18(L)F23/24/43/44K22 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item No. Issue Summary Affected Revisions(1) A1 A2 Comparators CxSYNC Control 1. The comparator output to the device pin (Cx) always bypasses the Timer1 synchronization latch. X Clock Switching Fail-Safe Clock Monitor 2. When the FCMEN Configuration bit is set and the IESO Configuration bit is not set, then a clock failure during Sleep will not be detected. X Power-on Reset (POR) Power-on Reset 3. Transient current spikes on some parts during power-up may cause the part to become stuck in Reset. X Timer1/3/5 Gate Timer1/3/5 Gate 4. The Timer1/3/5 gate times cannot be resolved to the two Least Significant bits, when using FOSC as the Timer1/ 3/5 source. X X Timer1/3/5 Interrupt 5. When the timer is operated in Asynchronous External Input mode, unexpected interrupt flag generation may occur. X X EUSART EUSART Asynchronous Operation 6.1 The EUSART asynchronous operation may miss the Start bit edge. X EUSART EUSART Synchronous Operation 6.2 LSb of transmitted data can be corrupt. X X MSSP (Master Synchronous Serial Port) SPI Master Mode 7. Buffer Full (BF) bit or MSSP Interrupt Flag (SSPIF) bit becomes set half SCK cycle too early. X X Note 1: X Only those issues indicated in the last column apply to the current silicon revision. DS80000512J-page 2 2010-2015 Microchip Technology Inc. PIC18(L)F23/24/43/44K22 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A2). 1. Module: Comparators The CxSYNC controls are inoperative. The comparator output (Cx) always bypasses the Timer1 synchronization latch. 4. Module: Timer1/3/5 Gate The Timer gate times cannot be resolved to the two Least Significant timer bits when the source frequency is FOSC (TMRxCS <1:0> = 01). This is because the gate edges are synchronized with the FOSC/4 clock. Work around None. Affected Silicon Revisions A1 A2 X X Work around None. Affected Silicon Revisions A1 A2 X 2. Module: Clock Switching When the FCMEN Configuration bit is set and the IESO Configuration bit is not set, then a clock failure during Sleep will not be detected. Work around The IESO Configuration bit must also be set when the FCMEN Configuration bit is set. Affected Silicon Revisions A1 A2 X X 3. Module: Power-on Reset (POR) There may be transient current spikes on some parts during power-up. If the application cannot supply enough current to get past these transients, then the part may become stuck in Reset. Work around Ensure that the application is capable of supplying at least 30 mA of transient current during power-up. Affected Silicon Revisions A1 A2 X 2010-2015 Microchip Technology Inc. DS80000512J-page 3 PIC18(L)F23/24/43/44K22 5. Module: Timer1/3/5 When Timer1, Timer3 or Timer5 is operated in Asynchronous External Input mode, unexpected interrupt flag generation may occur if an external clock edge arrives too soon following a firmware write to the TMRxH:TMRxL registers. An unexpected interrupt flag event may also occur when enabling the module or switching from Synchronous to Asynchronous mode. Work around This issue only applies when operating the timer in Asynchronous mode. Whenever possible, operate the timer module in Synchronous mode to avoid spurious timer interrupts. If Asynchronous mode must be used in the application, potential strategies to mitigate the issue may include any of the following: EXAMPLE 1: • Design the firmware so it does not rely on the TMRxIF flag or keep the respective interrupt disabled. The timer still counts normally and does not reset to 0x0000 when the spurious interrupt flag event is generated. • Design the firmware so that it does not write to the TMRxH:TMRxL registers or does not periodically disable/enable the timer, or switch modes. Reading from the timer does not trigger the spurious interrupt flag events. • If the firmware must use the timer interrupts and must write to the timer (or disable/enable, or mode switch the timer), implement code to suppress the spurious interrupt event, should it occur. This can be achieved by following the process shown in Example 1. ASYNCHRONOUS TIMER MODE WORK AROUND TO AVOID SPURIOUS INTERRUPT //Timer1 update procedure in asynchronous mode //The code below uses Timer1 as example T1CONbits.TMR1ON = 0; //Stop timer from incrementing PIE1bits.TMR1IE = 0; //Temporarily disable Timer1 interrupt vectoring TMR1H = 0x00; //Update timer value TMR1L = 0x00; T1CONbits.TMR1ON = 1; //Turn on timer //Now wait at least two full T1CKI periods + 2TCY before re-enabling Timer1 interrupts. //Depending upon clock edge timing relative to TMR1H/TMR1L firmware write operation, //a spurious TMR1IF flag event may sometimes assert. If this happens, to suppress //the actual interrupt vectoring, the TMR1IE bit should be kept clear until //after the "window of opportunity" (for the spurious interrupt flag event has passed). //After the window is passed, no further spurious interrupts occur, at least //until the next timer write (or mode switch/enable event). while(TMR1L < 0x02); //Wait for 2 timer increments more than the Updated Timer //value (indicating more than 2 full T1CKI clock periods elapsed) NOP(); //Wait two more instruction cycles NOP(); PIR1bits.TMR1IF = 0; //Clear TMR1IF flag, in case it was spuriously set PIE1bits.TMR1IE = 1; //Now re-enable interrupt vectoring for timer 1 Affected Silicon Revisions A1 A2 X X DS80000512J-page 4 2010-2015 Microchip Technology Inc. PIC18(L)F23/24/43/44K22 6. Module: EUSART 6.1 EUSART Asynchronous Operation The EUSART asynchronous operation has a probability of 1 in 256 of missing the Start bit edge for all combinations of BRGH and BRG16 values, other than BRGH = 1, BRG16 = 1. Work around Set BRGH = 1, and BRG16 = 1 and use this baud rate formula: Baud_Rate = F OSC / 4 SPBRGH:SPBRGL +1 Affected Silicon Revisions A1 A2 X 6.2 EUSART Synchronous Operation In Synchronous mode operation, if SPBRG[H:L] = 0x0001, any character that is put in TXREG while a character is still in TSR, will transmit TX9D as the LSb. Work around Use the TRMT bit in place of, or in addition to the TXIF bit to ensure that only one character is set to transmit at a time Affected Silicon Revisions A1 A2 X X 2010-2015 Microchip Technology Inc. 7. Module: MSSP (Master Synchronous Serial Port) 7.1 SPI Master mode When the MSSP is used in SPI Master mode and the CKE bit is clear (CKE = 0), the Buffer Full (BF) bit and the MSSP Interrupt Flag (SSPIF) bit become set half an SCK cycle early. If the user software immediately reacts to either of the bits being set, a write collision may occur as indicated by the WCOL bit being set. Work around To avoid a write collision one of the following methods should be used: Method 1: Add a software delay of one SCK period after detecting the completed transfer (the BF bit or SSPIF bit becomes set) and prior to writing to the SSPBUF register. Verify the WCOL bit is clear after writing to SSPBUF. If the WCOL bit is set, clear the bit in software and rewrite the SSPBUF register. Method 2: As part of the MSSP initialization procedure, set the CKE bit (CKE = 1). Affected Silicon Revisions A1 A2 X X DS80000512J-page 5 PIC18(L)F23/24/43/44K22 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41412F): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: ECCP The auto-shutdown options for the ECCPxAS register (Register 14-5) have been changed as shown below in bold text. REGISTER 14-5: R/W-0 ECCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0 CCPxASE R/W-0 CCPxAS<2:0> R/W-0 R/W-0 R/W-0 PSSxAC<1:0> R/W-0 R/W-0 PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-shutdown Event Status bit if PxRSEN = 1; 1 = An Auto-shutdown event occurred; CCPxASE bit will automatically clear when event goes away; CCPx outputs in shutdown state 0 = CCPx outputs are operating if PxRSEN = 0; 1 = An Auto-shutdown event occurred; bit must be cleared in software to restart PWM; CCPx outputs in shutdown state 0 = CCPx outputs are operating bit 6-4 CCPxAS<2:0>: CCPx Auto-Shutdown Source Select bits (1) 000 = Auto-shutdown is disabled 001 = Comparator C1 (async_C1OUT) – output high will cause shutdown event 010 = Comparator C2 (async_C2OUT) – output high will cause shutdown event 011 = Either Comparator C1 or C2 – output high will cause shutdown event 100 = FLT0 pin – low level will cause shutdown event 101 = FLT0 pin – low level will cause shutdown event or Comparator C1 (async_C1OUT) – output high will cause shutdown event 110 = FLT0 pin – low level will cause shutdown event or Comparator C2 (async_C2OUT) – output high will cause shutdown event 111 = FLT0 pin – low level will cause shutdown event or Comparators C1 or C2 – output high will cause shutdown event bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to ‘0’ 01 = Drive pins PxA and PxC to ‘1’ 1x = Pins PxA and PxC tri-state bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to ‘0’ 01 = Drive pins PxB and PxD to ‘1’ 1x = Pins PxB and PxD tri-state Note 1: If C1SYNC or C2SYNC bits in the CM2CON1 register are enabled, the shutdown will be delayed by Timer1. DS80000512J-page 6 2010-2015 Microchip Technology Inc. PIC18(L)F23/24/43/44K22 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (7/2010) Initial release of this document. Rev B Document (8/2010) Updated errata to the new format; Added Module 3.1, 3.2 and 4; Revised Module 1. Data Sheet Clarifications: Added Module 1. Rev C Document (8/2011) Added Module 5, EUSART; Other minor corrections. Data Sheet Clarifications: No changes. Rev D Document (12/2011) Removed Module 3.2; Other minor corrections. Data Sheet Clarifications: Removed Module 1. Rev E Document (2/2012) Removed Module 3.2; Other minor corrections. Data Sheet Clarifications: No changes. Rev F Document (7/2012) Added MPLAB® X IDE; Added Module 5.2. Rev G Document (7/2014) Added Module 5, Timer1/3/5. Rev H Document (10/2014) Added Module 7, MSSP. Other minor corrections. Rev J Document (12/2015) Data Sheet Clarifications: Added Module 1: ECCP, applying corrections to bits 6-4 in Register 14-5. 2010-2015 Microchip Technology Inc. DS80000512J-page 7 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. 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Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2010-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0082-0 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS80000512J-page 8 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010-2015 Microchip Technology Inc. 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