SC4808C Datasheet

SC4808C
High Performance Dual
Ended PWM Controller
POWER MANAGEMENT
Description
Features
The SC4808C is a dual-ended, high frequency, integrated
PWM controller, optimized for isolated applications that
require minimum space. It can be configured for current
or voltage mode operation with required control circuitry
where secondary side error amplifier is used.
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‹
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Some of the key features are high frequency operation of
1 MHz that allows the use of smaller components thus
saving cost and valuable board space. An internal ramp
on the Current Sense pin allows Internal Slope
Compensation programmed by an external resistor. Other
features include programmable frequency up to 1MHz, ‹
Pulse by Pulse current and Line Monitoring Input with ‹
Hysteresis to reduce stress on the power components.
‹
‹
A unique oscillator is used to synchronize two SC4808C’s
to work out of phase. This minimizes the input and output
ripple thus reducing noise on the output line and reducing
stress and size of input/output filter components. The dual
outputs can be configured in Push-Pull, Half Bridge and
Full Bridge format with programmable dead time between
two outputs depending on the size of the timing
components.
120µA starting current
Pulse by pulse current limit
Programmable operation up to 1MHz
Internal soft start
Programmable line undervoltage lockout
Over current shutdown
Dual output drive stages on push-pull configuration
Programmable internal slope compensation
Programmable mode of operation (peak current mode
or voltage mode)
External frequency synchronization
Bi-phase mode of operation
-40 to 105 °C operating temperature
MSOP-10 lead free package. This product is fully WEEE
and RoHS compliant
Applications
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‹
‹
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‹
‹
The SC4808C also features a turn on threshold of 8V and
‹
is available in MSOP-10 package.
Telecom equipment and power supplies
Networking power supplies
Industrial power supplies
Push-pull converter
Half bridge converter
Full bridge converter
Isolated VRM’s
Typical Application Circuit
Vo
Gnd_Out
Vin
RSENSE
Gnd_In
OUTA
RC
OUTB
REF
CS
VCC
SYNC
FB
SYNC
LUVLO GND
SC4808
Revision: July 13, 2006
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SC4808C
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Supply Voltage
VCC
-0.5 to18
V
Supply Current
ICC
20
mA
-0.5 to 7
V
SYNC, RC,CS, LUVLO, REF to GND
FB to GND
V FB
-0.5 to (VREF+ 0.5)
V
REF Current
IREF
10
mA
VOUTA/B
-0.5 to 18
V
Isource
-250
mA
OUTA/OUTB Sink Current (peak)
Isink
250
mA
Thermal Resistance
θJ A
136*
°C/W
Junction Temperature
TJ
-40 to 150
°C
Storage Temperature Range
TSTG
-65 to 150
°C
Lead Temperature (Soldering) 10 Sec.
TLEAD
+300
°C
ESD Rating (Human Body Model)
V ESD
2
kV
OUTA/OUTB to GND
OUTA/OUTB Source Current (peak)
*Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad as per JESD51 standards.
Electrical Characteristics
Unless specified: VCC = 12V; CL = 100pF; TA = -40°C to 105°C
Parameter
Test Conditions
Min
Typ
Max
Unit
Maximum Duty Cycle
Fosc = 50kHz, FB = 3.5V,
Measured at OUTA or OUTB
48
49
50
%
Minimum Duty Cycle
Fosc = 50kHz, FB = 1.5V,
Measured at OUTA or OUTB
0
%
575
mV
PWM
Current Sense
Gain
3
Maximum Input Signal
475
CS to Output Delay
525
100
Over Current Threshold
600
Internal Slope Compensation Resistor
700
ns
800
25
FB to CS Offset
mV
kΩ
1.30
1.50
1.70
V
OUT Low Level
0
.50
.70
V
OUT High Level
11.0
11.25
12.00
V
Output
Rise Time
25
ns
Fall Time
25
ns
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SC4808C
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VCC = 12V; CL = 100pF; TA = -40°C to 105°C
Parameter
Test Conditions
Min
Typ
Max
Unit
Turn-on
7.5
8
8.5
V
Turn-off
6.5
7
7.5
V
-3%
VREF
+3%
V
VCC Under Voltage Lockout
Line Under Voltage Lockout
Start Threshold
RTOP = 14kΩ, RBOT = 10kΩ
Hysteresis
RTOP = 14kΩ, RBOT = 10kΩ
5.6% of
VREF
mV
200
µs/V
12
µs
140
µs
Soft Start
Internal Soft Start Ramp
Soft Start Duration
Rcs = 1kΩ
(See formula in the Application
Information Soft Start section)
Soft Start Delay
Oscillator
Oscillator Frequency
Rosc = 11kΩ, Cosc = 200pF
450
Oscillator Ramp
RC pin to GND capacitance
Oscillator Frequency Range
500
550
KHz
VREF/2
+0.25
V
22
pF
50
1000
KHz
Sync/CLOCK
Clock SYNC Threshold
1.0
Sync Frequency Range
V
Fosc*1.3
KHz
3.280
V
B an d g ap
Reference Voltage
2.970
Reference Current
3.125
5
mA
Overall
Startup Current
VCC < start threshold
150
µA
Operating Supply Current
FB = 0V, CS = 0V
7
mA
VCC Zener Shunt Voltage
IDD = 10mA
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SC4808C
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Pin Configuration
Ordering Information
Top View
Part Number
P ackag e
Top Mark
SC4808CMSTRT(1)(2)
MSOP-10
A B 0C
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
(MSOP-10)
Block Diagram
VCC
CS
Slope Comp.
OVER CURRENT
Peak Current
OUTA
Enable
S
OSC
Q
R
Disable
500mv
Q
T
S
REF
R
Bandgap
Q
Q
LUVLO
SOFT
START
UVLO
R
OUTB
SYNC
2R
LUVLO
GND
LUVLO
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FB
RC
4
SYNC
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SC4808C
POWER MANAGEMENT
Pin Descriptions
LUVLO: Line undervoltage lockout pin. An external resistive divider will program the undervoltage lockout level. The
external divider should be referenced to the quiet analog
ground. During the LUVLO, the driver outputs are disabled
and the softstart is reset. This pin can also function as an
Enable/Disable.
FB: The inverting input to the PWM comparator. Stray inductances and parasitic capacitance should be minimized
by utilizing ground planes.
REF: Bandgap reference output It should be by passed with
a 2.2uF low ESR capacitance, right at the IC pin.
SYNC: SYNC is a positive edge triggered input with a threshold set to 1.0V. In a single controller operation, SYNC could
be grounded or connected to an external synchronization
clock within the SYNC frequency range. In the Bi-Phase
operation mode SYNC pins could be connected to the Cosc
(Timing Capacitors) of the other controller. This will force
an out of phase operation.
CS: Current sense input and internal slope compensation
are both provided via the CS pin. The current sense input
from a sense resistor is used for the peak current and
overcurrent comparators. An internal 1 to 3 feed back voltage divider provides a 3X amplification of the CS signal.
This is used for comparison to the external error amplifier
signal. If an external resistor is connected from CS to the
current sense resistor, the internal current source will provide a programmable slope compensation. The value of
the resistor will determine the level of compensation. At
higher compensation levels, voltage mode of operation can
be achieved.
GND: Device power and analog ground. Careful attention
should be paid to the layout of the ground planes (see page
16.)
OUTA and OUTB: Out of phase gate drive stages. The
driver’s peak source and sink current drive capability of
100mA, enables the use of an external MOSFET driver or
a NPN/PNP transistor buffer.
The oscillator RC network programs the oscillator frequency,
which is twice the OUTA/OUTB frequency. To insure that
the outputs do not overlap, a dead time can be generated
between the two outputs by sizing the oscillator timing
capacitor.
RC: The oscillator programming pin. The oscillator should
be referenced to a stable reference voltage for an accurate and stable frequency. Only two components are required to program the oscillator, a resistor (tied to Vref and
RC), and a capacitor (tied to the RC and GND). The following formula can be used for a close approximation of the
oscillator frequency.
FOSC ≅
1
ROSCCTOT × 0.8
VCC: The supply input for the device. Once VCC has exceeded the UVLO limit, the internal reference, oscillator,
drivers and logic are powered up. A low ESR capacitance,
should be used for decoupling right at the IC pin to minimize noise problems.
where:
CTOT = COSC + CSC 4808 + CCircuit
CSC 4808 ≅ 22pF
Where the frequency is in Hertz, resistance in ohms, and
capacitance in farads. The recommended range of timing
resistors is between 10 kOhm and 200kOhm and range of
timing capacitors is between 100pF and 1000pF. Timing
resistors less than 10 kOhm should be avoided.
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SC4808C
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Application Information
THEORY OF OPERATION
The SC4808C is a versatile double ended, high speed, low
power, pulse width modulator that is optimized for applications requiring minimum space.
The device contains all of the control and drive circuity required for isolated or non isolated power supplies where
an external error amplifier is used. A fixed oscillator frequency (up to 1MHz) can be programmed by an external
RC network.
The SC4808C is a peak current or voltage mode controller,
depending on the amount of slope compensation,
programmable with only one external resistor. The cycle by
cycle peak current limit prevents core saturation when a
transformer is used for isolation while the overcurrent
circuitry initiates the softstart cycle.
The SC4808C dual output drive stages are arranged in a
push-pull configuration. Both outputs switch at half the
oscillator frequency using a toggle flip flop. The dead time
between the two outputs is programmable depending on
the values of the timing capacitor and resistors, thus limiting
each output stage duty cycle to less than 50%.
The SC4808C also provides flexibility with programmable
LUVLO thresholds, with built-in hysteresis.
The current sense input and internal slope compensation
are both provided via the CS pin. The current sense input
from a sense resistor is used for the peak current and
overcurrent comparators. An internal 1 to 3 feedback voltage divider provides a 3X amplification of the CS signal.
This is used for comparison to the external error amplifier
signal. If an external resistor is connected from CS to the
current sense resistor, the internal current source will provide a programmable slope compensation. The value of
the resistor will determine the level of compensation. At
higher compensation levels, voltage mode of operation can
be achieved. The error amplifier signal at the FB pin will be
used in conjunction with the CS signal to achieve regulation.
Two levels of undervoltage lockout are also available. The
LUVLO (line under voltage lockout) pin via an external resistive divider will program the undervoltage lockout level.
During the LUVLO, the driver outputs are disabled and the
softstart is reset.
Once VCC has exceeded the UVLO (VCC under voltage lockout) limit, the internal reference, oscillator, drivers and logic
are powered up.
SUPPLY
SYNC is a positive edge triggered input with a threshold
set to 1.0V.
By connecting an external control signal to the SYNC pin,
the internal oscillator frequency will be synchronized to the
positive edge of the external control signal. In a single controller operation, SYNC should be grounded or connected
to an external synchronization clock within the SYNC frequency range .
In the Bi-phase operation mode a very unique oscillator
is utilized to allow two SC4808C to be synchronized
together and work out of phase. This feature is setup by
simple connection of the SYNC input to the RC pin of the
other part. The fastest oscillator automatically becomes
the master, forcing the two PWMs to operate out of
phase. This feature minimizes the input and output
ripples, and reduces stress on the capacitors.
A single supply, VCC is used to provide the bias for the
internal reference, oscillator, drivers, and logic circuitry of
SC4808C. To ensure proper operation during start up, VCC
slew rate of less than 10V/mS is recommended.
PWM CONTROLLER
SC4808C is a double ended PWM controller that can be
used in voltage or current mode applications. The SC4808C
provides a 7.5V VCC UVLO, and a 3.125V reference. The
oscillator frequency is programmed by a resistor and a capacitor network connected to an external reference provided by the SC4808C. The two outputs, OUTA and OUTB,
are 180 degrees out of phase and run at half of the oscillator frequency.
An external error amplifier will provide the error signal to
the FB pin of the SC4808C.
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SC4808C
POWER MANAGEMENT
Application Information (Cont.)
VCC UNDER VOLTAGE LOCK OUT
The oscillator frequency is set by connecting a RC network
as shown below.
Depending on the application and the voltages available,
the SC4808C can be used to provide the VCC undervoltage
lock out function to ensure the converters controlled start
up.
Before the VCC UVLO has been reached, the internal reference, oscillator, OUTA/OUTB drivers, and logic are disabled.
REF
VCC
R27
15k
LINE UNDER VOLTAGE LOCK OUT
U4
5
REF
4
The SC4808C also provides a line undervoltage (LUVLO =
Vref) function. The LUVLO pin is programmed via an external resistor divider connected as shown below. The actual
start-up voltage can be calculated by using the equation
below:
3
2
C31
200p
1
15
= V REF ×
(R 23
R24 10k
+ R 33
R 33
OUTB
CS
OUTA
RC
VCC
SYNC
U4
5
3
2
C31
200p
8
9
10
C33
0.1u,25V
0
56.2k
10k
R23
R33
VCC
4
82p
7
The oscillator has a ramp voltage of about Vref/2. The oscillator frequency is twice the frequency of the OUTA and
OUTB gate drive controls.
The oscillator capacitor C31 is charged by a current sourced
from the Vref through R27. Once the RC pin reaches about
Vref/2, the capacitor is discharged internally by the
SC4808C. It should be noted that larger capacitor values
will result in a longer dead time during the down slope of
the ramp.
The following equation can be used as an approximation
of the oscillator frequency and the Dead time:
R25 18
C29
R28
10
6
)
REF
R27
15k
LUVLO
SC4808
SYNC
C26
2.2u,16V
R26
2.2k
GND
FB
Vin
V Startup
0
C26
2.2u,16V
1
REF
GND
FB
OUTB
CS
OUTA
RC
VCC
SYNC
LUVLO
SC4808
SYNC
Vin
R28
10
6
7
8
9
10
C33
0.1u,25V
56.2k
10k
R23
R33
FOSC ≅
1
ROSCCTOT × 0.8
where:
REFERENCE
CTOT = COSC + CSC 4808 + CCircuit
A 3.125V(SC4808C) reference voltage is available that can
be used to source a typical current of 5mA to the external
circuitry. The Vref can be used to provide the oscillator RC
network with a regulated bias.
CSC 4808 ≅ 22pF
Tdeadtime ≅
The recommended range of timing resistors is between 10
kOhm and 200kOhm, range of timing capacitors is between
100pF and 1000pF. Timing resistors less than 10 kOhm
should be avoided.
OSCILLATOR
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COSC × VREF × 0.5
3 ⋅ 10 −3
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SC4808C
POWER MANAGEMENT
Application Information (Cont.)
SYNC/Bi-Phase operation
FEED BACK
In noise sensitive applications where synchronization of
the oscillator frequency to a reference frequency is required,
the SYNC pin can accept the external clock. By connecting
an external control signal to the SYNC pin, the internal oscillator frequency will be synchronized to the positive edge
of the external control signal. SYNC is a positive edge triggered input with a threshold set to 1.0V (SC4808C).
In a single controller operation, SYNC should be grounded
or connected to an external synchronization clock within
the SYNC frequency range.
The error signal from the output of an external error amplifier such as SC431 or SC4431 is applied to the inverting
input of the PWM comparator at the FB pin either directly
or via an opto coupler for the isolated applications. For best
stability, keep the FB trace length as short as possible.
Vref
Vout
Vout
R37
2.2k
C35
R34
FB
6
3
5
4
C36
C40
22pF
5
R36
1
MOCD207
C38
0.1u
R32
R35
C37
4
C39
22n
SC4431
OUTA (PWM1)
R38
Vref
2
OUTB (PWM1)
The signal at the FB pin is then compared to the 3X amplified signal from the current sense/ slope compensation
CS pin. Matched out of phase signals are generated to
control the OUTA and OUTB gate drives of the two phases.
A single ramp signal is used to generate the control signals for both phases, hence achieving a tightly matched
per phase operation.
Voltages below 1.5V at the FB pin, will produce a 0% duty
cycle at the OUTA/OUTB gate drives. This offset is to provide enough head room for the opto coupler used in isolated applications.
OUTA (PWM2)
OUTB (PWM2)
REF
REF
U1
Rosc1
5
4
3
2
Cosc1
1
REF
GND
FB
OUTB
CS
OUTA
RC
SYNC
U2
Rosc2
VCC
LUVLO
SC4808
6
5
7
4
8
3
9
2
10
Cosc2
1
REF
GND
FB
OUTB
CS
OUTA
RC
VCC
SYNC
LUVLO
6
7
8
9
GATE DRIVERS
10
OUTA and OUTB are out of phase bipolar gate drive output
stages, that are supplied from VCC and provide a peak
source/sink current of about 100mA. Both stages are capable of driving the logic input of external MOSFET drivers
or a NPN/PNP transistor buffer. The output stages switch
at half the oscillator frequency. When the voltage on the
RC pin is rising, one of the two outputs is high, but during
fall time, both outputs are off. This “dead time” between
the two outputs, along with a slower output rise and fall
time, insures that the two outputs can not be on at the
same time. The dead time is programmable and depends
upon the timing capacitor.
SC4808
In the Bi-phase operation mode a very unique oscillator is
utilized to allow two SC4808C’s to be synchronized together
and work out of phase. This feature is set up by a simple
connection of the SYNC input to the RC pin of the other
part. The fastest oscillator automatically becomes the
master, forcing the two PWMs to operate out of phase. This
feature minimizes the input and output ripples, and reduces
stress on the capacitors.
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SC4808C
POWER MANAGEMENT
Application Information (Cont.)
It should be noted that if high speed/high current drivers
such as the SC1301 are used, careful layout guide lines
must be followed in order to minimize stray inductance,
which might cause negative voltages at the output of the
drivers. This negative voltage can be clamped to a reasonable level by placing a small Schottky diode directly at the
output of the driver as shown below.
VCC
EN
SC1301A
3 5 U3
F
C23
0.1u
VCC
1
4
C26
2.2u,16V
D_B
U4
5
4
3
2
1
REF
GND
FB
OUTB
CS
OUTA
RC
VCC
SYNC
LUVLO
SC4808
SYNC
Vin
Gate_B
2
R28
10
6
7
8
VCC
9
10
EN
SC1301A
C33
0.1u,25V
3 5 U6
C34
0.1u
56.2k
R23
10k
1
4
Gate_A
D_A
R33
2
OVER CURRENT
Two levels of over current protection are provided by the
SC4808C. The current information is sensed at the CS pin
and compared to a peak current limit level of 525mV. If
the 525mV limit is exceeded, the OUTA and OUTB pulse
widths and duty cycle is reduced until the CS pin reaches a
second threshold of 700mV. At that point, the OUTA and
OUTB are disabled, and after a delay of 140µs, the internal softstart sequence is started. After the softstart duration, normal operation is achieved, unless the over current condition is still present.
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SC4808C
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Application Information (Cont.)
SLOPE COMPENSATION (Current or Voltage mode of operation)
In applications where a current mode control is used for regulation, the peak inductor current information is used to
produce the average output current. If a small perturbation due to changes in supply voltage or noise pick up is generated, instability may occur if the duty cycle is >50%.
This phenomenon is graphically shown below. The inductor current and disturbed inductor current are shown for three
different duty cycles conditions.
The top wave form shows the applications where the duty cycle D is less than 50%. As shown, even if an error is
introduced, after only a few cycles the error converges to zero.
The second wave form shows the case where D = 50%. Under this condition, even though the error does not completely
disappear, it stays constant and is not getting larger. This will be seen as jitter at the inductor voltage.
The bottom wave form shows D>50%. As shown, a very small error results in a much larger error only after a few cycles.
This will cause instability in the converter and the average output inductor current. The output load will not be able to be
kept in regulation.
i
I
L
: Small Inductor current perturbation
L
: Inductor current
D<50%
I
L
Instability in current mode operation
due to Duty cycle >50%
i
L
Error
Note: After afew c ycles the perturbation
disappears and stable operation returns.
Time
D=50%
I
L
i
i
L
L
Error
Note: After afew c ycles the perturbation
is still pres ent, although this w ill caus e
jitter, but there is no instability.
Time
I
L
i
i
L
L
Error
D>50%
Time
 2006 Semtech Corp.
Note: After afew c ycles the perturbation
becomes larger, and causes instability.
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SC4808C
POWER MANAGEMENT
Application Information (Cont.)
If the Rslope comp is increased, the internal ramp becomes the
dominant signal and more voltage mode of operation is
achieved. As it can be calculated from the second formula
below, a 100% voltage mode operation can be achieved by
choosing Rslope comp to be greater than 6.25kOhm. Also if a
100% current mode of operation is required, Rslope comp is
reduced to zero and the contribution from the internal ramp
is completely eliminated.
The instability can be corrected by modification of the peak
current information slope. One of the methods to alter the
peak current information is to add a positive going ramp to
the output of the current sensing circuitry.
The SC4808C achieves this by using an internal slope compensation circuit. The oscillator ramp is internally buffered
and an internal 25kOhm resistor in conjunction with an
external resistor at the CS pin will program the level of slope
compensation.
VRamp ×
%Slope _ Comp=
Current Transformer
N = 100
R
REF
 0.2 × (%slope _ Comp) 
R external ≅ Rint ernal • 

 1 − (0.2 × %slope _ Comp)
C
2.2u,16V
Rsense
Rosc
15k
RSlope Comp
5
4
3
REF
GND
6
Next page illustrates how the buffered oscillator ramp is
used to modify the sensed inductor current.
It should be noted that in order for the slope compensation to be effective, the current sensed signal slope should
be at least 50% less steeper than the oscillator positive
ramp slope. The slope will include the magnetizing current
of the transformer and the inductor output current in isolated applications. In non-isolated applications, the slope
will only include the inductor output current.
7
FB
25k
CS
Cfilter
82p
2
Cosc
200p
1
RC
SYNC
SC4808
RSlope Comp value will determine the Mode of operation (Voltage or Current)
The Peak current information is sensed and the result is
realistically summed to the buffered oscillator ramp, as
shown above. The value of the external resistor Rslope comp
will determine the percentage of the slope compensation.
As the value for Rslope comp is reduced, the current information becomes more dominant and the mode of operation
becomes more current mode. At the same time the slope
of the current information is modified to provide the slope
compensation.
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VCS
or
10k
D
(Rslope _ Comp + Rsense )
(Rslope _ Comp + Rsense ) + Rint ernal
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SC4808C
POWER MANAGEMENT
Application Information (Cont.)
i
I
L
I
I
L
: Sm all Inductor current perturbation
: Inductor current
Slope Compensation generation from
Buffered Oscillator Ramp
Sense
: Sensed Mosfet current
CS
: Sum m ation of Isense and slope com pensation, at the CS pin of the SC4808.
D>50%
Note: Below wave form s are not to scale.
I
L
I
Sense
Buffered
Oscillator
Ramp
I
CS
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SC4808C
POWER MANAGEMENT
Application Information (Cont.)
Below the benefits from the slope compensation become apparent. The top wave form shows the stable operation
before the perturbation. The second wave form shows the perturbation and the instability caused from it if no slope
compensation is added to the current information. The last wave form shows the slope compensation and the effect of
it. The increase in the slope of the current information results in an early termination of the inductor current, hence a
reduction in the amount of error. As the cycle is repeated, the perturbation is reduced and finally eliminated.
i
∆I
I
I
δ
: Small Inductor current perturbation
L
: Inductor current
L
Stable current mode operation with Slope
Compensation
Sense
: Sensed Mosfet current
CS
: Summation of Isense and slope compensation, at the CS pin of the SC4808.
D>50%
Stable operation
( no perturbation)
Error Signal from Error amplifier
∆
I
I
L
Sense
Note: After a few cycles the perturbation
becomes larger, and causes instability.
Instable operation
( with perturbation)
Error Signal from Error amplifier
∆
I
I
L
Sense
δ
i
L
Note: After a few cycles the perturbation
disappears and stable operation returns.
Stable operation
(Slope Compensation Added)
I
∆
CS
 2006 Semtech Corp.
I
L
δ
Error Signal from Error amplifier
i
L
13
www.semtech.com
SC4808C
POWER MANAGEMENT
Application Information (Cont.)
SOFT START
START UP SEQUENCE
During start up of the converter, the discharged output capacitor and the load current have large supply current requirements. To avoid this a soft start scheme is usually
implemented where the duty cycle of the regulator is gradually increased from 0% until the soft start duration is
elapsed.
SC4808C has an internal soft start circuit that limits the
duty cycle for a duration approximated by the formula below. Also the soft start circuitry is activated if an over current condition occurs. After an over current condition, OUTA
and OUTB are disabled and kept low for a duration of about
140µs. After the delay, the OUTA and OUTB are enabled
while the soft start limits the duty cycle. If the over current
condition persists, the soft start cycle repeats indefinitely.
Approximate internal soft start duration can be calculated
as below:
Initially during the power up, the SC4808C is in under voltage lock out condition. As the Vcc supply exceeds the UVLO
limit of the SC4808C, the internal reference, oscillator, and
logic circuitry are powered up.
The OUTA and OUTB drivers are not enabled until the line
under voltage lock out limit is reached. At that point, once
the FB pin is above 1.5V, soft start circuitry starts the output drivers, and gradually increases the duty cycle from
0%. The soft start duration is internally set (see formula in
Soft Start section).
As the output voltage starts to increase, the error signal
from the error amplifier starts to decrease. If isolation is
required, the error amplifier output can drive the LED of
the opto isolator. The output of the opto is connected in a
common emitter configuration with a pull-up resistor to a
reference voltage connected to the FB pin of the SC4808C.
The voltage level at the FB pin provides the duty cycle necessary to achieve regulation.
If an over current condition occurs, the outputs are disabled and after a soft start delay time of about 100µs, the
softstart sequence mentioned above is repeated.
≅
T SoftStart
(Ramp
SoftStart
 R Internal


R CS

) × 
VREF
2


+ 1


_ SlopeComp
_ to _ GND



If longer soft start durations are required, the simple external circuit shown below can be implemented.
REF
VCC
C26
2.2u,16V
REF
R37
1k
R27
15k
6
U4
5
4
C40
NA
3
5
2
56.2K
C31
200p
MOCD207
Csoft start
1
GND
REF
FB
OUTB
CS
OUTA
RC
VCC
SYNC
LUVLO
SC4808
SYNC
Vin
R28
10
6
7
8
9
10
C33
0.1u,25V
56.2k
10k
R23
R33
Approximate soft start duration can be calculated as below:
TSoftStart ≅ CSoftStart × R37
 2006 Semtech Corp.
14
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SC4808C
POWER MANAGEMENT
Application Information (Cont.)
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary for
successful implementation of the SC4808C PWM controller.
High current switching is present in the application and
their effect on ground plane voltage differentials must be
understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and position of ground plane interruptions should be such as to
not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be
deliberately introduced to constrain ground currents to
particular areas, such as the input capacitor and FET
ground.
2). In the loop formed by the Input Capacitor(s) (Cin), the
FET must be kept as small as possible. This loop contains
all the high current, fast transition switching. Connections
should be as wide and as short as possible to minimize
loop inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c)
minimize source ringing, resulting in more reliable gate
switching signals.
3). The connection between FETs and the Transformer
should be a wide trace or copper region. It should be as
short as practical. Since this connection has fast voltage
transitions, keeping this connection short will minimize EMI.
4) The Output Capacitor(s) (Cout) should be located as close
to the load as possible. Fast transient load currents are
supplied by Cout only, and connections between Cout and
the load must be short, wide copper areas to minimize inductance and resistance.
5) The SC4808C is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin FET loop flowing in
this area. GND should be returned to the ground plane close
to the package and close to the ground side of (one of) the
VCC supply capacitor(s). Under no circumstances should
GND be returned to a ground inside the Cin, Q1, Q2 loop.
Avoid making a star connection between the quiet GND
planes that the SC4808C will be connected to and the noisy
high current GND planes connected to the FETs.
6) The feed back connection between the error amplifier
and the FB pin should be kept as short as possible The
GND connections should be connected to the quiet GND
used for the SC4808C.
 2006 Semtech Corp.
7) If an Opto isolator is used for isolation, quiet primary
and secondary ground planes should be used. The same
precautions should be followed for the primary GND plane
as mentioned in item 5 mentioned above. For the secondary GND plane, the GND plane method mentioned in item
4 should be followed.
8) All the noise sensitive components such as LUVLO resistive divider, reference by pass capacitor, Vcc bypass capacitor, current sensing circuitry, feedback circuitry, and
the oscillator resistor/capacitor network should be connected as close as possible to the SC4808C. The GND
return should be connected to the quiet SC4808C GND
plane.
9) The connection from the OUTA and OUTB of the
SC4808C should be minimized to avoid any stray inductance. If the layout can not be optimized due to constraints,
a small Schottky diode may be connected from the OUTA/
B pins to the ground directly at the IC. This will clamp excessive negative voltages at the IC. If drivers are used, the
Schottky diodes should be connected directly at the IC from
the output of the driver to the driver ground.
10) If the SYNC function is not used, the SYNC pin should
be grounded at the SC4808C GND to avoid noise pick up.
15
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SC4808C
POWER MANAGEMENT
Gain & Phase Margin
50
Gain
Phase (deg)
Gain
40
225
180
135
Phase
30
90
45
0
10
Phase (deg)
Gain (dB)
20
-45
0
-90
-10
-135
-20
-180
-30
10
100
1000
10000
-225
100000
Freq (Hz)
Typical SC4808C Push Pull Converter Gain/Phase plot at Vin = 36V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz
 2006 Semtech Corp.
16
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SC4808C
POWER MANAGEMENT
Gain & Phase Margin (Cont.)
50
Gain
Phase (deg)
Gain
40
225
180
135
Phase
30
90
45
0
10
Phase (deg)
Gain (dB)
20
-45
0
-90
-10
-135
-20
-180
-30
10
100
1000
10000
-225
100000
Freq (Hz)
Typical SC4808C Push Pull Converter Gain/Phase plot at Vin = 48V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz
 2006 Semtech Corp.
17
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SC4808C
POWER MANAGEMENT
Gain & Phase Margin (Cont.)
50
Gain
Phase (deg)
Gain
40
225
180
135
Phase
30
90
45
10
0
Phase (deg)
Gain (dB)
20
-45
0
-90
-10
-135
-20
-180
-30
10
100
1000
10000
-225
100000
Freq (Hz)
Typical SC4808C Push Pull Converter Gain/Phase plot at Vin = 72V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz
 2006 Semtech Corp.
18
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SC4808C
POWER MANAGEMENT
Typical Step Load
Vout
500mV/Div
Iout
5A/Div
Cout = 6X22uF (132uF) Ceramic
100us/Div
Typical SC4808C Push Pull Converter Step Load plot at Vin = 48V, Vout = 3.3V, Step = 37% to 75% Iout, Fosc = 650kHz
 2006 Semtech Corp.
19
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SC4808C
POWER MANAGEMENT
Evaluation Board Schematics
Vin+
CON2
ON/OFF
Vin-
1
2
4
3input_half_brick
C12
D4
R3
20k
R8
0
ZM4743A
GRM55DR72E105KW01
C11
1u,100V 1u,100V
R12
56.2k
REF
R32
56.2k
C35
2.2uF 16V
C
B
FZT853
Q1
C
E
A
C14
.1u,16V
D3
1N5819HW
R4
250
VCC
1
GRM55DR72E105KW01
C13
REF
J1
JP1
R17
15k
1u,100V
VCC = 15V
10u,16V
C15
R13 10k
R14 15
82p
C22
GRM32DR61C106KA01
LS4448
D8
R16
1k
82p
C21
FMMT718
Q2
8
T2
7
P8208T
3
D5
1
3
2
M1
R18
10
0.1u,25V
C23
VCC
J2
R9
SUD19N20-90
6
7
8
9
10
C25
10k R21
G_B
2.2
1N5819HW
C19
2.2u,16V
GND
OUTB
OUTA
U1
CS
LUVLO
VCC
SYNC
RC
FB
REF
N = 100
5
4
3
2
1
SC4808
J3
SYNC
10nF
C17
0.1u
C24
0.1u
3
2
1
1
1
G_A
2.2
SUD19N20-90
U3
4
4
D6
G_B
1N5819HW
D7
CMOSH-3
D9
CMOSH-3
G_A
CMOSH-3
D15
D14
CMOSH-3
SC1301A
U2
SC1301A
R10
M2
VCC
3 5
2
3 5
VCC
2
C18
22nF
1
3
U7
CBRHD-02
4
2
R15
0
R19
0
2
3
4
6T
6T
5
1
4T
6
T1
10
10
R2
R5
2.2n C1
10
2.2n C3
Sync Drive Supply
D11
CMOSH-3
D12
CMOSH-3
8
1T
9
1T
PA0500
D10
CMOSH-3
D13
1u,16V
C20
CMOSH-3
16.2 R31
3
1
2
L2
LQH43MN102K011
1
C16
4
6
10u,16V
GRM32DR61C106KA01
VCC
T3
PE-68386
0
1
1
3
MBRB2535CTL
4
D1
D2
3
MBRB2535CTL
4
REF
R24
1k
C28
NA
Note:
2
PG0006.102T
L1
0.9uH
6
7
8
4
3
2
1
1
U6
5
MOCD207
C
A
R29
100
R20
2.2k
C26
0.1u
R26
2.2k
C32
0.1u
1N5819HW
D16
C4
C6
C7
C8
C9
Murata GRM32DR60J226KA01
C5
5
5
Vref
Sync Drive Supply
1
2
U4
SC4431
100pF C29
R27
15k
SC4431
U5
4
C30
Vref
1nF
Sync Drive Supply
1
4
0
22u,6.3V 22u,6.3V 22u,6.3V 22u,6.3V 22u,6.3V 22u,6.3V
C27
22n
C33
22n
2
SEMTECH CORPORATION
SC4808 Push Pull 3.3V 50W non Synchronous
Sheet
1
R22
37.4k
R23
18.2k
C10
0.1u
of
R1
0
R7
0
C2
0.1u
C34
.1uF
For output power > 30W, adequate air flow should be provided to avoid over dissipation.
Title
Size
Document Number
SC4808EVB__non_sync
Date: Monday, October 07, 2002
R11
TBD
R30
15k
1
R6
TBD
R28
25.5k
Sense+
Vout+
8
Trim
9
CON1
7
Sense-
Vout-
6
5
5output_half_brick
R25
11.5k
C31
470pF
Rev
1.1
www.semtech.com
20
 2006 Semtech Corp.
SC4808C
POWER MANAGEMENT
Evaluation Board Bill of Materials
SC4808 Push Pull 3.3V 50W non Synchronous
SC4808EVB__non_sync
Revision: 1.1
Bill Of Materials
Item
Quantity
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
1
2
6
6
3
1
2
1
1
1
2
1
1
2
1
1
1
1
1
1
2
4
1
8
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
1
1
1
1
1
1
1
2
1
1
4
2
1
1
2
1
2
1
1
1
2
3
1
2
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
 2006 Semtech Corp.
October 7,2002
13:35:18
Reference
CON1
CON2
C3,C1
C2,C10,C17,C24,C26,C32
C4,C5,C6,C7,C8,C9
C11,C12,C13
C14
C15,C16
C18
C19
C20
C22,C21
C23
C25
C27,C33
C28
C29
C30
C31
C34
C35
D2,D1
D3,D5,D6,D16
D4
D7,D9,D10,D11,D12,D13,
D14,D15
D8
JP1
J1
J2
J3
L1
L2
M1,M2
Q1
Q2
R1,R7,R15,R19
R5,R2
R3
R4
R6,R11
R8
R9,R10
R12
R13
R14
R16,R24
R17,R27,R30
R18
R26,R20
R21
R22
R23
R25
R28
R29
R31
R32
T1
T2
T3
U1
U2,U3
U4,U5
U6
U7
Part
Manufacturer #
5output_half_brick
3input_half_brick
2.2n
0.1u
22u,6.3V
1u,100V
.1u,16V
10u,16V
22nF
2.2u,16V
1u,16V
82p
0.1u,25V
10nF
22n
NA
100pF
1nF
470pF
.1uF
2.2uF 16V
MBRB2535CTL
1N5819HW
ZM4743A
CMOSH-3
GRM32DR60J226KA01
GRM55DR72E105KW01
GRM32DR61C106KA01
GRM32RR71H105KA011
CMOSH-3 (Central Semiconductor)
LS4448
short
REF
Vcc
SYNC
0.9uH
LQH43MN102K011
SUD19N20-90
FZT853
FMMT718
0
10
20k
250
TBD
0
2.2
56.2k
10k
15
1k
15k
10
2.2k
10k
37.4k
18.2k
11.5k
25.5k
100
16.2
56.2k
PA0500
P8208T
PE-68386
SC4808
SC1301A
SC4431
MOCD207
CBRHD-02
LQH43MN102K01L
SUD19N20-90
Foot Print
CON\5OUTPUT_HALF_BRICK
CON\3INPUT_HALF_BRICK
SM/C_1206
SM/C_0805
SM/C_1210_GRM
SM/C_2220
SM/C_0805
SM/C_1210_GRM
SM/C_1206
SM/C_1206
SM/C_1210_GRM
SM/C_0805
SM/C_1206
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
DIODE_D2PAK
SOD123
SMB/DO214
SOD523
SM/DO213AC
VIA\2P
ED5052
ED5052
ED5052
PG0006
SDIP0302
DPAKFET
SM/SOT223_BCEC
SM/R_0805
SM/R_1206
SM/R_1206
SM/R_1210_MCR
SM/R_0805
SM/R_1206
SM/R_0805
SM/R_1206
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_1206
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_1206
SM/R_0805
PA0500
P8208T
PE-68386
MSOP10
SOT23_5PIN
SOT23_5PIN
SO-8
CBRHD-02
21
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SC4808C
POWER MANAGEMENT
Evaluation Board Gerber Plots
Board Layout Assembly Top
Board Layout Assembly Bottom
Board Layout Top
Board Layout Bottom
 2006 Semtech Corp.
22
www.semtech.com
SC4808C
POWER MANAGEMENT
Evaluation Board Gerber Plots
Board Layout INNER1
 2006 Semtech Corp.
Board Layout INNER2
23
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SC4808C
POWER MANAGEMENT
Outline Drawing - MSOP-10
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
e
A
DIM
D
2X E/2
ccc C
2X N/2 TIPS
E
E1
PIN 1
INDICATOR
.043
.000
.006
.030
.037
.007
.011
.003
.009
.114 .118 .122
.114 .118 .122
.193 BSC
.020 BSC
.016 .024 .032
(.037)
10
8°
0°
.004
.003
.010
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
N
12
B
1.10
0.00
0.15
0.75
0.95
0.17
0.27
0.08
0.23
2.90 3.00 3.10
2.90 3.00 3.10
4.90 BSC
0.50 BSC
0.40 0.60 0.80
(.95)
10
0°
8°
0.10
0.08
0.25
D
aaa C
SEATING
PLANE
A2
H
A
bxN
bbb
c
GAGE
PLANE
A1
C
C A-B D
0.25
L
(L1)
DETAIL
SEE DETAIL
SIDE VIEW
01
A
A
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-187, VARIATION BA.
Land Pattern - MSOP-10
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.161)
.098
.020
.011
.063
.224
(4.10)
2.50
0.50
0.30
1.60
5.70
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
 2006 Semtech Corp.
24
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