SC4810B/E High Performance Current Mode PWM Controller with Complementary Output, Programmable Delay POWER MANAGEMENT Description Features The SC4810B/E is a 16 pin BICMOS primary side PWM controller for use in Isolated DC-DC and off-line switching power supplies. It is a highly integrated solution, requiring few external components. It features a high frequency of operation, accurately programmable maximum duty cycle, current mode control, line voltage monitoring, supply UVLO, low start-up current, and programmable soft start with user accessible reference. It operates in a fixed frequency, highly desirable for Telecom applications. The output for switch is complementary to each other with programmable delay between each transition. The active technique allows single ended converters beyond 50% duty cycle and greater flux swing for the power transformer while reducing voltage stresses on the switches. The separate sync pin simplifies synchronization to an external clock. Feeding the oscillator of one device to the sync of another forces biphase operation which reduces input ripple and filter size. Operation to 1MHz Accurate programmable maximum duty cycle Line voltage monitoring External frequency synchronization Bi-phase mode of operation for low ripple Independent programmable delays Hiccup mode current limit Under 250µA start-up current Programmable maximum volt-second clamp Accessible reference voltage VDD undervoltage lockout -40°C to 105°C operating temperature 16 lead TSSOP or MLPQ lead free packages. Both fully WEEE and RoHS compliant Applications Telecom equipment and power supplies Networking power supplies Power over LAN applications Industrial power supplies Isolated power supplies VoIP phones The SC4810B/E has a turn-on voltage threshold of 7V. In the SC4810B, OUT2 is inverted to drive the N-MOSFET. In the SC4810E, OUT2 is non-inverted to drive the P-MOSFET. These devices are available in a TSSOP-16 or MLPQ-16 lead package. Typical Application Circuit D1 R1 T1 D3 C1 D2 L1 Vout Q1 C2 D4 +48V C3 C4 R2 C5 C6 C7 U1 SC1302A R4 C8 5 R12 7 R17 RCT VDD SC4810 DMAX CS FB DELAY 1 VREF DELAY 2 SS R18 R19 12 Q4 OUT1 GND R14 8 OUT2 SY NC 13 2 7 4 5 R9 Q3 15 10 R11 U3 C11 11 R13 5 C12 9 1 6 16 C15 2 R8 R15 C14 7 4 U2 3 R10 RAMP PGND 3 1 2 6 LUVLO C10 C13 R7 R6 8 C9 D5 R16 U4 SC431L 14 R5 Q2 T2 6 1 R3 R20 R21 R22 R23 Revision: July 27, 2006 C16 1 www.semtech.com SC4810B/E POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Parameter Symbol Maximum Units Supply Voltage V DD 19 V Supply Current IDD 25 mA VLUVLO 10 V -0.3V to VREF + 0.3V V IREF 15 mA Current LUVLO ILUVLO -1 mA Storage Temperature Range TSTG -65 to +150 °C Junction Temperature Range TJ -40 to +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C Peak IR Reflow Temperature 20 - 40 Sec. TPKG 260 °C LUVLO SS, DMAX, RCT, FB, CS, RAMP, SYNC Current VREF Electrical Characteristics Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75kΩ, TA = TJ = -40ºC to 105ºC Parameter Test Conditions Min Typ Max Unit 15 V Supply Section Supply Voltage IDD IDD Shutdown VDD = 15V, NO LOAD 3.5 4.5 mA S S = 0V 100 250 µA Ramp Section Ramp Clamp Threshold Voltage 3 V UVLO Section (B/E version) Start Threshold 8 Hysteresis 2006 Semtech Corp. 8.4 2 2 8.8 V V www.semtech.com SC4810B/E POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75kΩ, TA = TJ = -40ºC to 105ºC Parameter Test Conditions Min Typ Max Unit 0 - 5mA 4.85 5 5.15 V 2.91 3 3.09 V VREF Section VREF (B/E version) Line Under Voltage Lockout Start Threshold Hysteresis Input Bias Current(1) LUVLO = 3.2V 150 mV -100 nA -200 nA 75 ns Comparator Section CS Input Current(1) PWM to OUT Propagation Delay (No Load)(1) Current Limit Section Current Limit Threshold 590 ILIM to OUT Propagation Delay(1) 625 660 75 mV ns Soft Start Section ISS V S S = 0V Shutdown Threshold -2.5 -5 -7.5 500 µA mV Oscillator Section Frequency Range 50 (2) 1100 kHz RCT Peak Voltage 3.00 V RCT Valley Voltage 0.05 V Maximum Duty Cycle DMAX = 2.8V, OUT1 85 % Maximum Duty Cycle DMAX = 1.25V, OUT1 29 % Frequency 380 420 460 kHz Sync/CLOCK Clock SYNC Threshold Minimum Sync Input Pulse Width(1) 2006 Semtech Corp. Positive Edge Triggered FSYNC > Fosc 3 2 V 50 ns www.semtech.com SC4810B/E POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75kΩ, TA = TJ = -40ºC to 105ºC Parameter Test Conditions Min Typ Max Unit 500 mV Output Section (OUT1 and OUT2) Output VSAT Low IOUT = 5mA sinking Output VSAT High IOUT = 5mA sourcing VREF - 0.6 V Rise Time(1) COUT = 20pF 10 ns Fall Time(1) COUT = 20pF 10 ns OUT1 Fall to OUT2 Rise (SC4810B) 120 ns OUT2 Fall to OUT1 Rise (SC4810B) 140 ns OUT1 Fall to OUT2 Fall (SC4810E) 120 ns OUT2 Rise to OUT1 Rise (SC4810E) 140 ns Program Delay Section Notes: (1) Guaranteed by design. (2) Guaranteed by characterization. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required. 2006 Semtech Corp. 4 www.semtech.com SC4810B/E POWER MANAGEMENT Pin Configurations Ordering Information Part Number(2) TOP VIEW SC4810BITSTRT VDD 1 16 VREF LUVLO 2 15 OUT1 SYNC 3 14 PGND RCT 4 13 OUT2 DMAX 5 12 GND RAMP 6 11 FB DELAY 1 7 10 CS DELAY 2 8 9 SS SC4810EITSTRT SC4810BIMLTRT SC4810EIMLTRT Package(1) Temp. Range (TJ) TSSOP-16 -40°C to 105°C MLPQ-16 Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for TSSOP and 3000 parts for MLP package. (2) Lead free product. This product is fully WEEE and RoHS compliant. (16 Pin TSSOP ) TOP VIEW (16 Pin MLPQ) 2006 Semtech Corp. 5 www.semtech.com SC4810B/E POWER MANAGEMENT Pin Descriptions Pin # TSSOP Pin # MLPQ Pin Name Pin Function 1 15 VD D The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1µF ceramic capacitor. 2 16 LUVLO Line undervoltage lock out pin. An external resistive divider will program the undervoltage lock out level. During the LUVLO, the Driver OUT1 is disabled and the softstart is reset. OUT2 continues with a fixed on time of DELAY 1 + DELAY2 approximately. 3 1 SYNC SYNC is a positive edge triggered input with a threshold set to 2.1V. In the Bi-Phase operation mode the SYNC pin should be connected to the CT (Timing Capacitor) of the second controller. This will force a out of phase operation. In a single controller operation, SYNC could be grounded or connected to an external synchronization clock with a frequency higher than the on-board oscillator frequency. The external OSC frequency should be 30% greater for guaranteed SYNC operation. 4 2 RCT The oscillator frequency is configured by connecting resistor RT from VREF to RCT and capacitor CT from RCT to ground. Using the equation below values for RT and CT can be selected to provide the desired OUT frequency. F= where VP-K = RCT peak voltage 1 V − (RT + 1k ) • CT • ln 1 − P−K VREF 5 3 DMAX Duty cycle up to 95% can be programmed via R18 and R12 (the resistor divider from Vref in the Application Circuit). When DMAX pin is taken above 3V, 100% duty cycle is achieved. 6 4 RAMP A resistor from the RAMP to the input voltage and a capacitor from the RAMP to GND forms the ramp signal of maximum allowable volt-second product. The RAMP is discharged to GND when OUT1 is low and allowed to charge when OUT1 is high. A volt-second comparator compares the ramp signal to 3V to limit the maximum allowable volt-second product: Volt-second product clamp = 3 • Rramp • Cramp. 7 5 DELAY 1 A resistor from these pins to GND programs the non-overlap delay time between OUT1 and OUT2. 8 6 DELAY 2 A resistor from these pins to GND programs the non-overlap delay time between OUT2 and OUT1. 2006 Semtech Corp. 6 www.semtech.com SC4810B/E POWER MANAGEMENT Pin Descriptions (Cont.) Pin # TSSOP Pin # MLPQ Pin Name Pin Function 9 7 SS This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 5µA current source. Under normal soft start SS is discharged to less than 0.65V and then ramps positive to 1V during which time the OUT1 is held low. As SS charges from 1V to 2.5V, soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 4V (A and D) or 5V (B, C and E) voltage reference also goes low and IDD = 100µA. 10 8 CS Current sense input is provided via the CS pin. The current sense input from a sense resistor provides current feedback to the PWM comparator and current limit signal to terminate the PWM pulse. When a pulse peak voltage provided at this pin exceeds 600mV, a soft-restart sequence will follow. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal PNP transistor. 11 9 FB This pin is used to generate a reset signal when compared to CS for the PWM comparator with an offset voltage of 600mV and 1/2 attenuation. The feedback analog signal from the output of an error amplifier or an opto-coupler will be connected to this pin to provide regulation. 12 10 GND Signal ground for all functions. 13 11 OUT2 This pin is the logic level drive output to the external MOSFET driver circuit (similar to SC1302) for the complementary switch. 14 12 PGND Ground connection for the gate drivers. Connect PGND and GND at a single point. 15 13 OUT1 This pin is the logic level drive output to the external MOSFET driver circuit (similar to SC1302) for the main switch. 16 14 VREF The 5V reference output. This reference is buffered and is available on the VREF pin. VREF should be bypassed with a 0.47 - 1.0µF ceramic capacitor. N/A 2006 Semtech Corp. THERMAL Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not PAD connected internally. 7 www.semtech.com SC4810B/E POWER MANAGEMENT Block Diagram 2006 Semtech Corp. 8 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information Introduction Circuit Description The SC4810B/E is a 16 pin BICMOS peak current mode The schematic of the active clamp forward converter is controlled PWM controller for isolated DC-DC and off- illustrated in Figure. 1 below. T4 is the power transformer. line switching power supplies. It features a high switching M17 is the N-channel main switching MOSFET and M15 frequency of operation, programmable limits for both is the auxiliary N-channel MOSFET. C35 is the reset power transformer voltage-second product and maximum capacitor for resetting the power transformer’s core. M14 PWM duty cycle, line under-voltage lockout, auxiliary switch and M16 construct the synchronous rectification circuit. activation complementary to main power switch drive, L2 and C32 and C33 construct the low-pass output programmable leading-edge delay time between filtering circuit. T6 is the current sensing transformer. R62 activation of each switch, multiple protection features is the reset resistor for resetting the magnetic core of with programmable cycle -by-cycle current limit and hiccup the current sensing transformer. D18 is the rectifying mode over-current protection plus soft-restart. It diode. R63 is the current sensing resistor. R60 and C41 operates in a fixed frequency programmed by external construct the low-pass filtering circuit for the sensed components. The separate sync pin simplifies current signal. The primary bias circuit consists of R55, synchronization to an external clock. Feeding the oscillator R58, D17, Q8, C40, C31, D14 and R51. R55 and R58 of one device to the sync of another forces biphase construct a voltage divider, which limits the bias voltage operation which reduces input ripple and input and output to 6.9V until the line voltage reach 36V. D17 is a zener filter size. diode that limits the bias voltage to under 8V. R51, D14 The SC4810 can be applied in an active clamp forward and C31 construct the peak charge circuit. The peak topology with the input voltage ranging from 36V to 72V. charge circuit will provide bias to the PWM IC U9 (SC4810) This topology allows the converter to achieve an efficiency and the driver U8 (SC1302A) after the converter starts of 92.4% at normal input voltage of 48V. Figure 1: Active Clamp Forward Converter T4 1 5.11 6 1.3uH L2 48V C34 1u,100V 3300pF R53 C33 680uF 4 3 2 1 1 M15 2 Si4488DY 3 4 100uF C32 8 9 2 8 7 6 5 Si4842DY 11 7 5.11 0.1uF C35 3.3V/30A M14 R51 C31 1N4148WS D13 R50 10 5 6 7 8 D14 1N4148WS 4 10K 10K R52 D15 1N4148WS R54 C36 0.1uF 6 30K Q8 T5 PE68386 FZT458 D17 open M16 Si4842DY 1 2 3 4 Q7 FZT458 R56 10K R57 0.1uF C38 3 1 C37 0.1uF R58 8K 8 7 6 5 4 20K R55 10 1N4148WS D18 P8208T 8 T6 1 R59 R61 1.1M D19 1N5819HW 7 3 R62 10K R63 6.8 6 3 RAMP 1 R66 OUT1 7 DMAX DELAY1 VREF DELAY2 SS Q9 FMMT718 R77 18K R78 5.6K FB GND 8 SC4810 R79 100K 12 100K R75 C49 180pF 50 13 4 5 15 D20 1N5819HW R69 10K C45 R72 5.11K R73 11 3.01K U10 16 9 R70 open open 3 10 8 CS PGND 5 R74 4.3K RCT R67 R68 4 3 2 1 OUT2 SYNC open 1K 14 4 open 7 R71 10K 330pF C41 C42 Si4488DY U8 2 U9 VDD C44 220pF 0.1uF R60 5 6 7 8 6 1 R65 100K 2 C43 100pF LUVLO R64 C39 D16 open M17 SC1302A 165k 5.11K 1K C40 10uF U11 MOC207 0.1uF 6 5 C46 open 0.01uF SC431 1 C48 C47 R76 3.01K 2 1000pF C50 7 R80 1.47K R81 4.7K R82 5.11K 2006 Semtech Corp. C51 0.01uF 9 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) up so that the total power loss is less. D19, R59, C37, T5, C36, D15 and R53 construct the driving circuit for the auxiliary reset switch M15. The secondary side bias circuit composed of R50, D13 and C38 is regulated to about 7.5V via a linear regulator composed of R57, Q7 D16 and C39. The feedback of the converter is composed of U10 (SC431), U11, R73, C47, C45, R72, R76, R70 and C46. A self-driven configuration was adopted on the secondary side for driving the synchronous rectification FETs. One extra winding (Pin8~Pin9) was added at the bottom side of the power transformer’s secondary side to drive the freewheeling FET. The forward FET was driven directly from the top of the power winding. Primary side auxiliary winding was used to generate primary side bias to improve the converter’s efficiency. SC4810 is the PWM controller which processes the voltage feedback plus current signal and generates driving signals to drive the main switch and auxiliary reset switch. SC1302A is a dual driver IC which is capable of sourcing 3A peak current. To obtain the best performance, SC1302A is adopted to drive M17 and M15 in the Semtech application circuits. SC4810 features dual complementary driving signals. And SC4810 also provides adjustable leading-edge delay time for the driving signals, which helps to achieve zero-voltage switching in active clamp forward converter. R75 and R79 are the two resistors available to adjust the delay for the complementary driving. C50 is the soft-start capacitor. R61 and R65 construct the voltage divider for the line under voltage lock out protection. R64 and C44 construct the circuit for the programmable power transformer voltage-second production protection limits. This special protection function provide the voltage-second balance for the power transformer under different input line conditions. R78 and R74 also provide an extra maximum duty cycle protection for the power converter. The final configuration of the power transformer is illustrated as Fig. 2. 2 6T(PRI) 4 1 2T(PRI AUX) 6 1T(SEC) 10 9 1T(SEC AUX) 8 1T(SEC) 7 Fig.2 Illustration of the power transformer PA0944G (PUSLE ENGINEERING) Power MOSFET Selection The selection of the switching power MOSFET is based on the peak & RMS current rating, the total gate charge, Rds and drain to source voltage rating. In this application, SI4842 was chosen for the secondary side synchronous rectification MOSFET. And SI4488 was chosen for the primary side main switching and reset MOSFET. The clock signal is generated by C49 and R77. When VDD of SC4810 hits the threshold voltage, VREF jumps up to 5.0V. VREF charges C49 via R77. C49 will be discharged via an internal FET whenever the voltage on C49 reaches 3.0V. The selection of C49 and R77 is described in the “Set Clock Frequency” section on the following page. Q9 works as a buffer between the clock signal and the slope compensation signal to minimize the interference on the system clock signal. R80 is a pull-up resistor tied to VREF. Since SYNC function is not utilized, SYNC pin is grounded via R71. Output Filter Design The output filtering circuit consists of the output inductor and output capacitors. The design of the output capacitor usually depends on the specification of the requirement of the output ripple. Given the worst case output ripple requirement and peak to peak output current ripple plus the duty ratio under the different line and load condition, output capacitance is calculated to meet the output ripple requirement. After all, ESR and ESL of the output capacitor under certain switching frequency should also be considered during the calculation. The value of the output inductance would affect the peak to peak value of the output current, which would also influence the Power Transformer Design A power transformer with the turns ratio of 6 to 1 was designed for this application. With the turns ratio of 6:1, the duty ratio under different input line and load conditions were calculated to verify feasibility. 2006 Semtech Corp. 11 10 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) output voltage ripple. The designer needs to take the output inductance and output capacitance and the ESL and ESR of the output capacitor into consideration during the design. VRCT VPK 3V 0V For this application, one Panasonic power choke output inductor was selected and three 6.3V, 100uF TDK ceramic capacitors were adopted in the design. As illustrated, the capacitor C is charged via the resistor R from VREF. Whenever the voltage on the RCT pin reaches 3V, the capacitor C will be discharged through an internal FET shorted to ground. When the clock signal circuit is connected as in Fig.3, the frequency of the clock signal is defined, as in equation 2. Selection of the Current Sensing Resistor The selection of the current sensing resistor is based on the over-current protection triggering point. SC4810 employs a Hiccup mode over-current protection with an overcurrent threshold of 600mV. A voltage signal above 600mV on the CS pin will trigger hiccup mode overcurrent protection. Suppose the over-current protection setpoint is set to be Iov. The threshold voltage of SC4810 is Vthreshold. The turns ratio of the power transformer is Ns/Np. The turns ratio of the current sensing transformer is Ncs:1. Then the Rsense would be calculated as: R sense = t Fig.4 Voltage Waveform on RCT Pin F= 1 V − (RT + 1k ) • CT • ln 1 − P−K VREF ........( 2) V REF is the reference voltage of the SC4810, 4V for SC4810A/D and 5V for SC4810B/C/E. In this application, to get 600kHz, C = 180pF, (R + 1k) = 10k ohms and VP-K = 3V. VThreshold × NP × NCS ......(1) IOV × NS Set Clock Frequency Maximum Duty Ratio Limit The SC4810 uses a pair of resistors and capacitors to generate a triangle signal as the clock signal, as illustrated in Fig. 3. SC4810 features maximum duty ratio limitation for extra protection. The maximum duty ratio is determined by the voltage on DMAX pin. As illustrated as in Fig. 5, VDMAX will be compared with VRCT and DMAX is determined by the comparison of the two signals. VRCT RCT VREF C R Fig. 3 Configuration for Clock Signal The voltage waveform on the RCT pin is illustrated as in Fig. 4. 2006 Semtech Corp. 11 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) Voltage waveform on RAMP pin Clock Signal of SC4810 VRAMP VRCT 3V 3V VDMAX 0V t 0V t OUT1 Maximum OUT1 of SC4810 DMAX 0V t 0V Fig. 5 Illustration for DMAX Fig. 6 Illustration of the programmable limits for power transformer voltage-second product t In this application, VDMAX was designed to be 2.8V. So the DMAX = 90%. VIN Limit for Power Transformer Voltage Second Product R The SC4810 also features programmable limits for power transformer voltage-second product. As illustrated in Fig. 6 and Fig. 7 RAMP pin is charged up via a resistor R from the input line voltage. The capacitor C will be discharged via an internal FET shorted to ground and the output OUT1 will be pulled low whenever the voltage on RAMP pin hits 3V. By adjusting the values of the resistor R and the value of the capacitor C, the maximum voltage-second product imposed on the power transformer is preset. The maximum voltage-second product limitation helps prevent saturation of the power transformer. 2006 Semtech Corp. RAMP C Fig. 7 Illustration for Maximum voltagesecond product on the power transformer The selection of the R and C should consider the maximum voltage rating of the main switching FET. In this application, the voltage rating of SI4488 is 150V. Since Vin*D/(1-D) = 150V, D = 0.8 for low line 36V. So to get 80% at low line, R = 165kOhms and C = 220pF were selected using volt-second product equation: 3 • Ramp • Cramp. 12 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) VDD and LUVLO SC4810 features three different input turn-on voltage thresholds, as specified in the Electrical Characteristics on page 2. V starts to regulate when the supply voltage on the VDD pin is above the turn-on voltage threshold. V drops to ground when VDD is lower than the turn-on threshold minus the hysteresis value. The soft start cap remains grounded as long as LUVLO is below the threshold voltage 3V. The soft start cap will be charged up through an internal 5uA current source when LUVLO is above the threshold voltage. REF REF Soft Start The soft-start function is implemented by charging the soft-start cap through an internal 5uA current source. Under normal soft-start, the SS pin is discharged below 0.65V and ramps up to 1V, during which time the output driving signals OUT1 and OUT2 are held low. During the time when the SS pin is charged from 1V to 2.5V, softstart is implemented by an increasing output duty ratio. The duty ratio is completely under the control of the feedback after the SS pin is above 2.5V. When the SS pin is pulled down below 0.5V, OUT1 and OUT2 will be held low and the VREF pin will be grounded via an internal FET. Complementary Driving with Programmable Delays The SC4810 features dual driving signals to drive two power switches complementarily. This feature makes the SC4810 suitable for a variety of applications in which dual complimentary driving signals are needed. The SC4810 even provides programmable driving delay as an extra feature for applications such as active-clamp forward topology. The users can program the driving delay by adjusting the resistors tied to pin DELAY1 and pin DELAY2 respectively to achieve the optimum delay for each output. The delay of OUT1 is controlled by the resistor tied to pin DELAY1 and the delay of OUT2 is controlled by the resistor tied to pin DELAY2. For illustration, see Fig. 8. 2006 Semtech Corp. Over Current Protection The SC4810 provides Hiccup mode over-current protection when the sensed current signals are beyond 0.6V. When the hiccup mode over-current protection is triggered, the soft-start cap will be discharged immediately by an internal grounded FET. When the softstart pin SS is pulled down below 1V, OUT1 and OUT2 will be disabled, and a soft re-start sequence will follow. SC4810 can also be configured to implement cycle-bycycle over-current limit. As illustrated in Fig. 9, cycle-bycycle over-current limitation can be achieved by adjusting the values of R1 and R2 to limit the voltage of FB pin to less than the threshold voltage (0.6Volt) of the hiccup over-current protection, using equations (3) and (4). 13 www.semtech.com SC4810B/E POWER MANAGEMENT Application Information (Cont.) guaranteed synchronization. SYNC pin should be grounded if synchronization is unused. (The patent for the synchronization scheme is pending). VREF VBias The synchronous function is illustrated as in Fig. 10. R3 R1 Vout FB Clock Signal of the Master SC4810 VRCT R4 3V R2 R5 2.1V SC431 GND 0V t Fig.9 Cycle-by-cycle over-current limitation OUT1 of the Master SC4810 VFB = 2 • VCS + 1.3 V........( 3) VFB = VREF • R2 ........( 4) R1 + R 2 0V t Synchronization SC4810 features a special synchronization function which is leading-edge triggered with a threshold set to 2.1V. Applications like multi-phase interleaving can be achieved using the SYNC pin. When the SYNC pin is connected to the RCT pin of the master SC4810, the outputs of the two SC4810’s will be out of phase. The frequency of the master SC4810 clock signal should be at least 30% faster than that of the slave SC4810 for the 2006 Semtech Corp. OUT1 of the Slave SC4810 0V t Fig. 10 Illustration for Synchronization 14 www.semtech.com SC4810B/E POWER MANAGEMENT Applications Information (Cont.) PCB Layout Guidelines PCB layout is very critical, and the following should be used to insure proper operation of the SC4810. High switching currents are present in applications and their effect on ground plane must be understood and minimized. 6) The feed back connection between the error amplifier and the FB pin should be kept as short as possible, and the GND connections should be to the quiet GND used for the SC4810. 7) If an opto-coupler is used for isolation, quiet primary and secondary ground planes should be used. The same precautions should be followed for the primary GND plane as mentioned in item 5. For the secondary GND plane, the GND plane method mentioned in item 4 should be followed. 8) All the noise sensitive components such as VDD bypass capacitor, RCT oscillator resistor/capacitor network, DMAX resistive divider, VREF by pass capacitor, delay setting resistors, current sensing circuitry and feedback circuitry should be connected as close as possible to the SC4810. The GND return should be connected to the quiet SC4810 GND plane. 9) The connection from the OUT of the SC4810 should be minimized to avoid any stray inductance. If the layout can not be optimized due to constraints, a small Schottky diode may be connected from the OUT pin to the ground directly at the IC. This will clamp excessive negative voltages at the IC. 10) If the SYNC function is not used, the SYNC pin should be grounded at the SC4810 GND to avoid noise pick up. 1) The high power parts of the circuit should be placed on a board first. A ground plane should be used. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and the main switch FET ground. 2) The loop formed by the Input Capacitor(s) (Cin), the main transformer and the main switch FET must be kept as small as possible. This loop contains all the high fast transient switching current. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3) The connection between FETs and the main transformer should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. 4) The output capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only. Connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) A 0.1uF to 1uF ceramic capacitor should be directly connected between VDD and PGND and a 1uF to 4.7uF ceramic capacitor between VREF and PGND. The SC4810 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin and the main switch FET loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the VDD supply capacitor(s). Under no circumstances should GND be returned to a ground inside the Cin and the main switch FET loop. This can be achieved by making a star connection between the quiet GND planes that the SC4810 will be connected to and the noisy high current GND planes connected to the FETs. 2006 Semtech Corp. 15 www.semtech.com Vin=48V C10 1u,100V TP11 C12 1u,100V R38 1.47K C25 220pF Q6 FMMT718 R30 10K C22 220pF R23 160K R61 200K R31 7.5K R35 10K D20 MMSZ4697(10V) C11 1u,100V TP12 R36 7.5K R37 100K C21 100pF R57 5.1 SY NC RAMP SC4810 0(short) TP13 10K 9 16 11 10 15 13 C20 1uF 0.1uF C50 SS VREF FB CS OUT1 OUT2 U3 C19 1uF C27 R33 100K DELAY 2 DELAY 1 DMAX RCT C53 1uF C16 47uF/16V R43 8 7 5 4 3 6 R24 100K R21 1.1M 1N4148WS D21 Q10 FMMT493 R13 open C13 22nF/100V 1 8 7 6 5 C15 0.1uF U2 SC1302A C24 1uF 4 2 R56 5.1 D7 1N4148WS D6 1N4148WS 5 TP10 7 10 C18 0.1uF R22 TP2 Q2 FMMT718 TP8 open R15 8 9 11 7 7 R28 10K 8 7 6 5 R19 10K M10Si4842DY 1 2 3 4 8 7 6 5 1 2 3 4 1.5K R44 R60 open C4 0.1uF R2 5.1K 5 6 7 8 5.11K R3 M2 Open MMSZ4702(15V) D3 R54 5.1 M1 Open C52 0.1uF U4 SC431 4 3 2 1 U1 MOCD207 C17 180pF R17 1K R63 10K R20 8.2(16//16) R18 1K M7 SI2308 M14 SI2308 M9 SI2308 M13 Si4488DY TP7 R8 10K TP4 C3 0.1uF M8 Si4842DY 1 2 3 4 8 7 6 5 M6 Open M12 Open 3 P8208T 8 T3 1 4 2 6 1 T1 PA0944G 10 M11 Open R42 2.4K Q5 FMMT718 D10 1N4148WS D9 1N5819HW TP9 T2 PE68386 10K D11 1N5819HW R10 1 M5 2 Si4488DY 3 4 C5 0.1uF 5.11 D2 1N4148WS D1 TP3 R29 6.34K R25 5.1K open TP6 U6 SC431 open R14 R16 1K C14 R9 10K C8 100uF 10Vbias C7 100uF 10Vbias R34 1K C26 47nF R62 4.75K C23 open TP14 C6 680uF L1 M3 Si4842DY M4 Si4842DY 1.3uH D4 MMSZ4698(11V) C2 0.1uF Q1 FMMT618 5 6 7 8 4 3 2 1 1N4148WS 5 6 7 8 4 3 2 1 D5 1N4148WS 6 D8 MMSZ4698(11V) Q3 FZT853 6 1 4 1 5 6 7 8 4 3 2 1 R1 5 6 7 8 4 3 2 1 R12 5.1K 2 LUVLO GND 12 VDD PGND 14 8 5 6 7 8 4 3 2 1 3 3 5 6 7 8 16 4 3 2 1 5 6 7 8 2006 Semtech Corp. 4 3 2 1 C1 2.2nF/630V 15.8K R40 R32 5.1K R52 51 C51 open R50 open C9 100uF TP5 Vout=3.3V/20A SC4810B/E POWER MANAGEMENT SC4810B Evaluation Board - Schematic www.semtech.com SC4810B/E POWER MANAGEMENT SC4810B Evaluation Board - BOM Item Quantity Reference Part Package Manufacturer P/N 1 1 2.2nF/630V SM0805 TDK C3216X7R2J222K 2 11 C1 C2,C3,C4,C5, C15,C18,C19, C20,C50,C52,C53 0.1uF SM0805 3 1 C6 680uF SM/CT_7343_12 Sanyo 4TPB680M 4 3 C7,C8,C9 100uF SM/C_1812 TDK C4532X5ROJ107MT 5 3 C10,C11,C12 1u,100V SM/C_1210 TDK C3225X7R2A105K 6 1 C13 22nF/100V SM1206 TDK C3216X7R2J223M 8 1 C16 47uF/16V SM/CT_7343 Sanyo 16TQC47M 9 1 C17 180pF SM0805 10 1 C21 100pF SM0805 11 2 C25,C22 220pF SM0805 12 1 C24 1uF SM0805 13 1 C26 47nF SM0805 14 1 0(short) SM0805 15 7 C27 D1,D2,D5, D6,D7,D10,D21 1N4148WS SOD123 Vishay 1N4148WS 16 1 D3 MMSZ4702(15V) SOD123 On Semi MMSZ4702T1 17 2 D4,D8 MMSZ4698(11V) SOD123 On Semi MMSZ4698T1 18 2 D9,D11 SL04 SOD123 Vishay SL04 19 1 D20 MMSZ4697(10V) SOD123 On Semi MMSZ4697T1 20 1 L1 1.3uH PCC-S1 Panasonic ETQPAF1R3EFA 22 4 M3,M4,M8,M10 Si4842DY SO-8 Vishay Si4842DY 23 2 M5,M13 Si4488DY SO-8 Vishay Si4488DY 24 3 M7,M9,M14 SI2308 SOT-23 Vishay SI2308 25 1 Q1 FMMT618 SOT-23 Zetex FMMT618 26 3 Q2,Q5,Q6 FMMT718 SOT-23 Zetex FMMT718 27 1 Q3 FZT853 SM/SOT223_BCEC Zetex FZT853 28 1 Q10 FMMT493 SOT-23 Zetex FMMT493 29 1 R1 5.11 SM0805 30 4 R2,R12,R25,R32 5.1K SM0805 31 1 5.11K SM0805 32 9 R3 R8,R9,R10,R19, R28,R30,R35,R43,R63 10K SM0805 33 1 R13 open SM1206 34 1 R16 1K RC0805 35 3 R17,R18,R34 1K SM0805 2006 Semtech Corp. 17 www.semtech.com SC4810B/E POWER MANAGEMENT SC4810B Evaluation Board - BOM (Cont.) 36 1 R20 8.2 SM0805 37 1 R21 1.1M SM0805 38 1 R22 10 SM0805 39 1 R23 160K SM0805 40 1 R24 100K SM0805 41 1 R29 6.34K SM0805 42 2 R31,R36 7.5K SM0805 43 2 R33,R37 100K SM0805 44 1 R38 1.47K SM0805 45 1 R40 15.8K SM0805 46 1 R42 2.4K SM0805 47 1 R44 1.5K SM0805 48 1 R52 51 SM0805 49 3 R54,R56,R57 5.1 SM0805 50 1 R61 200K SM0805 51 1 R62 4.75K SM0805 53 1 T1 PA0944G PA0646 Pulse PA0944G 54 1 T2 PE68386 PE68386 Pulse PE68386 55 1 T3 P8208T P8208 Pulse P8208T 56 1 U1 MOCD207 SO-8 Fairchild MOCD207 57 1 U2 SC1302A MSOP-8 Semtech SC1302A 58 1 U3 SC4810 TSSOP16 Semtech SC4810 59 2 U4,U6 SC431 SOT-23 Semtech SC431 2006 Semtech Corp. 18 www.semtech.com Vin=48V C10 1u,100V TP11 C12 1u,100V R38 1.47K C25 220pF Q6 FMMT718 R30 10K C22 220pF R23 160K R61 200K R31 7.5K R35 10K D20 MMSZ4697(10V) C11 1u,100V TP12 R36 7.5K R37 80.6K C21 100pF R57 5.1 SYNC RAMP SC4810 0(short) TP13 10K 9 16 11 10 15 13 0.1uF C50 SS VREF FB CS OUT1 OUT2 U3 C19 1uF C20 1uF C16 47uF/16V C27 R33 80.6K DELAY2 DELAY1 DMAX RCT C53 1uF R13 open 1 R43 8 7 5 4 3 6 R24 100K R21 1.1M 1N4148WS D21 Q10 FMMT493 D8 MMSZ4698(11V) Q3 FZT853 2 LUVLO GND 12 VDD PGND 14 1 2 3 4 U2 SC1302A 1uF C24 4 2 R56 5.1 1N5819HW D6 R10 10K C5 0.1uF 5 D9 1N5819HW TP9 TP2 TP8 open R15 8 9 11 7 M12 Open 7 3 P8208T 8 T3 1 4 2 6 1 T1 PA0944G 10 R28 10K R42 2.4K Q5 FMMT718 D10 1N4148WS 8 7 6 5 C13 22nF/100V D11 1N5819HW TP10 7 R22 2 C18 0.1uF M5 IRF6216 5.11 R1 8 7 6 5 8 7 6 5 8 7 6 5 1 2 3 4 M13 Si4488DY R19 10K M10Si4842DY 1 2 3 4 M8 Si4842DY 1 2 3 4 M6 Open 1.5K R44 R60 open TP7 R8 10K TP4 C3 0.1uF D2 1N4148WS 5 6 7 8 5.11K R3 M2 Open MMSZ4702(15V) D3 R54 5.1 M1 Open C52 0.1uF U4 SC431 4 3 2 1 U1 MOCD207 C17 180pF R17 1K R63 10K R20 8.2(16//16) R18 1K M7 SI2308 M14SI2308 M9 SI2308 C4 0.1uF R2 5.1K TP3 R29 6.34K R25 5.1K open TP6 U6 SC431 open R14 R16 1K C14 R9 10K C8 100uF 10Vbias C7 100uF 10Vbias R34 1K C26 47nF R62 4.75K C23 open TP14 C6 680uF L1 M3 Si4842DY M4 Si4842DY 1.3uH D4 MMSZ4698(11V) C2 0.1uF Q1 FMMT618 5 6 7 8 4 3 2 1 D1 5 6 7 8 4 3 2 1 1N4148WS 5 6 7 8 4 3 2 1 D5 1N4148WS 6 1 8 5 6 7 8 4 3 2 1 R12 5.1K 3 5 6 7 8 19 4 3 2 1 5 6 7 8 2006 Semtech Corp. 4 3 2 1 C1 2.2nF/630V 15.8K R40 R32 5.1K R52 51 C51 open R50 open C9 100uF TP5 Vout=3.3V/20A SC4810B/E POWER MANAGEMENT SC4810E Evaluation Board - Schematic www.semtech.com SC4810B/E POWER MANAGEMENT SC4810E Evaluation Board - BOM Item 1 Quantity 1 2 10 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 1 3 3 1 1 1 1 2 1 1 1 5 1 2 3 1 1 4 1 3 1 1 1 2 1 1 4 1 33 9 35 1 2006 Semtech Corp. Reference C1 C2,C3,C4,C5,C18, C19,C20,C50,C52,C53 C6 C7,C8,C9 C10,C11,C12 C13 C16 C17 C21 C25,C22 C24 C26 C27 D1,D2,D5,D10,D21 D3 D4,D8 D6,D9,D11 D20 L1 M3,M4,M8,M10 M5 M7,M9,M14 M13 Q1 Q3 Q5,Q6 Q10 R1 R2,R12,R25,R32 R3 R8,R9,R10,R19, R28,R30,R35,R43,R63 R16 Part 2.2nF/630V Package SM0805 0.1uF SM0805 680uF SM/CT_7343 100uF SM/C_1812 1u,100V SM/C_1210 22nF/100V SM1206 47uF/16V SM/CT_7343 180pF SM0805 100pF SM0805 220pF SM0805 1uF SM0805 47nF SM0805 0(short) SM0805 1N4148WS SOD123 MMSZ4702(15V) SOD123 MMSZ4698(11V) SOD123 SL04 SOD123 MMSZ4697(10V) SOD123 1.3uH PCC-S1 Si4842DY SO-8 IRF6216 SO-8 SI2308 SOT-23 Si4488DY SO-8 FMMT618 SOT-23 FZT853 SM/SOT223 FMMT718 SOT-23 FMMT493 SOT-23 5.11 SM0805 5.1K SM0805 5.11K SM0805 10K SM0805 1K SM0805 20 Manufacturer TDK P/N C3216X7R2J222K Sanyo TDK TDK TDK Sanyo 4TPB680M C4532X5ROJ107MT C3225X7R2A105K C3216X7R2J223M 16TQC47M Vishay On Semi On Semi Vishay On Semi Panasonic Vishay I. R. Vishay Vishay Zetex Zetex Zetex Zetex 1N4148WS MMSZ4702T1 MMSZ4698T1 SL04 MMSZ4697T1 ETQPAF1R3EFA Si4842DY IRF6216 SI2308 Si4488DY FMMT618 FZT853 FMMT718 FMMT493 www.semtech.com SC4810B/E POWER MANAGEMENT SC4810E Evaluation Board - BOM 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 54 55 56 57 58 59 3 1 1 1 1 1 1 2 2 1 1 1 1 1 3 1 1 1 1 1 1 1 2 2006 Semtech Corp. R17,R18,R34 R20 R21 R22 R23 R24 R29 R31,R36 R33,R37 R38 R40 R42 R44 R52 R54,R56,57 R61 R62 T1 T3 U1 U2 U3 U4,U6 1K 8.2 1.1M 2 160K 100K 6.34K 7.5K 80.6K 1.47K 15.8K 2.4K 1.5K 51 5.1 200K 4.75K PA0944G P8208T MOCD207 SC1302A SC4810 SC431 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 PA0646 P8208 SO-8 MSOP-8 TSSOP16 SOT-23 21 Pulse Pulse Fairchild Semtech Semtech Semtech PA0944G P8208T MOCD207 SC1302A SC4810 SC431 www.semtech.com SC4810B/E POWER MANAGEMENT Outline Drawing - TSSOP-16 A DIM D e N A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc 2X E/2 E1 E PIN 1 INDICATOR 1 2 3 ccc C 2X N/2 TIPS e/2 B .047 .002 .006 .031 .042 .007 .012 .003 .007 .192 .196 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 16 0° 8° .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 16 0° 8° 0.10 0.10 0.20 D aaa C SEATING PLANE DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX A2 A C H A1 bxN bbb C A-B D c GAGE PLANE 0.25 SIDE VIEW SEE DETAIL L (L1) DETAIL A 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE-H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB. Land Pattern - TSSOP-16 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20 P NOTES: 1. 2006 Semtech Corp. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 22 www.semtech.com SC4810B/E POWER MANAGEMENT Outline Drawing - MLPQ-16, 4 x 4 A DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX D A A1 A2 b D D1 E E1 e L N aaa bbb B PIN 1 INDICATOR (LASER MARK) E A2 A 1.00 0.80 0.05 0.00 (0.20) 0.25 0.30 0.35 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.65 BSC 0.30 0.40 0.50 16 0.08 0.10 SEATING PLANE aaa C A1 .040 .031 .002 .000 (.008) .010 .012 .014 .153 .157 .161 .100 .106 .110 .153 .157 .161 .100 .106 .110 .026 BSC .012 .016 .020 16 .003 .004 C D1 e/2 LxN E/2 E1 2 1 N e D/2 bxN bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 2006 Semtech Corp. 23 www.semtech.com SC4810B/E POWER MANAGEMENT Land Pattern - MLPQ-16, 4 x 4 K DIM 2x (C) H 2x G 2x Z Y X C G H K P X Y Z DIMENSIONS INCHES MILLIMETERS (.156) .122 .106 .106 .026 .016 .033 .189 (3.95) 3.10 2.70 2.70 0.65 0.40 0.85 4.80 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2006 Semtech Corp. 24 www.semtech.com