SC4809A/B/C High Performance Current Mode PWM Controller POWER MANAGEMENT Description Features The SC4809A/B/C is a 10 pin BICMOS primary side current mode controller for use in Isolated DC-DC and off-line switching power supplies. It is a highly integrated solution, requiring few external components. It features a high frequency of operation, accurately programmable maximum duty cycle, current mode control, line voltage monitoring, supply UVLO, low start-up current, and programmable soft start with user accessible reference. It operates in a fixed frequency, highly desirable for Telecom applications. Features a separate sync pin which simplifies synchronization to an external clock. Feeding the oscillator of one device to the sync of another forces biphase operation which reduces input ripple and filter size. Operation to 1MHz Accurate programmable maximum duty cycle Line voltage monitoring External frequency synchronization Bi-phase mode of operation for low ripple Under 100µA start-up current Accessible reference voltage VDD undervoltage lockout -40°C to 105°C operating temperature 10 lead MSOP package. Lead free package available. Fully WEEE and RoHS compliant Applications Telecom equipment and power supplies Networking power supplies Power over LAN applications Industrial power supplies Isolated power supplies The SC4809A/B/C have different threshold and VREF to accommodate a wide variety of applications. These devices are available in the MSOP–10 lead free package. Typical Application Circuit T1 +48V C1 R2 R1 D1 D2 U1 SC4809 R3 SYNC C7 VDD 2 LUVLO OUT 9 1 IN 3 SYNC GND 8 2 GND VREF 10 4 RCT FB 7 5 DMAX SS 6 Vout C8 U2 SC1301 1 3 EN 5 OUT 4 Q2 R13 R12 VCC U3 R9 C9 R4 R6 R5 -- 48V R10 R7 C3 R8 R11 U4 SC4431 R14 Q1 C2 C4 C5 C6 DISABLE Revision: September 21, 2005 1 www.semtech.com SC4809A/B/C POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Supply Voltage V DD 19 V Supply Current IDD 25 mA -0.3V to VREF + 0.3V V IREF 15 mA Current LUVLO ILUVLO -1 mA Storage Temperature Range TSTG -65 to +150 °C Junction Temperature TJ -40 to +150 °C Thermal Resistance θJ A 113 °C/W Lead Temperature (Soldering) 10 Sec. TLEAD +300 °C ESD Rating (Human body model) ESD 2 kV SS, UVLO, DMAX, RCT Current VREF Electrical Characteristics Unless specified: VDD = 12V, CSS =1nF, FOSC = 500kHz, RT = 10K, CT = 100pF, DMAX = 2V, TA = TJ = -40ºC to +105ºC. Parameter Test Conditions Min Typ Max Unit 16 17.5 19 V 1.5 2.5 mA 110 µA 4.5 V 0.3 V 12 V 4 V 6.95 V 0.75 V Supply Section VDD Clamp IDD B version IDD Starting UVLO Section (A version) Start Threshold 4.35 Hysteresis UVLO Section (B version) Start Threshold 11 Hysteresis UVLO Section (C version) Start Threshold 6.55 Hysteresis VREF Section VREF (A version) 0 - 5mA -3% 4 +3% V VREF (B, C version) 0 - 5mA -3% 5 +3% V 2005 Semtech Corp. 2 www.semtech.com SC4809A/B/C POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VDD = 12V, CSS =1nF, FOSC = 500kHz, RT = 10K, CT = 100pF, DMAX = 2V, TA = TJ = -40ºC to +105ºC. Parameter Test Conditions Min Typ Max Unit Start Threshold RA = 61.9k, RB = 10k -3% 3 -3% V Hysteresis RA = 61.9k, RB = 10k 150 LUVLO = 3.2V -100 Output Off -100 Line Under Voltage Lockout Input Bias Current mV -250 nA Comparator Section IFB nA Comparator Threshold (A, B version) 570 600 630 mV Comparator Threshold (C version) 950 1000 1050 mV 75 100 ns -8.0 µA OUT Propagation Delay (No Load) VFB = 0.8V to 1.2V at TR = 10ns Soft Start Section ISS VSS = 0V; -40 °C <Ta +105°C -2 Shutdown Threshold (A, B version) 300 340 mV Shutdown Threshold (C version) 440 500 mV Oscillator Section Frequency range 50 1100 kHz RCT Peak Voltage 3.00 V RCT Valley Voltage 0.05 V 50 ns 90 % 2.1 V Minimum Duty Cycle Pulse Width V FB = 2V Maximum Duty Cycle Sync/CLOCK Clock SYNC Threshold Minimum Sync Input Pulse Width Positive Edge Triggered FSYNC > Fosc 50 ns Output VSAT Low IOUT = 1mA 500 mV Output VSAT High IOUT = 1mA Output Section VREF - 0.5 V Rise Time COUT = 20pF 10 25 ns Fall Time COUT = 20pF 10 25 ns 2005 Semtech Corp. 3 www.semtech.com SC4809A/B/C POWER MANAGEMENT Pin Configuration Ordering Information Part Number Top View Package(1) Temp. Range (TJ) MSOP-10 -40°C to +150°C SC4809AIMSTR SC4809AIMSTRT(2) SC4809BIMSTR SC4809BIMSTRT(2) SC4809CIMSTR SC4809CIMSTRT(2) Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. MSOP-10 2005 Semtech Corp. 4 www.semtech.com SC4809A/B/C POWER MANAGEMENT Pin Descriptions FB: This pin is the summing node for current sense feedback, voltage sense feedback (by optocoupler) and slope compensation. Slope compensation is derived from the rising voltage at the time capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250Ω on-resistance NMOS FET during PWM off -time and offers effective leading edge blanking set by the RC time constant of the feedback resistance from the current sense resistor to the FB input and the high frequency filter capacitor capacitance at this node to GND. DMAX: Duty cycle up to 98% can be programmed via R4 and R5 (the resistor divider from Vref in the Application Circuit). When DMAX pin is taken above 3V, 100% duty cycle is achieved. SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 8µA current source. Under normal soft start SS is discharged to less than 1V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V, soft start is implemented by an increasing output duty cycle. If SS is taken below shutdown threshold, the output driver is inhibited and held low. The user accessible voltage reference also goes low and IDD < 100µA. GND: Reference ground and power ground for all functions. OUT: This pin is the logic level drive output to the external MOSFET driver circuit (similar to SC1301). VDD: The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1µF ceramic capacitor. VREF: The internal 4V (A) / 5V (B & C) reference output. This reference is buffered and is available on the VREF pin. VREF should be bypassed with a 0.47 - 1.0µF ceramic capacitor. LUVLO: Line undervoltage lock out pin. An external resistive divider will program the undervoltage lock out level. During the LUVLO, the Driver outputs are disabled and the softstart is reset. RCT: The oscillator frequency is configured by connecting resistor RT from VREF to RCT and capacitor CT from RCT to ground. Using the equation below values for RT and CT can be selected to provide the desired OUT frequency. F= SYNC: SYNC is a positive edge triggered input with a threshold set to 2.1V. In the Bi-Phase operation mode the SYNC pin should be connected to the CT (Timing Capacitor) of the second controller. This will force a out of phase operation. In a single controller operation, SYNC could be grounded or connected to an external synchronization clock with a frequency higher than the on-board oscillator frequency. The external OSC frequency should be 30% greater for guaranteed SYNC operation. 1 V − RT • CT • ln 1 − P −K VREF where VP-K = RCT peak voltage 2005 Semtech Corp. 5 www.semtech.com SC4809A/B/C POWER MANAGEMENT Block Diagram Marking Information Top Mark AF0A yyww Bottom Mark xxxx xxxx Top Mark AF0B yyww Bottom Mark xxxx xxxx Top Mark AF0C yyww Bottom Mark xxxx xxxx Part Number (Example: 1456) yyww = Datecode (Example: 0012) xxxxx = Semtech Lot # (Example: E901 xxxxx = 01-1) 2005 Semtech Corp. 6 www.semtech.com 90 - 300VDC C1 1/450V 2005 Semtech Corp. C2 2.2n L1 (Opt.) C3 2.2n Q2 FMMT718 C4 47/400V 7 C8 0.1 R7 7.5k C5 0.1 R8 4.3k R6 10k Z1 BZX84C12 D1 SD103C R9 5.6k 5 4 3 2 1 R5 510 SS FB GND OUT VREF Fsw = 500kHz DMAX RCT SYNC LUVLO VDD U1 SC4809 C9 33n C11 0.33 C12 0.1 3 2 1 VCC GND IN OUT EN U2 SC1301A T1 ----------------------------------------Core: EFD15, 3C85 Magnetizing L = 230uH Np1 = 24 ts Np2 = 5 ts Ns1 = 2 ts Approximate Gap = 0.038mm AL value = 397 nH/N² C10 1n 6 7 8 9 10 4 5 R14 100 R13 300 R12 2.2 D2 US1G Z3 SMBJ85 R15 1.5 Q3 IRFR420 Np1 T1 D3 US1B 2 1 R16 150 U3 MOC207 7 D4 B240 C15 0.1 Vcc R17 1k C13 4.7/20V/1.8 Ohm R18 3k U4 SC4431 C17 1n C16 2.7n R19 10k C18 330/6.3V/0.04 Ohm L2 10uH U2: SC1301AISKTR, SOT-23-5, SEMTECH U4: SC4431CSK, SOT-23-5, SEMTECH Q3: IRFR420, Dpak, Inter.Rect. B240, SMB, Vishay C17: 6TPB330M, "7343", Sanyo L2: TOKO, A920CY-100M or similar U1: SC4809AIMSTR, MSOP-10, SEMTECH CRITICAL COMPONENTS: 5 6 C14 220pF Ns1 Np2 11 C19 10uF/6.3V C21 2.2n C20 0.1 R21 102 R20 316 + _ 5V@1A POWER MANAGEMENT Applications Information R11 3k C6 100p Z2 CMZ5929 R10 1k C7 100p R4 100k R3 820k R2 2M R1 750k Q1 FZT458 SC4809A/B/C Flyback, 90V - 300V to 5V @ 1A typ. www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information The flyback power stage is very popular in 48V input telecom applications for output power levels up to approximately 50 watts. The exact power rating of the flyback power stage, of course, is dependent on the input voltage/output voltage combination, its operating environment and many other factors. Additional output voltages can be generated easily by simply adding another winding to the coupled inductor along with an output diode and output capacitor. Obtaining multiple output voltages from a single power stage is another advantage of the flyback power stage. A simplified schematic of the flyback power stage with a drive circuit block included is shown in Figure 1. In the schematic shown, the secondary winding of the coupled inductor is connected to produce output voltage. The power switch, Q1, is an N-channel MOSFET. The secondary inductance, LSEC and capacitor C, make up the output filter, The resistor R, represents the load seen by the power supply output. Figure 2: Discontinuous Mode Flyback Waveforms The simplified voltage conversion relationship for the flyback power stage operating in CCM is given by: Figure 1: Flyback Power Converter VO = VI • The important waveforms of the flyback power stage operating in DCM are shown in Figure 2. NS D • NP 1 − D The simplified voltage conversion relationship for the flyback power stage operating in DCM is given by: VO = VI • NS D • NP K Where K is defined as: K= 2005 Semtech Corp. 8 2 • L SEC R • TS www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information (Cont.) The DC transfer function of a CCM flyback converter is: Control-to-Output transfer function for the flyback power stage operating in CCM is given by: S S 1 + • 1 − ωz1 ωz 2 dVO N VI = • S • 2 dD (1 − D) NP S S2 + 1+ ωO • Q ωO 2 VO + VD 1 Dmax = • VIN(min) − VRds( on ) N 1 − Dmax where VO = output voltage, VD = forward voltage drop across rectifier D1, where: N = turns ratio, equal to NP/NS, 1 ωz1 = RC • C ωz 2 ≈ ωO ≈ Q≈ D = duty cycle. (1 − D) • R D • L SEC 2 Transformer Design 1− D The transformer in a flyback converter is actually a coupled inductor with multiple windings. Transformers provide coupling and isolation whereas inductors provide energy storage. The energy stored in the air gap of the inductor is equal to: L SEC • C (1 − D) x R L SEC C L P • (IPEAK ) 2 2 E= Control-to Output transfer function for the flyback power stage operating in DCM is given by: N R • TS dVO • = VI • S • NP 2 • L SEC dD where E is in Joules, LP is the primary inductance in Henries, and IPEAK is the primary peak current in Amperes. When the switch is on, D1 is reverse biased due to the dot configuration of the transformer. No current flows in the secondary windings and the current in the primary winding ramps up at a rate of: 1 1+ S ωP where: ωP = 2 R•C ∆IL VIN(min) − VRds( on ) = ∆t LP Peak current mode control requires simpler compensation, has pulse-by-pulse current limiting, and has better load current regulation. Primary and secondary RMS currents can be up to two times higher for discontinuous mode than for CCM. Discontinuous conduction mode would require using a transistor with a higher current rating. Because the output ripple current is less than it would be continuous mode were used, the output capacitors are smaller. Continuous conduction mode (CCM) was therefore chosen. 2005 Semtech Corp. The output capacitor, COUT, supplies all of the load current at this time. Because the converter is operating in the continuous conduction mode, ∆IL is the change in the inductor current which appears as a positive slope ramp on a step. The step is present because there is still current left in the secondary windings when the primary turns on. When the switch turns off, current flows through the secondary winding and D1 as a negative ramp on a step, replenishing COUT and supplying current directly to the load. 9 www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information (Cont.) MOSFET Selection The primary inductance can be calculated given an acceptable current ripple, ∆IL. ∆IL was set to equal onehalf the peak primary current. For a CCM flyback design, the peak primary current is calculated: IOUT (max) IPEAK = N 1 • 1− D max The switching element in a flyback converter must have a voltage rating high enough to handle the maximum input voltage and the reflected secondary voltage, not to mention any leakage inductance induced spike that is inevitably present. Approximate the required voltage rating of the MOSFET using. ∆IL + 2 N Vds = (VIN(max) + VL ) + P NS Because the converter is operating in the continuous mode, the maximum peak flux density BMAX, is limited by the saturation flux density, B SAT. Taking all this into consideration, the maximum core size is determined by. L •I •I • 10 4 AP = P PEAK RMS 420 • k • BMAX where Vds = the required drain to source voltage rating of the MOSFET, 1.31 VL = the voltage spike due to the leakage inductance of the transformer, estimated to be thirty percent of VIN(MAX), and the additions 1.3 factor includes an overall thirty percent margin. where AP = the core area product in cm4, k = winding factor, BMAX ≈ BSAT, This FET will experience both switching and conduction losses. The conduction losses will be equal to the I2R losses, as shown by: The result is compared to the product of the winding area, Aw (cm2), and effective core area, Ae (cm2), listed in the core manufacturer’s data sheet. PCOND = (IRMS ) • R DS( ON) 2 Switching losses are the result of overlapping drain current and drain to source voltage at turn on and turn off. The minimum number of primary turns is determined by: NP = L P • IPEAK • 10 4 B MAX • Ae The total switching losses are estimated based on equation: Based upon this result and the predetermined turns ratio, the number of secondary turns is established. PSW = The energy stored in the flyback transformer is actually stored in an air gap in the core. This is because the high permeability of the ferrite material can’t store much energy without saturating first. By adding an air gap, the hysteresis curve of the magnetic material is actually tilted, requiring a much higher field strength to saturate the core. The length of the air gap is calculated by: lg = 2005 Semtech Corp. • (VO + VD ) • 1.3 C OSS • ( VDS )2 • fSW + VDS • IPEAK • t ch • fsw 2 where tch: t CH = Q gd • R g VDD − Vgs( th ) Diode Selection Schottky rectifiers have a lower forward voltage drop than typical PN devices, making it the rectifier of choice when considering reducing converter losses and improving overall efficiency. Selecting the appropriate Schottky for a specific application depends mainly on the working peak reverse voltage rating and peak repetitive forward current. µ o • µ r • (NP )2 • Ae • 10 −2 LP 10 www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information (Cont.) Input and Output Capacitors Slope Compensation The input capacitors are chosen based upon their ripple current rating and their rated voltage. The actual capacitor value is not that critical as long as the minimum capacitance gives an acceptable ripple voltage determined by the following equation: Sensing peak inductor current instead of average inductor current results in a loop response that is Less than ideal. Adding slope compensation to the current signal cancels this error by maintaining a constant average current independent of duty cycle. Slope compensation is required for open loop stability in a current mode system with 50% or greater duty cycles, but will benefit any current mode application at the cost of a few small parts. CMIN = IRMS 8 • fSW • ∆V The output capacitors are also chosen based upon their low equivalent series resistance (ESR), ripple current and voltage ratings. The ripple current that the output capacitor experiences is a result of supplying the load current during the FET conduction time and its charging current during the FET off-time. Loop Compensation The continuous current mode flyback will contain a righthalf-plane (RHP) zero in its transfer function. Any increase in load current will require the primary peak inductor current to increase. The duty cycle must increase to accomplish this. In a flyback converter, the inductor current flows to the output only when the FET is off and the diode is conducting. Increasing the duty cycle increases the FET condition time but decreases the diode conduction time. The result of this is the average diode current, the current that supplies the load, actually decreases. This is a temporary situation; as the inductor current rises, the diode current eventually reaches its proper value. The condition where the average diode current must actually decrease before it can increase is referred to as a right-half-plane zero. To complicate matters, this zero contributes a phase lag, not a phase lead as a normal zero would. This zero moves in frequency as a function of load and input voltage, making it impossible to cancel out by the insertion of a pole. Voltage Feedback The FB pin of the SC4809 sums the voltage feedback signal to the current sense signal and any added slope compensation. The voltage feedback signal is from an optocoupler, which is driven from an error amplifier on the secondary side of the converter. The signal from the optocoupler is designed to trip the FB threshold of the SC4809 internal comparator when the output voltage exceeds its specified limit. Current Limit Selection of the current sense resistor is accomplished by dividing the FB threshold value by the peak primary current at the desired current limit point. This groundreferenced RSENSE must be a low inductance type and have a rated power level to meet the (I RMS ) 2• R SENSE requirement. 2 fRHPZERO = The easiest way to deal with a right-half-plane zero is to roll off the loop gain at a relatively low frequency using simple dominant pole compensation. Unfortunately, the result of this is poor dynamic response. Current spikes caused by the leakage inductance of the flyback transformer and the reverse recovery of the diode could trip the current sense latch and prematurely shut off the output. This unwanted spike can be suppressed by adding a small RC filter for effective leading edge blanking. 2005 Semtech Corp. 2 • π • R OUT N • VIN • L P • ( VIN + N • VOUT ) The primary goal of the compensation network is to provide good line and load regulation and dynamic response. These objectives are best met by providing high gain at low frequencies for good DC regulation and high bandwidth for good transient response. Optimum closed loop performance can only be achieved by first 11 www.semtech.com SC4809A/B/C POWER MANAGEMENT Application Information (Cont.) knowing what the transfer characteristic of the PWM and switching circuit looks like. Constructing a Bode plot of the known poles and zeros in the power stage does this. Bode plots give a visual interpretation of the gain versus frequency and phase versus frequency characteristics of a system. In the gain plot, the gain shown at each frequency represents the amount by which the feedback loop will reduce a disturbance at that frequency. The scheme shown below will handle most compensation requirements. There is a pole at the origin which contributes a -1 slope in the gain plot, a low frequency zero, fEAZERO flattens out the slope so the mid-range gain is equal to Rf/Ri. A high frequency pole, fEAPOLE helps suppress any high frequency noise from propagating through the system. Rd forms a voltage divider with Ri and provides a DC offset. Besides the RHP zero, the output capacitor and the load contribute a pole and the output capacitor alone will contribute a zero based upon its ESR. fEAZERO = 1 2 • π • R f • Cf fEAPOLE = 1 2 • π • R f • Cp fpole = 1+ D 2 • π • R OUT • C OUT f zero = 1 2π • ESR • C OUT The control to output gain is calculated by: ISC • R OUT • VIN GAIN = 20 • log• VC • (1 − D) • (2 • N • VO + VIN ) Once the frequency response of the uncompensated system is determined, the next step is to determine what compensation is needed around the error amplifier for optimum performance. As stated earlier, optimum performance requires a high gain at low frequencies for good DC regulation and high bandwidth for good transient response. The crossover frequency, fc, is the frequency at which the gain magnitude equals 0dB. High bandwidth is achieved by having the highest possible fc. Because of the RHP zero, the highest possible crossover frequency is limited to fRHPZERO/π. The phase margin, or the amount the phase lag measures at fc less 180°, should be at least 45° for good transient response with little overshoot. The magnitude of the gain at the frequency where the phase plot measures - 180° is referred to as the gain margin. If the slope of the gain plot is -2, or -40dB/decade, at low frequencies, it much transition to a -20dB/decade slope, also known as a -1 slope, one decade before crossing the 0dB point. If the slope remains at the -2 slope the resultant gain margin would be too small causing sever underdamped oscillations at fc. 2005 Semtech Corp. By combining the Bode plots of the PWM and power stage with the error amplifier compensation, a plot of the entire system is realized. 12 www.semtech.com Za ZMM5242B Ra 300 1W Qa TIP30C 2005 Semtech Corp. C1 1.0/100V 13 R5 7.5k R4 2.7k R3 1k C1 1.0/100V R5 7.5k R4 2.7k R3 1k C2 100p R6 10k R2 20k C2 150p R6 10k R2 20k R7 1k 5 4 3 2 1 R7 1k 5 4 3 2 1 U1 SC4809 R8 3.9k SS FB GND OUT VREF DISABLE Q1 MMBT2907A C3 0.47 DMAX RCT SYNC LUVLO VDD R8 3.9k SS FB GND OUT VREF DISABLE Q1 MMBT2907A C3 0.47 DMAX RCT SYNC LUVLO VDD U1 SC4809 C4 0.1 6 7 8 9 10 C4 0.1 6 7 8 9 10 C5 C6 0.47 200p C7 0.1 C5 C6 0.47 200p C7 0.1 R11 7.5k VCC R11 7.5k OUT EN U2 SC1301 R9 100 GND IN R10 47k VCC OUT EN U2 SC1301 GND IN R10 47k 3 2 1 Z1 ZMM5242B 3 2 1 Z1 ZMM5242B R9 100 R12 1k 4 5 R12 1k 4 5 Q2 IRF640N Q2 IRF640N R14 0.2 1/2W R13 10 C8 1.0 L1 10uH R14 0.2 1/2W R13 10 C8 1.0 L1 10uH R15 22k C9 1n D1 MURD620CT R17 1k R15 22k C9 1n D1 MURD620CT R17 1k R16 47k Q3 BSS64ZXCT R16 47k Z2 ZMM5242B C10 150/16V Q3 BSS64ZXCT Z2 ZMM5242B C10 150/16V C11 1.0 C11 1.0 R18 200 1W R18 200 1W +12V GND +12V GND POWER MANAGEMENT Applications Information (Cont.) -- 48V "MASTER" "SLAVE" +48V R1 1k Rb 300 1W SC4809A/B/C Out of Phase, Synchronized, Dual Converter www.semtech.com 2005 Semtech Corp. 14 10k 10k 8.2k A B C R10 Q1 MMBT2222A SYNC 100 62 62 604 604 1k R7 5 4 3 2 1 R8 1.5k 0.22 0.15 0.15 R18 C3 0.1/25V 10k R17 R6 2k C4 * Q2 MMBT2907A R16 R5 10k R4 10k C2 0.01 R3 100k 2x10k| | 3x12k| | 2x12k| | R12 R10 * R9 7.5k C5 0.01 300p 300p 200p 6 7 8 9 10 C7 0.47 390p 680p 680p C8 C6 0.033 Z1 ZMM5245B C4 SS FB GND OUT VREF Fsw=330kHz DMAX RCT SYNC LUVLO VDD U1 SC4809_A_B_C R11 100 C8 * C9 1/25V R12 * 3 2 1 VCC GND IN 4 5 R17 * R16 * R15 3.3 SMA D2 ES1D R18 * 4 2 3 1 6 5 7 C12 220pF Q3 IRF640NS U3 MOC207 R19 20 1/4W 10,11,12 7,8,9 C14-16: 6TPB470M, PosCap, Sanyo C18 0.022 1 2 C13 1nF/50V L1: ETQP6F2R5SFA, Panasonic T1: PA0273, Pulse Eng. OUT EN U2 SC1301A C11 0.01/100V 6 R14 3.3k 1W 5 R20 1k C19 0.01 U4 SC4431 R24 1.21k C21 0.01 R23 62k C17 10.0 C20 430pF C14-16 470/6.3V R22 39.2k R21 1k Vcc D3 MBRB1530CT L1 2.5uH@10A R26 0 R25 3.83k POWER MANAGEMENT Evaluation Board Schematic R2 1k R1 5.1k C1 1.0/100V C10 1.0/16V SC4809A/B/C 50W Forward Converter www.semtech.com SC4809A/B/C POWER MANAGEMENT Evaluation Board Layout 50W Forward Converter Layout Top Bottom 2005 Semtech Corp. 15 www.semtech.com SC4809A/B/C POWER MANAGEMENT Outline Drawing - MSOP-10 DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX e A DIM D 2X E/2 ccc C 2X N/2 TIPS E E1 PIN 1 INDICATOR .043 .000 .006 .030 .037 .007 .011 .003 .009 .114 .118 .122 .114 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 8° 0° .004 .003 .010 A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc N 12 B 1.10 0.00 0.15 0.75 0.95 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0° 8° 0.10 0.08 0.25 D aaa C SEATING PLANE A2 H A bxN bbb c GAGE PLANE A1 C C A-B D 0.25 L (L1) DETAIL SEE DETAIL SIDE VIEW 01 A A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP-10 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2005 Semtech Corp. 16 www.semtech.com