Surface Mount Micromachined Accelerometer

Document Number: MMA2241KEG
Rev 3, 11/2012
Freescale Semiconductor
Data Sheet: Technical Data
Surface Mount
Micromachined Accelerometer
MMA2241KEG
The MMA2241KEG is a silicon capacitive, micromachined accelerometer
featuring signal conditioning, a 2-pole low pass filter and temperature
compensation. Zero-g offset full scale span and filter cut-off are factory set and
require no external devices. A full system self-test capability verifies system
functionality.
X-AXIS SENSITIVITY
MICROMACHINED
ACCELEROMETER
±10g
Features
•
•
•
•
•
•
•
•
•
•
•
Integral Signal Conditioning
Linear Output
Ratiometric Performance
2nd Order Bessel Filter Preserves Pulse Shape Integrity
Calibrated Self-test
Low Voltage Detect, Clock Monitor, and EPROM Parity Check Status
Transducer Hermetically Sealed at Wafer Level for Superior Reliability
Robust Design, High Shocks Survivability
Pb-Free Termination
Environmentally Preferred Package
Qualified AEC-Q100, Rev. F Grade 2 (-40C/ +105C)
KEG SUFFIX (Pb-FREE)
16-LEAD SOIC
CASE 475-01
Typical Applications
•
•
Vibration Monitoring and Recording
Dynamic Suspension Control
ORDERING INFORMATION
Device Name
Temperature Range
Case No.
Package
MMA2241EG
–40to 125C
475-01
SOIC-16
MMA2241EGR2
–40to 125C
475-01
SOIC-16, Tape & Reel
MMA2241KEG*
–40to 125C
475-01
SOIC-16
MMA2241KEGR2*
–40to 125C
475-01
SOIC-16, Tape & Reel
*Part number sourced from a different facility.
VDD
G-Cell
Sensor
ST
Self-test
Integrator
Gain
Control Logic &
EPROM Trim Circuits
Filter
Oscillator
Temp
Comp
Clock
Generator
VOUT
VSS
N/C
N/C
N/C
ST
VOUT
STATUS
VSS
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
STATUS
Figure 1. Simplified Accelerometer Functional Block Diagram
© 2011, 2012 Freescale Semiconductor, Inc. All rights reserved.
Figure 2. Pin Connections
The block diagram of the MMA2241EG is shown in
Figure 1. The X-axis g-cell is constructed using surface
micromachining; and the interface IC is fabricated in a
1.2 micron (60%) silicon gate CMOS process.
The signal conditioning of the accelerometer channel
begins with a capacitance to voltage conversion (C to V)
followed by a 2-stage switched capacitor amplifier. This
2-stage amplifier has adjustable offset and gain trimming.
The offset and gain of the interface IC can be controlled by
the serially accessed EPROM trimming register.
Following the 2-stage amplifier the signal passes through
a 2-pole, switched capacitor filter with a Bessel characteristic.
The rolloff frequency of the filter is trimmed by adjusting the
frequency of the single on-chip oscillator. The frequency is
adjusted by trimming the bias current to the oscillator using
the EPROM trim register.
The output of the filter is then amplified by the output stage
which also has a temperature compensation circuit for
sensitivity which can be adjusted using the EPROM trim
register.
An adjustable self-test voltage to be applied to the
electrostatic deflection plate in the sensing element. Other
support circuits include a bandgap voltage reference for the
bias sources and the self-test voltage. The interface IC also
has its own power supply filter which feeds all the analog
functions in order to increase the power supply rejection ratio
(PSRR).
Included are several fault checks for low voltage detect
(LVD), clock and/or bias monitoring, and a check of the stored
“even” parity of the EPROM trim register. Failure of any of
these monitoring functions will result in the STATUS
input being driven high.
Table 1. Maximum Ratings
(Maximum ratings are the limits to which the device can be exposed without causing permanent damage.)
Rating
Symbol
Value
Unit
gshock
2000
0.5 ms duration
g
In use g shocks powered or unpowered
Capable of < 5 ppm device failure rate
Gshock in use
< 100
any duration
g
In use g shocks powered or unpowered
Capable of < 50 ppm device failure rate
Gshock in use
< 100 - 1500
0.6 ms duration
g
Supply Voltage
VDD
–0.3 to +7.0
V
Storage Temperature Range
Tstg
–40 to +125
°C
Unpowered Acceleration (all axes)
This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part or
cause the part to otherwise fail.
ELECTRO STATIC DISCHARGE (ESD)
WARNING: This device is sensitive to electrostatic
discharge.
Although the Freescale accelerometers contain internal
2kV ESD protection circuitry, extra precaution must be taken
by the user to protect the chip from ESD. A charge of over
2000 volts can accumulate on the human body or associated
test equipment. A charge of this magnitude can alter the
performance or cause failure of the chip. When handling the
accelerometer, proper ESD precautions should be followed
to avoid exposing the device to discharges which may be
detrimental to its performance.
Document Number: MMA2241KEG
2
Sensors
Freescale Semiconductor, Inc.
Table 2. Operating Characteristics
(Unless otherwise noted: –40°C TA +125°C, 4.75 VDD 5.25, Acceleration = 0g, Loaded output.(1))
Characteristic
Symbol
Min
Typ
Max
Unit
VDD
IDD
TA
gFS
4.75
4.0
40
—
5.00
5.0
—
10
5.25
6.0
+125
—
V
mA
C
g
VOFF
VOFF,V
S
SV
f–3dB
NLOUT
2.30
0.46 VD
194.0
37.2
360
–1.0
2.500
0.50 VDD
200.0
40.0
400
—
2.70
0.54 VDD
206.0
42.8
440
+1.0
V
V
mV/g
mV/g/V
Hz
% FSO
nRMS
—
3.5
5.0
mVrms
Self-Test
Output Response(6)
Input Low
Input High
Input Loading(7)
Response Time(8)
gST
VIL
VIH
IIN
tST
4.0
VSS
0.7 xVDD
–30
—
5.0
—
—
–100
2.0
6.0
0.3 x VDD
VDD
–300
10
g
V
V
A
ms
Status(9), (10)
Output Low (Iload = 100 A)
Output High (Iload = 100 A)
VOL
VOH
—
VDD –0.8
—
—
0.4
—
V
V
Minimum Supply Voltage (LVD Trip)
VLVD
2.7
3.25
4.0
V
fmin
150
—
400
kHz
Output Stage Performance
Electrical Saturation Recovery Time(11)
Full Scale Output Range (IOUT = 200 A)
Capacitive Load Drive(12)
Output Impedance
tDELAY
VFSO
CL
ZO
—
0.25
—
—
0.2
—
—
300
—
VDD –0.25
100
—
ms
V
pF

Mechanical Characteristics
Transverse Sensitivity(13)
Package Resonance
VXZ,YZ
fPKG
—
—
—
10
5.0
—
% FSO
kHz
Operating Range(2)
Supply Voltage(3)
Supply Current
Operating Temperature Range
Acceleration Range
Output Signal
Zero-g (TA = 25°C, VDD = 5.0 V)(4)
Zero-g
Sensitivity (TA = 25°C, VDD = 5.0 V)(5)
Sensitivity
Bandwidth Response
Nonlinearity
Noise
RMS (10 Hz – 1 kHz)
Clock Monitor Fail Detection Frequency
1. For a loaded output the measurements are observed after an RC filter consisting of a 1 k resistor and a 0.01 F capacitor to ground.
2. These limits define the range of operation for which the part will meet specification.
3. Within the supply range of 4.75 V and 5.25 V, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits the
device may operate as a linear device but is not guaranteed to be in calibration.
4. The device can measure both + and – acceleration. With no input acceleration the output is at midsupply. For positive acceleration the output
will increase above VDD/2 and for negative acceleration the output will decrease below VDD/2.
5. The device is calibrated at 5g.
6. VOFF calculated with typical sensitivity.
7. The digital input pin has an internal pull-down current source to prevent inadvertent self test initiation due to external board level leakages.
8. Time for the output to reach 90% of its final value after a self-test is initiated.
9. The Status pin output is not valid following power-up until at least one rising edge has been applied to the self-test pin. The Status pin is
high whenever the self-test input is high, as a means to check the connectivity of the self-test and Status pins in the application.
10. The Status pin output latches high if a Low Voltage Detection or Clock Frequency failure occurs, or the EPROM parity changes to odd. The
Status pin can be reset low if the self-test pin is pulsed with a high input for at least 100 s, unless a fault condition continues to exist.
11. Time for amplifiers to recover after an acceleration signal causing them to saturate.
12. Preserves phase margin (60°) to guarantee output amplifier stability.
13. A measure of the device's ability to reject an acceleration applied 90° from the true axis of sensitivity.
Document Number: MMA2241KEG
Sensors
Freescale Semiconductor, Inc.
3
PRINCIPLE OF OPERATION
The Freescale accelerometer is a surface-micromachined
integrated-circuit accelerometer.
The device consists of a surface micromachined
capacitive sensing cell (g-cell) and a CMOS signal
conditioning ASIC contained in a single integrated circuit
package. The sensing element is sealed hermetically at the
wafer level using a bulk micromachined “cap'' wafer.
The g-cell is a mechanical structure formed from
semiconductor materials (polysilicon) using semiconductor
processes (masking and etching). It can be modeled as two
stationary plates with a moveable plate in-between. The
center plate can be deflected from its rest position by
subjecting the system to an acceleration (Figure 3).
When the center plate deflects, the distance from it to one
fixed plate will increase by the same amount that the distance
to the other plate decreases. The change in distance is a
measure of acceleration.
The g-cell plates form two back-to-back capacitors
(Figure 4). As the center plate moves with acceleration, the
distance between the plates changes and each capacitor's
value will change, (C = A/D). Where A is the area of the
plate,  is the dielectric constant, and D is the distance
between the plates.
The CMOS ASIC uses switched capacitor techniques to
measure the g-cell capacitors and extract the acceleration
data from the difference between the two capacitors. The
ASIC also signal conditions and filters (switched capacitor)
the signal, providing a high level output voltage that is
ratiometric and proportional to acceleration.
Filtering
The Freescale accelerometers contain an onboard 2-pole
switched capacitor filter. A Bessel implementation is used
because it provides a maximally flat delay response (linear
phase) thus preserving pulse shape integrity. Because the
filter is realized using switched capacitor techniques, there is
no requirement for external passive components (resistors
and capacitors) to set the cut-off frequency.
Self-Test
The sensor provides a self-test feature that allows the
verification of the mechanical and electrical integrity of the
accelerometer at any time before or after installation. This
feature is critical in applications such as automotive airbag
systems where system integrity must be ensured over the life
of the vehicle. A fourth “plate'' is used in the g-cell as a selftest plate. When the user applies a logic high input to the selftest pin, a calibrated potential is applied across the self-test
plate and the moveable plate. The resulting electrostatic
2

1 V 
force  Fe = --- A ------ causes the center plate to deflect.
2 d2 

The resultant deflection is measured by the accelerometer's
control ASIC and a proportional output voltage results. This
procedure assures that both the mechanical (g-cell) and
electronic sections of the accelerometer are functioning.
Status
Freescale accelerometers include fault detection circuitry
and a fault latch. The Status pin is an output from the fault
latch, OR'd with self-test, and is set high whenever the
following event occurs:
• Parity of the EPROM bits becomes odd in number.
The fault latch can be reset by a rising edge on the self-test
input pin, unless one (or more) of the fault conditions
continues to exist.
Acceleration
Figure 3. Transducer
Physical Model
SPECIAL FEATURES
Figure 4. Equivalent
Circuit Model
Document Number: MMA2241KEG
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Freescale Semiconductor, Inc.
BASIC CONNECTIONS
Pinout Description
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
STATUS
P1
ST
P0
Accelerometer
N/C
N/C
N/C
ST
VOUT
STATUS
VSS
VOUT
VSS
VDD
R
1 k
A/D In
C 0.01 F
C 0.1 F
Microcontroller
PCB Layout
VSS
C 0.1 F
VDD
VRH
C 0.1 F
Table 3. Pin Descriptions
Power Supply
Pin No.
Pin Name
Description
1 thru 3
—
No internal connection. Leave
unconnected.
4
ST
Logic input pin used to initiate
self-test.
5
VOUT
Output voltage of the
accelerometer.
6
STATUS
Logic output pin to indicate fault.
7
VSS
The power supply ground.
8
VDD
The power supply input.
9 thru 13
Trim pins
14 thru 16
—
Used for factory trim. Leave
unconnected.
No internal connection. Leave
unconnected.
Figure 5. Recommended PCB Layout for Interfacing
Accelerometer to Microcontroller
NOTES:
1. Use a 0.1 F capacitor on VDD to decouple the power
source.
2. Physical coupling distance of the accelerometer to the
microcontroller should be minimal.
3. Place a ground plane beneath the accelerometer to
reduce noise, the ground plane should be attached to
all of the open ended terminals shown in Figure 5.
4. Use an RC filter of 1 k and 0.01 F on the output of
the accelerometer to minimize clock noise (from the
switched capacitor filter circuit).
5. PCB layout of power and ground should not couple
power supply noise.
6. Accelerometer and microcontroller should not be a
high current path.
VDD
Logic
Input
4
MMA2241KEG
ST
8 VDD
C1
0.1 F
7 VSS
VOUT
6
5
R1
1 k
STATUS
Output
Signal
7. A/D sampling rate and any external power supply
switching frequency should be selected such that they
do not interfere with the internal accelerometer
sampling frequency. This will prevent aliasing errors.
C2
0.01 F
Figure 4. SOIC Accelerometer with Recommended
Terminations
Document Number: MMA2241KEG
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Freescale Semiconductor, Inc.
5
Dynamic Acceleration Sensing Direction
Acceleration of the package in the
X direction (center plate moves in
the X direction) will result in an
increase in the output.
+x
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
–x
Activation of Self Test moves the
center plate in the X direction,
resulting in an increase in the
output.
16-Pin SOIC Package
N/C pins are recommended to be left FLOATING
Top View
Static Acceleration Sensing Direction
8 7 6 5 4 3 2 1
Direction of Earth’s gravity field(1)
9 10 11 12 13 14 15 16
Front View
Side View
1. When positioned as shown, the Earth’s gravity will result in a positive 1g output.
Document Number: MMA2241KEG
6
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Freescale Semiconductor, Inc.
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the surface mount packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct
footprint, the packages will self-align when subjected to a
solder reflow process. It is always recommended to design
boards with a solder mask layer to avoid bridging and
shorting between solder pads.
0.380 in.
9.65 mm
0.050 in.
1.27 mm
0.024 in.
0.610 mm
0.080 in.
2.03 mm
Figure 6. Footprint SOIC-16 (Case 475-01)
Document Number: MMA2241KEG
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7
PACKAGE DIMENSIONS
PAGE 1 OF 2
CASE 475-01
ISSUE C
16-LEAD SOIC
Document Number: MMA2241KEG
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Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
PAGE 2 OF 2
CASE 475-01
ISSUE C
16-LEAD SOIC
Document Number: MMA2241KEG
Sensors
Freescale Semiconductor, Inc.
9
Table 4. Revision History
Revision
number
Revision
date
3
11/2012
Description of changes
• Table 2. Operating Characteristics, added footnote for Self-Test Output Response, updated page
4: Principle of Operation
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© 2012 Freescale Semiconductor, Inc.
Document Number: MMA2241KEG
Rev. 3
11/2012