MB9D560 Series
32-bit Microcontroller Traveo Family
Fact Sheet
TM
®
®
The Traveo family MB9D560, features 32-bit RISC microcontrollers with two ARM Cortex R5 cores and operate at 200 MHz.
The dual-core structure on a single chip has two interface circuits for resolver sensors (R/D converter) for automotive motor control, and
two hardware IP circuits as motor vector operation accelerator to reduce motor control operations. Each core has a built-in floating point
unit (FPU), with each motor running independently but monitoring the operation of each other.The motor vector operation accelerator
has some error detection circuits with functional safety and is ideal for hybrid vehicles (HEV) and electrical vehicles (EV)with two driving
motors.
Features
Product Lineup
32bitARM Cortex-R5F CPU Core
Split mode(2CPU)
FPU(double precision)
Clock
Maximum clock frequency: 200MHz
DMA controller: 16 channels
Base timer: 6 or12 channels
32-bit free-run timer: 5 channels
32-bit Input capture: 6 channels
16-bit free-run timer: 20 channels
16-bit Input capture: 13 or15 channels
16-bit Output compare: 18 or24 channels
Waveform Generator: 3 or4 units
12-bit A/D converter: 32 channels(1 unit)
4ch-sample hold 12-bit A/D converter: 8 channels(2 units)
R/D converter: 2 units (option)
D/A converter: 2 channels (option)
Up/down counter: 4 channels
Motor vector operation accelerator: 2 units
Multi-function serial interface: 3 or5 channels, Selectable
from UART/CSIO/LIN
CAN(64msb): 3 channels
Flex Ray(128msb): 1 unit(option)
Core communication(IPCU)
Exclusion access memory
Watchdog timer: 2 channels(SW)+1 channel(HW)
CRC generation: 2channels
General Purpose I/O port: 125(Max)
Built-in CR oscillator
Debug interface
JTAG Debug Port
Low Voltage Detector
Clock Supervisor
Power Supply: 2 power voltage(5V,1.2V)
Cypress Semiconductor Corporation
Document Number: 002-08972 Rev. *A
•
198 Champion Court
Part number
Parameter
Main Flash
(Byte)
Work Flash
(Byte)
RAM
(Byte)
MB9DF564
MB9DF565
MB9DF566
(512K+128K)
x2
(768K+128K)
x2
(1024K+128K)
x2
64Kx2
64Kx2
64Kx2
64Kx2
96Kx2
128Kx2
Ordering Information
Package
Part number
MB9DF564MxEEQ
MB9DF565MxEEQ
MB9DF566MxEEQ
MB9DF564LxEEQ
MB9DF565LxEEQ
MB9DF566LxEEQ
Plastic
TEQFP(0.5mm pitch),
208pin
Plastic
TEQFP(0.5mm pitch),
176pin
Package Example of Reference
Plastic・TEQFP, 208pin
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 27, 2016
MB9D560 Series
Block Diagram
Debug I/F
(JTAG)
JTAG_SWCLKTCK
JTAG Wakeup
Debug Group
(CoreSightTM)
DAP
Security
APB-M
APB-S
AHB-M
CLK_DBG
AHB2APB
(Priviledge
Protection)
Debug APB
APB-32
Trace Group
Security
Checker
ETB (Trace Buffer)
ATB
CLK_ATB
Debug APB
ETM
#1
ATB
CLK_PERI0
CLK_ATB
Core Group (2-Core)
AHB-32
ETM
#0
DMAC
(Ch.0-15)
Processor
CLK_CPU1
CLK_CPU0
CPU #1
TCRAM #1
TCFLASH
#1
Security
CPU #0
CortexTM -R5F
AHB-M
TCRAM #0
CortexTM -R5F
B0TCM
B0TCM
B1TCM
#1
B1TCM
#0
MPU
#1
I$
#1
ATCM
#1
LLPP(AXI32-M) AXI-S
D$
#1
MPU
#0
I$
#0
D$
#0
CLK_PERI0
MPU_DMA
Exclusive
Access Memory
(EAM)
TCFLASH
Security
#0
ATCM
#0
AXI-M AXI-S LLPP(AXI32-M)
AXI-M
AHB-64
CLK_DMA
AHB-32
AXI2AHB
AHB2AXI
AXI-S
AHB2AXI
High Performance Matrix (HPM)
AXI-64
AXI2AHB
AXI2AHB
AXI2AHB
BBU
BBU
BBU
CLK_HPM
AXI2AHB
AXI2AHB
AHB-32
CLK_PERI5
Mode cntl
System Controller
(SYSC)
WorkFLASH
#0
AHB-32
CLK_SYSC_PD1
Security
AHB-64
CLK_MEMC
Security
RST manage
Protection
PONR
State
Source Clock
Timer
CSV
Slow-CR
CR
FlexRay
(A+Bch)
MPU_DMA
(Config, Slave)
CAN
Prescaler
DMAC
(Config, Slave)
CR
Calibration
Timing
Protection
(TPU) #0
CRC
(Ch.0-1)
Timing
Protection
(TPU) #1
GPIO
Port Pin Config
(Config, Slave)
Resource Input Config
(Config, Slave)
RAM
AHB2APB
IRC #1
APB-32
RAM
Clock output
CLK_PERI1
MFS
(Ch.0-4)
NMI
HW-WDT
SW-WDT #0
SW-WDT #1
EXT-IRC
(NMI)
RDC
(Ch.0)
RDC
(Ch.1)
DAC
(Ch.0)
DAC
(Ch.1)
WFG (Ch.0-5)
WFG (Ch.6-11)
16bit OCU
(Ch.0-5)
16bit OCU
(Ch.6-11)
4ch-SH ADC
(Unit0, Ch.0-3)
4ch-SH ADC
(Unit1, Ch.4-7)
MVA (Ch.0)
MVA (Ch.1)
16bit ICU
(Ch.0-3)
16bit ICU
(Ch.4-7)
8/16bit
UDC for RDC
(Ch.1)
8/16bit
UDC for RDC
(Ch.3)
8/16bit UDC
(Ch.0)
8/16bit UDC
(Ch.2)
16bit FRT for
RDC
(Ch.18)
16bit FRT for
RDC
(Ch.19)
IRC #0
PLL
Wakeup
detect
BBU
AHB-32
CLK_PERI0
RAM
BootROM
Clock
LVD
CAN
(Ch.0-2)
WorkFLASH
#1
AHB-32
CLK_PERI4
BBU
AHB2RBus
Wakeup
Request #0
16bit FRT
(Ch.6-11)
16bit FRT
(Ch.0-5)
32bit FRT
(Ch.0-4)
IPCU
CLK_PERI7
32bit ICU
(Ch.0-5)
AHB2APB
FlexRay/RDC
Clock Cntl
Wakeup
Request #1
Clock Monitor
16bit Base
Timer
[PWM/PPG/
RLT/PWC]
(Ch.0-11)
TCFLASH #0
(Config, Slave)
TCRAM #0
(Config, Slave)
16bit OCU
(Ch.12-23)
12bit
A/D Converter
(1unit, Ch.0-31)
TCRAM #1
(Config, Slave)
Memory & Config Group
Common Peripheral Group
Application Specific Peripheral Group
Resource Input
Config
PORT MUX (Port Pin Config)
IO
Document Number: 002-08972 Rev. *A
16bit FRT
(Ch.12-17)
WFG (Ch.12-23)
16bit ICU
(Ch.8-14)
TCFLASH #1
(Config, Slave)
MCU Config Group
CLK_PERI6
Page 2 of 4
MB9D560 Series
Document History
Document Title: MB9D560 Series, 32-bitMicrocontroller Traveo FamilyFact Sheet
Document Number: 002-08972
Revision
ECN
Orig. of
Change
Submission
Date
**
−
FUKO
05/19/2014
*A
5159018
FUKO
04/25/2016
Document Number: 002-08972 Rev. *A
Description of Change
Migrated to Cypress and assigned document number 002-08972.
No change to document contents or format.
Updated to Cypress template
Added TEQFP176pin
Page 3 of 4
MB9D560 Series
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Document Number: 002-08972 Rev. *A
Revised
April 27, 2016Page 4 of 4