1 2 3 4 5 6 7 8 A A Standard Extension Header (Female) Extension Identification NLVCC0ID VCC_ID COR10 4.7uF 8 PIU108 VCC COC100 C100 1 PIR10 1 NLID0DATA0B ID_DATA_B 9 PIU109 PAD 4 PIU104 GND NC NC NC IO NC0 NC PIJ30 PIJ302 PIJ301 1 2 3 PIU103 5 PIU105 6 PIU106 7 PIU107 PIU101 3 2 1 2 2 1 1 R100 1 2 100k 2 PIR10 2 2 PID10002 BAT54XV2T1G COU1 U1 PIC10 2 PIC10 1 COD100 D100 1 PID10001 NLID0DATA0A ID_DATA_A ADC(+) GPIO1 PWM(+) IRQ_GPIO TWI_SDA UART_RX SPI_SS_A SPI_MISO PIU102 COJS3 JS3 Default Connect Pin 2&3 SNT-100-BK-G HMTSW-103-23-F-S-237 COJ3 J3 GND ATSHA204A-SWI ATSHA204 SWI UDFN8 B COJ100 J100 1 PIJ10001 2 PIJ10002 PIJ10003 PIJ10004 3 5 PIJ10005 7 PIJ10007 9 PIJ10009 11 PIJ100011 13 PIJ100013 15 PIJ100015 17 PIJ100017 19 PIJ100019 4 6 PIJ10006 8 PIJ10008 10 PIJ100010 12 PIJ100012 14 PIJ100014 16 PIJ100016 18 PIJ100018 20 PIJ100020 GND ADC(-) GPIO2 PWM(-) SPI_SS_B/GPIO TWI_SCL UART_TX SPI_MOSI SPI_SCK VCC TF201-2*10RGF-W2-NF COC101 C101 2PIC10102 PIC101011 1 2 B 4.7uF GND GND [DESIGN NOTE] The ATSHA204 is powered through an IO Pin from the EDBG on an MCU board. R100 is present to drain the capacitor C100 when power is removed from an MCU board. [DESIGN NOTE] IMPORTANT NOTICE: UART_RX and UART_TX refer to RX (input) and TX (output) at the target device side. Connect UART_RX to TX of the UART device on the extension board and UART_TX to RX of the UART device on the extension board. NLAES0AUTHO AES_AUTHO POAES0AUTHO AES_AUTHO NLTWI0SDA TWI_SDA POTWI0SDA TWI_SDA COJ2 J2 19 PIJ2019 17 PIJ2017 15 PIJ2015 13 PIJ2013 11 PIJ2011 9 PIJ209 7 PIJ207 5 PIJ205 3 PIJ203 1 PIJ201 C 20 NLTWI0SCL TWI_SCL POTWI0SCL TWI_SCL VCC PIJ2020 18 PIJ2018 16 PIJ2016 14 PIJ2014 12 PIJ2012 10 PIJ2010 8 PIJ208 6 PIJ206 4 PIJ204 2 PIJ202 C HEADER 2x10 P101-2*10RGF-139-ND GND ATMEL Colorado * 1150 E. Cheyenne * Mtn Blvd D D Colorado Springs * Colorado, USA Date: 4/27/2015 5:41:31 PM Document number: * PAGE: 2 of Revision: 1 TITLE: XPRO_Extension_Connector_Template_4L CryptoAuth_Xplained_Pro_Connector.SchDoc 1 2 3 4 5 6 7 8 3 1 2 3 4 VCC 5 6 7 8 VCC 1 VCC 1 PIR101 2 1 2 PIR102 PIC102 PIC101 8 PIU208 COC1 C1 100n 9 4 PIU204 PIU209 A COR2 R2 3.9k PIR202 2 COU2 U2 PIR201 2 1 COR1 R1 3.9k A VCC NC NC NC SDA PAD SCL GND NC 1 PIU201 2 PIU202 3 PIU203 5 PIU205 6 PIU206 7 PIU207 TWI_SDA POTWI0SDA TWI_SDA TWI_SCL POTWI0SCL TWI_SCL ATECC508A-I2C ATECC508A I2C UDFN GND ATECC508A UDFN TWI VCC B B COU3 U3 PIC302 PIC301 8 PIU308 COC3 C3 100n 9 PIU309 4 PIU304 VCC NC AUTHO NC SDA PAD SCL GND NC 1 2 3 PIU303 5 PIU305 6 PIU306 7 PIU307 GND PIU301 COR3 R3 PIU302 PIR301 PIR302 POAES0AUTHO AES_AUTHO 0R TWI_SDA TWI_SCL ATAES132A-I2C ATAES132A I2C UDFN ATASE132A UDFN TWI GND C C NLVCC VCC PIC402 PIC401 COC4 C4 COU4 U4 8 PIU408 VCC 100n 9 PIU409 4 PIU404 NC NC NC SDA PAD SCL GND NC VCC COF1 F1 1 PIU401 2 PIU402 3 PIU403 5 PIU405 6 PIU406 7 PIU407 COF2 F2 PIF101 NLTWI0SDA TWI_SDA FIDUCIAL FIDUCIAL 1.5mm NLTWI0SCL TWI_SCL PIF201 FIDUCIAL FIDUCIAL 1.5mm Atmel Colorado ATSHA204A-I2C ATSHA204A I2C UDFN D GND 1150 E. Cheyenne Mtn Blvd ATSHA204A UDFN TWI D Colorado Springs * Colorado USA Date: 4/27/2015 5:41:31 PM Document number: * PAGE: 3 of Revision: 1 TITLE: Crypto Device Schematic CryptoAuth_Xplained_Pro_CRYPTO.SchDoc 1 2 3 4 5 6 7 8 3