Simplifying the Design of Switch Applications with LIN Bus Connections Daniel Yordanov, Berthold Gruber How LIN Systems Benefit from Systemin-Package Devices Low-cost local interconnect networking (LIN) is a serial protocol used for in-car communications. LIN systems are typically used throughout the automobile in comfort, powertrain, sensor and actuator applications. Atmel® supports these applications with a modular LIN family that ranges from simple transceiver ICs to complex system basis chips (SBCs) and system-in-package (SiP) solutions. System in package is used for devices that integrate several semiconductor chips within one package, thus forming a complete electronic system. In contrast to standard solutions where the functionalities of a complete system are performed by separate ICs, a SiP can do so with one single device. That said, SiPs are another milestone of continuous IC performance improvement, power loss and cost reduction, as well as miniaturization at the system level. With the rapid LIN market growth, the requirements for everincreasing system efficiency, higher integration and lower costs have increased as well. Similarly, the number of control switches for various applications has also increased. Applications where the switches are located very remote from the control Automotive Compilation Vol. 9 electronics and wires integrated within the wiring harness do require high-voltage switches. The Atmel ATA6642 SiP has been developed to fulfill these increasingly demanding market requirements. Figure 1. ATA6642 SiP Atmel ATA6642 LIN SiP The new ATA6642 LIN SiP is designed for complete LIN-bus node applications, in particular for LIN switch applications. Integrating almost the complete LIN node, the device consists of two ICs within one package. The first chip is the ATA6641 LIN SBC, encompassing a LIN transceiver, a 5V regulator (up to 80mA load current), a window watchdog, an 8-channel high-voltage switch interface with high-voltage current sources and a 16-bit SPI for configuration and diagnostic purposes. The second chip is the Atmel AVR® ATtiny167 automotive 8-bit microcontroller with advanced RISC architecture and 16KB Flash memory. With its industry-leading design, the ATA6642 offers designers great flexibility, so that the SiP can be used in various applications such as port/contact monitoring, switches (towards GND or VBAT), LED/ relay/ power transistor control or switches connected through the wiring harness. Integrated LIN System Basis Chip The block diagram in Figure 2 provides a basic overview of the structure of the ATA6641 LIN SBC. CL15 VS HV Input 5V Voltage Regulator The window watchdog ensures a correct function of the microcontroller. A total of eight high-voltage (HV) current sources with HV comparators and voltage dividers implemented in the HV switch interface are available for switch scanning. Using the HV current sources also enables direct driving of LEDs, relays and transistors. All eight are high-side current sources; three of them can also be switched to low-side current sinks. The ATA6641 device's functionalities can be configured via the 16-bit SPI. This SPI interface simplifies and speeds up the configuration of the slave/master LIN node for any given application. Integrated AVR MCU Functionality GND NCS SCK MOSI 16-bit Serial Programming Interface (SPI) VCC Watchdog Timer MISO Watchdog Oscillator VBATT LIN LIN Physical Layer Interface Voltage Divider Control Logic TXD Int. Oscillator VCC VRLS Power Supervision POR/ BOD and RESET debugWIRE Flash SRAM Oscillator Circuits/ Clock Generation VDIV RXD Program Logic NIRQ NRES HV Switch Interface Unit (8x) Window Watchdog WD Oscillator AVR CPU GND EEPROM AGND AVCC NTRIG WDOSC MODE CSPWM IREF CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 Figure 2. ATA6641 LIN SBC Block Diagram DATA BUS AREF Timer/ Counter-1 Timer/ Counter-0 SPI and USI Analog Comp. A/D Conv. Internal Voltage References The ATA6641 LIN SBC with its flexible operation modes (sleep mode and active low-power mode) guarantees a very low current consumption even in the case of a floating bus line or a short circuit on the LIN bus to GND. Special techniques ensure that the circuit switches back to sleep mode after approximately 10ms if the bus line is floating or if a short circuit occurs to keep the current consumption at a minimum level. In sleep mode the entire SiP is switched off, with a current consumption as low as 8µA. The SiP can be easily woken up via the LIN bus or CL15, and is ready to operate within a couple of microseconds. Figure 3. AVR Core Block Diagram The LIN transceiver is compliant to LIN2.1 and SAEJ2602-2. The slope control at the LIN driver ensures secure data communication up to 20kBit/s. Data rates of up to 200kBit/s are also possible and enable high-speed data communication (for example, programming at line end over the LIN bus). The ATA6642 device's high-performance AVR core enables designers to build flexible and cost-effective embedded control applications. By executing powerful instructions within a single clock cycle, engineers can achieve throughputs approaching 1 MIPS per MHz, helping them, optimize power consumption 2 11 PORT B (8) PORT A (8) LIN/ UART RESET XTAL[1; 2] PB[0 to 7] PA[0 to 7] © 2012 / www.atmel.com VBAT 51Ω MISO MOSI SCK PB2 NCS TXD PB1 PA2 PA1 RXD PA2 PB0 NTRIG PA0 MOSI_ISP PA4 CL15 PA3 SCK_ISP PA5 100nF (1) DEBUG 10kΩ AVCC PA7 LIN NIRQ PB6 VBAT VDD CL15 PWM3 PB4 PWM2 PB5 10nF LIN 47nF CS3 Atmel ATA6642 CS2 CS1 PWM2 TXD NCS PWM2 SCK PWM3 MOSI PWM3 MISO WDOSC CS8 NIRQ CS7 RXD VDIV NTRIG CS6 VCC IREF GND CS5 VS 12 220pF PB3 PB7 CS4 12kΩ 51kΩ 10nF PWM1 GND 24 + PA2 SCK NCS MOSI MISO RXD TXD 100nF NTRIG 22µF 36 NRES NRES 100nF 1 AGND 10nF PA6 48 NRES VS NIRQ 10kΩ 10kΩ PA2 VCC 100nF + 2.2µF SCK_ISP NRES 1 2 3 4 5 6 VCC MOSI_ISP ISP Note: If the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin VDIV must be tied to high level until the reset phase ends (positive slope at pin NRES). (1) USI used as SPI, because PA2 is used for third PWM signal. Figure 4. Basic Application Example versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing the access of two independent registers in one single instruction executed within one clock cycle. One of the AVR core's main features is the LIN UART, designed to match as closely as possible to the LIN software application structure, thus helping to save development time and CPU resourses. A debug wire and an ISP interface are available to program the microcontroller. Application Examples Figure 4 shows a LIN slave application with the ATA6642 where several external devices are connected to the CSx pins of the HV switch interface. Only a minimum number of external parts is needed due to the device's very high level of integration. Automotive Compilation Vol. 9 Switch Control Application Eight high-voltage I/O ports are the heart of the ATA6642; these ports make the device perfectly suited for switch control applications with higher ESD requirements. These I/O ports allow a very flexible control of up to eight single switches, a switch matrix or any combinations of both, as shown in Figure 4, supplied by an internal current source in the range of 5mA to 25mA. Three of the I/O ports can be configured either as current sources (i.e., for switches towards ground) or as current sinks (i.e., for switches towards battery); the other five pins serve for current sourcing only. Each of the eight current sources delivers a constant current level derived from a reference value measured at the IREF pin. This pin is voltage stabilized (VIREF = 1.23 V typ.) so that the reference current directly depends on the externally applied resistor connected between the IREF pin and ground. The resulting current at the CSx pins is (1.23V/ RIref) x rICS. For example, with a 12kΩ resistor between IREF and GND, the value of the current at the CSx pins is 10mA (assuming IMUL for this, or due to a failure, e.g., a hanging switch or a shorted connection line—it can be prevented by disabling the current source in the SPI configuration register. = `0´ => rICS_H = 100). Missing and short-circuited resistors will be detected for failsafe reasons. In such cases, an internally generated reference current IIREFfs will be used instead to maintain a certain level of functionality. VS Each switch input has a HV comparator, a state-changedetection register for wake-up and interrupt request generation, and a voltage divider with a low-voltage output that can be fed through to the measurement pin VDIV. CSSM_x IIREF × rlCS CSE_x PWMY CSC_x State Change Detector d_statechange_x VCSxth (4V) The I/O interface is shown in Figure 5. HV Comp CSx MUX The ATA6642 offers flexible switch monitoring. A state-change detection circuitry is implemented so that each input can be configured to trigger an interrupt upon state change even during low-power mode. Therefore, the respective current source needs to be configured so that it is controlled via the corresponding pin. A rising edge on this pin enables the current source and delivers a stable switch readback signal at the CS pin. With the falling edge on the corresponding PWMy pin, the switch state is updated. If a change of state is monitored, an interrupt request is generated. If no wake-up occurs on a certain switch—either because there is no application demand dout_cs_x CSA[2 to 0] 3R VBATT VDIV VDIVP R AGND VDIVE IIREF × rlCS Figure 5. Principle Schematic of a High-side / Low-side Switch Interface VBAT 100nF NTRIG NIRQ TXD MISO RXD NCS MOSI SCK 51Ω (1) DEBUG 100nF PB6 VBAT VDD CL15 PB4 CS3 Atmel ATA6642 10kΩ 10nF CL15 CS1 47nF 12kΩ IREF NCS SCK MOSI MISO NIRQ TXD NRES PWM3 RXD CS8 NTRIG WDOSC VCC VDIV CS7 GND CS6 VS LIN CS2 CS5 51kΩ 10nF PWM2 PWM1 GND 24 + PA2 NCS SCK MOSI MISO RXD TXD 100nF NTRIG 22µF PB2 PB1 PB0 PA1 PA2 PA0 LIN CS4 12 36 PB3 PB7 PB5 3 x 2 Low Voltage Switch Matrix PA3 AVCC PA7 AGND PA6 1 NRES PA4 10nF PA5 48 NRES NIRQ 10kΩ 3 x 3 High Voltage Switch Matrix 10kΩ VCC 100nF + 2.2µF (1) Note: If the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin VDIV must be tied to high level until the reset phase ends (positive slope at pin NRES). Figure 6. 3 x 3 High-voltage and 3 x 2 Low-voltage Switch Matrix Application © 2012 / www.atmel.com If switches are placed outside and connected via a wiring harness to the ECU, the ATA6642 permits a complete diagnosis of short circuits or cable breaks. If ports are not used for switch detection, they can be switched off. PWM Control Application The ATA6642's switch interface current sources can be used to directly control pulse-width-modulated loads (i.e., switch scanning or LED driving). The PWM signal applied to the PWM1 to PWM3 input pin is used as control signal for the chosen current sources at the corresponding I/O ports. The assignment of the current sources to the three PWM input pins is shown in Table 1. The ATA6642 comprises a high-precision current source for multi-resistor coding. The scan current through the switches can be chosen to be sufficiently high so that it cleans the switches. Voltage Measurement Application Port CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 PWM1 X - - - - - X X PWM2 - X - - X X - - PWM3 - - X X - - - - In addition to the high-voltage (HV) comparator for simple switches, the ATA6642 device's HV I/O ports are also equipped with a voltage divider. The low-voltage signal at the tap of the divider is linearly dependant on the input voltage and is provided at the VDIV pin to enable analog voltage measurements on the HV pins by using one of the AVR core's ADC pins. Table 1. CSx Port Configuration Table The VDIV pin guarantees a voltage and temperature-stable output ratio of the selected input. It can be sourced either by the VBATT pin or by one of the switch input pins CS1 to CS8. Depending on the application, it might be required to control the HV I/O ports with different PWM signals. The ATA6642 device's AVR core provides three different PWM signals. In VBAT 51Ω NCS SCK MOSI MISO TXD NTRIG RXD CL15 MOSI_ISP SCK_ISP 100nF (1) DEBUG 10kΩ PB2 PB1 PB0 PA1 PA2 PA0 PA3 AVCC PA7 AGND PA6 1 PA4 10nF PA5 48 PB7 LIN NIRQ PB6 VBAT VDD CL15 PB4 CS3 Atmel ATA6642 PB5 CS4 NCS SCK RXD TXD MOSI PWM3 MISO WDOSC CS8 NIRQ CS7 NRES VDIV NTRIG CS6 VCC LIN 47nF CS1 IREF GND 10nF CS2 CS5 VS 12 220pF PB3 NRES 100nF 12kΩ 51kΩ 10nF PWM2 PWM1 24 + PA2 NCS SCK MOSI MISO RXD TXD 100nF NTRIG 22µF 36 GND NRES NIRQ 10kΩ USI used as SPI, because PA2 is used for third PWM signal. 10kΩ VCC 100nF + Figure 7. LIN Slave for HV/ PWM Control with ATA6642 Microcontroller Automotive Compilation Vol. 9 2.2µF (1)Note: If the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin VDIV must be tied to high level until the reset phase ends (positive slope at pin NRES). those applications, a universal serial interface (USI) needs to be used instead of the hardware SPI. This is because of the dual function of the pin PA2 (SPI master input/ slave output and PWM output A for timer/counter0). the applied LED, this LED can be connected to a single I/O HV port. The ATA6642 device is capable of driving up to 25mA per channel. In case a higher current is needed, two or more I/O HV ports can be combined. The USI provides the basic hardware resources for serial communication. Along with a minimum of control software, the USI allows for significantly higher transfer rates and uses less code space than merely software-based solutions. Interrupts are included to reduce the processor load. Example Controlling an RGB LED with the following forward current capabilities: • Red = 20mA • Green = 20mA • Blue = 10mA RGB LED Control Application can be done by setting a constant current of 10mA for all I/O HV ports. 20mA are achieved by connecting two I/O ports. In the case of the blue LED, which is only capable of 10mA, only one of the connected I/O ports needs to be switched on. With its constant current sources, the ATA6642 device is perfectly suited for LED control systems. The most typical application is shown in Figure 8, where the ATA6642 device controls an RGB LED. Depending on the current capability of VBAT 51Ω NCS SCK MOSI MISO TXD PA2 NTRIG RXD CL15 MOSI_ISP SCK_ISP 100nF (1) DEBUG 10kΩ PB2 PB1 PB0 PA1 PA2 PA0 PA3 AVCC AGND PA6 PA7 PB7 LIN NIRQ PB6 VBAT VDD CL15 PWM3 PB4 PWM2 PB5 10nF CS2 LIN 100nF VS CS1 TXD NCS PWM2 SCK PWM2 MOSI PWM3 MISO PWM3 NIRQ WDOSC CS8 RXD CS7 NTRIG VDIV VCC IREF CS6 GND CS5 VS 12 220pF CS3 Atmel ATA6642 CS4 12kΩ 10nF 51kΩ R PWM1 24 + G PA2 NCS SCK MOSI MISO RXD TXD 100nF NTRIG 22µF 36 PB3 NRES NRES 100nF 1 PA4 10nF PA5 48 B GND NRES NIRQ 10kΩ 10kΩ PA2 VCC 100nF + 2.2µF SCK_ISP NRES 1 2 3 4 5 6 VCC MOSI_ISP ISP USI used as SPI, because PA2 is used for third PWM signal. (1)Note: If the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin VDIV must be tied to high level until the reset phase ends (positive slope at pin NRES). Figure 8. LIN Slave for RGB LED Control © 2012 / www.atmel.com H-bridge Relay Control Application Conclusion The ATA6642 can also be used as a relay driver. In case the 20mA output current of each I/O port is not sufficient to drive the load, the output pins can be interconnected to achieve a higher load current. With its system-in-package (SiP) architecture and rich set of features the ATA6642 fulfills the increasingly demanding market requirements for improved system efficiency, higher integration and lower costs. The SiP device offers designers extended flexibility and is well suited for a broad range of LINrelated applications such as port/contact monitoring, switches (towards GND or VBAT), LED/ relay/ power transistor control or switches connected through the wiring harness. In the example shown in Figure 8, three outputs are connected, so that the minimum achievable output current is 3 x 20mA = 60mA. As an additional safety feature, the CS1 and CS2 HV interface pins are used as sense inputs that monitor the proper relay operation. The relays are configured as an H-bridge, which enables driving of a motor in both directions. A typical application example for such a configuration is a window lifter system. VBAT M 51Ω NTRIG NIRQ TXD MISO RXD NCS MOSI SCK 100nF (1) DEBUG NRES PB2 PB1 PA1 PB0 PA2 PA0 PA3 AVCC PA7 AGND PA6 1 PA4 10nF PA5 48 PB3 PB7 LIN PB6 VBAT PWM1 PB4 PWM2 PB5 CS3 Atmel ATA6642 CS4 CS2 CS1 NCS SCK MOSI TXD MISO PWM3 NIRQ WDOSC CS8 NRES CS7 RXD VDIV NTRIG CS6 VCC IREF GND CS5 VS 12 PWM2 12kΩ 51kΩ 10nF PWM2 PWM1 24 + GND PWM1 NCS SCK MOSI MISO RXD TXD 100nF NTRIG 22µF LIN 10nF CL15 VDD 100nF 36 NRES NIRQ 10kΩ 10kΩ MISO VCC 100nF + 2.2µF SCK NRES 1 2 3 4 5 6 ISP Note: If the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin VDIV must be tied to high level until the reset phase ends (positive slope at pin NRES). (1) Figure 9. LIN Slave Relay Driver Automotive Compilation Vol. 9 VCC MOSI Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441-0311 F: (+1)(408) 487-2600 | www.atmel.com © 2012 Atmel Corporation. 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