View detail for ULC Design Checklist

ULC Design Checklist
®
To perform the FPGA/CPLD toULC feasibility study and conversion rapidly and accurately, please fill out the
form below and supply the requested material.
1.
Customer
Company:
Address:
City/State:
Zip/Postal Code:
Telephone:
Technical Contact
Name:
Position:
Telephone:
Fax:
Email:
2.
FPGA to be Converted:
FPGA part type (e.g., Xilinx XC4013E-3PQ208C):
FPGA Package Type (e.g. 100 PQFP):
ULC Package Type if different from FPGA package type:
Program Name:
EAU (Estimated Annual Usage):
Application:
Approx. number of gates in the design (combinational and FFs, not RAM):
Approx. number of latches in the design (level-sensitive, not RAM):
Approx. amount of memory (bits) used in the design:
Number of I/O pins:
Input
Block RAM
Distributed RAM
Output
Bi-directional
Design Environment
If device is used in multiple sockets, do all sockets use the same program code?
3.
N/A
Yes
No
Yes
No
Yes
No
Initialization Information
Global Reset Pin (Master Clear) available? …………………………………………………………
Do you use the FPGAs POR (Power-On Reset)?…………….…….………………………..
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4.
Special Functions:
On chip oscillator (with external Crystal/RC). Frequency?
Yes
No
PLL or DLL ………………………………………………………………………………………
Yes
No
Is PLL/DLL programmable or fixed operation.…………………………....…....…
Input frequency (at CLKIN)?
Phase Shift?
0°
Programmable
Fixed
Output frequency?
90°
180°
270°
Memories (RAMs, DPRAMs, FIFOs)? ………………………………………………………….
Yes
No
Yes
No
Yes
No
Yes
No
Are there multiplier blocks inside (if yes, specify)?
Yes
No
If being converted from old ASIC, does design include custom cells?
Yes
No
If new RTL, and not proto'd, is design proven by sims/STA?
Yes
No
Yes
No
Timing Specification available?……………………………………………………………………… Yes
No
Setup/Hold time requirements on input pin(s) and output pin(s)? Please list………………….
Incl.
If yes, Synchronous? …………………………………………………………………….
Please specify on a separate sheet (initialization, size, single or dual port, timing).
Is there logic between memory outputs and receiving registers (if yes, specify)?
Do you use any IP (Intellectual Property) cores in the design?…………………………………
If yes, specify cores and whether each is from FPGA vendor or third party.
5.
Clocking Scheme Information
Does your design use one clock only?…………………………………………………………..
Primary (master) clock Pin Number, Name, and Frequency:
Other External Clock and Frequency(list on separate sheet if more clocks)
None
Do any signals cross clock domains? ………………………………………………………………… Yes
6.
No
Inputs and Outputs
Provide a complete pin out list including:
Pin #, signal name, I/O, TTL/CMOS, output drive, output pull up/down, triggered inputs, ext. crystal, etc.
The Customer will be asked to sign off on this list as reproduced by Atmel’s CAD system.
General IO's
Inputs
Outputs
TTL
CMOS
Drive(s):
Other (PCI, GTL, GTL+, LVDS, etc.)
mA
Load(s):
pF
Special noise standard? If so, please describe on a separate sheet. …………………………...
Is boundary scan (JTAG) used on FPGA for
programming?
Boundary Scan needed on ULC (beyond internal scan)?
Yes
No
test purposes at board level?
No
Atmel / IEEE
No
Spare pins available for ULC internal scan (list)
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VOLTAGES
1.8V
PERIPHERY
Outputs
1.8V
Inputs
2.5V
2.5V
3.3V
3.3V
5V
5V
1.8V
Volt?
2.5V
3.3V
CORE
5V
1.8V
Yes
2.5V
No
3.3V
5V
Outputs
Is output pull-up voltage the same or different among outputs?
Are inputs driven while the circuit is not powered?________________
7.
Dynamic Consumption:
Max dynamic consumption required
8.
mW
at frequency
MHz
Simulation Vectors:
Pin level stimuli in ASCII format, or VHDL/Verilog test bench (preferred)……………………
9.
(specify)
Yes
No
Customer CAD environment:
Synthesis:
Synopsys
Leonardo
Synplicity
Logic Simulator:
Modelsim
None
Other
Timing Analysis:
Primetime
None
Other
None
Other
10. Environmental
Temp. Range:
Commercial (0°C to 70°C)
Quality Flow:
Commercial/Industrial
Military-883 Class B
Military-883 Class S
QML-Q
QML-V
Military Temp (-2)
SEU:
N/A
Radiation Tolerance:
Total Dose:
Industrial (-40°C to 85°C)
Military Temp (-55°C to 125°C)
(All RT parts are latchup immune (>100MeV/mg/cm²))
11. Marking Instructions:
or
Provide part number for ULC top mark:
Incl.
If company logo is desired, include PC file and paper copy of logo
12. Design File Format
VHDL source file, or
Verilog source file, or
Flat edif/verilog gate-level netlist
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Checklist
prepared by:
Date:
COMMENTS:
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Atmel Corporation