Features • • • • • • • • • • • • • • • • • • • • • • High-performance ULC Family Suitable for Large-sized CPLDs and FPGAs From 46K Gates up to 780K Gates Supported From 18 Kbit to 390 Kbit DPRAM Compatible with Xilinx or Altera Pin-counts to Over 976 pins Any Pin–out Matched Full Range of Packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA Low Quiescent Current: 0.3 nA/gate Available in Commercial, Industrial and Military Grades 0.35 µm Drawn CMOS, 3 and 4 Metal Layers Library Optimised for Synthesis, Floor Plan & Testability Generation (ATPG) High Speed Performances: – 150 ps Typical Gate Delay @3.3V – Typical 600 MHz Toggle Frequency @3.3V – Typical 360 MHz Toggle Frequency @2.5V High System Frequency Skew Control: – Clock Tree Synthesis Software Low Power Consumption: – 0.25 µ W/Gate/ MHz @3.3V – 0.18 µW/Gate/ MHz @2.5V Power on Reset (Internal) Standard 2, 4, 6, 8,10, 12 and 18mA I/Os CMOS/TTL/PCI LVCMOS, LVTTL, GTL, HSTL, LVDS Interfaces ESD (2 kV) and Latch-up Protected I/O High Noise & EMC Immunity: – I/O with Slew Rate Control – Internal Decoupling – Signal Filtering between Periphery & Core Thick oxide matrices allowing 5V Compliance Internal Regulator 5V -> 3.3V PLL 0.35µm with Integrated Filter 0.35 µm ULC Series with Embedded DPRAM UA1E Description The UA1E series of ULCs is well suited for conversion of large sized CPLDs and FPGAs. We can support within one ULC from 18 Kbits to 390 Kbits DPRAM and from 46 Kgates to 780 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA die size. DPRAM blocks are compatible with Xilinx or Altera FPGA blocks. Devices are implemented in high–performance CMOS technology with 0.35µm (drawn) channel lengths, and are capable of supporting flip–flop toggle rates of 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V. The architecture of the UA1E series allows for efficient conversion of many PLD architecture and FPGA device types with higher IO count. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary–scan and scan–path testing. Conversion to the UA1E series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA1E series has a very low standby consumption of 0.3nA/gate typically commercial temperature, which would yield a standby current of 42µA on a 144,000 gates design. Operating consumption is a strict 4319D–ULC–04/08 function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared. The UA1E series provides several options for output buffers, including a variety of drive levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available if required. The UA1E series is designed to allow conversion of high performance 3.3V devices as well as 2.5V devices. Support of mixed supply conversions is also possible, allowing optimal trade–offs between speed and power consumption. Array Organization Table 1. Matrices Note: 2 Part Number Max Pads KGates DPRAM Kbits PLL USD700 700 780 390 4 USD594 594 590 230 3 USD492 492 520 243 2 USD432 432 374 144 2 USD384 384 300 99 0 USD312 312 150 72 0 USD256 256 124 48 2 USD228 228 98 38 2 USD210 210 95 18 2 USD170(1) 170 67 0 0 USD134(1) 134 33 0 0 1. Arrays with internal regulators 5V -> 3.3V and Power on Reset. UAE1 4319D–ULC–04/08 UAE1 Matrix Examples Figure 1. ATL35_M484E1 Matrix with 108 DPRAMS and 2 PLL’s PLL DPRAM PLL 3 4319D–ULC–04/08 Figure 2. ATL35_MI34E1 Matrix with 1 voltagte Regulator 5V - 3V and Power on Reset 5V - 3V Regulator POR Architecture The basic element of the UA1E family is called a cell. One cell can typically implement between one to four FPGA gates. Cells are located contiguously throughout the core of the device, with routing resources provided in three to four metal layers above the cells. Some cell blockage does occur due to routing, and utilization will be significantly greater with three metal routing than two. The sizes listed in the Product Outline are estimated usable amounts using three metal layers. I/O cells are provided at each pad, and may be configured as inputs, outputs, I/Os, VDD or VSS as required to match any FPGA or PLD pinout. In order to improve noise immunity within the device, separate VDD and VSS busses are provided for the internal cells and the I/O cells. I/O buffer interfacing I/O Flexibility 4 All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator could be located close to each buffer. UAE1 4319D–ULC–04/08 UAE1 I/O Options Inputs Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull up or pull down resistor. Fast Output Buffer Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen option. 36mA achievable, using 2 pads. Slew Rate Controlled Output Buffer In this mode, the p– and n–output transistors commands are delayed, so that they are never set “ON” simultaneously, resulting in a low switching current and low noise. These buffers are dedicated to very high load drive. 2.5V Compatibility The UA1E series of ULC’s is fully capable of supporting high–performance operation at 2.5V or 3.3V. The performance specifications of any given ULC design however, must be explicitly specified as 2.5V, 3.3V or both. Power Supply and Noise Protection In order to improve the noise immunity of the UA1E core matrix, several mechanisms have been implemented inside the UA1E arrays. Two types of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. The speed and density of the UA1E technology cause large switching current spikes, for example when: • 16 high current output buffers switch simultaneously, or • 10% of the 700 000 gates are switching within a window of 1ns. Sharp edges and high currents cause some parasitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the setting time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). I/O Buffers Switching Protection Matrix Switching Current Protection PLL Characterisitics Three features are implemented to limit the noise generated by the switching current: • The power supplies of the input and output buffers are separated. • The rise and fall times of the output buffers can be controlled by an internal regulator. • A design rule concerning the number of buffers connected on the same power supply line has been imposed. This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: • Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. • A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. • A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers. The following list the caracteristics of the PLL 0.35µm with integrated filter: • Input frequency from 5 to 100 MHz 5 4319D–ULC–04/08 Application • Outout frequency from 20 to 200 MHz • Frequency multiplication by 2 or 4 • Phase shifter 0, 90, 180, 270 degrees • Output lock signal: lock_in time: 50us • Supply: 3.3V • Power consumption max: 3.32mA Use for XILINX and ALTERA conversions, in the following cases: • clock deskew • frequency synthesis • clock latency reduction • phase shift Note: 6 For detailed information, please contact our technical center. UAE1 4319D–ULC–04/08 UAE1 Electrical Characteristics Absolute Maximum Ratings *NOTICE: Max Supply Voltage (VDD)...................................................4.0V Max Supply Voltage (VDD5).................................................6.0V Input Voltage (VIN)......................................................VDD+0.5V Input voltage 5V Tolerant/Compliant ........................VDD5 +0.5V Storage Temperature...........................................-65° to 150°C Operating Ambient Temperature.......................-55° to 125°C Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. This value is based on the maximum allowable die temperature and the thermal resistance of the package. Recommended Operating Range VDD ............................................................................................ 2.5V ± 5% or 3.3V ± 5% VDD5 ........................................................................................... 5V ± 5% Operating Temperature Commercial ...............................................................................0° to 70°C Industrial ....................................................................................-40° to 85°C Military ...................................................................................... -55° to 125°C 7 4319D–ULC–04/08 DC Characteristics 2.5V Supply for Core and Periphary Symbol Parameter Buffer Min TA Operating Temperature All -40 VDD Supply Voltage All 2.3 IIH High level input current IIL Low Level input current Max Unit +85 °C 2.7 V CMOS 10 µA VIN = VDD,VDD = VDD (max) PCI 10 µA VIN = VSS,VDD = VDD (max) CMOS Typ 2.5 -10 Conditions PCI IOZ IOS VIH VIL Output Current Output short-circuit current High-level Input Voltage Low-Level Input Voltage All -10 9 PO11 6 CMOS 0.7VDD PCI 0.475VDD CMOS Schmitt 0.7VDD 0.325VDD CMOS Schmitt 1.0 0.5 High-Level output voltage PO11 0.7VDD PCI 0.9VDD VOUT = VDD,VDD = VDD (max) VOUT = VSS,VDD = VDD (max) 1.5 PCI VOH VIN = VDD or VSS, VDD = VDD (max), No Pull-up V 0.3VDD CMOS Schmitt µA mA CMOS Hysteresis Low-Level output voltage 10 PO11 Vhys VOL 8 High-Impedance State V 0.3VDD V V PO11 0.4 PCI 0.1VDD V IOH = 1.4mA,VDD = VDD (min) IOH = -500µA IOL = 1.4mA,VDD = VDD (min) IOL = 1.5mA UAE1 4319D–ULC–04/08 UAE1 3.3V Supply for Core and Periphery Symbol Parameter Buffer Min TA Operating Temperature All -40 VDD Supply Voltage All 3.0 IIH High level input current IIL Low Level input current Max Unit +85 °C 3.6 V CMOS 10 µA VIN = VDD,VDD = VDD (max) PCI 10 µA VIN = VSS,VDD = VDD (max) CMOS Typ 3.3 -10 Conditions PCI IOZ IOS VIH VIL High-Impedance State Output Current Output short-circuit current High-level Input Voltage Low-Level Input Voltage All -10 PO11 14 PO11 -9 CMOS, LVTTL 2.0 PCI 0.475VDD CMOS Schmitt 2.0 0.325VDD CMOS/TTL-level Schmitt 1.1 0.6 VOH High-Level output voltage PO11 0.7VDD PCI 0.9VDD Low-Level output voltage VOUT = VDD,VDD = VDD (max) VOUT = VSS,VDD = VDD (max) 1.7 PCI TTL-level Schmitt VIN = VDD or VSS, VDD = VDD (max), No Pull-up V 0.8 Hysteresis µA mA CMOS Vhys VOL 10 V 0.8 V V PO11 0.4 PCI 0.1VDD V IOH = 2mA,VDD = VDD (min) IOH = -500µA IOL = 2mA,VDD = VDD (min) IOL = 1.5mA 9 4319D–ULC–04/08 3.3V or 5V supply for Periphery, 3.3V for Core Symbol Parameter Buffer Min TA Operating Temperature All -55 VDD Supply Voltage 5V Tolerant 3.0 VDD5 Supply Voltage 5V Compliant 4.5 IIH High level input current CMOS IIL Low Level input current CMOS -10 All -10 High-Impedance State IOZ IOS VIH VIL Output Current Output short-circuit current High-level Input Voltage Low-Level Input Voltage Unit +125 °C 3.3 3.6 V 5.0 5.5 V 10 µA VIN = VDD,VDD = VDD (max) µA VIN = VSS,VDD = VDD (max) 10 8 PO11V -7 PICV5 2.0 5.0 CMOS/TTL-level Schmitt 2.0 1.7 5.5 V V 0.8 CMOS/TTL-level Schmitt 1.1 0.8 0.6 VOH High-Level output voltage PO11V 0.7VDD PO11V5 0.7VCC VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD,VDD = VDD (max) mA 0.5VCC TTL-level Schmitt Conditions µA PICV5 Hysteresis Low-Level output voltage Max PO11V Vhys VOL Typ VOUT = VSS,VDD = VDD (max) V IOH = -1.7mA V PO11V 0.5 PO11V5 0.5 IOH = -1.7mA V IOL = 1.7mA I/O Buffer 10 Symbol Parameter Typ Unit Conditions C IN Capacitance, Input Buffer (Die) 2.4 pF 3.3V C OUT Capacitance, Output Buffer (Die) 5.6 pF 3.3V C I/O Capacitance, Bidirectional 6.6 pF 3.3V UAE1 4319D–ULC–04/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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