CN-0335: 12-Bit, 300 kSPS, Single-Supply, Fully Isolated, Data Acquisition...

Circuit Note
CN-0335
Devices Connected/Referenced
Circuits from the Lab® reference designs are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit http://www.analog.com/CN0335.
AD8606
Precision, Low Noise, Dual CMOS, Railto-Rail Input/Output Op Amp
AD7091R
1 MSPS, Ultralow Power, 12-Bit ADC
ADuM5401
Quad-Channel, 2.5 kV Isolators with
Integrated DC-to-DC Converter
12-Bit, 300 kSPS, Single-Supply, Fully Isolated, Data Acquisition System
for ±10 V Inputs
EVALUATION AND DESIGN SUPPORT
The system processes ±10 V input signals using a single 3.3 V
supply. The total error after room temperature calibration is less
than ±0.1% FSR over a ±10°C temperature change, making it
ideal for a wide variety of industrial measurements.
Circuit Evaluation Boards
CN0335 Circuit Evaluation Board (EVAL-CN0335-PMDZ)
SDP/PMD Interposer Board (SDP-PMD-IB1Z)
System Demonstration Platform (EVAL-SDP-CB1Z)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
The small footprint of the circuit makes this combination an
industry-leading solution for data acquisition systems where the
accuracy, speed, cost, and size play a critical role. Both data and
power are isolated, thereby making the circuit robust to high
voltages and also ground-loop interference often encountered
in harsh industrial environments.
CIRCUIT FUNCTION AND BENEFITS
The circuit shown in Figure 1 is a completely isolated 12-bit,
300 kSPS data acquisition system utilizing only three active devices.
U1B
1/2 AD8606
U2
ADuM5401
(C-GRADE)
VREF
R2
12kΩ
R1
52.3kΩ
+3.3V
+3.3V
U1A
1/2 AD8606
GND_ISO
R3
51Ω
REFOUT
VIN
C9
4.7nF
INPUT
–10V TO +10V
1
C10
DNP
2
R5
12kΩ
VDD
VISO
U3
AD7091R
SS
SCLK
VOB
VIB
SCK
CONVST
VOC
VIC
CONVST
VID
VOD
+3.3V
VSEL
GNDISO
GND1
ISOLATION
GND_ISO
GND_ISO
GND_ISO
MISO
RCOUT
R6
10kΩ
CON
J2
GND
VIA
C8
1µF
GND_ISO
+3.3V_IN
VOA
SDO
VREF
2.5V
VDD1
GND1
CS
GND REGCAP VDRIVE
GND_ISO
R4
52.3kΩ
+3.3V
GNDISO
TP1
+0.1V TO +2.4V
GND_ISO
GND
PMOD CON
12-PIN
J1
11649-001
C11
DNP
Figure 1. ±10 V Single Supply Data Acquisition System with Isolation (All Connections and Decoupling Not Shown)
Rev. A
Circuits from the Lab® reference designs from Analog Devices have been designed and built by Analog
Devices engineers. Standard engineering practices have been employed in the design and
construction of each circuit, and their function and performance have been tested and verified in a lab
environment at room temperature. However, you are solely responsible for testing the circuit and
determining its suitability and applicability for your use and application. Accordingly, in no event shall
Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due
toanycausewhatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage)
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Fax: 781.461.3113
©2014 Analog Devices, Inc. All rights reserved.
CN-0335
Circuit Note
The circuit consists of an input signal conditioning stage, an
ADC stage, and an output isolation stage. The ±10 V input
signal is level shifted and attenuated by the U1A op amp that is
one-half of the dual AD8606. The output of the op amp is 0.1 V
to 2.4 V, which matches the input range of the ADC (0 V to
2.5 V) with 100 mV headroom to maintain linearity. The
buffered voltage reference (VREF =2.5 V) from the ADC is used
to generate the required offset. Resistor values can be modified
to accommodate other popular input ranges as described later
in this circuit note.
The circuit design allows single supply operation. The minimum
output voltage specification of the AD8606 is 50 mV for a 2.7 V
power supply and 290 mV for 5 V power supply with 10 mA
load current, over the temperature range of −40°C to +125°C. A
minimum output voltage of 45 mV to 60 mV is a conservative
estimate for a 3.3 V power supply, a load current less than
1 mA, and a narrower temperature range.
Considering the tolerances of the parts, the minimum output
voltage (low limit of the range) is set to 100 mV to allow a safety
margin. The upper limit of the output range is set to 2.4 V in
order to give 100 mV headroom for the positive swing at the
ADC input. Therefore, the nominal output voltage range of the
input op amp is 0.1 V to 2.4 V.
The second half of the AD8606 (U1B) is used to buffer the
internal 2.5 V voltage reference of the AD7091R (U3) ADC.
The AD8606 is chosen for this application because of its low offset
voltage (65 μV maximum), low bias current (1 pA maximum)
and low noise (12 nV/√Hz maximum). Power dissipation is
only 9.2 mW on a 3.3 V supply.
A single-pole RC filter (R3/C9) follows the op amp output stage
to reduce the out-of-band noise. The cutoff frequency of the RC
filter is set to 664 kHz. An optional second order filter (R4, C10,
and R1, R2, C11) can be added to reduce the filter cutoff frequency
even further in case of low frequency industrial noise. In such
case, the sampling rate of the AD7091R can be reduced because
of the lower signal bandwidth.
Galvanic isolation is provided by the ADuM5401 (C-Grade)
quad channel digital isolator. In addition to the isolated output
data, the ADuM5401 also provides isolated 3.3 V for the circuit.
The ADuM5401 is not required for normal circuit operation
unless isolation is needed. The ADuM5401 quad-channel,
2.5 kV isolators with integrated dc-to-dc converter, is available
in a small 16-lead SOIC. Power dissipation of the ADuM5401
with a 7 MHz clock is approximately 140 mW.
The AD7091R requires a 50 MHz serial clock (SCLK) to achieve
a 1 MSPS sampling rate. However, the ADuM5401 (C-grade)
isolator has a maximum data rate of 25 Mbps that corresponds
to a maximum serial clock frequency of 12.5 MHz. In addition,
the SPI port requires that the trailing edge of the SCLK clock
the output data into the processor, therefore the total round-trip
propagation delay through the ADuM5401 (120 ns maximum)
limits the upper clock frequency to 1/120 ns = 8.3 MHz.
Even though the AD7091R is a 12-bit ADC, the serial data is
formatted into a 16-bit word to be compatible with the processor
serial port requirements. The sampling period, TS, therefore
consists of the AD7091R 650 ns conversion time plus 58 ns
(extra time required from data sheet, t1 delay + tQUIET delay) plus
16 clock cycles for the SPI interface data transfer.
TS = 650 ns + 58 ns + 16 × 120 ns = 2628 ns
fS = 1/TS = 1/2628 ns = 380 kSPS
In order to provide a safety margin, a maximum SCLK of
7 MHz and a maximum sampling rate of 300 kSPS is
recommended. The digital SPI interface can be connected to the
microprocessor evaluation board using the 12-pin Pmodcompatible connector (Digilent Pmod Specifications).
Circuit Design
The circuit shown in Figure 2 attenuates and level shifts the −10 V
to +10 V input signal to the ADC input range of 0.1 V to 2.4 V.
The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its
ultralow power 349 μA at 3.3 V (1.2 mW) which is significantly
lower than any competitive ADC currently available in the market.
The AD7091R also contains an internal 2.5 V reference with
±4.5 ppm/oC typical drift. The input bandwidth is 7.5 MHz,
and the high speed serial interface is SPI compatible. The
AD7091R is available in a small footprint 10-lead MSOP.
The total power dissipation of the circuit (excluding the
ADuM5401 isolator) is approximately 10.4 mW when
operating on a 3.3 V supply.
Rev. A | Page 2 of 8
R1
52.3kΩ
R2
12kΩ
+3.3V
U1A
1/2 AD8606
GND_ISO
OUTPUT
+0.1V TO +2.4V
GND_ISO
INPUT
–10V TO +10V
1
R4
52.3kΩ
R5
12kΩ
VREF
2.5V
GND_ISO
R6
10kΩ
2
GND_ISO
GND_ISO
Figure 2. Input Voltage Signal Conditioning Circuit
11649-002
CIRCUIT DESCRIPTION
Circuit Note
CN-0335
The transfer function is obtained from the superposition principle:
V OUT = V IN
= V IN
R4 R6 

R2 
R2 
1+
 + V REF
1+
=




R4 + R5 R6 
R1 
R5 + R4 R6 
R1 
R
R4 + R
R5 R6
R0
k + V REF
R5 + R0
k = V IN GAIN + OFFSET
(1)
where:
R = R5 R6 =
R5R6 ,
R4R6
R0 = R4 R6 =
R5 + R6
R4 + R6
(2)
In the actual circuit the nearest available standard resistor
values were chosen for R4 and R5. The values selected were R4
= 52.3 kΩ and R5 = 12 kΩ. Note that R1 = R4 and R2 = R5.
If these values are chosen carefully, the overall error due to
substituting standard value resistors can be made less than a few
percent. However, use Equation 1 to recalculate the U1A op
amp output for ±10 V inputs to ensure that the required
headroom is preserved.
The absolute accuracy in this type of circuit is primarily
determined by the resistors, and therefore gain and offset
calibration is required to remove the error due to standard value
substitution and resistor tolerances.
Calculation of Resistor Values for Different Input Ranges
and k =  1 + R2 


R1 

(3)
Calculation of the Gain, Output Offset, and the Resistor
Values
For input ranges other than ±10 V complete the following
calculation steps.
Define the input span, the output span, and the offset:
For input voltage range ±10 V, the calculations are as follows.
The gain of the circuit is:
GAIN =
∆V OUT
∆V IN
=
2.4 V − 0.1 V
+ 10 V − ( −10 V)
=
2.3 V
= 0.115
(4)

R2 
R
=
1+
k
GAIN =


R4 + R5 R6 
R1  R4 + R
OFFSET = V OUT ( V IN = 0 V) = 0.1 V +
∆VOUT
+ VOUT _ MIN
2
(13)
GAIN =
∆VOUT
∆VIN
(14)
Calculate the offset:
2.4 V − 0.1 V
2
Offset =
= 1.25 V
(6)

R0
R2 
 = V REF
1+
k


R5 + R0
R5 + R4 R6 
R1 
R4 R6

R2 

k =  1 +

R1 

GAIN =
(9)
Using Equation 2 for the resistors R and R0, and the ratios in
Equation 8 and Equation 9, the ratio R4/R6 can be calculated:
(10)
(16)
R
R4 + R
(17)
k
Calculate the ratio R5/R0, using:
Offset = V REF
(8)
From Equation 7, for VREF = 2.5V and k =1.23 the ratio R5/R0
can be calculated:
(15)
Calculate the ratio R4/R, using:
(7)
From Equation 4, for k =1.23 (this value can vary, depending on
the value of the standard value resistors R1 and R2), the ratio
R4/R can be calculated:
∆VOUT
+ VOUT _ MIN
2
Choose the value for the parameter k:
and according to the transfer function:
R4 = 5.346 R6
(12)
Offset =
(5)
The output offset of the circuit is:
R5 = 1.46 R0
∆VOUT = VIOUT _ MAX − VOUT _ MIN
Calculate the gain:
R5 R6
R4 = 9.696 R
(11)
20 V
and according to the transfer function:
OFFSET = V REF
∆VIN = VIN _ MAX − VIN _ MIN
R0
R5 + R0
k
(18)
Replace R and R0 in Equation 17 and Equation 18 with the
values defined in Equation 2, and solve both equations find the
ratio R4/R6.
Choose a value for the resistor R6. Calculate R4 using the ratio of
R4/R6. Knowing the values for R4 and R6, calculate R5 using
Equation 2 and the R4/R6 ratio. Calculate R2 and R1 using
Equation 16. It is reasonable to choose R1 = R4 and calculate R2.
From Equation 8, Equation 9, and Equation 10, the resistors R4,
R5, and R6 can be calculated. For example choosing R6 = 10 kΩ
leads to R4 = 53.46 kΩ, and R5 =12.3 kΩ.
Rev. A | Page 3 of 8
CN-0335
Circuit Note
Effect of Resistor Temperature Coefficients on Overall
Error
Test Data Before and After Two-Point Calibration
Equation 1 shows that the output voltage is a function of five
resistors: R1, R2, R4, R5, and R6. The sensitivity of the full-scale
output voltage at TP1 to small changes in each of the five
resistors was calculated using a simulation program. The input
voltage to the circuit was +10 V. The individual sensitivities
calculated were SR1 = 0.19, SR2 = 0.19, SR4 = 0.39, SR5 = 0.11, SR6 =
0.50. Assuming the individual temperature coefficients combine
in a root-sum-square (rss) manner, then the overall full-scale
drift using 100 ppm/°C resistors is approximately:
Full scale drift =
To perform the two-point calibration, −10 V is first applied to
the input, and the ADC output code is recorded as Code_1.
Then +10 V is applied to the input, and the ADC output code is
recorded as Code_2. The gain factor is calculated by
GF =
Code_2 − Code_1
The input voltage can now be calculated corresponding to any
output code, Code_x, using the equation:
V IN = −10 V + GF ( Code_x − Code_1) .
The error before calibration is obtained by comparing the ideal
transfer function calculated using the nominal values of the
components, and real circuit transfer function without
calibration. The tested circuits have been built with resistors
having ±1% tolerance. The test results do not include
temperature changes.
=100 ppm/°C √(SR12 + SR22 + SR42 + SR52 + SR62)
=100 ppm/°C √(0.192 + 0.192 + 0.392 + 0.112 + 0.502)
= 69 ppm/°C
The full scale drift of 69 ppm/°C corresponds to 0.0069%
FSR/°C. Using 25 ppm/°C resistors reduces the drift error to
0.25 × 69 ppm/°C = 17 ppm/°C, or 0.0017% FSR/°C.
Effect of Active Component Temperature Coefficients on
Overall Error
The dc offsets of the AD8606 op amps and the AD7091R ADC
are eliminated by the calibration procedure.
The graph in Figure 3 shows test results for percent error (FSR)
before and after calibration at ambient temperature. As it is shown,
the maximum error before calibration is about 0.23% FSR.
After calibration, the error decreases to ±0.03% FSR, which
approximately corresponds to 1 LSB error of the ADC.
0.25
The offset drift of the ADC AD7091R internal reference is
4.5 ppm/°C typical and 25 ppm/°C maximum.
0.20
ERROR (% FSR)
The offset drift of the AD8606 op amp is 1μV/°C typical and
4.5μV/°C maximum.
The error due to the U1A input AD8606 is referenced to the
2.3 V output range and is therefore 2 ppm/°C. The error due to
the U1B reference buffer is referenced to 2.5 V and is also
approximately 2 ppm/°C.
0.15
0.10
0.05
0
–0.05
–10
11649-003
Note that resistor drift is the largest contributor to total drift if
50 ppm/°C or 100 ppm/°C resistors are used, and the drift due
to active components can be neglected.
ERROR BEFORE CALIBRATION
ERROR AFTER CALIBRATION
The total drift error is summarized in Table 1. These errors do
not include the ±1 LSB integral nonlinearity error of the AD7091R.
–5
0
INPUT VOLTAGE (V)
5
10
Figure 3. Circuit Test Error Before and After Room Temperature Calibration
PCB Layout Considerations
Table 1. Error Due to Temperature Drift
Error Source
Resistors (1%, 100 ppm/°C)
AD7091R (∆VVREF/∆T = 25 ppm/°C)
AD8606, U1A (∆VOS/∆T= 4.5 μV/°C), 2
ppm/°C, Referenced to 2.3 V
AD8606, U1B (∆VOS/∆T= 4.5 μV/°C), 2
ppm/°C, Referenced to 2.5 V
Total FSR Error Temperature Coefficient
(100 ppm/°C Resistors)
Total % FSR Error for ∆T=±10°C (100 ppm/°C
Resistors)
Total % FSR Error for ∆T=±10°C (25 ppm/°C
Resistors)
20 V
Total Error
±0.0069% FSR/°C
±0.0025% FSR/°C
±0.0002% FSR/°C
±0.0002% FSR/°C
±0.0098% FSR/°C
±0.098% FSR
±0.046% FSR
In any circuit where accuracy is crucial, it is important to consider
the power supply and ground return layout on the board. The
PCB should isolate the digital and analog sections as much as
possible. The PCB for this system was constructed in a simple
2-layer stack up, but a 4-layer stack up gives better EMS. See the
MT-031 Tutorial for more information on layout and grounding
and the MT-101 Tutorial for information on decoupling
techniques. Decouple the power supply to AD8606 with 10 μF
and 0.1 μF capacitors to properly suppress noise and reduce ripple.
Place the capacitors as close to the device as possible with the
0.1 μF capacitor having a low ESR value. Ceramic capacitors are
advised for all high frequency decoupling. Power supply lines
should have as large trace width as possible to provide a low
impedance path and to reduce glitch effects on the supply line.
Rev. A | Page 4 of 8
Circuit Note
CN-0335
COMMON VARIATIONS
The ADuM5401 isoPower integrated dc-to-dc converter requires
power supply bypassing at the input and output supply pins. Note
that low ESR bypass capacitors are required between Pin 1 and
Pin 2 and between Pin 15 and Pin 16, as close to the chip pads
as possible. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended
capacitor values are 0.1 μF and 10 μF for VDD1 and VISO. The
smaller capacitor must have a low ESR, for example, use of a
ceramic capacitor is advised. The total lead length between the
ends of the low ESR capacitor and the input power supply pin
must not exceed 2 mm. Installing the bypass capacitor with
traces more than 2 mm in length may result in data corruption.
Consider bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16, unless both common ground pins are connected
together close to the package. For more information, see the
ADuM5401 datasheet.
The circuit is proven to work with good stability and accuracy
with component values shown. Other precision op-amps and
other ADCs can be used in this configuration to convert ±10V
input voltage range to digital output and for other various
applications for this circuit.
The circuit in Figure 1 can be designed for other than ±10 V
input voltage ranges, following the equations given in the
Circuit Design section. Table 2 shows the resistor calculations
for some standard voltage ranges.
Table 2. Component Values for Standard Voltage Ranges
Range (V)
±5
±2
±1
0 to 1
0 to 2
0 to 2.5
0 to 5
0 to 10
0 to 24
A complete documentation package including schematics,
board layout, and bill of materials (BOM) can be found at
www.analog.com/CN0335-DesignSupport.
High Voltage Capability
This PCB is designed in adherence with 2500 V basic insulation
practices. High voltage testing beyond 2500 V is not recommended.
Take appropriate care when using this evaluation board at high
voltages, and do not rely on the PCB for safety functions because it
has not been high potential tested (also known as hipot tested
or dielectric withstanding voltage tested) or certified for safety.
k
1.2
2
4
4
2
2
2
1
1
R4 (kΩ)
40.87
32.174
40.87
14.435
14.087
22.609
65.217
63.478
90.174
R5 (kΩ)
18.8
37
94
830
405
520
750
365
216
R6 (kΩ)
20
20
20
20
20
20
20
20
10
In the cases, when the lower range is zero and the upper range is
greater than the reference voltage the conversion does not need
gain (k = 1), and the circuit can be simplified. An example is
shown in Figure 4 for the input range 0 V to 10 V.
U1B
1/2 AD8606
U2
ADuM5401
(C-GRADE)
+3.3V
+3.3V
U1A
1/2 AD8606
REFOUT
R3
51Ω
C9
4.7nF
1
R4
63.4kΩ
C10
DNP
2
R5
365kΩ
VIN
VDD
VISO
U3
AD7091R
VOA
VIA
SS
VOB
VIB
SCK
CONVST
VOC
VIC
VID
VOD
+3.3V
VREF
VSEL
GNDISO
C8
1µF
CONVST
MISO
RCOUT
GND1
ISOLATION
GND_ISO
R6
20kΩ
+3.3V_IN
GND
CS
SDO
GND_ISO
VDD1
GND1
SCLK
GND REGCAP VDRIVE
GND_ISO
INPUT
–10V TO +10V
+3.3V
GNDISO
TP1
0.1V TO 2.4V
GND
PMOD CON
12-PIN
J1
GND_ISO
CON
GND_ISO
GND_ISO
Figure 4. 0 V to 10 V Single Supply Analog to Digital Conversion with Isolation (All connections and Decoupling Not Shown)
Rev. A | Page 5 of 8
11649-004
VREF
CN-0335
Circuit Note
The AD7091 is similar to the AD7091R, but without the voltage
reference output, and the input range is equal to the power
supply voltage. The AD7091 can be used with a 2.5 V ADR391
reference. The ADR391 does not require buffering, therefore a
single AD8605 can be used in the circuit.
The ADR391 is a precision 2.5 V band gap voltage reference,
featuring low power and high precision (9 ppm/°C of
temperature drift) in a tiny TSOT package.
The AD8608 is a quad version of the AD8605 and can be used
as a substitute for the AD8606, if additional precision op-amps
are needed.
The AD8601, AD8602 and AD8604 are single, dual, and quad
rail-to-rail, input and output, single-supply amplifiers featuring
very low offset voltage and wide signal bandwidth, that can be
used in place of AD8605, AD8606, and AD8608.
The AD7457 is a 12-bit, 100 kSPS, low power, SAR ADC, and
can be used in combination with the ADR391 voltage reference
in place of AD7091R, when a 300 kSPS throughput rate is not
needed.
CIRCUIT EVALUATION AND TEST
This circuit uses the EVAL-CN0335-PMDZ circuit board, the
SDP-PMD-IB1Z and the EVAL-SDP-CB1Z system
demonstration platform (SDP) evaluation board. The
interposer board SDP-PMD-IB1Z and the SDP board EVALSDP-CB1Z have 120-pin mating connectors. The interposer
board and the EVAL-CN0335-PMDZ board have 12-pin Pmod
matching connectors, allowing quick setup and evaluation of
the circuit’s performance. The EVAL-CN0335-PMDZ board
contains the circuit to be evaluated, as described in this note
and the SDP evaluation board is used with the CN0335
evaluation software to capture the data from the EVALCN0335-PMDZ circuit board.
Equipment Needed
• PC with a USB port Windows® XP or Windows Vista®
(32-bit), or Windows® 7/8 (64 or 32-bit)
• EVAL-CN0335-PMDZ circuit evaluation board
• EVAL-SDP-CB1Z SDP evaluation board
• SDP-PMD-IB1Z interposer board
• CN0335 evaluation software
• Precision voltage source
Getting Started
Load the evaluation software by placing the CN0335 evaluation
software disc in the CD drive of the PC. You also can download
the most up to date copy of the evaluation software from
CN0335 evaluation software. Using "My Computer," locate the
drive that contains the evaluation software disc and open the
setup.exe. Follow the on-screen prompts to finish the
installation. It is recommended to install all software
components to the default locations.
Functional Block Diagram
Figure 5 shows the functional diagram of the test setup.
Setup
1.
2.
3.
4.
5.
Connect the EVAL-CFTL-6V-PWRZ (+6 V dc power
supply) to SDP-PMD-IB1Z interposer board via the dc
barrel jack.
Connect the SDP-PMD-IB1Z (interposer board) to EVALSDP-CB1Z SDP board via the 120-pin ConA connector.
Connect the EVAL-SDP-CB1Z (SDP board) to the PC via
the USB cable.
Connect the EVAL-CN0335-PMDZ evaluation board to
the SDP-PMD-IB1Z interposer board via the 12-pin
header Pmod connector.
Connect the voltage source (voltage generator) to the
EVAL-CN0335-PMDZ evaluation board via the terminal
block J2.
Test
Launch the evaluation software. The software communicates to
the SDP board if the Analog Devices System Development
Platform drivers are listed in the Device Manager. After USB
communications are established, the SDP board can be used to
send, receive, and capture serial data from the EVAL-CN0335PMDZ board. Data can be saved in the computer for various
values of input voltages. Information and details regarding how
to use the evaluation software for data capturing can be found
at CN0335 Software User Guide.
A photo of the EVAL-CN0335-PMDZ board is shown in Figure 6.
Rev. A | Page 6 of 8
Circuit Note
CN-0335
EVAL-CFTL-6V-PWRZ
6V WALL WART
EVAL-SDP-CB1Z
SDP-B BOARD
J1
EVAL-CN0335-PMDZ
J1
PMOD
J3
PMOD
120-PIN
J4
SDP-PMD-IB1Z
INTERPOSER BOARD
CON A
USB
11649-005
J2
PC
Figure 5. Test Setup Functional Block Diagram
11649-006
±10V
VOLTAGE
SOURCE
Figure 6. Photo of EVAL-CN0335-PMDZ Board
Rev. A | Page 7 of 8
CN-0335
Circuit Note
LEARN MORE
REVISION HISTORY
CN0335 Design Support Package:
http://www.analog.com/CN0335-DesignSupport
3/14—Rev. 0 to Rev. A
Chen, Baoxing, John Wynne, and Ronn Kliger. High Speed
Digital Isolators Using Microscale On-Chip Transformers,
Analog Devices, 2003
2/14—Revision 0: Initial Version
Change to Circuit Function and Benefits Section ........................ 1
Chen, Baoxing. iCoupler® Products with isoPower™ Technology:
Signal and Power Transfer Across Isolation Barrier Using
Microtransformers, Analog Devices, 2006
Ghiorse, Rich. Application Note AN-825, Power Supply
Considerations in iCoupler® Isolation Products, Analog
Devices
Krakauer, David. “Digital Isolation Offers Compact, Low-Cost
Solutions to Challenging Design Problems.”Analog Dialogue.
Volume 40, December 2006.
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND," Analog Devices
MT-101 Tutorial, Decoupling Techniques, Analog Devices
Wayne, Scott. “iCoupler® Digital Isolators Protect RS-232, RS485, and CAN Buses in Industrial, Instrumentation, and
Computer Apps, Analog Dialogue, Volume 39, Number 4,
2005.
Data Sheets and Evaluation Boards
AD8606 Data Sheet
AD7091R Data Sheet
ADuM5401 Data Sheet
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CN11649-0-3/14(A)
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