ISL65426MREP ® Data Sheet October 29, 2007 Enhanced Product (EP) 6.0A Dual Synchronous Buck Regulator with Integrated MOSFETs FN6575.0 Features • Specifications per DSCC VID V62/07639 • Full Mil-Temp Electrical Performance from -55°C to +125°C The ISL65426MREP is a high efficiency dual output monolithic synchronous buck converter operating over an input voltage range of 2.5V to 5.5V. This single chip power solution provides two output voltages which are selectable or externally adjustable from 1.2V to 80% of the supply voltage while delivering up to 6.0A of total combined output current when used at TJ of +125°C or less. The two PWMs are synchronized 180° out of phase reducing the RMS input current and ripple voltage. The ISL65426MREP switches at a fixed frequency of 1MHz and utilizes current-mode control with integrated compensation to minimize the size and number of external components. The internal synchronous power switches are optimized for good thermal performance, high efficiency, and eliminate the need for an external Schottky diode. A unique power block architecture allows partitioning to support one of four configuration options. One master power block is associated with each synchronous converter channel. Four floating slave power blocks allow the user to assign them to either channel. Proper external configuration of the power blocks is verified internally prior to soft-start initialization. Independent enable inputs allow for synchronization or sequencing soft-start intervals of the two converter channels. A third enable input allows additional sequencing for multi-input bias supply designs. Individual power good indicators (PG1, PG2) signal when output voltage is within regulation window. The ISL65426MREP integrates protection for both synchronous buck regulator channels. The fault conditions include overcurrent, undervoltage, and IC thermal monitor. High integration contained in a thin Quad Flat No-lead (QFN) package makes the ISL65426MREP an ideal choice to power many of today’s small form factor applications. A single chip solution for large scale digital ICs, like field programmable gate arrays (FPGA), requiring separate core and I/O voltages. Device Information The specifications for an Enhanced Product (EP) device are defined in a Vendor Item Drawing (VID), which is controlled by the Defense Supply Center in Columbus (DSCC). “Hotlinks” to the applicable VID and other supporting application information are provided on our website. • Controlled Baseline with One Wafer Fabrication Site and One Assembly/Test Site • Full Homogeneous Lot Processing in Wafer Fab • Current Density Validated per MIL-PRF-38535 • Full Traceability Through Assembly and Test by Date/Trace Code Assignment • Enhanced Process Change Notification • Enhanced Obsolescence Management • Eliminates Need for Up-Screening a COTS Component • High Efficiency of up to 90% • Fixed Frequency: 1MHz • Operates From 2.5V to 5.5V Supply • ±2.0% Reference • Flexible Output Voltage Options - Programmable 2-Bit VID Input - Adjustable Output From 1.2V to 4.0V • Power Blocks are Rated at: - 1A typ for TJ < +125°C and VIN Range 4.0V to 5.5V - 0.7A typ for TJ < +125°C and VIN Range 2.5V to 5.5V • Ultra-Compact DC/DC Converter Design • PWMs Synchronized 180° Out of Phase • Independent Enable Inputs and System Enable • Independent Output Digital Soft-Start • Power Good Output Voltage Monitor • Short-Circuit and Thermal-Overload Protection • Overcurrent and Undervoltage Protection Applications • FPGA, CPLD, DSP, and CPU Core and I/O Voltages • Point-of-Load Regulation in Distributed Power Systems Ordering Information VENDOR PART NUMBER VENDOR ITEM (Notes 1, 2) DRAWING TEMP. RANGE (°C) PKG. PACKAGE DWG. # ISL65426MREP V62/07639-01XB -55 to +125 50 Ld 5x10 L50.5x10 QFN NOTES: 1. Add -TK suffix for 1000 piece tape and reel. Please refer to TB347 for details on reel specifications. 2. Devices must be procured to the VENDOR PART NUMBER. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL65426MREP Pinout PG2 FB2 PG1 EN ISET2 EN2 EN1 FB1 ISL65426MREP (50 LD QFN) TOP VIEW 50 49 48 47 46 45 44 43 PGND 1 42 PGND PGND 2 41 PGND PGND 3 40 PGND PGND 39 PGND 4 LX1 5 38 LX6 LX1 6 37 LX6 PVIN1 7 36 PVIN6 PGND PVIN2 8 35 PVIN5 LX2 9 34 LX5 PGND 10 33 PGND PGND 11 32 PGND LX3 12 31 LX4 PVIN3 13 30 PVIN4 VCC 14 29 PGND VCC 15 28 PGND VCC 16 27 GND PGND 17 26 GND 2 PGND PGND V2SET2 V2SET1 ISET1 V1SET2 PGND V1SET1 18 19 20 21 22 23 24 25 FN6575.0 October 29, 2007 ISL65426MREP L50.5x10 50 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 7/06 5.00 0.10 M C A B 0.05 M C A B 4 0.25 0.50 43 A PIN 1 INDEX AREA (C 0.40) 50 42 1 26 17 9.20 0.50x16=8.00 REF 0.50 8.10 10.00 PIN 1 INDEX AREA 0.15 (4X) A 25 18 VIEW "A-A" 0.40±0.10 3.30 0.50x7=3.50 REF 0.40±0.10 TOP VIEW 4.20 BOTTOM VIEW SEE DETAIL "X" C 0.10 C SEATING PLANE 0.08 C SIDE VIEW MAX. 1.00 9.80 C 8.10 0.2 REF 5 0.00 MIN. 0.05 MAX. (46 x 0.50) DETAIL "X" (50 x 0.25) NOTES: 1. CONTROLLING DIMENSIONS ARE IN MM. (50 x 0.60) 2. UNLESS OTHERWISE SPECIFIED TOLERANCE : DECIMAL ±0.05 ANGULAR ±2× 3. DIMENSIONING AND TOLERANCE PER ASME Y 14.5M-1994. 4. DIMENSION LEAD WIDTH APPLIES TO THE PLATED TERMINAL AND IS MEASURED BETWEEN 0.23MM AND 0.28MM FROM THE TERMINAL TIP. 3.30 4.80 RECOMMENDED LAND PATTERN 5. TIEBAR SHOWN (if present) IS A NON-FUNCTIONAL FEATURE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 3 FN6575.0 October 29, 2007