FEATURES FUNCTIONAL BLOCK DIAGRAM Fully integrated single-lead ECG front end Low supply current: 170 µA (typical) Common-mode rejection ratio: 80 dB (dc to 60 Hz) Two or three electrode configurations High signal gain (G = 100) with dc blocking capabilities 2-pole adjustable high-pass filter Accepts up to ±300 mV of half cell potential Fast restore feature improves filter settling Uncommitted op amp 3-pole adjustable low-pass filter with adjustable gain Leads off detection: ac or dc options Integrated right leg drive (RLD) amplifier Single-supply operation: 2.0 V to 3.5 V Integrated reference buffer generates virtual ground Rail-to-rail output Internal RFI filter 8 kV HBM ESD rating Shutdown pin 20-lead 4 mm × 4 mm LFCSP package 20 HPSENSE 19 18 IAOUT REFIN S1 10kΩ A3 17 16 +VS GND HPDRIVE 1 FR 15 AC/DC 14 SDN 13 +IN 2 IA –IN 3 150kΩ AD8232 4 LOD+ 12 C1 RLDFB LEADS-OFF DETECTION A2 5 RLD LOD– 11 C2 S2 10kΩ A1 OPAMP+ SW 6 REFOUT 7 OPAMP– 8 9 OUT 10 10866-001 Data Sheet Single-Lead, Heart Rate Monitor Front End AD8232 Figure 1. APPLICATIONS Fitness and activity heart rate monitors Portable ECG Remote health monitors Gaming peripherals Biopotential signal acquisition GENERAL DESCRIPTION The AD8232 is an integrated signal conditioning block for ECG and other biopotential measurement applications. It is designed to extract, amplify, and filter small biopotential signals in the presence of noisy conditions, such as those created by motion or remote electrode placement. This design allows for an ultralow power analog-to-digital converter (ADC) or an embedded microcontroller to acquire the output signal easily. The AD8232 can implement a two-pole high-pass filter for eliminating motion artifacts and the electrode half-cell potential. This filter is tightly coupled with the instrumentation architecture of the amplifier to allow both large gain and high-pass filtering in a single stage, thereby saving space and cost. An uncommitted operational amplifier enables the AD8232 to create a three-pole low-pass filter to remove additional noise. The user can select the frequency cutoff of all filters to suit different types of applications. Rev. A To improve common-mode rejection of the line frequencies in the system and other undesired interferences, the AD8232 includes an amplifier for driven lead applications, such as right leg drive (RLD). The AD8232 includes a fast restore function that reduces the duration of otherwise long settling tails of the high-pass filters. After an abrupt signal change that rails the amplifier (such as a leads off condition), the AD8232 automatically adjusts to a higher filter cutoff. This feature allows the AD8232 to recover quickly, and therefore, to take valid measurements soon after connecting the electrodes to the subject. The AD8232 is available in a 4 mm × 4 mm, 20-lead LFCSP package. Performance is specified from 0°C to 70°C and is operational from −40°C to +85°C. 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Technical Support www.analog.com AD8232 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Standby Operation ..................................................................... 19 Applications ....................................................................................... 1 Input Protection ......................................................................... 19 Functional Block Diagram .............................................................. 1 Radio Frequency Interference (RFI) ........................................ 20 General Description ......................................................................... 1 Power Supply Regulation and Bypassing ................................ 20 Revision History ............................................................................... 2 Input Referred Offsets ............................................................... 20 Specifications..................................................................................... 3 Layout Recommendations ........................................................ 20 Absolute Maximum Ratings............................................................ 5 Applications Information .............................................................. 21 ESD Caution .................................................................................. 5 Eliminating Electrode Offsets .................................................. 21 Pin Configuration and Function Descriptions ............................. 6 High-Pass Filtering .................................................................... 21 Typical Performance Characteristics ............................................. 7 Low-Pass Filtering and Gain..................................................... 23 Instrumentation Amplifier Performance Curves ..................... 7 Driving Analog-to-Digital Converters .................................... 23 Operational Amplifier Performance Curves .......................... 10 Driven Electrode ........................................................................ 23 Right Leg Drive (RLD) Amplifier Performance Curves ....... 13 Application Circuits ....................................................................... 24 Reference Buffer Performance Curves .................................... 14 Heart Rate Measurement Next to the Heart ........................... 24 System Performance Curves ..................................................... 15 Exercise Application: Heart Rate Measured at the Hands .... 24 Theory of Operation ...................................................................... 16 Cardiac Monitor Configuration ............................................... 25 Architecture Overview .............................................................. 16 Instrumentation Amplifier ........................................................ 16 Portable Cardiac Monitor with Elimination of Motion Artifacts ....................................................................................... 25 Operational Amplifier ............................................................... 16 Packaging and Ordering Information ......................................... 27 Right Leg Drive Amplifier ......................................................... 17 Outline Dimensions ................................................................... 27 Reference Buffer ......................................................................... 17 Ordering Guide .......................................................................... 27 Fast Restore Circuit .................................................................... 17 Leads Off Detection ................................................................... 18 REVISION HISTORY 2/13—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 6 Change to Figure 17 ......................................................................... 9 Changes to Figure 22 and Figure 25............................................. 11 Changes to Figure 34 and Figure 36............................................. 14 Changes to Figure 45, Architecture Overview Section, and Instrumentation Amplifier Section .............................................. 17 Changes to Right Leg Drive Amplifier Section, Reference Buffer Section, Fast Restore Circuit Section, and Figure 48; Added Figure 46, Renumbered Sequentially ........................................... 18 Changes to Figure 49 ...................................................................... 19 Changes to AC Leads Off Detection Section and Standby Operation Section ........................................................................... 20 Changes to Input Referred Offsets Section ................................. 21 Changes to Figure 53 and High-Pass Filtering Section ............. 22 Changes to Additional High-Pass Filtering Options Section; Added Table 4 ................................................................................. 23 Changes to Low-Pass Filtering and Gain Section; Added Driving Analog-to-Digital Converters Section and Figure 61................ 24 Changes to Figure 62, Figure 64, and Heart Rate Measurement Next to the Heart Section .............................................................. 25 Changes to Exercise Application: Heart Rate Measured at the Hands and Figure 66 ...................................................................... 26 Changes to Figure 68...................................................................... 27 8/12—Revision 0: Initial Version Rev. A | Page 2 of 28 Data Sheet AD8232 SPECIFICATIONS VS = 3 V, VREF = 1.5 V, VCM = 1.5 V, TA = 25°C, FR=low, SDN=high, AC/DC = low, unless otherwise noted. Table 1. Parameter INSTRUMENTATION AMPLIFIER Common-Mode Rejection Ratio, DC to 60 Hz Power Supply Rejection Ratio Offset Voltage (RTI) Instrumentation Amplifier Inputs DC Blocking Input 1 Average Offset Drift Instrumentation Amplifier Inputs DC Blocking Input1 Input Bias Current Symbol Test Conditions/Comments Min Typ CMRR VCM = 0.35 V to 2.85 V, VDIFF = 0 V 80 86 dB VCM = 0.35 V to 2.85 V, VDIFF = ±0.3 V VS = 2.0 V to 3.5 V 76 80 90 dB dB PSRR VOS 3 5 10 0.05 50 1 25 1 IB TA = 0°C to 70°C Input Offset Current IOS TA = 0°C to 70°C Input Impedance Differential Common Mode Input Voltage Noise (RTI) Spectral Noise Density Peak-to-Peak Voltage Noise Input Voltage Range DC Differential Input Range Output Output Swing Short-Circuit Current Gain Gain Error Average Gain Drift Bandwidth RFI Filter Cutoff (Each Input) OPERATIONAL AMPLIFIER (A1) Offset Voltage Average TC Input Bias Current f = 1 kHz f = 0.1 Hz to 10 Hz f = 0.5 Hz to 40 Hz TA = 0°C to 70°C VDIFF RL = 50 kΩ VOS IB TA = 0°C to 70°C Input Offset Current IOS TA = 0°C to 70°C Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range Short-Circuit Current Limit Gain Bandwidth Product Slew Rate Voltage Noise Density (RTI) Peak-to-Peak Voltage Noise (RTI) nV/√Hz µV p-p µV p-p V mV +VS +300 +VS − 0.1 1 5 100 1 100 1 TA = 0°C to 70°C 0.1 CMRR PSRR AVO VCM = 0.5 V to 2.5 V RL = 50 kΩ IOUT GBP SR en en p-p f = 1 kHz f = 0.1 Hz to 10 Hz f = 0.5 Hz to 40 Hz Rev. A | Page 3 of 28 100 µV/°C µV/°C pA nA pA nA 100 12 14 6.3 100 0.4 1 12 2 1 BW 200 mV µV GΩ||pF GΩ||pF 0.1 VDIFF = 0 V VDIFF = −300 mV to +300 mV TA = 0°C to 70°C 8 50 Unit 10||7.5 5||15 0.2 −300 IOUT AV Max 3.5 5 +VS − 0.1 100 100 110 0.1 +VS − 0.1 12 100 0.02 60 6 8 V mA V/V % % ppm/°C kHz MHz mV µV/°C pA nA pA nA V dB dB dB V mA kHz V/µs nV/√Hz µV p-p µV p-p AD8232 Parameter RIGHT LEG DRIVE AMPLIFIER (A2) Output Swing Short-Circuit Current Integrator Input Resistor Gain Bandwidth Product REFERENCE BUFFER (A3) Offset Error Input Bias Current Short-Circuit Current Limit Voltage Range DC LEADS OFF COMPARATORS Threshold Voltage Hysteresis Propagation Delay AC LEADS OFF DETECTOR Square Wave Frequency Square Wave Amplitude Impedance Threshold Detection Delay FAST RESTORE CIRCUIT Switches On Resistance Off Leakage Window Comparator Threshold Voltage Propagation Delay Switch Timing Characteristics Feedback Recovery Switch On Time Filter Recovery Switch On Time Fast Restore Reset LOGIC INTERFACE Input Characteristics Input Voltage (AC/DC and FR) Low High Input Voltage (SDN) Low High Output Characteristics Output Voltage Low High SYSTEM SPECIFICATIONS Quiescent Supply Current Data Sheet Symbol Test Conditions/Comments Min RL = 50 kΩ 0.1 IOUT 120 GDP VOS IB IOUT RL > 50 kΩ RL = 50 kΩ 11 150 100 Max Unit +VS − 0.1 V mA kΩ kHz 180 1 100 12 0.1 +VS − 0.7 +VS − 0.5 60 0.5 FAC IAC 50 Between +IN and −IN 10 mV pA mA V V mV µs 100 200 20 110 175 kHz nA p-p MΩ μs 10 100 12 kΩ pA S1 and S2 RON 8 From either rail 50 2 mV µs tSW1 tSW2 tRST 110 55 2 ms ms µs VIL VIH 1.24 1.35 V V VIL VIH 2.1 0.5 V V 0.05 2.95 V V LOD+ and LOD− terminals VOL VOH 170 210 40 100 TA = 0°C to 70°C Shutdown Current TA = 0°C to 70°C Supply Range Specified Temperature Range Operational Temperature Range 1 Typ 2.0 0 −40 Offset referred to the input of the instrumentation amplifier inputs. See the Input Referred Offsets section for additional information. Rev. A | Page 4 of 28 230 500 3.5 70 +85 µA µA nA nA V °C °C Data Sheet AD8232 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Parameter Supply Voltage Output Short-Circuit Current Duration Maximum Voltage, Any Terminal1 Minimum Voltage, Any Terminal1 Storage Temperature Range Operating Temperature Range Maximum Junction Temperature θJA Thermal Impedance2 θJC Thermal Impedance ESD Rating Human Body Model (HBM) Charged Device Model (FICDM) Machine Model (MM) Rating 3.6 V Indefinite +VS + 0.3 V −0.3 V −65°C to +125°C −40°C to +85°C 140°C 48°C/W 4.4°C/W ESD CAUTION 8 kV 1.25 kV 200 V This level or the maximum specified supply voltage, whichever is the lesser, indicates the superior voltage limit for any terminal. If input voltages beyond the specified minimum or maximum voltages are expected, place resistors in series with the inputs to limit the current to less than 5 mA. 2 θJA is specified for a device in free air on a 4-layer JEDEC board. 1 Rev. A | Page 5 of 28 AD8232 Data Sheet 20 19 18 17 16 HPSENSE IAOUT REFIN +VS GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 AD8232 TOP VIEW 15 14 13 12 11 FR AC/DC SDN LOD+ LOD– NOTES 1. CONNECT THE EXPOSED PAD TO GND OR LEAVE UNCONNECTED. 10866-002 SW 6 OPAMP+ 7 REFOUT 8 OPAMP– 9 OUT 10 HPDRIVE +IN –IN RLDFB RLD Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic HPDRIVE 2 3 4 5 6 7 8 +IN −IN RLDFB RLD SW OPAMP+ REFOUT 9 10 OPAMP− OUT 11 LOD− 12 LOD+ 13 14 SDN AC/DC 15 16 17 18 19 20 FR GND +VS REFIN IAOUT HPSENSE EP Description High-Pass Driver Output. Connect HPDRIVE to the capacitor in the first high-pass filter. The AD8232 drives this pin to keep HPSENSE at the same level as the reference voltage. Instrumentation Amplifier Positive Input. +IN is typically connected to the left arm (LA) electrode. Instrumentation Amplifier Negative Input. −IN is typically connected to the right arm (RA) electrode. Right Leg Drive Feedback Input. RLDFB is the feedback terminal for the right leg drive circuit. Right Leg Drive Output. Connect the driven electrode (typically, right leg) to the RLD pin. Fast Restore Switch Terminal. Connect this terminal to the output of the second high-pass filter. Operational Amplifier Noninverting Input. Reference Buffer Output. The instrumentation amplifier output is referenced to this potential. Use REFOUT as a virtual ground for any point in the circuit that needs a signal reference. Operational Amplifier Inverting Input. Operational Amplifier Output. The fully conditioned heart rate signal is present at this output. OUT can be connected to the input of an ADC. Leads Off Comparator Output. In dc leads off detection mode, LOD− is high when the electrode to −IN is disconnected, and it is low when connected. In ac leads off detection mode, LOD− is always low. Leads Off Comparator Output. In dc leads off detection mode, LOD+ is high when the +IN electrode is disconnected, and it is low when connected. In ac leads off detection mode, LOD+ is high when either the −IN or +IN electrode is disconnected, and it is low when both electrodes are connected. Shutdown Control Input. Drive SDN low to enter the low power shutdown mode. Leads Off Mode Control Input. Drive the AC/DC pin low for dc leads off mode. Drive the AC/DC pin high for ac leads off mode. Fast Restore Control Input. Drive FR high to enable fast recovery mode; otherwise, drive it low. Power Supply Ground. Power Supply Terminal. Reference Buffer Input. Use REFIN, a high impedance input terminal, to set the level of the reference buffer. Instrumentation Amplifier Output Terminal. High-Pass Sense Input for Instrumentation Amplifier. Connect HPSENSE to the junction of R and C that sets the corner frequency of the dc blocking circuit. Exposed Pad. Connect the exposed pad to GND or leave it unconnected. Rev. A | Page 6 of 28 Data Sheet AD8232 TYPICAL PERFORMANCE CHARACTERISTICS VS = 3 V, VREF = 1.5 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted. INSTRUMENTATION AMPLIFIER PERFORMANCE CURVES 1200 50 40 1000 INPUT BIAS CURRENT (pA) 30 UNITS 800 600 400 20 10 0 –10 –20 –30 200 –90 –60 –30 0 30 60 90 120 CMRR (µV/V) –50 10866-003 0 –120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 INPUT COMMON-MODE VOLTAGE (V) Figure 3. Instrumentation Amplifier CMRR Distribution 10866-006 –40 Figure 6. Instrumentation Amplifier Input Bias Current vs. CMV 50 NO DC OFFSET 300mV OFFSET 1400 40 1200 30 GAIN (dB) UNITS 1000 800 600 20 10 400 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 GAIN ERROR (%) –10 10866-004 0 –2.0 1 100 1k 10k 100k FREQUENCY (Hz) Figure 4. Instrumentation Amplifier Gain Error Distribution Figure 7. Instrumentation Amplifier Gain vs. Frequency 3.5 120 3.0 100 2.5 CMRR (dB) 2.0 1.5 1.0 80 60 0.5 40 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (V) 3.5 Figure 5. Instrumentation Amplifier Input Common-Mode Range vs. Output Voltage 20 10 100 1k 10k 100k FREQUENCY (Hz) Figure 8. Instrumentation Amplifier CMRR vs. Frequency, RTI Rev. A | Page 7 of 28 10866-008 NO DC OFFSET +300mV OFFSET –300mV OFFSET 0 10866-005 INPUT COMMON-MODE VOLTAGE (V) 10 10866-007 0 200 AD8232 Data Sheet 120 110 100 PSRR (dB) 90 10µV/DIV 80 70 60 50 30 10866-012 40 1 10 100 1k 10k 100k FREQUENCY (Hz) 10866-009 200ms/DIV 20 0.1 Figure 9. Instrumentation Amplifier PSRR vs. Frequency Figure 12. Instrumentation Amplifier 0.5 Hz to 40 Hz Noise 10k 1.0 0.9 0.7 1k GAIN ERROR (%) NOISE (nV/√Hz) 0.8 100 0.6 0.5 0.4 0.3 0.2 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 10. Instrumentation Amplifier Voltage Noise Spectral Density (RTI) 0 0 50 100 150 200 250 300 DC OFFSET (mV) Figure 13. Instrumentation Amplifier Gain Error vs. DC Offset 22pF 470pF 1nF 100µs/DIV Figure 11. Instrumentation Amplifier 0.1 Hz to 10 Hz Noise 50mV/DIV 10866-014 1s/DIV 10866-011 10µV/DIV Figure 14. Instrumentation Amplifier Small Signal Pulse Response Rev. A | Page 8 of 28 10866-013 1 0.1 10866-010 0.1 Data Sheet AD8232 0.7 3.0 0.6 2.5 0.5 2.0 0.4 1.5 0.3 1.0 0.2 0.5 0.1 0 10866-015 100µs/DIV 0 –0.5 –0.1 –1.0 –40 –20 –0 20 40 60 80 –0.2 100 10866-018 INPUT BIAS CURRENT (nA) 3.5 0.5V/DIV 0.8 IB IOS INPUT OFFSET CURRENT (nA) 4.0 TEMPERATURE (°C) Figure 15. Instrumentation Amplifier Large Signal Pulse Response Figure 18. Instrumentation Amplifier Input Bias Current and Input Offset Current vs. Temperature 1.5 0.5 0.4 0.3 0.2 GAIN ERROR (%) 0.5 0 –0.5 0 –0.1 –0.3 –40-°C +25°C +85°C –1.5 100 1k 10k 100k 1M LOAD (Ω) –0.4 –0.5 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 16. Instrumentation Amplifier Output Swing vs. Load 10866-019 –1.0 Figure 19. Instrumentation Amplifier Gain Error vs. Temperature 0.4 50 40 0.3 30 0.2 20 CMRR (µV/V) 0.1 0 –0.1 10 0 –10 –20 –0.2 –30 –0.3 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 17. Instrumentation Amplifier DC Blocking Input Offset Drift –50 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 20. Instrumentation Amplifier CMRR vs. Temperature Rev. A | Page 9 of 28 10866-020 –0.4 –40 –40 10866-017 DC BLOCKING INPUT OFFSET (mV) 0.1 –0.2 10866-016 OUTPUT SWING (V) 1.0 AD8232 Data Sheet OPERATIONAL AMPLIFIER PERFORMANCE CURVES 1000 800 UNITS 600 400 0.5V/DIV –2 0 2 4 OFFSET VOLTAGE (mV) Figure 21. Operational Amplifier Offset Distribution 140 80 120 60 100 40 80 20 60 0 40 –20 20 1 10 100 1k 10k 100k 0 1M FREQUENCY (Hz) Figure 22. Operational Amplifier Open-Loop Gain and Phase vs. Frequency NOISE (nV/√Hz) 100 –40 0.1 10k 1k 100 10 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 25. Operational Amplifier Voltage Spectral Noise Density vs. Frequency 22pF 470pF 1nF 10µS/DIV 50mV/DIV 1s/DIV Figure 23. Operational Amplifier Small Signal Response for Various Capacitive Loads Figure 26. Operational Amplifier 0.1 Hz to 10 Hz Noise Rev. A | Page 10 of 28 10866-026 5µV/DIV 10866-023 GAIN (dB) 120 180 160 PHASE MARGIN (Degrees) GAIN PHASE MARGIN 10866-022 140 Figure 24. Operational Amplifier Large Signal Transient Response 10866-025 –4 100µV/DIV 10866-021 0 10866-024 200 Data Sheet AD8232 120 110 100 90 80 PSRR (dB) 5µV/DIV 70 60 50 40 30 10866-027 20 10 0 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 27. Operational Amplifier 0.5 Hz to 40 Hz Noise 10866-030 200ms/DIV Figure 30. Operational Amplifier Power Supply Rejection Ratio 100 80 INPUT BIAS CURRENT (pA) 60 40 20 0 –20 –40 –60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 INPUT COMMON-MODE VOLTAGE (V) 10866-028 –100 10866-031 20V/DIV 10µV/DIV –80 Figure 31. Operational Amplifier Load Transient Response (100 μA Load Change) Figure 28. Operational Amplifier Bias Current vs. Input Common-Mode Voltage 0.8 1.5 0.6 1.0 OFFSET (mV) 0 0.2 0 –0.2 –0.5 –0.4 –40°C +25°C +85°C –1.5 100 1k 10k 100k 1M LOAD (Ω) –0.6 –0.8 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 32. Operational Amplifier Offset vs. Temperature Figure 29. Operational Amplifier Output Voltage Swing vs. Output Current Rev. A | Page 11 of 28 100 10866-032 –1.0 10866-029 OUTPUT SWING (V) 0.4 0.5 AD8232 Data Sheet 1,000 100 10 1 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 10866-033 INPUT BIAS CURRENT (pA) 10,000 Figure 33. Operational Amplifier Bias Current vs. Temperature Rev. A | Page 12 of 28 Data Sheet AD8232 RIGHT LEG DRIVE (RLD) AMPLIFIER PERFORMANCE CURVES 160 100 140 80 120 60 100 40 80 20 60 0 40 –20 20 5µV/DIV 1s/DIV 0.1 1 10 100 1k 10k 100k 0 1M 10866-034 –40 0.01 10866-037 120 OPEN-LOOP GAIN (dB) 180 GAIN PHASE PHASE (Degrees) 140 FREQUENCY (Hz) Figure 37. RLD Amplifier 0.1 Hz to 10 Hz Noise Figure 34. RLD Amplifier Open-Loop Gain and Phase vs. Frequency 1.5 5µV/DIV 0.5 0 –40°C +25°C +85°C –1.0 –1.5 100 1k 10k 100k 200ms/DIV 1M LOAD (Ω) Figure 38. RLD Amplifier 0.5 Hz to 40 Hz Noise Figure 35. RLD Amplifier Output Voltage Swing vs. Output Current 1k 100 10 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) 10866-036 NOISE (nV/√Hz) 10k Figure 36. RLD Amplifier Voltage Spectral Noise Density vs. Frequency Rev. A | Page 13 of 28 10866-038 –0.5 10866-035 OUTPUT SWING (V) 1.0 AD8232 Data Sheet REFERENCE BUFFER PERFORMANCE CURVES 20 15 10,000.0 SOURCE SINK 1,000.0 OUTPUT IMPEDANCE (Ω) 5 0 –5 –10 100.0 10.0 1.0 0.10 1 10 LOAD CURRENT (mA) 0.1 0.1 10866-039 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 39. Reference Buffer Load Regulation Figure 41. Reference Buffer Output Impedance vs. Frequency 1000 INPUT BIAS CURRENT (pA) 20mV/DIV 10µs/DIV 100 10 1 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 40. Reference Buffer Load Transient Response (100 μA Load Change) Figure 42. Reference Buffer Bias Current vs. Temperature Rev. A | Page 14 of 28 100 10866-042 –20 0.01 10866-041 –15 10866-040 OUTPUT ERROR (mV) 10 Data Sheet AD8232 SYSTEM PERFORMANCE CURVES 240 200 180 220 VS = 2V VS = 3V VS = 3.5V SHUTDOWN CURRENT (nA) 180 160 140 140 120 100 80 60 40 VS = 2V VS = 3V VS = 3.5V 100 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 20 100 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 44. Shutdown Current vs. Temperature Figure 43. Supply Current vs. Temperature Rev. A | Page 15 of 28 100 10866-044 120 10866-043 SUPPLY CURRENT (µA) 160 200 AD8232 Data Sheet THEORY OF OPERATION +VS HPDRIVE HPSENSE IAOUT SW 17 1 20 19 6 OPAMP– 7 9 10kΩ CHARGE PUMP +VS OPAMP+ A1 10 OUT S2 AC/DC –IN 2 RFI FILTER +IN 3 HPA GM1 GM2 VCM AC/DC S1 R 10kΩ 15 FR +VS – 0.05V 99R 13 SDN C1 0.05V 14 AC/DC INSTRUMENTATION AMPLIFIER (IA) S1 S2 SYNCH RECTIFIER RLDFB 4 SWITCH TIMING 12 LOD+ 0.7V 11 LOD– RLD 5 A2 +VS – 0.5V 150kΩ AC/DC 16 GND A3 8 *ALL SWITCHES SHOWN IN DC LEADS-OFF DETECTION POSITION AND FAST RESTORE DISABLED = REFOUT REFOUT 10866-045 REFIN 18 Figure 45. Simplified Schematic Diagram ARCHITECTURE OVERVIEW The AD8232 is an integrated front end for signal conditioning of cardiac biopotentials for heart rate monitoring. It consists of a specialized instrumentation amplifier (IA), an operational amplifier (A1), a right leg drive amplifier (A2), and a midsupply reference buffer (A3). In addition, the AD8232 includes leads off detection circuitry and an automatic fast restore circuit that brings back the signal shortly after leads are reconnected. The feedback of the amplifier is applied via GM2 through two separate paths: the two resistors divide the output signal to set an overall gain of 100, whereas the dc blocking amplifier integrates any deviation from the reference level. Consequently, dc offsets as large as ±300 mV across the GM1 inputs appear inverted and with the same magnitude across the inputs of GM2, all without saturating the signal of interest. The AD8232 contains a specialized instrumentation amplifier that amplifies the ECG signal while rejecting the electrode half-cell potential on the same stage. This is possible with an indirect current feedback architecture, which reduces size and power compared with traditional implementations To increase the common-mode voltage range of the instrumentation amplifier, a charge pump boosts the supply voltage for the two transconductance amplifiers. This further prevents saturation of the amplifier in the presence of large common-mode signals, such as line interference. The charge pump runs from an internal oscillator, the frequency of which is set around 500 kHz. INSTRUMENTATION AMPLIFIER OPERATIONAL AMPLIFIER The instrumentation amplifier is shown in Figure 45 as comprised by two well-matched transconductance amplifiers (GM1 and GM2), the dc blocking amplifier (HPA), and an integrator formed by C1 and an op amp. The transconductance amplifier, GM1, generates a current that is proportional to the voltage present at its inputs. When the feedback is satisfied, an equal voltage appears across the inputs of the transconductance amplifier, GM2, thereby matching the current generated by GM1. The difference generates an error current that is integrated across Capacitor C1. The resulting voltage appears at the output of the instrumentation amplifier. This general-purpose operational amplifier (A1) is a rail-to-rail device that can be used for low-pass filtering and to add additional gain. The following sections provide details and example circuits that use this amplifier. Rev. A | Page 16 of 28 Data Sheet AD8232 The right leg drive (RLD) amplifier inverts the common-mode signal that is present at the instrumentation amplifier inputs. When the right leg drive output current is injected into the subject, it counteracts common-mode voltage variations, thus improving the common-mode rejection of the system. The common-mode signal that is present across the inputs of the instrumentation amplifier is derived from the transconductance amplifier, GM1. It is then connected to the inverting input of A2 through a 150 kΩ resistor. An integrator can be built by connecting a capacitor between the RLD FB and RLD terminals. A good starting point is a 1 nF capacitor, which places the crossover frequency at about 1 kHz (the frequency at which the amplifier has an inverting unity gain). This configuration results in about 26 dB of loop gain available at a frequency range from 50 Hz to 60 Hz for common-mode line rejection. Higher capacitor values reduce the crossover frequency, thereby reducing the gain that is available for rejection and, consequently, increasing the line noise. Lower capacitor values move the crossover frequency to higher frequencies, allowing increased gain. The tradeoff is that with higher gain, the system can become unstable and saturate the output of the right leg amplifier. Note that when using this amplifier to drive an electrode, there should be a resistor in series with the output to limit the current to be always less than 10uA even in fault conditions. For example, if the supply used is 3.0V, this resistor should be greater than 330kΩ to account for component and supply variations. +VS R1 18 R2 REFIN A3 C1 Figure 47. Setting the Internal Reference To limit the power consumption of the voltage divider, the use of large resistors is recommended, such as 10 MΩ. The designer must keep in mind that high resistor values make it easier for interfering signals to appear at the input of the reference buffer. To minimize noise pickup, it is recommended to place the resistors close to each other and as near as possible to the REFIN terminal. Furthermore, use a capacitor in parallel with the lower resistor on the divider for additional filtering, as shown in Figure 47. Keep in mind that a large capacitor results in better noise filtering but it takes longer to settle the reference after power-up. The total time it takes the reference to settle within 1% can be estimated with the formula t SETTLE _ REFERENCE = 5 × R1R2C1 R1 + R2 Note that disabling the AD8232 with the shutdown terminal does not discharge this capacitor. Because of the low cutoff frequency used in high-pass filters in ECG applications, signals may require several seconds to settle. This settling time can result in a frustrating delay for the user after a step response: for example, when the electrodes are first connected. A2 150kΩ REFOUT *LIMIT CURRENT TO LESS THAN 10µA. VCM 10866-146 RLD Figure 46. Typical Configuration of Right-Leg Drive Circuit In two-electrode configurations, RLD can be used to bias the inputs through 10MΩ resistors as described in the Leads Off Detection section. If left unused, it is recommended to configure A2 as a follower by connecting RLDFB directly to RLD. REFERENCE BUFFER This fast restore function is implemented internally, as shown in Figure 48. The output of the instrumentation amplifier is connected to a window comparator. The window comparator detects a saturation condition at the output of the instrumentation amplifier when its voltage approaches 50 mV from either supply rail. FR 15 S1 +VS – 0.05V +IN SWITCH TIMING 2 The AD8232 operates from a single supply. To simplify the design of single-supply applications, the AD8232 includes a reference buffer to create a virtual ground between the supply voltage and the system ground. The signals present at the output of the instrumentation amplifier are referenced around this voltage. For example, if there is zero differential input voltage, IA 3 –IN Rev. A | Page 17 of 28 S2 IAOUT 0.05V LOD+ LOD– Figure 48. Fast Restore Circuit 10866-047 1nF 18 5 The reference voltage level is set at the REFIN pin. It can be set with a voltage divider or by driving the REFIN pin from some other point in the circuit (for example, from the ADC reference). The voltage is available at the REFOUT pin for the filtering circuits or for an ADC input. FAST RESTORE CIRCUIT RLDFB 4 TO DRIVEN R* ELECTRODE the voltage at the output of the instrumentation amplifier is this reference voltage. 10866-046 RIGHT LEG DRIVE AMPLIFIER AD8232 Data Sheet SATURATION DETECTED NO SATURATION tS1 S1 tS2 S2 10866-048 tRST LEADS OFF LEADS ON Figure 49. Timing Diagram for Fast Restore Switches (Time Base Not to Scale) These two switches (S1 and S2) enable two different 10 kΩ resistor paths: one between HPSENSE and IAOUT and another between SW and REFOUT. During the time Switch S1 and Switch S2 are enabled, these internal resistors appear in parallel with their corresponding external resistors forming high-pass filters. The result is that the equivalent lower resistance shifts the pole to a higher frequency, delivering a quicker settling time. Note that the fast restore settling time depends on how quickly the internal 10 kΩ resistors of the AD8232 can drain the capacitors in the high-pass circuit. Smaller capacitor values result in a shorter settling time. If, by the end of the timing, the saturation condition persists, the cycle repeats. Otherwise, the AD8232 returns to its normal operation. If either of the leads off comparator outputs is indicating that an electrode has been disconnected, the timing circuit is prevented from triggering because it is assumed that no valid signal is present. To disable fast restore, drive the FR pin low or tie it permanently to GND. LEADS OFF DETECTION The AD8232 includes leads off detection. It features ac and dc detection modes optimized for either two- or three-electrode configurations, respectively. DC Leads Off Detection The dc leads off detection mode is used in three-electrode configurations only. It works by sensing when either instrumentation amplifier input voltage is within 0.5 V from the positive rail. In this case, each input must have a pull-up resistor connected to the positive supply. During normal operation, the subject’s potential must be inside the common-mode range of the instrumentation amplifier, which is only possible if a third electrode is connected to the output of the right leg drive amplifier. +VS 10MΩ 10MΩ 2 IA 3 TO DRIVEN ELECTRODE 5 RLD 10866-049 If this saturation condition is present when both input electrodes are attached to the subject, the comparator triggers a timing circuit that automatically closes Switch S1 and Switch S2 (see Figure 49 for a timing diagram). Figure 50. Circuit Configuration for DC Leads Off Detection Because in dc leads off mode the AD8232 checks each input individually, it is possible to indicate which electrode is disconnected. The AD8232 indicates which electrode is disconnected by setting the corresponding LOD− or LOD+ pin high. To use this mode, connect the AC/DC pin to ground. Rev. A | Page 18 of 28 Data Sheet AD8232 AC Leads Off Detection The ac leads off detection mode is useful when using two electrodes only (it does not require the use of a driven electrode). In this case, a conduction path must exist between the two electrodes, which is usually formed by two resistors, as shown in Figure 51. These resistors also provide a path for bias return on each input. Connect each resistor to REFOUT or RLD to maintain the inputs within the common-mode range of the instrumentation amplifier. +VS 17 IA 3 10MΩ REFOUT During shutdown operation, the AD8232 is not able to maintain the REFOUT voltage, but it does not drain the REFIN voltage, thereby maintaining this additional conduction path from the supply to ground. INPUT PROTECTION 10866-050 8 Driving the SDN pin low places the AD8232 in shutdown mode and draws less than 200 nA of supply current, offering considerable power savings. To enter normal operation, drive SDN high; when not using this feature, permanently tie SDN to +VS. When emerging from a shutdown condition, the charge stored in the capacitors on the high-pass filters can saturate the instrumentation amplifier and subsequent stages. The use of the fast restore feature helps reduce the recovery time and, therefore, minimize on time in power sensitive applications. 2 10MΩ where power consumption is critical. A logic level signal can be applied to this pin to switch to shutdown mode, even when the supply is still on. Figure 51. Circuit Configuration for AC Leads Off Detection The AD8232 detects when an electrode is disconnected by forcing a small 100 kHz current into the input terminals. This current flows through the external resistors from IN+ to IN− and develops a differential voltage across the inputs, which is then synchronously detected and compared to an internal threshold. The recommended value for these external resistors is 10 MΩ. Low resistance values make the differential drop too low to be detected and lower the input impedance of the amplifier. When the electrodes are attached to the subject, the impedance of this path should be less than 3 MΩ to maintain the drop below the comparator’s threshold. As opposed to the dc leads off detection mode, the AD8232 is able to determine only that an electrode has lost its connection, not which one. During such an event, the LOD+ pin goes high. In this mode, the LOD− pin is not used and remains in a logic low state. To use the ac leads off mode, tie the AC/DC pin to the positive supply rail. Note that while REFOUT is at a constant voltage value, using the RLD output as the input bias may be more effective in rejecting common-mode interference. All terminals of the AD8232 are protected against ESD. In addition, the input structure allows for dc overload conditions that are a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, use an external resistor in series with each of the inputs to limit current for voltages beyond the supplies. In either scenario, the AD8232 safely handles a continuous 5 mA current at room temperature. For applications where the AD8232 encounters extreme overload voltages, such as in cardiac defibrillators, use external series resistors and gas discharge tubes (GDT). Neon lamps are commonly used as an inexpensive alternative to GDTs. These devices can handle the application of large voltages but do not maintain the voltage below the absolute maximum ratings for the AD8232. A complete solution includes further clamping to either supply using additional resistors and low leakage diode clamps, such as BAV199 or FJH1100. As a safety measure, place a resistor between the input pin and the electrode that is connected to the subject to ensure that the current flow never exceeds 10 μA. Calculate the value of this resistor to be equal to the supply voltage across the AD8232 divided by 10 μA. STANDBY OPERATION The AD8232 includes a shutdown pin (SDN) that further enhances the flexibility and ease of use in portable applications Rev. A | Page 19 of 28 AD8232 Data Sheet RADIO FREQUENCY INTERFERENCE (RFI) INPUT REFERRED OFFSETS Radio frequency (RF) rectification is often a problem in applications where there are large RF signals. The problem appears as a dc offset voltage at the output. The AD8232 has a 15 pF gate capacitance and 10 kΩ resistors at each input. This forms a low-pass filter on each input that reduces rectification at high frequency (see Figure 53) without the addition of external elements. Because of its internal architecture, the instrumentation amplifier should be used always with the DC blocking amplifier, shown as HPA in Figure 45. +IN 10kΩ CG –IN 10kΩ AD8232 IAOUT As described in the Theory of Operation section, the dc blocking amplifier attenuates the input referred offsets present at the inputs of the instrumentation amplifier. However, this is true only when the dc blocking amplifier is used as an integrator. In this configuration, the input offsets from the dc blocking amplifier dominate appear directly at the output of the instrumentation amplifier. If the dc blocking amplifier is used as a follower instead of its intended function as an integrator, the input referred offsets of the in-amp are amplified by a factor of 100. 10866-151 CG LAYOUT RECOMMENDATIONS Figure 52. RFI Filter Without External Capacitors For increased filtering, additional resistors can be added in series with each input. They must be placed as close as possible to the instrumentation amplifier inputs. These can be the same resistors used for overload and patient protection. POWER SUPPLY REGULATION AND BYPASSING The AD8232 is designed to be powered directly from a single 3 V battery, such as CR2032 type. It can also operate from rechargeable lithium-ion batteries, but the designer must take into account that the voltage during a charge cycle may exceed the absolute maximum ratings of the AD8232. To avoid damage to the part, use a power switch or a low power, low dropout regulator, such as ADP150. In addition, excessive noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the chip power supplies. Place a 0.1 μF capacitor close to the supply pin. A 1 μF capacitor can be used farther away from the part. In most cases, the capacitor can be shared by other integrated circuits. Keep in mind that excessive decoupling capacitance increases power dissipation during power cycling. It is important to follow good layout practices to optimize system performance. In low power applications, most resistors are of a high value to minimize additional supply current. The challenge of using high value resistors is that high impedance nodes become even more susceptible to noise pickup and board parasitics, such as capacitance and surface leakages. Keep all of the connections between high impedance nodes as short as possible to avoid introducing additional noise and errors from corrupting the signal. To maintain high CMRR over frequency, keep the input traces symmetrical and length matched. Place safety and input bias resistors in the same position relative to each input. In addition, the use of a ground plane significantly improves the noise rejection of the system. Rev. A | Page 20 of 28 Data Sheet AD8232 APPLICATIONS INFORMATION ELIMINATING ELECTRODE OFFSETS The instrumentation amplifier in the AD8232 is designed to apply gain and to filter out near dc signals simultaneously. This capability allows it to amplify a small ECG signal by a factor of 100 yet reject electrode offsets as large as ±300 mV. To achieve offset rejection, connect an RC network between the output of the instrumentation amplifier, HPSENSE, and HPDRIVE, as shown in Figure 53. 1 HPDRIVE R 20 f 3dB f 3dB IAOUT IN+ HPA 2 IN– GM2 VCM ELECTRODE OFFSETS S1 R 99R C1 = REFOUT Figure 53. Eliminating Electrode Offsets This RC network forms an integrator that feeds any near dc signals back into the instrumentation amplifier, thus eliminating the offsets without saturating any node and maintaining high signal gain. In addition to blocking offsets present across the inputs of the instrumentation amplifier, this integrator also works as a highpass filter that minimizes the effect of slow moving signals, such as baseline wander. The cutoff frequency of the filter is given by the equation f 3dB HIGH-PASS FILTERING The AD8232 can implement higher order high-pass filters. A higher filter order yields better artifact rejection but at a cost of increased signal distortion and more passive components on the printed circuit board (PCB). Two-Pole High-Pass Filter A two-pole architecture can be implemented by adding a simple ac coupling RC at the output of the instrumentation amplifier, as shown in Figure 55. C1 100 2 RC 1 HPDRIVE where R is in ohms and C is in farads. IAOUT S1 10kΩ SW 10kΩ R2 S2 3 REFOUT 8 –IN = REFOUT Figure 55. Schematic for a Two-Pole High-Pass Filter Note that the right side of C2 connects to the SW terminal. Just like S1, S2 reduces the recovery time for this ac coupling network by placing 10 kΩ in parallel with R2. See the Fast Restore Circuit section for additional details on switch timing and trigger conditions. 40 30 Keep in mind that if this passive network is not buffered, it exhibits higher output impedance at the input of a subsequent low-pass filter, such as with Sallen-Key filter topologies. Careful component selection can yield good results without a buffer. See the Low-Pass Filtering and Gain section for additional information on component selection. 20dB PER DECADE 10 0.1 1 10 100 FREQUENCY (Hz) 10866-153 MAGNITUDE (dB) 6 19 HPSENSE 2 50 0 0.01 20 TO NEXT STAGE C2 R1 HPA +IN Note that the filter cutoff is 100 times higher than is typically expected from a single-pole filter. Because of the feedback architecture of the instrumentation amplifier, the typical filter cutoff equation is modified by the gain of 100 of the instrumentation amplifier. 20 1 200 C This higher cutoff reduces the settling time and enables faster recovery of the ECG signal. For more information, see the Fast Restore Circuit section. 10kΩ 10866-253 GM1 3 (1) For values of R greater than 100 kΩ, the expression in Equation 1 can be approximated by 19 HPSENSE 100(R 10 4 ) 2 RC (10 4 ) 10866-053 C Just like with any high-pass filter with low frequency cutoff, any fast change in dc offset takes a long time to settle. If such change saturates the instrumentation amplifier output, the S1 switch briefly enables the 10 kΩ resistor path, thus moving the cutoff frequency to Figure 54. Frequency Response of Single-Pole DC Blocking Circuit Rev. A | Page 21 of 28 AD8232 Data Sheet Additional High-Pass Filtering Options In addition to the topologies explained in the previous sections, an additional pole may be added to the dc blocking circuit for additional rejection of low frequency signals. This configuration is shown in Figure 56. R1 TO NEXT STAGE R2 C1 R1 RCOMP RCOMP 20 IAOUT HPA +IN S1 10kΩ 1 6 19 HPSENSE HPDRIVE SW 10kΩ HPA +IN S2 SW 10kΩ S1 10kΩ C2 R3 S2 2 3 REFOUT 8 10866-155 = REFOUT REFOUT 8 –IN –IN = REFOUT Figure 57. Schematic for a Three-Pole High-Pass Filter Figure 56. Schematic for an Alternative Two-Pole High-Pass Filter With this topology, the filter attenuation reverts to a single pole roll off at very low frequencies. Because the initial roll off was 40 dB per decade, this reversion to 20 dB per decade has little impact on the ability of the filter to reject out-of-band low frequency signals. The designer may choose different values to achieve the desired filter performance. To simplify the design process, use the following recommendations as a starting point for component value selection. 60 40dB PER DECADE 40 MAGNITUDE (dB) An extra benefit of this circuit topology is that it allows lower cutoff frequency with lower R and C values and the resistor, RCOMP, can be used to control the Q of the filter to achieve narrow band-pass filters (for heart rate detection) or maximum passband flatness (for cardiac monitoring). 20 60dB PER DECADE 20dB PER DECADE 0 –20 –40 40dB PER DECADE –60 0.01 0.1 THREE-POLE FILTER TWO-POLE FILTER 1 FREQUENCY (Hz) R1 = R2 ≥ 100 kΩ 10 100 Figure 58. Frequency Response of Circuits in Figure 56 and Figure 57 C1 = C2 RCOMP = 0.14 × R1 The cutoff frequency is located at fC 6 19 IAOUT C2 2 3 20 HPSENSE 10866-156 1 HPDRIVE TO NEXT STAGE C3 R2 10866-157 C1 When additional low frequency rejection is desired, a high-order high-pass filter can be implemented by adding an ac coupling network at the output of the instrumentation amplifier, as shown in Figure 57. The SW terminal is connected to the ac coupling network to obtain the best settling time response when fast restore engages. 10 2 R1 C1 R2 C2 The selection of RCOMP to be 0.14 times the value of the other two resistors optimizes the filter for a maximally flat pass band. Reduce its value to increase the Q and, consequently, the peaking of the filter. Keep in mind that a very low value of RCOMP can result in an unstable circuit. The selection of values based on these criteria result in a transfer function similar to the one shown in Figure 58. Careful analysis and adjustment of all of the component values in practice is recommended to optimize the filter characteristics. A useful hint is to reduce the value of RCOMP to increase the peaking of the active filter to overcome the additional roll off introduced by the ac coupling network. Proper adjustment can yield the best pass-band flatness. The design of the high-pass filter involves tradeoffs between signal distortion, component count, low frequency rejection, and component sizes. For example, a single-pole high-pass filter results in the least distortion to the signal, but its rejection of low-frequency artifacts is the lowest Table 4 compares the recommended filtering options. Table 4. Comparison of High-Pass Filtering Options Figure 53 Figure 55 Figure 56 Figure 57 1 2 Filter Order 1 2 2 3 Component Count 2 4 5 7 Low Frequency Rejection Good Better Better Best Capacitor Sizes/Values Large Large Smaller Smaller Signal Distortion1 Low Medium Medium Highest Output Impedance2 Low Higher Low Higher For equivalent corner frequency location. Output impedance refers to the drive capability of the high-pass filter before the low-pass filter. Low output impedance is desirable to allow flexibility in the selection of values for a low-pass filter, as explained in the Low-Pass Filtering and Gain section. Rev. A | Page 22 of 28 Data Sheet AD8232 LOW-PASS FILTERING AND GAIN The AD8232 includes an uncommitted op amp that can be used for extra gain and filtering. For applications that do not require a high-order filter, a simple RC low-pass filter should suffice, and the op amp can buffer or further amplify the signal. FROM IN-AMP STAGE R A1 To connect these two filtering stages properly without a buffer, make the value of R1 at least ten times larger than the resistor of the ac coupling network (labeled as R2 in Figure 55). DRIVING ANALOG-TO-DIGITAL CONVERTERS FILTERED SIGNAL C 10866-158 REFOUT the instrumentation amplifier output and the input of the lowpass filter without a buffer. Figure 59. Schematic for a Single-Pole Low-Pass Filter and Additional Gain Applications that require a steeper roll off or a sharper cut off, a Sallen-Key filter topology can be implemented, as shown in Figure 60. The ability of AD8232 to drive capacitive loads makes it ideal to drive an ADC without the need for an additional buffer. However, depending on the input architecture of the ADC, a simple lowpass RC network may be required to decouple the transients from the switched-capacitor input typical of modern ADCs. This RC network also acts as an additional filter that can help reduce noise and aliasing. Follow the recommended guidelines from the ADC data sheet for the selection of proper R and C values. AD8232 C1 A1 R2 A1 FILTERED SIGNAL R3 DRIVEN ELECTRODE Figure 60. Schematic for a Two-Pole Low-Pass Filter The following equations describe the low-pass cut off frequency, gain, and Q: fC = 1/(2π√(R1 C1 R2 C2)) Gain = 1 + R3/R4 Q R1 C1 R2 C2 R1 C2 R2 C 2 R1 C11 Gain Note that changing the gain has an effect on Q and vice versa. Common values for Q are 0.5 to avoid peaking or 0.7 for maximum flatness and sharp cut off. A high value of Q can be used in narrow-band applications to increase peaking and the selectivity of the band-pass filter. A common design procedure is to set R1 = R2 = R and C1 = C2 = C, which simplifies the expressions for cutoff frequency and Q to fC = 1/(2πRC) Q ADC Figure 61. Driving an ADC 10866-159 R4 R C C2 REFOUT 10 10866-261 FROM IN-AMP STAGE R1 1 3 Gain Note that Q can be controlled by setting the gain with R3 and R4; however, this limits the gain to be less than 3. For gain values equal to or greater than 3, the circuit becomes unstable. A simple modification that allows higher gains is to make the value of C2 at least four times larger than C1. It is important to note that these design equations only hold true in the case that the output impedance of the previous stage is much lower than the input impedance of the Sallen-Key filter. This is not the case when using an ac coupling network between A driven lead (or reference electrode) is often used to minimize the effects of common-mode voltages induced by the power line and other interfering sources. The AD8232 extracts the commonmode voltage from the instrumentation amplifier inputs and makes it available through the RLD amplifier to drive an opposing signal into the patient. This functionality maintains the voltage between the patient and the AD8232 at a near constant, greatly improving the common-mode rejection ratio. As a safety measure, place a resistor between the RLD pin and the electrode connected to the subject to ensure that current flow never exceeds 10 μA. Calculate the value of this resistor to be equal to the supply voltage across the AD8232 divided by 10 μA. The AD8232 implements an integrator formed by an internal 150 kΩ resistor and an external capacitor to drive this electrode. Choice of the integrator capacitor is a tradeoff between line rejection capability and stability. The capacitor should be small to maintain as much loop gain as possible, around 50 Hz and 60 Hz, which are typical line frequencies. For stability, the gain of the integrator should be less than unity at the frequency of any other poles in the loop, such as those formed by the patient’s capacitance and the safety resistors. The suggested application circuits use a 1 nF capacitor, which results in a loop gain of about 20 at line frequencies, with a crossover frequency of about 1 kHz. In a two-lead configuration, the RLD amplifier can be used to drive the bias current resistors on the inputs. Although not as effective as a true driven electrode, this configuration can provide some common-mode rejection improvement if the sense electrode impedance is small and well matched. Rev. A | Page 23 of 28 AD8232 Data Sheet APPLICATION CIRCUITS HEART RATE MEASUREMENT NEXT TO THE HEART For wearable exercise devices, the AD8232 is typically placed in a pod near the heart. The two sense electrodes are placed underneath the pectoral muscles; no driven electrode is used. Because the distance from the heart to the AD8232 is small, the heart signal is strong and there is less muscle artifact interference. In this configuration, space is at a premium. By using as few external components as possible, the circuit in Figure 62 is optimized for size. 10MΩ IAOUT –IN REFIN +VS RLDFB 10MΩ +VS 10MΩ 0.1µF 1nF RLD SW 0.1µF 10MΩ GND AD8232 +VS OPAMP+ AC/DC REFOUT SDN OPAMP– LO+ OUT LO– 10MΩ +VS 10MΩ 180kΩ LA TO DIGITAL INTERFACE 180kΩ RA 0.22µF SIGNAL OUTPUT 360kΩ RL Figure 62. Circuit for Heart Rate Measurement Next to Heart A single-pole high-pass filter is set at 7 Hz, and there is no lowpass filter. No gain is used on the output op amp thereby reducing the number of resistors for a total system gain of 100. 70 1MΩ +IN IAOUT –IN REFIN +VS 10MΩ 10MΩ 0.1µF 0.1µF GND RLD AD8232 FR OPAMP+ AC/DC REFOUT SDN OPAMP– LO+ OUT LO– +VS 22nF 1MΩ TO DIGITAL INTERFACE SIGNAL OUTPUT The circuit in Figure 64 uses a two-pole high-pass filter set at 7 Hz. A two-pole low-pass filter at 24 Hz follows the high-pass filters to eliminate any other artifacts and line noise. 50 60 40 50 MAGNITUDE (dB) 70 20 10MΩ Figure 64. Circuit for Heart Rate Measurement at Hands 60 30 +VS RLDFB 100kΩ 3.3nF HPSENSE 1nF 1MΩ 100kΩ 10 40 30 20 10 100 1k 10k FREQUENCY (Hz) 10 0 0.1 Figure 63. Frequency Response for HRM Next to Heart Circuit 1 10 100 1k FREQUENCY (Hz) Figure 65. Frequency Response for HRM Circuit Taken at the Hands Rev. A | Page 24 of 28 10866-059 1 10866-057 MAGNITUDE (dB) HPDRIVE SW A shorter distance from the AD8232 to the heart makes this application less vulnerable to common-mode interference. However, since RLD is not used to drive an electrode, it can be used to improve the common-mode rejection by maintaining the midscale voltage through the 10 MΩ bias resistors. 0 0.1 0.22µF FR 10866-262 180kΩ HPSENSE +IN In this application, the heart rate signal is measured at the hands with stainless steel electrodes. The user’s arm and upper body movement create large motion artifacts and the long lead length makes the system susceptible to common-mode interference. A very narrow band-pass characteristic is required to separate the heart signal from the interferers. 10866-161 10MΩ HPDRIVE 180kΩ The schematic also shows two 10 MΩ resistors to set the midscale reference voltage. If there is already a reference voltage available, it can be driven into the REFIN input to eliminate these two 10 MΩ resistors. EXERCISE APPLICATION: HEART RATE MEASURED AT THE HANDS 0.22µF ELECTRODE INTERFACE The input terminals in this configuration use two 180 kΩ resistors, to protect the user from fault conditions. Two 10 MΩ resistors provide input bias. Use higher values for electrodes with high output impedance, such as cloth electrodes. Data Sheet AD8232 The overall narrow-band nature of this filter combination distorts the ECG waveform significantly. Therefore, it is only suitable to determine the heart rate, and not to analyze the ECG signal characteristics. The low-pass filter stage also includes a gain of 11, to bring the total system gain close to 1100 (note that the filter roll off prevents the maximum gain from reaching this value). Because the ECG signal is measured at the hands, it is weaker than when measured closer to the heart. The RLD circuit drives to the third electrode, which can also be located at the hands, to cancel common-mode interference. CARDIAC MONITOR CONFIGURATION This configuration is designed for monitoring the shape of the ECG waveform. It assumes that the patient remains relatively still during the measurement, and therefore, motion artifacts are less of an issue. 0.33µF +VS 0.33µF REFOUT 10MΩ 10MΩ 10MΩ LA HPDRIVE 180kΩ 180kΩ RA HPSENSE RL +VS REFIN –IN +VS 0.1µF 10MΩ GND RLD SW 1MΩ 10MΩ 0.1µF 1nF 1MΩ 10MΩ IAOUT +IN RLDFB 360kΩ 1.4MΩ AD8232 FR OPAMP+ AC/DC REFOUT SDN OPAMP– 1MΩ LO+ OUT LO– TO DIGITAL INTERFACE 10866-266 1.5nF PORTABLE CARDIAC MONITOR WITH ELIMINATION OF MOTION ARTIFACTS The circuit in Figure 68 shows an implementation of a batterypowered embedded system for monitoring heart rate in applications where the patient engages in moderate activity, such as with a Holter monitor. The AD8232 uses a threeelectrode patient interface and implements a two-pole highpass filter with a cutoff at 0.3 Hz, and a two-pole low-pass filter with a cutoff frequency of 37 Hz. The total signal gain in the pass band is 400. The fully conditioned signal is sampled by the sigma-delta ADC integrated on the low power microcontroller, ADuCM360. The wide dynamic range of this ADC provides flexibility to reduce the signal gain to avoid saturation, depending on electrode placement. Because the pass band is relatively wide for ambulatory applications, the ADXL346 accelerometer signal can be used to further minimize the noise introduced by the motion of the patient. Moreover, the microcontroller can use the motion information to monitor inactivity and to issue a system shutdown to save battery power. The low dropout regulator ensures that the maximum of 3 V is not exceeded, especially during charge cycles of the battery, which can be a lithium-ion cell. +VS 10nF 100kΩ In addition to 40 Hz filtering, the op amp stage is configured for a gain of 11, resulting in a total system gain of 1100. To optimize the dynamic range of the system, the gain level is adjustable, depending on the input signal amplitude (which may vary with electrode placement) and ADC input range. SIGNAL OUTPUT Figure 66. Circuit for ECG Waveform Monitoring To obtain an ECG waveform with minimal distortion, the AD8232 is configured with a 0.5 Hz two-pole high-pass filter followed by a two-pole, 40 Hz, low-pass filter. A third electrode is driven for optimum common-mode rejection. 70 60 In this application, the ADuCM360 uses its Port 0 to perform DMA transfers to the host communication interface or to an on-board memory, if recording the waveform for later transfer. However, in any particular application, this port should be used for the busiest interface to minimize CPU cycles and maintain low power operation. Note that this circuit is shown to demonstrate the capabilities of AD8232 and other system components. It is not a complete system design and additional effort must be made to ensure compliance with medical safety guidelines from regulatory agencies. 40 30 20 10 0 0.01 0.1 1 10 100 FREQUENCY (Hz) 1k 10866-061 MAGNITUDE (dB) 50 Figure 67. Frequency Response of Cardiac Monitor Circuit Rev. A | Page 25 of 28 AD8232 Data Sheet +VS 4.7µF 10MΩ LA ELECTRODE INTERFACE 180kΩ RA 4.7µF 360kΩ RL HPDRIVE +IN 100kΩ 332kΩ 2.7nF 1MΩ REFIN –IN +VS 1nF 10MΩ ADP150x-2.8 VOUT IAOUT RLDFB 1µF 10MΩ VIN 1µF GND VBATT 0.1µF 0.1µF GND RLD 1MΩ +VS = +2.8V 10MΩ +VS SW 1MΩ HPSENSE AD8232 FR OPAMP+ AC/DC REFOUT SDN +VS ADXL346 ADuCM360 6.8nF P1.2 P0.6/IRQ2 P1.7/CS0 OPAMP– LO+ P1.1 OUT LO– P1.0 INT2 VS CS P1.6/MOSI0 SDO/ALT_ADD P1.4/MISO0 SDA/SDI/SDIO P1.SCLK0 +VS VDDIO 1µF GND SCL/SCLK AIN0 AIN1 +VS 4.7µF VREF+ AVDD REG_DVDD 0.47µF P0.3/CS1 CS P0.0/MISO1 TX VREF– P0.2/MOSI1 RX GND P0.1/SCLK1 CLK IOVDD Figure 68. Low Power Portable Cardiac Monitor Rev. A | Page 26 of 28 0.47µF AVDD_REG TO HOST, MEMORY OR DISPLAY 10866-163 10MΩ 180kΩ Data Sheet AD8232 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 0.80 0.75 0.70 0.50 0.40 0.30 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 061609-B TOP VIEW Figure 69. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-20-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8232ACPZ-R7 AD8232ACPZ-RL AD8232ACPZ-WP AD8232-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 27 of 28 Package Option CP-20-10 CP-20-10 CP-20-10 AD8232 Data Sheet NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10866-0-2/13(A) www.analog.com/AD8232 Rev. A | Page 28 of 28