Quad ADC with Diagnostics ADAU1977 Data Sheet FEATURES GENERAL DESCRIPTION Programmable microphone bias (5 V to 9 V) with diagnostics Four 10 V rms capable direct-coupled differential inputs On-chip PLL for master clock Low EMI design 109 dB ADC dynamic range −95 dB THD + N Selectable digital high-pass filter 24-bit ADC with 8 kHz to 192 kHz sample rates Digital volume control with autoramp function I2C/SPI control Software-controllable clickless mute Software power-down Right justified, left justified, I2S justified, and TDM modes Master and slave operation modes 40-lead LFCSP package Qualified for automotive applications The ADAU1977 incorporates four high performance analog-todigital converters (ADCs) with direct-coupled inputs capable of 10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. The ADCs can be connected to the electret microphone (ECM) directly and provide the bias for powering the microphone. Built-in diagnostic circuitry detects faults on input lines and includes comprehensive diagnostics for faults on microphone inputs. The faults reported are short to battery, short to microphone bias, short to ground, short between positive and negative input pins, and open input terminals. In addition, each diagnostic fault is available as an IRQ flag for ease in system design. An I2C/SPI control port is also included. The ADAU1977 uses only a single 3.3 V supply. The part internally generates the microphone bias voltage. The microphone bias is programmable in a few steps from 5 V to 9 V. The low power architecture reduces the power consumption. An on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with a frame clock, the PLL eliminates the need for a separate high frequency master clock in the system. The ADAU1977 is available in a 40-lead LFCSP package. APPLICATIONS Automotive audio systems Active noise cancellation system AVDD2 AVDD3 AVDD1 VBAT SW VBOOST_IN VBOOST_OUT FUNCTIONAL BLOCK DIAGRAM ADAU1977 BOOST CONVERTER IOUT 50mA PGND PROGRAMMABLE GAIN DECIMATOR/HPF DC CALIBRATION ATTENUATOR 14dB AIN1P AIN1N AIN2P AIN2N AIN3P AIN3N AIN4P ADC ADC ADC ADC AIN4N AGND1 VBAT AVDDx AGND3 AVDD2 BG REF DIAGNOSTICS I2C/SPI CONTROL PLL AGND2 SA_MODE PLL_FILT MCLKIN VREF DGND AGND3 AGND2 PGND LRCLK BCLK SDATAOUT1 SDATAOUT2 SCL/CCLK SDA/COUT ADDR1/CIN ADDR0/CLATCH FAULT PD/RST AGND2 AGNDx AGND1 IOVDD 10296-001 PROG BIAS DVDD AVDD1 AVDD3 MICBIAS MB_GND 3.3V TO 1.8V REGULATOR SERIAL AUDIO PORT 5V TO 9V Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADAU1977 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Details ............................................................................... 37 Applications ....................................................................................... 1 Master Power and Soft Reset Register ..................................... 37 General Description ......................................................................... 1 PLL Control Register ................................................................. 38 Functional Block Diagram .............................................................. 1 DC-to-DC Boost Converter Control Register ....................... 39 Revision History ............................................................................... 3 MICBIAS and Boost Control Register .................................... 40 Specifications..................................................................................... 4 Block Power Control and Serial Port Control Register ......... 41 Analog Performance Specifications ........................................... 4 Serial Port Control Register1 .................................................... 42 Diagnostic and Fault Specifications ........................................... 5 Serial Port Control Register2 .................................................... 43 Digital Input/Output Specifications........................................... 6 Channel Mapping for Output Serial Ports Register............... 44 Power Supply Specifications........................................................ 6 Channel Mapping for Output Serial Ports Register............... 46 Digital Filters Specifications ....................................................... 7 Timing Specifications .................................................................. 8 Serial Output Drive and Overtemperature Protection Control Register ......................................................................... 48 Absolute Maximum Ratings.......................................................... 10 Post ADC Gain Channel 1 Control Register .......................... 49 Thermal Resistance .................................................................... 10 Post ADC Gain Channel 2 Control Register .......................... 50 ESD Caution ................................................................................ 10 Post ADC Gain Channel 3 Control Register .......................... 51 Pin Configuration and Function Descriptions ........................... 11 Post ADC Gain Channel 4 Control Register .......................... 52 Typical Performance Characteristics ........................................... 13 High-Pass Filter and DC Offset Control Register and Master Mute ................................................................................ 53 Theory of Operation ...................................................................... 15 Overview...................................................................................... 15 Power Supply and Voltage Reference ....................................... 15 Power-On Reset Sequence ........................................................ 15 PLL and Clock............................................................................. 16 DC-to-DC Boost Converter...................................................... 17 Microphone Bias ......................................................................... 18 Analog Inputs .............................................................................. 18 ADC ............................................................................................. 22 ADC Summing Modes .............................................................. 22 Diagnostics .................................................................................. 23 Serial Audio Data Output Ports—Data Format ..................... 25 Control Ports ................................................................................... 30 I2C Mode ...................................................................................... 31 SPI Mode ..................................................................................... 34 Register Summary .......................................................................... 36 Diagnostics Control Register .................................................... 54 Diagnostics Report Register Channel 1 .................................. 55 Diagnostics Report Register Channel 2 .................................. 56 Diagnostics Report Register Channel 3 .................................. 57 Diagnostics Report Register Channel 4 .................................. 58 Diagnostics Interrupt Pin Control Register 1......................... 59 Diagnostics Interrupt Pin Control Register 2......................... 60 Diagnostics Adjustments Register 1 ........................................ 61 Diagnostics Adjustments Register 2 ........................................ 62 ADC Clipping Status Register .................................................. 63 Digital DC High-Pass Filter and Calibration Register .......... 64 Applications Circuit ....................................................................... 65 Outline Dimensions ....................................................................... 66 Ordering Guide .......................................................................... 66 Automotive Products ................................................................. 66 Rev. C | Page 2 of 68 Data Sheet ADAU1977 REVISION HISTORY 1/14—Rev. B to Rev. C 3/13—Rev. 0 to Rev. A Change to Features Section .............................................................. 1 Change to Dynamic Range (A-Weighted) Parameter, Table 1 .... 4 Change to Figure 9 .......................................................................... 13 Change to Figure 36 ........................................................................ 32 Change to Figure 46 ........................................................................ 65 Changed CP-40-9 to CP-40-14 .........................................Universal Changes to Hysteresis AINxP and AINxN Shorted Together Parameter, Table 2 ............................................................................. 4 Changes to Thermal Resistance Section and Table 8 ................... 9 Changes to SPI Mode Section ....................................................... 32 Changes to Channel Mapping for Output Serial Ports Register Section and Table 34 ....................................................................... 44 Changes to Figure 46 ...................................................................... 63 Changes to Ordering Guide ........................................................... 64 9/13—Rev. A to Rev. B Changes to Figure 1 .......................................................................... 1 Moved Revision History Section ..................................................... 3 Changes to Figure 14 ...................................................................... 16 Changes to Figure 46 ...................................................................... 65 1/13—Revision 0: Initial Version Rev. C | Page 3 of 68 ADAU1977 Data Sheet SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. AVDDx/IOVDD = 3.3 V; DVDD (internally generated) = 1.8 V; VBAT = 14.4 V; TA = −40°C to +105°C, unless otherwise noted; master clock = 12.288 MHz (48 kHz fS, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = ±1 mA; digital input voltage high = 2.0 V; digital input voltage low = 0.8 V. ANALOG PERFORMANCE SPECIFICATIONS Table 1. Parameter LINE INPUT APPLICATION Full-Scale Differential Input Voltage Full-Scale Single-Ended Input Voltage MICROPHONE INPUT APPLICATION Differential Input Voltage QUASI DC INPUT Single-Ended Input Voltage Input Common-Mode Voltage Peak Input Voltage MICROPHONE BIAS Output Voltage Load Regulation Output Current Output Noise Power Supply Rejection Ratio (PSRR) Interchannel Isolation at MICBIAS Pin Start-Up Time BOOST CONVERTER Input Voltage Input Current Output Current Load Regulation Input Overcurrent Threshold Switching Frequency External Load Capacitor at VBOOST_OUT Pin ANALOG-TO-DIGITAL CONVERTERS Input Resistance Differential Single-Ended (Rin1977) ADC Resolution Dynamic Range (A-Weighted) 1 Line Input Microphone Input Total Harmonic Distortion Plus Noise (THD + N) Test Conditions/Comments See Figure 46 DC-coupled, VCM at AINxP/AINxN = 7 V DC-coupled, VCM at AINxP/AINxN = 7 V See Figure 46, MICBIAS = 8.5 V DC-coupled, VCM at AINxP = 5.66 V, AINxN = 2.83 V Min Typ Max VCM at AINxP/AINxN pins VCM + V ac peak at AINxP/AINxN pins 0 0 8 14 V peak V dc V Programmable from 5 V to 9 V in steps of 0.5 V; the output voltage is within the specified load regulation From no load to maximum load of 25 mA at 5 V From no load to maximum load of 45 mA at 9 V At MICBIAS = 5 V At MICBIAS = 9 V 20 Hz to 20 kHz, MICBIAS = 5 V 20 Hz to 20 kHz, MICBIAS = 9 V 350 mV rms, 1 kHz ripple on VBOOST_IN at 10 V Referred to full scale at 1 kHz With CLOAD = 1 nF 5 9 V +1 +1 25 45 32 54 % % mA mA µV rms µV rms dB dB ms 3.63 10 5 V rms V rms 2 V rms 5 −1 −1 −1 +1 V mA mA mA mA % −1 +1 % 22 mA peak MHz MHz µF fS = 48 kHz L = 2.2 µH fS = 48 kHz, L = 4.7 µH 4.7 Between AINxP and AINxN Between AINxP and AINxN Input = 1 kHz, −60 dBFS Referred to full-scale differential input = 10 V rms Referred to full-scale differential input = 2 V rms Input = 1 kHz, −1 dBFS (0 dBFS = 10 V rms input) Rev. C | Page 4 of 68 +0.2 +0.3 22 35 60 60 40 2.97 L = 4.7 µH, fSW = 1.536 MHz, MICBIAS = 9 V at 45 mA load L = 2.2 µH, fSW = 3.072 MHz, MICBIAS = 9 V at 45 mA load MICBIAS = 5 V MICBIAS = 9 V From no load to maximum load of 50 mA at MICBIAS =5V From no load to maximum load of 88 mA at MICBIAS =9V Unit 103 3.3 195 220 50 88 900 3.072 1.536 10 50 25 24 kΩ kΩ Bits 109 95 −95 dB dB dB −89 Data Sheet Parameter Digital Gain Post ADC Gain Error Interchannel Gain Mismatch Gain Drift Common-Mode Rejection Ratio (CMRR) Power Supply Rejection Ratio (PSRR) Interchannel Isolation Interchannel Phase Deviation REFERENCE Internal Reference Voltage Output Impedance ADC SERIAL PORT Output Sample Rate 1 ADAU1977 Test Conditions/Comments Gain step size = 0.375 dB Min −35.625 −10 −0.25 Typ Max +60 +10 +0.25 Unit dB % dB ppm/°C dB dB dB dB Degrees 1.54 V kΩ 192 kHz 0.6 60 56 70 100 0 1 V rms, 1 kHz 1 V rms, 20 kHz 100 mV rms, 1 kHz on AVDDx = 3.3 V VREF pin 1.47 1.50 20 8 For fS ranging from 44.1 kHz to 192 kHz. DIAGNOSTIC AND FAULT SPECIFICATIONS Applicable to differential microphone input using MICBIAS on AINxP and AINxN pins. Table 2. Parameter INPUT VOLTAGE THRESHOLDS FOR FAULT DETECTION1 Hysteresis AINxP or AINxN Shorted to VBAT Hysteresis AINxP and AINxN Shorted Together Hysteresis AINxP or AINxN Shorted to Ground Hysteresis AINxP Shorted to MICBIAS Hysteresis AINxP or AINxN Open Circuit 2 FAULT DURATION Test Conditions/ Comments Min Typ Max Unit SHT_B_TRIP = 10 SHT_B_TRIP = 01 SHT_B_TRIP = 00 SHT_B_TRIP = 11 SHT_T_TRIP = 00 0.79 × VBAT 0.84 × VBAT 0.89 × VBAT 0.93 × VBAT MICBIAS(0.5 ± 0.015) MICBIAS(0.5 ± 0.001) SHT_T_TRIP = 10 MICBIAS(0.5 ± 0.05) SHT_G_TRIP = 10 SHT_G_TRIP = 01 SHT_G_TRIP = 00 SHT_G_TRIP = 11 SHT_M_TRIP = 10 SHT_M_TRIP = 01 SHT_M_TRIP = 00 SHT_M_TRIP = 11 Refer to the AINxP shorted to MICBIAS and the AINxN shorted to ground specifications for upper and lower thresholds. Programmable 0.04 × VREF 0.08 × VREF 0.12 × VREF 0.19 × VREF 0.82 × MICBIAS 0.87 × MICBIAS 0.92 × MICBIAS 0.95 × MICBIAS 0.86 × VBAT 0.91 × VBAT 0.96 × VBAT 0.99 × VBAT MICBIAS(0.5 ± 0.047) MICBIAS(0.5 ± 0.03) MICBIAS(0.5 ± 0.08) 0.13 × VREF 0.16 × VREF 0.22 × VREF 0.28 × VREF 0.89 × MICBIAS 0.94 × MICBIAS 1.0 × MICBIAS 1.0 × MICBIAS V V V V V SHT_T_TRIP = 01 0.85 × VBAT 0.9 × VBAT 0.95 × VBAT 0.975 × VBAT MICBIAS(0.5 ± 0.035) MICBIAS(0.5 ± 0.017) MICBIAS(0.5 ± 0.071) 0.1 × VREF 0.133 × VREF 0.2 × VREF 0.266 × VREF 0.85 × MICBIAS 0.9 × MICBIAS 0.95 × MICBIAS 0.975 × MICBIAS 10 100 150 ms V V V V V V V V V V The threshold limits are tested with VREF = 1.5 V, MICBIAS = 5 V to 8.5 V, and VBAT = 11 V to 18 V set using an external source. When VBAT ≤ MICBIAS, a short to VBAT cannot be distinguished from a short to MICBIAS, and reporting a short to VBAT fault takes precedence over a short to MICBIAS fault. 2 The AINxP open terminal fault cannot be distinguished from the AINxN open terminal fault because the voltage at the AINxP and AINxN pins remain at MICBIAS and ground, respectively, when either of these two terminals becomes open circuit. 1 Rev. C | Page 5 of 68 ADAU1977 Data Sheet DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 3. Parameter INPUT High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage Current Input Capacitance OUTPUT High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Test Conditions/Comments Min Max Unit 0.3 × IOVDD ±10 5 V V µA pF 0.4 V V 0.7 × IOVDD IOH = 1 mA IOL = 1 mA IOVDD − 0.60 POWER SUPPLY SPECIFICATIONS L = 4.7 µH, AVDDx = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V, fS = 48 kHz (master mode), unless otherwise noted. Table 4. Parameter DVDD AVDDx IOVDD VBAT 1 IOVDD Current Normal Operation Power-Down AVDDx Current Normal Operation Power-Down Boost Converter Current Normal Operation Power-Down DVDD Current Normal Operation Power-Down VBAT Current Normal Operation Power-Down POWER DISSIPATION Normal Operation AVDDx Power-Down, All Supplies 1 Test Conditions/Comments On-chip LDO Master clock = 256 fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz Min 1.62 3.0 1.62 Typ 1.8 3.3 3.3 14.4 Max 1.98 3.6 3.6 18 Unit V V V V 450 880 1.75 20 µA µA mA µA Boost off, 4-channel ADC, DVDD internal Boost on, 4-channel ADC, DVDD internal Boost off, 4-channel ADC, DVDD external Boost on, 4-channel ADC, DVDD external 14 14.5 9.6 10.1 270 mA mA mA mA µA Boost on, 4-channel ADC, MICBIAS = 8.5 V, no load Boost on, 4-channel ADC, MICBIAS = 8.5 V, 42 mA 34 168 180 mA mA µA DVDD external = 1.8 V 4.5 65 mA µA VBAT = 14.4 V 575 575 Master clock = 256 fS, 48 kHz DVDD internal, MICBIAS = 8.5 V at 42 mA load PD/RST pin held low 265 9 625 625 µA µA mW mW When VBAT ≤ MICBIAS, a short to VBAT cannot be distinguished from a short to MICBIAS, and reporting a short to VBAT fault takes precedence over a short to MICBIAS fault. Rev. C | Page 6 of 68 Data Sheet ADAU1977 DIGITAL FILTERS SPECIFICATIONS Table 5. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay HIGH-PASS FILTER Cutoff Frequency Phase Deviation Settling Time ADC DIGITAL GAIN Gain Step Size Mode All modes, typical at fS = 48 kHz Factor Min 0.4375 × fS Typ Max 21 ±0.015 24 27 0.5 × fS 0.5625 × fS 479 35 kHz dB kHz kHz dB µs µs 0.9375 10 Hz Degrees 79 fS = 8 kHz to 96 kHz fS = 192 kHz All modes, typical at 48 kHz At −3 dB point At 20 Hz All modes 22.9844/fS 0 60 0.375 Rev. C | Page 7 of 68 Unit dB dB ADAU1977 Data Sheet TIMING SPECIFICATIONS Table 6. Parameter INPUT MASTER CLOCK (MCLK) Duty Cycle fMCLK RESET Reset Pulse PLL Lock Time I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tDH tSCR tSCF tSDR tSDF tBFT tSUSTO SPI PORT tCCPH tCCPL fCCLK tCDS tCDH tCLS tCLH tCLPH tCOE tCOD tCOTS ADC SERIAL PORT tABH tABL tALS tALH tABDD Limit at Min Max Unit Description 40 60 See Table 10 % MHz MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS MCLKIN frequency, PLL in MCLK mode 15 ns RST low 10 ms 400 kHz µs µs µs µs ns 300 300 300 300 ns ns ns ns µs µs SCL frequency SCL high SCL low Setup time; relevant for repeated start condition Hold time; after this period of time, the first clock pulse is generated Data setup time Data hold time SCL rise time SCL fall time SDA rise time SDA fall time Bus-free time; time between stop and start Setup time for stop condition 30 30 30 ns ns MHz ns ns ns ns ns ns ns ns CCLK high CCLK low CCLK frequency CIN setup to CCLK rising CIN hold from CCLK rising CLATCH setup to CCLK rising CLATCH hold from CCLK rising CLATCH high COUT enable from CLATCH falling COUT delay from CCLK falling COUT tristate from CLATCH rising 18 ns ns ns ns ns BCLK high, slave mode BCLK low, slave mode LRCLK setup to BCLK rising, slave mode LRCLK hold from BCLK rising, slave mode SDATAOUTx delay from BCLK falling 0.6 1.3 0.6 0.6 100 0 1.3 0.6 35 35 10 10 10 10 40 10 10 10 10 5 Rev. C | Page 8 of 68 Data Sheet ADAU1977 tALS LRCLK tALH tABH BCLK tABL SDATAOUTx LEFT JUSTIFIED MODE tABDD MSB MSB – 1 tABDD SDATAOUTx I2S MODE MSB tABDD SDATAOUTx RIGHT JUSTIFIED MODE LSB MSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 10296-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2. Serial Output Port Timing tCLH tCLS tCOE tCLPH tCCPL tCCPH CLATCH CCLK CIN tCDH tCDS 10296-003 tCOTS COUT tCOD Figure 3. SPI Port Timing tSCH tDS tSDR STOP tSCH START SDA tSDF tSCLH tBFT tSCR tSCLL tDH tSCF tSCS Figure 4. I2C Port Timing Rev. C | Page 9 of 68 tSUSTO 10296-004 SCL ADAU1977 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter Analog Supply (AVDDx) Digital Supply DVDD IOVDD Input Current (Except Supply Pins) Analog Input Voltage (AINx, VBAT Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Ambient) Junction Temperature Range Storage Temperature Range Rating −0.3 V to +3.63 V −0.3 V to +1.98 V −0.3 V to +3.63 V ±20 mA −0.3 V to +18 V −0.3 V to +3.63 V −40°C to +105°C −40°C to +125°C −65°C to +150°C θJA represents thermal resistance, junction-to-ambient, and θJC represents the thermal resistance, junction-to-case. All characteristics are for a standard JEDEC board per JESD51. Table 8. Thermal Resistance Package Type 40-Lead LFCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 10 of 68 θJA 32.8 θJC 1.93 Unit °C/W Data Sheet ADAU1977 40 39 38 37 36 35 34 33 32 31 AVDD1 AIN4P AIN4N AIN3P AIN3N AIN2P AIN2N AIN1P AIN1N AVDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADAU1977 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 VBAT AGND3 MB_GND MICBIAS VBOOST_IN VBOOST_OUT SW SW PGND PGND 10296-005 DGND IOVDD SDATAOUT1 SDATAOUT2 LRCLK BCLK SDA/COUT SCL/CCLK ADDR0/CLATCH ADDR1/CIN 11 12 13 14 15 16 17 18 19 20 AGND1 1 VREF 2 PLL_FILT 3 AVDD2 4 AGND2 5 PD/RST 6 MCLKIN 7 FAULT 8 SA_MODE 9 DVDD 10 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO THE GROUND PLANE ON THE PCB. Figure 5. Pin Configuration, 40-Lead LFCSP Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic AGND1 VREF PLL_FILT AVDD2 AGND2 PD/RST MCLKIN FAULT SA_MODE DVDD DGND IOVDD SDATAOUT1 SDATAOUT2 LRCLK BCLK SDA/COUT SCL/CCLK ADDR0/CLATCH ADDR1/CIN PGND PGND SW SW VBOOST_OUT VBOOST_IN MICBIAS MB_GND In/Out 1 P O O P P I I O I O P P O O I/O I/O I/O I I I P P I I O I O P 29 30 AGND3 VBAT P I Description Analog Ground. Voltage Reference. Decouple this pin to AGNDx with 10 µF||100 nF capacitors. PLL Loop Filter. Return this pin to AVDDx using recommended loop filter components. Analog Power Supply. Connect this pin to analog 3.3 V supply. Analog Ground. Power-Down Reset (Active Low). Master Clock Input. Fault Output. Programmable logic output. Standalone Mode. Connect this pin to IOVDD using a 10 kΩ pull-up resistor for standalone mode. 1.8 V Digital Power Supply Output. Decouple this pin to DGND with a 0.1 µF capacitor. Digital Ground. Digital Input and Output Power Supply. Connect this pin to a supply in the range of 1.8 V to 3.3 V. ADC Serial Data Output Pair 1. ADC Serial Data Output Pair 2. Frame Clock for the ADC Serial Port. Bit Clock for the ADC Serial Port. Serial Data Output I2C/Control Data Output (SPI). Serial Clock Input I2C/Control Clock Input (SPI). Chip Address Bit 0 Setting I2C/Chip Select Input for Control Data (SPI). Chip Address Bit 1 Setting I2C/Control Data Input (SPI). Power Ground Boost Converter. Power Ground Boost Converter. Inductor Switching Terminal. Inductor Switching Terminal. Boost Converter Output. Decouple this pin to PGND with a 10 µF capacitor. MICBIAS Regulator Input. Connect this pin to VBOOST_OUT (Pin 25). Microphone Bias Output. Decouple this pin to AGNDx using a 10 µF capacitor. Analog Return Ground for the Microphone Bias Regulator. Connect this pin directly to AGNDx for best noise performance. Analog Ground. Voltage Sense for Diagnostics. Connect this pin to a load dump suppressed battery voltage. Decouple this to AGNDx using a 0.1 µF capacitor. Rev. C | Page 11 of 68 ADAU1977 Pin No. 31 32 33 34 35 36 37 38 39 40 1 Mnemonic AVDD3 AIN1N AIN1P AIN2N AIN2P AIN3N AIN3P AIN4N AIN4P AVDD1 EP Data Sheet In/Out1 P I I I I I I I I P Description Analog Power Supply. Connect this pin to an analog 3.3 V supply. Analog Input Channel 1 Inverting Input. Analog Input Channel 1 Noninverting Input. Analog Input Channel 2 Inverting Input. Analog Input Channel 2 Noninverting Input. Analog Input Channel 3 Inverting Input. Analog Input Channel 3 Noninverting Input. Analog Input Channel 4 Inverting Input. Analog Input Channel 4 Noninverting Input. Analog Power Supply. Connect this pin to an analog 3.3 V supply. Exposed Pad. The exposed pad must be connected to the ground plane on the printed circuit board (PCB). I = input, O = output, I/O = input/output, and P = power. Rev. C | Page 12 of 68 Data Sheet ADAU1977 0 –10 –20 –50 –80 –90 –100 –110 –120 –130 –140 –160 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) 10296-006 –150 0 –10 –20 –20 –30 –30 –40 –40 –50 –50 AMPLITUDE (dBFS) 0 –10 –60 –70 –80 –90 –100 –110 –70 –80 –90 –100 –110 –120 –130 –130 –140 –140 –150 –150 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) 20k –60 –120 –160 10k Figure 9. CMRR Differential Input, Referenced to 1 V Differential Input –160 10296-007 AMPLITUDE (dBFS) Figure 6. Fast Fourier Transform, 2 mV Differential Input at fS = 48 kHz 1k FREQUENCY (Hz) 100 0 2 4 6 8 10 12 14 16 18 FREQUENCY (kHz) 20 10296-010 –60 –70 CMRR (dB) AMPLITUDE (dBFS) –30 –40 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 20 10296-009 TYPICAL PERFORMANCE CHARACTERISTICS Figure 10. Fast Fourier Transform, No Input Figure 7. Fast Fourier Transform, −1 dBFS Differential Input 0.10 0 –10 0.08 –20 –30 0.06 –40 0.04 MAGNITUDE (dB) –60 –70 –80 –90 –100 –110 0.02 0 –0.02 –0.04 –120 –130 –0.06 –140 –0.08 –160 0 2 4 6 8 INPUT AMPLITUDE (V rms) 10 12 –0.10 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 FREQUENCY (Hz) Figure 11. ADC Pass-Band Ripple at fS = 48 kHz Figure 8. THD + N vs. Input Amplitude Rev. C | Page 13 of 68 10296-011 –150 10296-008 THD + N (dB) –50 ADAU1977 Data Sheet 0 –10 –20 –40 –50 –60 –70 –80 –90 –100 0 5000 10000 15000 20000 25000 30000 35000 40000 FREQUENCY (Hz) 10296-012 MAGNITUDE (dB) –30 Figure 12. ADC Filter Stop-Band Response at fS = 48 kHz Rev. C | Page 14 of 68 Data Sheet ADAU1977 THEORY OF OPERATION The ADAU1977 incorporates four high performance ADCs with an integrated boost converter for microphone bias, the associated microphone diagnostics for fault detection, and a phase-locked loop circuit for generating the necessary on-chip clock signals. POWER SUPPLY AND VOLTAGE REFERENCE The ADAU1977 requires a single 3.3 V power supply. Separate power supply input pins are provided for the analog and boost converter. These pins should be decoupled to AGND with 100 nF ceramic chip capacitors placed as close as possible to the pins to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 10 μF must be provided on the same PCB as the ADC. It is important that the analog supply be as clean as possible for best performance. The supply voltage for the digital core (DVDD) is generated using an internal low dropout regulator. The typical DVDD output is 1.8 V and must be decoupled using a 100 nF ceramic capacitor and a 10 µF capacitor. Place the 100 nF ceramic capacitor as close as possible to the DVDD pin. The voltage reference for the analog blocks is generated internally and output at the VREF pin (Pin 2). The typical voltage at the pin is 1.5 V with an AVDDx of 3.3 V. All digital inputs are compatible with TTL and CMOS levels. All outputs are driven from the IOVDD supply. The IOVDD can be in the range of 1.8 V to 3.3 V. The IOVDD pin must be decoupled with a 100 nF capacitor placed as close to the IOVDD pin as possible. It is recommended to connect the AGND, DGND, PGND, and exposed pad to a single GND plane on the PCB for best performance. The ADC internal voltage reference is output from the VREF pin and should be decoupled using a 100 nF ceramic capacitor in parallel with a 10 μF capacitor. The VREF pin has limited current capability. The voltage reference is used as a reference to the ADC; therefore, it is recommended not to draw current from this pin for external circuits. When using this reference, use a noninverting amplifier buffer to provide a reference to other circuits in the application. In reset mode, the VREF pin is disabled to save power and is enabled only when the RST pin is pulled high. POWER-ON RESET SEQUENCE The ADAU1977 requires that a single 3.3 V power supply be provided externally at the AVDDx pin. The part internally generates DVDD (1.8 V), which is used for the digital core of the ADC. The DVDD supply output pin (Pin 10) is provided to connect the decoupling capacitors to DGND. The typical recommended values for the decoupling capacitors are 100 nF in parallel with 10 µF. During a reset, the DVDD regulator is disabled to reduce power consumption. After the PD/RST pin (Pin 6) is pulled high, the part enables the DVDD regulator. However, the internal ADC and digital core reset is controlled by the internal POR signal (power-on reset) circuit, which monitors the DVDD level. Therefore, the device does not come out of a reset until DVDD reaches 1.2 V and the POR signal is released. The DVDD settling time depends on the charge-up time for the external capacitors and on the AVDDx ramp-up time. The internal POR circuit is provided with hysteresis to ensure that a reset of the part is not initiated by an instantaneous glitch on DVDD. The typical trip points are 1.2 V with RST high and 0.6 V (±20%) with RST low. This ensures that the core is not reset until the DVDD level falls below the 0.6 V trip point. As soon as the PD/RST pin is pulled high, the internal regulator starts charging up the CEXT on the DVDD pin. The DVDD chargeup time is based on the output resistance of the regulator and the external decoupling capacitor. The time constant can be calculated as tC = ROUT × CEXT (ROUT = 20 Ω typical) For example, if CEXT is 10 µF, then tC is 200 µs and is the time to reach the DVDD voltage, within 63.6%. The POR circuit releases an internal reset of the core when DVDD reaches 1.2 V (see Figure 13). Therefore, it is recommended to wait for at least the tC period to elapse before sending I2C or SPI control signals. AVDDx PD/RST tRESET tC DVDD (1.8V) 1.2V tD 0.48V 10296-013 OVERVIEW POR Figure 13. Power-On Reset Timing When applying a hardware reset to the part by pulling the PD/RST pin (Pin 6) low and then high, there are certain time restrictions. During the RST low pulse period, the DVDD starts discharging. The discharge time constant is decided by the internal resistance of the regulator and CEXT. The time required for DVDD to fall from 1.8 V to 0.48 V (0.6 V − 20%) can be estimated using the following equation: tD = 1.32 × RINT × CEXT where RINT = 64 kΩ typical. (RINT can vary due to process by ±20%.) For example, if CEXT is 10 µF, then tD is 0.845 sec. Rev. C | Page 15 of 68 ADAU1977 Data Sheet Depending on CEXT, tD may vary and in turn decide the minimum hold period for the RST pulse. The RST pulse must be held low for the tD time period to initialize the core properly. The required RST low pulse period can be reduced by adding a resistor across CEXT. The new tD value can then be calculated as tD = 1.32 × REQ × CEXT where REQ = 64 kΩ || REXT. The resistor ensures that DVDD not only discharges quickly during a reset or an AVDDx power loss but also resets the internal blocks correctly. Note that some power loss in this resistor is to be expected because the resistor constantly draws current from DVDD. The typical value for CEXT is 10 µF and for REXT is 3 kΩ. This results in a time constant of tD = 1.32 × REQ × CEXT = 37.8 ms where REQ = 2.866 kΩ (64 kΩ || 3 kΩ). Using this equation at a set CEXT value, the REXT can be calculated for a desired RST pulse period. There is also a software reset register (S_RST, Bit 7 of Register 0x00) available that can be used to reset the part, but it must be noted that during an AVDDx power loss, the software reset may not ensure proper initialization because DVDD may not be stable. +3.3V AVDD1 AVDD3 AVDD2 3.3V TO 1.8V REGULATOR TO INTERNAL BLOCKS DVDD C 0.1µF CEXT 10µF MLCC X7R REXT 3kΩ +1.8V OR +3.3V The PLL_LOCK bit (Bit 7) of Register 0x01 indicates the lock status of the PLL. It is recommended that after initial power-up the PLL lock status be read to ensure that the PLL outputs the correct frequency before unmuting the audio outputs. Table 10. Required Input MCLK for Common Sample Rates MCS (Bits[2:0]) 000 001 010 011 100 000 001 010 011 100 000 001 010 011 100 000 001 010 011 100 000 001 010 011 100 fS (kHz) 32 32 32 32 32 44.1 44.1 44.1 44.1 44.1 48 48 48 48 48 96 96 96 96 96 192 192 192 192 192 Frequency Multiplication Ratio 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 64 × fS 128 × fS 192 × fS 256 × fS 384 × fS 32 × fS 64 × fS 96 × fS 128 × fS 192 × fS MCLKIN Frequency (MHz) 4.096 8.192 12.288 16.384 24.576 5.6448 11.2896 16.9344 22.5792 33.8688 6.144 12.288 18.432 24.576 36.864 6.144 12.288 18.432 24.576 36.864 6.144 12.288 18.432 24.576 36.864 IOVDD Figure 14. DVDD Regulator Output Connections PLL AND CLOCK The ADAU1977 has a built-in analog PLL to provide a jitterfree master clock to the internal ADC. The PLL must be programmed for the appropriate input clock frequency. The PLL Control Register 0x01 is used for setting the PLL. The CLK_S bit (Bit 4) of Register 0x01 is used for setting the clock source for the PLL. The clock source can be either the MCLKIN pin or the LRCLK pin (slave mode). In LRCLK mode, the PLL can support sample rates between 32 kHz and 192 kHz. The PLL can accept the audio frame clock (sample rate clock) as input, but the serial port must be configured as a slave and the frame clock must be fed to the part from the master. It is strongly recommended that the PLL be disabled, reprogrammed with the new setting, and then reenabled. A lock bit is provided that can be polled via the I2C to check whether the PLL has acquired lock. The PLL requires an external filter, which is connected at the PLL_FILT pin (Pin 3). The recommended PLL filter circuit for MCLK or LRCLK mode is shown in Figure 15. Using NPO capacitors is recommended for temperature stability. Place the filter components close to the device for best performance. In MCLK input mode, the MCS bits (Bits[2:0] of Register 0x01) must be set to the desired input clock frequency for the MCLKIN pin. Table 10 shows the input MCLK required for the most common sample rates and the MCS bit settings. Rev. C | Page 16 of 68 AVDDx AVDDx 5.6nF 39nF 4.87kΩ 2.2nF 1kΩ PLL_LF PLL_LF LRCLK MODE MCLK MODE Figure 15. PLL Filter 390pF 10296-014 C 0.1µF 10296-114 ADAU1977 Data Sheet ADAU1977 DC-TO-DC BOOST CONVERTER The boost converter generates a supply voltage for the microphone bias circuit from a fixed 3.3 V supply. The boost converter output voltage is programmable using Register 0x03. The boost converter output voltage is approximately 1 V above the set microphone bias voltage. The boost converter uses the clock from the PLL, and the switching frequency is dependent on the sample rate of the ADC. The FS_RATE bits (Bits[6:5] of Register 0x02) must be set to the desired sample rate. The boost converter switching frequency can be selected to be 1.5 MHz or 3 MHz using Bit 4 of Register 0x02. For the 1.5 MHz switching frequency, the recommended value for the inductor is 4.7 µH, whereas for the 3 MHz switching frequency, the recommended value for the inductor is 2.2 µH. Table 11 lists the typical switching frequency based on the sample rates. Capacitor Selection The boost converter output is available at the VBOOST_OUT pin (Pin 25) and must be decoupled to PGND using a 10 µF ceramic capacitor to remove the ripple at the switching frequency. The capacitor must have low ESR and good temperature stability. The MLCC X7R/NPO dielectric type with 25 V is recommended. Care must be taken to place this capacitor as close as possible to the VBOOST_OUT pin (Pin 25). Table 11. Typical Switching Frequency Based on the Sample Rates Base Sample Rate (kHz) 32 44.1 48 Boost Converter Switching Frequency Inductor = 2.2 µH Inductor = 4.7 µH (1024/12) × fS (1024/22) × fS (1024/16) × fS (1024/30) × fS (1024/16) × fS (1024/32) × fS Sample Rates (kHz) 8/16/32/64 11.025/22.05/44.1/88.2/176.4 12/24/48/96/192 Rev. C | Page 17 of 68 ADAU1977 Data Sheet MICROPHONE BIAS The block diagram shown in Figure 16 represents the typical input circuit. The microphone bias is generated by the input voltage at the VBOOST_IN pin (Pin 26) via a linear regulator to ensure low noise performance and to reject the high frequency noise from the boost converter. If the internal boost converter output is used, the VBOOST_OUT pin (Pin 25) must be connected to the VBOOST_IN pin (Pin 26). If an external supply is used for the microphone bias, the supply can be fed at the VBOOST_IN pin (Pin 26); in this case, leave the VBOOST_OUT pin (Pin 25) open. The microphone bias voltage is programmable from 5 V to 9 V by using the MB_VOLTS bits (Bits[7:4] of Register 0x03). The microphone bias output voltage is available at the MICBIAS pin (Pin 27). This pin can be decoupled to AGND using a maximum of up to a 10 µF capacitor with an ESR of at least 1 Ω. For higher value capacitors, especially those above 1 nF, the ESR of the capacitor should be ≥ 1 Ω to ensure the stability of the microphone bias regulator. Register 0x03 can be used to enable the microphone bias. Table 11 lists the switching frequency of the boost converter based on the inductor value and common sample rates. In most audio applications, the dc content of the signal is removed by using a coupling capacitor. However, the ADAU1977 consists of a unique input structure that allows direct coupling of the input signal, eliminating the need for using a large coupling capacitor at the input. Each input has a fixed 14 dB attenuator connected to AGND for accommodating a 10 V rms differential input. The typical input resistance is approximately 26 kΩ from each input to AGND. In dc-coupled applications, if the VCM at AINxP and AINxN is the same, the dc content in the ADC output is close to 0. If the input pins are presented with different common-mode dc levels, the difference between the two levels appears at the ADC output and can be removed by enabling the high-pass filter. The high-pass filter has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency scales directly with the sample frequency. However, care is required in dc-coupled applications to ensure that the common-mode dc voltage does not exceed the specified limit. The common-mode loop can accommodate a common-mode dc voltage from 0 V to 7 V. The input required for the full-scale ADC output (0 dBFS) is typically 10 V rms differential. ANALOG INPUTS The ADAU1977 has four differential analog inputs. The ADCs can accommodate both dc- and ac-coupled input signals. R 2R VX R AINxP R VREF AINxN 2R VY R R Figure 16. Analog Input Block Rev. C | Page 18 of 68 10296-015 R VID = V INPUT DIFFERENTIAL VICM+ = VCM AT AINx+ VICM– = VCM AT AINx– Data Sheet ADAU1977 Line Inputs This section describes some of the possible ways to connect the ADAU1977 for line level inputs. Line Input Balanced or Differential Input DC-Coupled Case For example, in the case of a typical power amplifier for an automobile, the output can swing around 10 V rms differential with approximately 7.2 V common-mode dc input voltage (assuming a 14.4 V battery and bridge-tied load connection). The signal at each input pin has a 5 V rms or 14.14 V p-p signal swing. With a common-mode dc voltage of 7.2 V, the signal can swing between (7.2 V + 7.07 V) = +14.27 V p-p and (7 V − 7.07 V) = 0.13 V at each input. Therefore, this results in approximately a 28.54 V p-p differential signal swing and measures around −0.16 dBFS (ac only with dc high-pass filter) at the ADC output. See Figure 17. Line Input Balanced or Differential Input AC-Coupled Case For an amplifier output case with ac coupling, refer to Figure 18 for information about connecting the line level inputs to the ADAU1977. In this case, the AINxP/AINxN pins must be pulled up to the required common-mode level using the resistors on MICBIAS. The VCM must be such that the input never swings below a ground. In other words, if the input signal is 14 V p-p, the VCM must be around 14 V/2 = 7 V to ensure that the signal never swings below a ground. The microphone bias can provide the required clean reference for generating the VCM. The R1 value can be calculated as follows: R1 = Rin1977 (MB − VCM)/VCM where: VCM is the peak-to-peak input swing divided by 2. MB = 8.5 V. Rin1977 is the single-ended input resistance (see Table 1). Line Input Unbalanced or Single-Ended Pseudo Differential AC-Coupled Case For a single-ended application, the signal swing is reduced by half because only one input is used for the signal, and the other input is connected to 0 V. As a result, the input signal capability is reduced to 5 V rms in a single-ended application. With a common-mode dc voltage of 7.2 V, the signal can swing between (7.2 V + 7.07 V) = +14.27 V p-p and (7.2 V − 7 V) = 0.13 V. Therefore, this results in approximately a 14.14 V p-p differential signal swing and measures around −6.16 dBFS (ac only with dc high-pass filter) at the ADC output. See Figure 19. The values of the resistors (R1/R2) and capacitors (C1/C2) are similar to those for the balanced ac-coupled case described in the Line Input Balanced or Differential Input AC-Coupled Case section. Line Input Unbalanced or Single-Ended AC-Coupled Case For a single-ended application, the signal swing is reduced by half because only one input is used for the signal, and the other input is connected to 0 V. As a result, the input signal capability is reduced to 5 V rms in a single-ended application. With a common-mode dc voltage of 7.2 V, the signal can swing between (7.2 V + 7.07 V) = +14.27 V p-p and (7.2 V − 7 V) = 0.13 V. Therefore, this results in approximately a 14.14 V p-p differential signal swing and measures around −6.16 dBFS (ac only with dc high-pass filter) at the ADC output. The difference in the common-mode dc voltage between the positive and negative input (7.2 V) would appear at the ADC output if the signal was not high-pass filtered. See Figure 20. The values of the resistor (R1) and capacitor (C1) are similar to those for the balanced ac-coupled case described in the Line Input Balanced or Differential Input AC-Coupled Case section. However, in this case the equivalent input resistance of AINxP/ AINxN is reduced and can be calculated as R1 || Rin1977. Input Resistance = R1 × Rin1977/(R1 + Rin1977) where Rin1977 is the single-ended value from Table 1. The C1 and C2 values can be determined for the required low frequency cutoff using the following equation: C1 or C2 = 1/(2 × π × fC × Input Resistance) Rev. C | Page 19 of 68 ADAU1977 Data Sheet TYPICAL AUDIO POWER AMPLIFIER OUTPUT AINx+ ATTENUATOR 14dB ADAU1977 VDIFF = 10V rms AC VCM = 7V DC 10296-016 AINx– Figure 17. Connecting the Line Level Inputs—Differential DC-Coupled Case C3 TYPICAL AUDIO POWER AMPLIFIER OUTPUT MICBIAS R1 R2 C1 AINx+ ATTENUATOR 14dB ADAU1977 VDIF f = 10V RMS AC 10296-017 AINx– C2 Figure 18. Connecting the Line Level Inputs—Differential AC-Coupled Case C3 TYPICAL AUDIO POWER AMPLIFIER OUTPUT MICBIAS R1 C1 R2 AINx+ ATTENUATOR 14dB C2 ADAU1977 VIN = 5V rms AC 10296-018 AINx– Figure 19. Connecting the Line Level Inputs—Pseudo Differential AC-Coupled Case C3 TYPICAL AUDIO POWER AMPLIFIER OUTPUT C1 MICBIAS R1 AINx+ ATTENUATOR 14dB ADAU1977 VIN = 5V rms AC Figure 20. Connecting the Line Level Inputs—Single-Ended AC-Coupled Case Rev. C | Page 20 of 68 10296-019 AINx– Data Sheet ADAU1977 Microphone Inputs level of 2/3 × MICBIAS on the AINxP and 1/3 × MICBIAS on the AINxN pins, this results in around −14 dBFS (ac only with dc high-pass filter) at the ADC output because the input is 14 dB below the full-scale input of 10 V rms differential. See Figure 21. This section describes some ways to connect the ADAU1977 for microphone input applications. The MICBIAS voltage and the bias resistor value depend on the ECM selected. The ADAU1977 can provide the MICBIAS from 5 V up to 9 V in 0.5 V steps. In an application requiring multiple microphones, care must be taken not to exceed the MICBIAS output current rating. ECM Pseudo Differential Input AC-Coupled Case For a typical MEMS ECM module, the output signal swing is low. With a typical 3.3 V supply, the ECM module can output a 2 V rms differential signal. The signal at the input pin has a 1 V rms or 2.8 V p-p signal swing. For this application, it is recommended to bias the input pins using resistors to 7 V dc, similar to the case described in the Line Input Unbalanced or Single-Ended Pseudo Differential AC-Coupled Case section. See Figure 22. ECM Balanced or Differential Input DC-Coupled Case For example, in a typical ECM, the output signal swing depends on the MICBIAS voltage. With a typical 8.5 V supply, the ECM can output a 2 V rms differential signal. The signal at each input pin has a 1 V rms or 2.8 V p-p signal swing. With a common-mode dc MICBIAS TYPICAL ECM MODULE R MICROPHONE AINx+ ATTENUATOR 14dB AINx– ADAU1977 R 10296-020 VIN = 2V rms AC DIFFERENTIAL VCM+ ≈ 2/3 × MICBIAS VCM– ≈ 1/3 × MICBIAS R = TYPICAL 300Ω TO 500Ω NOTES 1. THE DIAGNOSTICS FEATURE IS AVAILABLE. Figure 21. Connecting the Microphone Inputs—Differential Input DC-Coupled Case TYPICAL ECM WITH PREAMP MODULE VDD C3 MICBIAS R1 R2 AINx+ ATTENUATOR 14dB AINx– NOTES 1. THE DIAGNOSTICS FEATURE IS NOT AVAILABLE. Figure 22. Connecting the Microphone Inputs—Pseudo Differential Input AC-Coupled Case Rev. C | Page 21 of 68 10296-021 ADAU1977 VMAX = 5V rms AC ADAU1977 Data Sheet ADC The ADAU1977 contains four Δ-Σ ADC channels configured as two stereo pairs with configurable differential/single-ended inputs. The ADC can operate at a nominal sample rate of 32 kHz up to 192 kHz. The ADCs include on-board digital antialiasing filters with 79 dB stop-band attenuation and linear phase response. Digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame clock (LRCLK) and bit clock (BCLK). Alternatively, one of the TDM modes can be used to support up to 16 channels on a single TDM data line. With smaller amplitude input signals, a 10-bit programmable digital gain compensation for an individual channel is provided to scale up the output word to full scale. Care must be taken to avoid overcompensation (large gain compensation), which leads to clipping and THD degradation in the ADC. The ADCs also have a dc-offset calibration algorithm to null the systematic dc offset of the ADC. This feature is useful for dc measurement applications. Inductor Selection For the boost converter to operate efficiently, the inductor selection is critical. The two most important parameters for the inductor are the saturation current rating and the dc resistance. The recommended saturation rating for the inductor must be >1 A. The dc resistance affects the efficiency of the boost converter. Assuming that the board trace resistances are negligible for 80% efficiency, the dc resistance of the inductor should be less than 50 mΩ. Table 12 lists some of the recommended inductors for the application. Each protection circuit has two modes for recovery after a fault event: autorecovery and manual recovery. The recovery mode can be selected using Bit 0 of Register 0x03. The autorecovery mode attempts to enable the boost converter after a set recovery time, typically 20 ms. The manual recovery mode enables the boost converter only if the user writes 1 to the MRCV bit (Bit 1). If the fault persists, the boost converter remains in shutdown mode until the fault is cleared. The boost converter is capable of supplying the 42 mA of total output current at the MICBIAS output. The boost converter has overcurrent protection at the input; the threshold is around 900 mA peak. Ensure that the 3.3 V power supply feeding the boost converter has built-in overcurrent protection because there is no protection internal to ADAU1977 for a short circuit to any of the ground pins (AGND/DGND/PGND) at the VBOOST_OUT or VBOOST_IN pin. By default, the boost converter is disabled on power-up to allow the flexibility of connecting an external voltage source at the VBOOST_IN pin to power the microphone bias circuit. The boost converter can be enabled by using the BOOST_EN bit (Bit 2 of Register 0x03). ADC SUMMING MODES The four ADCs can be grouped into either a single stereo ADC or a single mono ADC to increase the signal-to-noise ratio (SNR) for the application. Two options are available: one option for summing two channels of the ADC and another option for summing all four channels of the ADC. Summing is performed in the digital block. Table 12. Recommended Inductors1 2-Channel Summing Mode Value 2.2 μH 4.7 μH When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set to 01, the Channel 1 and Channel 2 ADC data are combined and output from the SDATAOUT1 pin. Similarly, the Channel 3 and Channel 4 ADC data are combined and output from the SDATAOUT2 pin. As a result, the SNR improves by 3 dB. For this mode, both Channel 1 and Channel 2 must be connected to the same input signal source. Similarly, Channel 3 and Channel 4 must be connected to the same input signal source. 1 Manufacturer Würth Elektronik Würth Elektronik Manufacturer Part Number 7440430022 7440530047 Check with the manufacturer for the appropriate temperature ratings for a given application. The boost converter has a soft start feature that prevents inrush current from the input source. The boost converter has built-in overcurrent and overtemperature protection. The input current to the boost converter is monitored and if it exceeds the set current threshold for 1.2 ms, the boost converter shuts down. The fault condition is recorded into Register 0x02 and asserts the fault interrupt pin. This condi tion is cleared after reading the BOOST_OV bit (Bit 2) or the BOOST_OC bit (Bit 0) in Register 0x02. The overcurrent protection bit, OC_EN (Bit 1), or the overvoltage protection bit, OV_EN (Bit 3), is on by default, and it is recommended not to disable the bit. 4-Channel Summing Mode When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set to 10, the Channel 1 through Channel 4 ADC data are combined and output from the SDATAOUT1 pin. As a result, the SNR improves by 6 dB. For this mode, all four channels must be connected to the same input signal source. Rev. C | Page 22 of 68 Data Sheet ADAU1977 DIAGNOSTICS Table 15. Setting the Short to MICBIAS Threshold The diagnostics block monitors the input pins in real time and reports a fault as an interrupt signal on the FAULT pin (Pin 8), which triggers sending an interrupt request to an external controller. The diagnostics status registers (Register 0x11 through Register 0x14) for Channel 1 through Channel 4 are also updated. Refer to the register map table (Table 25) and the register details tables (Table 42, Table 43, Table 44, and Table 45) for more information about the diagnostics register content. The diagnostics can be enabled or disabled for each channel using Bits[3:0] of Register 0x10. The diagnostics are provided only when MICBIAS is enabled and the microphone is connected as recommended in the appropriate application circuit (see Figure 21). SHT_M_TRIP (Register 0x17, Bits[5:4]) 00 01 10 11 Diagnostics Reporting The diagnostics status is reported individually for each channel in Register 0x11 through Register 0x14. The faults listed in Table 13 are reported on each input pin. Table 13. Faults Reported Fault Short to Battery Short to MICBIAS Short to Ground Short Between Positive and Negative Inputs Open Input AINxP Yes Yes Yes Yes Yes AINxN Yes No Yes Yes Yes Diagnostics Adjustments Short Circuit to Battery Supply When an input terminal is shorted to the battery, the voltage at the terminal approaches the battery voltage. Any voltage higher than the set threshold is reported as a fault. The threshold can be set using the SHT_B_TRIP bits, Bits[1:0] of Register 0x17 (see Table 14). Short Circuit to Ground When an input terminal is shorted to ground, the terminal voltage reaches close to 0 V. Any voltage lower than the set threshold is reported as a fault. The threshold is referenced to VREF and, therefore, scales with the voltage at the VREF pin. The threshold can be set using the SHT_G_TRIP bits, Bits[3:2] of Register 0x17 (see Table 16). Table 16. SHT_G_TRIP (Register 0x17, Bits[3:2]) 00 01 10 11 Short to Ground Threshold 0.2 × VREF 0.133 × VREF 0.1 × VREF 0.266 × VREF Microphone Terminal Short Circuited When both input terminals are shorted, both the AINxP and AINxN input terminals are at the same voltage—around MICBIAS/2. Any voltage between the set thresholds is reported as a fault. The upper and lower threshold voltages can be set using the SHT_T_TRIP bits, Bits[7:6] of Register 0x17 (see Table 17). The following equations can be used to calculate the upper and lower thresholds: Upper Threshold = MICBIAS(0.5 + x) Table 14. Setting the Short to Battery Threshold SHT_B_TRIP (Register 0x17, Bits[1:0]) 00 01 10 11 Short to MICBIAS Threshold 0.95 × MICBIAS 0.9 × MICBIAS 0.85 × MICBIAS 0.975 × MICBIAS Lower Threshold = MICBIAS(0.5 − x) where x can be set using the SHT_T_TRIP bits, Bits[7:6] of Register 0x17 (see Table 17). Short to Battery Threshold 0.95 × VBAT 0.9 × VBAT 0.85 × VBAT 0.975 × VBAT Table 17. Short Circuit to MICBIAS This feature is supported only on the AINxP terminal. When an AINxP terminal is shorted to MICBIAS, the voltage at the AINxP terminal approaches the MICBIAS voltage. Any voltage higher than the set threshold is reported as a fault. The threshold can be set using the SHT_M_TRIP bits, Bits[5:4] of Register 0x17 (see Table 15). SHT_T_TRIP (Register 0x17, Bits [7:6]) 00 01 10 11 Rev. C | Page 23 of 68 x 0.035 0.017 0.071 Reserved ADAU1977 Data Sheet Microphone Terminals Open In the event that any of the input terminals becomes open circuited, AINxP is pulled to MICBIAS and AINxN is pulled to a common ground. When the AINxP terminal is at a voltage that is higher than the short to the MICBIAS threshold (set using Bits[5:4] of Register 0x17) and the AINxN terminal voltage is at a voltage that is less than the short to the ground threshold (set using Bits[3:2] of Register 0x17), a fault is reported. The fault cannot indicate which terminal is open circuited because any terminal that is open circuited pulls AINxP to MICBIAS and AINxN to a common ground. FAULT Pin The FAULT pin is an output pin that can be programmed to be active high or active low logic using the IRQ_POL bit (Bit 4 of Register 0x15). In addition, the FAULT pin can be set using the IRQ_DRIVE bit (Bit 5 of Register 0x15) to drive always or to drive only during a fault and is otherwise set to high-Z. The fault status is registered in the IRQ_RESET bit (Bit 6 of Register 0x15). The IRQ_RESET bit is a latched bit and is set in the event of a fault and cleared only after the fault status bit is read. Fault Timeout To prevent the false triggering of a fault event, the fault timeout adjust bits (Bits[5:4] of Register 0x18) are provided. These bits can be used to set the time that the fault needs to persist before AINx+/ AINx– being reported. The timeout can be set to 0 ms, 50 ms, 100 ms, or 150 ms using the FAULT_TO bits (Bits[5:4] of Register 0x18). The default value is 100 ms. A fault is recorded only if the condition persists for more than a set minimum timeout. Fault Masking The faults can be masked to prevent triggering an interrupt on the FAULT pin. Fault masking can be set using Bits[6:0] of Register 0x16. The mask can be set for the faults listed in Table 18. Table 18. Fault Masking Fault Short to Battery Short to MICBIAS Short to Ground Short Between Positive and Negative Inputs Open Input AINxP Yes Yes Yes Yes Yes AINxN Yes No Yes Yes Yes When a fault mask bit is set, it is applied to all the channels. There is no individual fault mask available per channel using this bit. To mask individual channels, use the DIAG_MASK[4:1] bits (Bits[3:0] of Register 0x15). Diagnostics Sequence The sequence shown in Figure 23 is recommended for reading the faults reported by diagnostics. NORMAL NORMAL FAULT EVENT FAULT TIMEOUT FAULT TIMEOUT FAULT TIMEOUT FAULT TIMEOUT FAULT TIMEOUT IRQ TO SYSTEM MICRO IRQ TO SYSTEM MICRO IRQ TO SYSTEM MICRO IRQ TO SYSTEM MICRO I2C SEQUENCE I2C SEQUENCE I2C SEQUENCE I2C SEQUENCE IRQ TO SYSTEM MICRO I2C Figure 23. Diagnostics Sequence Rev. C | Page 24 of 68 I2C SEQUENCE 10296-023 FAULT PIN Data Sheet ADAU1977 In the event of a fault on an input pin, the FAULT pin goes low or high depending on the setting of the IRQ_POL bit in Register 0x15 to send an interrupt request to the system microcontroller. The system microcontroller responds to the interrupt request by communicating with the ADAU1977 via the I2C. The following is the typical interrupt service routine: 6. The serial audio port comprises four pins: BCLK, LRCLK, SDATAOUT1, and SDATAOUT2. The ADAU1977 ADC outputs are available on the SDATAOUT1 and SDATAOUT2 pins in serial format. The BCLK and LRCLK pins serve as the bit clock and frame clock, respectively. The port can be operated as master or slave and can be set either in stereo mode (2-channel mode) or in TDM multichannel mode. The supported popular audio formats are I2S, left justified (LJ), right justified (RJ). Stereo Mode In 2-channel or stereo mode, the SDATAOUT1 outputs ADC data for Channel 1 and Channel 2, and the SDATOUT2 outputs ADC data for Channel 3 and Channel 4. Figure 24 through Figure 28 show the supported audio formats. BCLK LRCLK SDATAOUT1 (I2S MODE) CHANNEL 1 CHANNEL 2 8 TO 32 BCLKs SDATAOUT2 (I2S MODE) 8 TO 32 BCLKs CHANNEL 3 CHANNEL 4 10296-024 3. 4. 5. SERIAL AUDIO DATA OUTPUT PORTS—DATA FORMAT NOTES 1. SAI = 0. 2. SDATA_FMT = 0 (I2S). Figure 24. I2S Audio Format BCLK LRCLK SDATAOUT1 (LJ MODE) SDATAOUT2 (LJ MODE) CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 10296-025 2. An interrupt request is generated from the ADAU1977 to the system microcontroller. Read Register 0x11 through Register 0x14. (It is recommended to read all four diagnostics status registers— Register 0x11 through Register 0x14—in one sequence. Reading the registers as a single read may not report the status accurately.) Write Register 0x15, Bit 6 (the IRQ_RESET bit). Wait for the fault timeout period to expire. If the fault was temporary and did not persist, the interrupt service ends and the intermittent fault is ignored. If the fault persists, another interrupt request is generated from the ADAU1977, and the user should continue on to Step 6. Repeat Step 2 through Step 4 four times. If after the fifth reading, the diagnostics still report the presence of a fault, the fault exists on the respective input and must be attended to. NOTES 1. SDATA_FMT = 1 (LJ). Figure 25. LJ Audio Format BCLK LRCLK SDATAOUT1 (RJ MODE) CHANNEL 1 SDATAOUT2 (RJ MODE) CHANNEL 3 CHANNEL 2 CHANNEL 4 10296-026 1. 7. NOTES 1. SDATA_FMT = 2 (RJ, 24-BIT). Figure 26. RJ Audio Format Rev. C | Page 25 of 68 ADAU1977 Data Sheet output pin goes high-Z so that the same data line can be shared with other devices on the TDM bus. TDM Mode Register 0x05 through Register 0x08 provide programmability for the TDM mode. The TDM slot width, data width, and channel assignment, as well as the pin used to output the data, are programmable. The TDM port can be operated as either a master or a slave. In master mode, the BCLK and LRCLK are output from the ADAU1977, whereas in slave mode, the BCLK and LRCLK pins are set to receive the clock from the master in the system. By default, serial data is output on the SDATAOUT1 pin; however, the SDATA_SEL bit (Bit 7 of Register 0x06) can be used to change the setting so that serial data is output from the SDATAOUT2 pin. Both the nonpulse and pulse modes are supported. In nonpulse mode, the LRCLK signal is typically 50% of the duty cycle, whereas in pulse mode, the LRCLK signal must be at least one BCLK wide (see Figure 27 and Figure 28). The TDM mode supports 2, 4, 8, or 16 channels. The ADAU1977 outputs four channels of data in the assigned slots (Figure 29 shows the data slot assignments). During the unused slots, the BCLK 32/24/16 BCLKs 32/24/16 BCLKs 32/24/16 BCLKs LRCLK CHANNEL 1 SDATA I 2S CHANNEL 2 SDATA LJ CHANNEL 2 CHANNEL 1 8 TO 32 BCLKs 8 TO 32 BCLKs CHANNEL N 8 TO 32 BCLKs CHANNEL 1 SDATA I 2S CHANNEL N 8 TO 32 BCLKs 8 TO 32 BCLKs 8 TO 32 BCLKs CHANNEL N CHANNEL 2 24 OR 16 BCLKs 24 OR 16 BCLKs 24 OR 16 BCLKs 10296-027 NOTES 1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS). 2. SDATA_FMT = 00 (I2S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT). 3. BCLK_EDGE = 0. 4. LRCLK_MODE = 0. 5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs). Figure 27. TDM Nonpulse Mode Audio Format BCLK 32/24/16 BCLKs 32/24/16 BCLKs 32/24/16 BCLKs LRCLK CHANNEL 2 CHANNEL 1 SDATA I 2S CHANNEL N 8 TO 32 BCLKs 8 TO 32 BCLKs 8 TO 32 BCLKs 8 TO 32 BCLKs 8 TO 32 BCLKs 8 TO 32 BCLKs SDATA LJ CHANNEL N CHANNEL 2 CHANNEL 1 SDATA I 2S CHANNEL 1 CHANNEL 2 24 OR 16 BCLKs 24 OR 16 BCLKs 24 OR 16 BCLKs 10296-028 NOTES 1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS) 2. SDATA_FMT = 00 (I2S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT) 3. BCLK_EDGE = 0 4. LRCLK_MODE = 1 5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs) CHANNEL N Figure 28. TDM Pulse Mode Audio Format Rev. C | Page 26 of 68 Data Sheet ADAU1977 LRCLK NUMBER OF BCLK CYCLES = (NUMBER OF BCLKs/SLOT) × NUMBER OF SLOTS BCLK SDATAOUTx-TDM2 SLOT1 SDATAOUTx-TDM4 SLOT2 SLOT1 SLOT1 SLOT1 HIGH-Z SLOT2 DATA WIDTH 16/24 BITS SLOT4 SLOT4 SLOT3 SLOT2 SLOT3 SLOT3 SLOT5 SLOT6 SLOT7 SLOT8 SLOT5 SLOT9 SLOT10 SLOT4 SLOT6 SLOT11 SLOT12 SLOT7 SLOT13 SLOT8 SLOT14 SLOT15 SLOT16 HIGH-Z 10296-029 SDATAOUTx-TDM8 SDATAOUTx-TDM16 SLOT2 SLOT WIDTH 16/24/32BITS Figure 29. TDM Mode Slot Assignment Rev. C | Page 27 of 68 ADAU1977 Data Sheet care must be taken to choose the combination that is most suitable for the application. The bit clock frequency depends on the sample rate, the slot width, and the number of bit clocks per slot. Table 19 can be used to calculate the BCLK frequency. Connection Options The sample rate (fS) can range from 8 kHz up to 192 kHz. However, in master mode, the maximum bit clock frequency (BCLK) is 24.576 MHz. For example, for a sample rate of 192 kHz, 128 × fS is the maximum possible BCLK frequency. Therefore, only 128 bit clock cycles are available per TDM frame. There are two options in this case: either operate with a 32-bit data width in TDM4 or operate with a 16-bit data width in TDM8. In slave mode, this limitation does not exist because the bit clock and frame clock are fed to the ADAU1977. Various combinations of BCLK frequency and mode are available, but Figure 30 through Figure 34 show the available options for connecting the serial audio port in I2S or TDM mode. In TDM mode, it is recommended to include the pull-down resistor on the data signal to prevent the line from floating when the SDATAOUTx pin of ADAU1977 goes high-Z during an inactive period. The resistor value should be such that no more than 2 mA is drawn from the SDATAOUTx pin. Although the resistor value is typically in the range of 10 kΩ to 47 kΩ, the appropriate resistor value depends on the devices on the data bus. Table 19. Bit Clock Frequency TDM Mode 16 Bit Clocks Per Slot 32 × fS 64 × fS 128 × fS 256 × fS BCLK Frequency 24 Bit Clocks Per Slot 48 × fS 96 × fS 192 × fS 384 × fS MASTER SLAVE ADAU1977 DSP BCLK LRCLK 10296-030 SDATAOUT1 SDATAOUT2 Figure 30. Serial Port Connection Option 1—I2S/LJ/RJ Mode, ADAU1977 Master SLAVE MASTER ADAU1977 DSP BCLK LRCLK SDATAOUT1 10296-033 Mode TDM2 TDM4 TDM8 TDM16 SDATAOUT2 Figure 31. Serial Port Connection Option 2—I2S/LJ/RJ Mode, ADAU1977 Slave Rev. C | Page 28 of 68 32 Bit Clocks Per Slot 64 × fS 128 × fS 256 × fS 512 × fS Data Sheet ADAU1977 MASTER SLAVE ADAU1977 DSP BCLK LRCLK SDATAOUTx SLAVE ADAU1977 OR SIMILIAR ADC BCLK LRCLK 10296-031 SDATAOUTx Figure 32. Serial Port Connection Option 3—TDM Mode, ADAU1977 Master SLAVE SLAVE ADAU1977 DSP BCLK LRCLK SDATAOUTx MASTER ADAU1977 OR SIMILIAR ADC BCLK LRCLK 10296-034 SDATAOUTx Figure 33. Serial Port Connection Option 4—TDM Mode, Second ADC Master SLAVE MASTER ADAU1977 DSP BCLK LRCLK SDATAOUTx SLAVE ADAU1977 OR SIMILIAR ADC BCLK LRCLK 10296-032 SDATAOUTx Figure 34. Serial Port Connection Option 5—TDM Mode, DSP Master Rev. C | Page 29 of 68 ADAU1977 Data Sheet CONTROL PORTS However, to operate the PLL, serial audio ports, and boost converter, the master clock is necessary. The ADAU1977 control port allows two modes of operation— either 2-wire I2C mode or 4-wire SPI mode—that are used for setting the internal registers of the part. Both the I2C and SPI modes allow read and write capability of the registers. All the registers are eight bits wide. The registers start at Address 0x00 and end at Address 0x1A. By default, the ADAU1977 operates in I2C mode, but the part can be put into SPI mode by pulling the CLATCH pin low three times. The control port in both I2C and SPI modes is slave only and, therefore, requires the master in the system to operate. The registers can be accessed with or without the master clock to the part. The control port pins are multifunctional, depending on the mode in which the part is operating. Table 20 describes the control port pin functions in both modes. Table 20. Control Port Pin Functions I2C Mode Pin No. 17 18 19 20 Pin Name SDA/COUT SCL/CCLK ADDR0/CLATCH ADDR1/CIN Pin Functions SDA: data SCL: clock I2C Device Address Bit 0 I2C Device Address Bit 1 Rev. C | Page 30 of 68 Pin Type I/O I I I SPI Mode Pin Functions COUT: output data CCLK: input clock CLATCH: input CIN: input data Pin Type O I I I Data Sheet ADAU1977 I2C MODE The ADAU1977 supports a 2-wire serial (I2C-compatible) bus protocol. Two pins—serial data (SDA) and serial clock (SCL)— are used to communicate with the system I2C master controller. In I2C mode, the ADAU1977 is always a slave on the bus, meaning that it cannot initiate a data transfer. Each slave device on the I2C bus is recognized by a unique device address. The device address and R/W byte for the ADAU1977 are shown in Table 21. The address resides in the first seven bits of the I2C write. Bit 7 and Bit 6 of the I2C address for the ADAU1977 are set by the levels on the ADDR1 and ADDR0 pins. The LSB of the first I2C byte (the R/W bit) from the master identifies whether it is a read or write operation. Logic Level 1 in LSB corresponds to a read operation, and Logic Level 0 corresponds to a write operation. Table 21. ADAU1977 I2C First Byte Format Bit 7 ADDR1 Bit 6 ADDR0 Bit 5 1 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 1 Bit 0 R/W The first seven bits of the I2C chip address for the ADAU1977 are xx10001. Bit 0 and Bit 1 of the address byte can be set using the ADDR1 and ADDR0 pins to set the chip address to the desired value. The 7-bit I2C device address can be set to one of four possible options using the ADDR1 and ADDR0 pins: • • • • I2C Device Address 0010001 (0x11) I2C Device Address 0110001 (0x31) I2C Device Address 1010001 (0x51) I2C Device Address 1110001 (0x71) In I2C mode, both the SDA and SCL pins require that an appropriate pull-up resistor be connected to IOVDD. The voltage on these signal lines should not exceed the voltage on the IOVDD pin. Figure 46 shows a typical connection diagram for the I2C mode. The value of the pull-up resistor for the SDA or SCL pin can be calculated as follows. Minimum RPULL UP = (IOVDD – VIL)/ISINK where: IOVDD is the I/O supply voltage, typically ranging from 1.8 V up to 3.3 V. VIL is the maximum voltage at Logic Level 0 (that is, 0.4 V, as per the I2C specifications). ISINK is the current sink capability of the I/O pin. The SDA pin can sink 2 mA current; therefore, the minimum value of RPULL UP for an IOVDD of 3.3 V is 1.5 kΩ. Depending on the capacitance of the board, the speed of the bus can be restricted to meet the rise time and fall time specifications. For fast mode with a bit rate time of around 1 Mbps, the rise time must be less than 550 ns. Use the following equation to determine whether the rise time specification can be met: t = 0.8473 × RPULL UP × CBOARD. To meet the 300 ns rise time requirement, the CBOARD must be less than 236 pF. For the SCL pin, the calculations depend on the current sink capability of the I2C master used in the system. Addressing Initially, each device on the I2C bus is in an idle state and monitors the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All devices on the bus respond to the start condition and acquire the next eight bits from the master (the 7-bit address plus the R/W bit) MSB first. The master sends the 7-bit device address with the read/write bit to all the slaves on the bus. The device with the matching address responds by pulling the data line (SDA) low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master is to write information to the slave, whereas a Logic 1 means that the master is to read information from the slave after writing the address and repeating the start address. A data transfer takes place until a master initiates a stop condition. A stop condition occurs when SDA transitions from low to high while SCL is held high. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence during normal read and write operations, the ADAU1977 immediately jumps to the idle condition. Rev. C | Page 31 of 68 ADAU1977 0 1 Data Sheet 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL 1 0 0 0 SECOND BYTE (REGISTER ADDRESS) 1 THIRD BYTE (DATA) R/W ACK ADAU1977 START STOP ACK ADAU1977 2 Figure 35. I C Write to ADAU1977 Single Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SCL FIRST BYTE (DEVICE ADDRESS) ADDR1 ADDR0 SDA 1 0 0 0 SECOND BYTE (REGISTER ADDRESS) 1 R/W 19 ACK ADAU1977 ACK ADAU1977 START 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 SCL THIRD BYTE (DEVICE ADDRESS) SDA ADDR1 ADDR0 REPEAT START 1 0 0 0 1 DATA BYTE FROM ADAU1977 R/W NO ACK ACK ADAU1977 Figure 36. I2C Read from ADAU1977 Single Byte Rev. C | Page 32 of 68 STOP 10296-036 ADDR1 ADDR0 10296-035 FIRST BYTE (DEVICE ADDRESS) SDA Data Sheet ADAU1977 followed by the chip address byte with the R/W bit set to 1 (read). This causes the ADAU1977 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1977. I2C Read and Write Operations Figure 37 shows the format of a single-word write operation. Every ninth clock pulse, the ADAU1977 issues an acknowledge by pulling SDA low. Figure 40 shows the format of a burst mode read sequence. This figure shows an example of a read from sequential single-byte registers. The ADAU1977 increments its address registers after every byte because the ADAU1977 uses an 8-bit register address. Figure 38 shows the format of a burst mode write sequence. This figure shows an example of a write to sequential singlebyte registers. The ADAU1977 increments its address register after every byte because the requested address corresponds to a register or memory area with a 1-byte word length. Figure 37 to Figure 40 use the following abbreviations: S = start bit P = stop bit AM = acknowledge by master AS = acknowledge by slave S CHIP ADDRESS, R/W = 0 AS REGISTER ADDRESS 8 BITS AS DATA BYTE P 10296-037 Figure 39 shows the format of a single-word read operation. Note that the first R/W bit is 0, indicating a write operation. This is because the address still needs to be written to set up the internal address. After the ADAU1977 acknowledges the receipt of the address, the master must issue a repeated start command CHIP ADDRESS, R/W = 0 CHIP AS REGISTER ADDRESS ADDRESS, R/W = 0 8 BITS AS DATA AS BYTE 1 DATA AS DATA BYTE 2 BYTE 3 AS DATA BYTE 4 AS ... S CHIP ADDRESS, R/W = 0 AS REGISTER ADDRESS 8 BITS AS S CHIP ADDRESS, R/W = 1 AS DATA BYTE 1 P AM ... 10296-039 Figure 38. Burst Mode I2C Write Format Figure 39. Single-Word I2C Read Format S CHIP ADDRESS, R/W = 0 AS REGISTER ADDRESS 8 BITS AS S CHIP ADDRESS, R/W = 1 AS DATA BYTE 1 Figure 40. Burst Mode I2C Read Format Rev. C | Page 33 of 68 AM DATA BYTE 2 P 10296-040 S P 10296-038 Figure 37. Single-Word I2C Write Format ADAU1977 Data Sheet SPI MODE Data Bytes By default, the ADAU1977 is in I2C mode. To invoke SPI control mode, pull CLATCH low three times. This can be done by performing three dummy writes to the SPI port (the ADAU1977 does not acknowledge these three writes; see Figure 41). Beginning with the fourth SPI write, data can be written to or read from the device. The ADAU1977 can be taken out of SPI mode only by a full reset initiated by power cycling the device. The number of data bytes varies according to the register being accessed. During a burst mode write, an initial register address is written followed by a continuous sequence of data for consecutive register locations. The SPI port uses a 4-wire interface, consisting of the CLATCH, CCLK, CIN, and COUT signals, and it is always a slave port. The CLATCH signal should go low at the beginning of a transaction and high at the end of a transaction. The CCLK signal latches CIN on a low-to-high transition. COUT data is shifted out of the ADAU1977 on the falling edge of CCLK and should be clocked into a receiving device, such as a microcontroller, on the CCLK rising edge. The CIN signal carries the serial input data, and the COUT signal carries the serial output data. The COUT signal remains tristated until a read operation is requested. This allows direct connection to other SPI-compatible peripheral COUT ports for sharing the same system controller port. All SPI transactions have the same basic format shown in Table 24. A timing diagram is shown in Figure 3. All data should be written MSB first. A sample timing diagram for a single-word SPI write operation to a register is shown in Figure 42. A sample timing diagram of a singleword SPI read operation is shown in Figure 43. The COUT pin goes from being high-Z to being driven at the beginning of Byte 3. In this example, Byte 0 to Byte 1 contain the device address, the R/W bit, and the register address to be read. Subsequent bytes carry the data from the device. Standalone Mode The ADAU1977 can also be operated in standalone mode. However, in standalone mode, the boost converter, microphone bias, and diagnostics blocks are powered down. To set the part in standalone mode, pull the SA_MODE pin to IOVDD. In this mode, some pins change functionality to provide more flexibility (see Table 23 for more information). Table 23. Pin Functionality in Standalone Mode Pin Function ADDR0 Setting 0 1 ADDR1 0 1 0 1 0 1 0 1 0 1 Chip Address R/W The LSB of the first byte of an SPI transaction is a R/W bit. This bit determines whether the communication is a read (Logic Level 1) or a write (Logic Level 0). This format is shown in Table 22. SDA Table 22. ADAU1977 SPI Address and R/W Byte Format SCL Bit 7 0 SDATAOUT2 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 R/W FAULT Register Address The 8-bit address word is decoded to a location in one of the registers. This address is the location of the appropriate register. Description I2S SAI format TDM modes, determined by the SDATAOUT2 pin Master mode SAI Slave mode SAI MCLK = 256 × fS, PLL on MCLK = 384 × fS, PLL on 48 kHz sample rate 96 kHz sample rate TDM4—LRCLK pulse TDM8—LRCLK pulse Slot 1 to Slot 4 in TDM8 Slot 5 to Slot 8 in TDM8 If set for TDM8 mode, the FAULT pin is used as an input for assigning the ADC data slot to prevent collision with other data on TDM bus. Table 24. Generic Control Word Format Byte 0 Device Address[6:0], R/W 1 Byte 1 Register Address[7:0] Byte 2 Data[7:0] Continues to end of data. Rev. C | Page 34 of 68 Byte 3 1 Data[7:0] Data Sheet 0 1 ADAU1977 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 16 17 18 19 20 21 22 23 24 25 27 CLATCH 10296-041 CCLK CIN Figure 41. SPI Mode Initial Sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 CLATCH DEVICE ADDRESS (7 BITS) 10296-042 CCLK R/W DATA BYTE REGISTER ADDRESS BYTE CIN Figure 42. SPI Write to ADAU1977 Clocking (Single-Word Write Mode) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CCLK CLATCH DEVICE ADDRESS (7 BITS) DATA BYTE R/W DATA BYTE FROM ADAU1977 COUT 10296-043 REGISTER ADDRESS BYTE CIN Figure 43. SPI Read from ADAU1977 Clocking (Single-Word Read Mode) CLATCH CCLK DEVICE ADDRESS BYTE REGISTER ADDRESS BYTE DATA BYTE1 DATA BYTE2 DATA BYTE n – 1 DATA BYTE n DATA BYTE n – 1 DATA BYTE n 10296-044 CIN Figure 44. SPI Write to ADAU1977 (Multiple Bytes) CLATCH CCLK CIN REGISTER ADDRESS BYTE COUT DATA BYTE1 DATA BYTE2 DATA BYTE3 Figure 45. SPI Read from ADAU1977 (Multiple Bytes) Rev. C | Page 35 of 68 10296-045 DEVICE ADDRESS BYTE ADAU1977 Data Sheet REGISTER SUMMARY Table 25 is the control register summary. The registers can be accessed using the I2C control port or the SPI control port. Table 25. ADAU1977 Register Summary Reg 0x00 0x01 0x02 Name M_POWER PLL_CONTROL BST_CONTROL Bits [7:0] [7:0] [7:0] 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x10 0x11 0x12 0x13 0x14 0x15 0x16 MB_BST_CONTROL BLOCK_POWER_SAI SAI_CTRL0 SAI_CTRL1 SAI_CMAP12 SAI_CMAP34 SAI_OVERTEMP POSTADC_GAIN1 POSTADC_GAIN2 POSTADC_GAIN3 POSTADC_GAIN4 MISC_CONTROL DIAG_CONTROL DIAG_STATUS1 DIAG_STATUS2 DIAG_STATUS3 DIAG_STATUS4 DIAG_IRQ1 DIAG_IRQ2 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x17 0x18 0x19 0x1A DIAG_ADJUST1 DIAG_ADJUST2 ASDC_CLIP DC_HPF_CAL [7:0] [7:0] [7:0] [7:0] Bit 7 S_RST PLL_LOCK BST_GOOD Bit 6 PLL_MUTE Bit 5 Bit 4 RESERVED FS_RATE MB_VOLTS BCLKEDGE LDO_EN SDATA_FMT SDATA_SEL SLOT_WIDTH CMAP_C2 CMAP_C4 SAI_DRV_C4 SAI_DRV_C3 SAI_DRV_C2 LR_POL Bit 3 RESERVED CLK_S RESERVED BOOST_SW_ OV_EN FREQ MB_EN VREF_EN ADC_EN4 SAI DATA_WIDTH LR_MODE Bit 2 Bit 1 BOOST_OV MCS OC_EN BOOST_EN ADC_EN3 MRCV ADC_EN2 FS SAI_MSB BCLKRATE CMAP_C1 CMAP_C3 OT_MCRV OT_RCVR SAI_DRV_C1 DRV_HIZ PADC_GAIN1 PADC_GAIN2 PADC_GAIN3 PADC_GAIN4 SUM_MODE RESERVED MMUTE RESERVED RESERVED DIAG_EN4 DIAG_EN3 RESERVED MIC_SHORT1 MICH_OPEN1 MICH_SB1 MICH_SG1 MICH_SMB1 RESERVED MIC_SHORT2 MIC_OPEN2 MICH_SB2 MICH_SG2 MICH_SMB2 RESERVED MIC_SHORT3 MIC_OPEN3 MICH_SB3 MICH_SG3 MICH_SMB3 RESERVED MIC_SHORT4 MIC_OPEN4 MICH_SB4 MICH_SG4 MICH_SMB4 RESERVED IRQ_RESET IRQ_DRIVE IRQ_POL DIAG_MASK4 DIAG_MASK3 BST_FAULT_ MIC_SHORT_ MIC_OPEN_ MICH_SB_ MICH_SG_ RESERVED MASK MASK MASK MASK MASK SHT_T_TRIP SHT_M_TRIP SHT_G_TRIP RESERVED FAULT_TO RESERVED HYST_SM_EN RESERVED ADC_CLIP4 ADC_CLIP3 DC_SUB_C4 DC_SUB_C3 DC_SUB_C2 DC_SUB_C1 DC_HPF_C4 DC_HPF_C3 Rev. C | Page 36 of 68 Bit 0 PWUP BOOST_OC BOOST_RCVR ADC_EN1 SAI_MS OT DC_CAL DIAG_EN2 DIAG_EN1 MICL_SB1 MICL_SG1 MICL_SB2 MICL_SG2 MICL_SB3 MICL_SG3 MICL_SB4 MICL_SG4 DIAG_MASK2 DIAG_MASK1 MICL_SB_ MICL_SG_ MASK MASK SHT_B_TRIP HYST_SG_EN HYST_SB_EN ADC_CLIP2 ADC_CLIP1 DC_HPF_C2 DC_HPF_C1 Reset 0x00 0x41 0x4A RW RW RW RW 0x7D 0x3F 0x02 0x00 0x10 0x32 0xF0 0xA0 0xA0 0xA0 0xA0 0x02 0x0F 0x00 0x00 0x00 0x00 0x20 0x00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0x00 0x20 0x00 0x00 RW RW RW RW Data Sheet ADAU1977 REGISTER DETAILS MASTER POWER AND SOFT RESET REGISTER Address: 0x00, Reset: 0x00, Name: M_POWER The power management control register is used for enabling boost regulator, microphone bias, PLL, band gap reference, ADC, and LDO regulator. Table 26. Bit Descriptions for M_POWER Bits 7 Bit Name S_RST Settings 0 1 [6:1] 0 RESERVED PWUP 0 1 Description Software Reset. The software reset resets all internal circuitry and places all control registers to their default state. It is not necessary to reset the ADAU1977 during a power-up or power-down cycle. Normal Operation Software Reset Reserved. Master Power-Up Control. The master power-up control fully powers up or powers down the ADAU1977. This must be set to 1 to power up the ADAU1977. Individual blocks can be powered down via their respective power control registers. Full Power-Down Master Power-Up Rev. C | Page 37 of 68 Reset 0x0 Access RW 0x00 0x0 RW RW ADAU1977 Data Sheet PLL CONTROL REGISTER Address: 0x01, Reset: 0x41, Name: PLL_CONTROL Table 27. Bit Descriptions for PLL_CONTROL Bits 7 Bit Name PLL_LOCK Settings 0 1 6 PLL_MUTE 0 1 5 4 RESERVED CLK_S 0 1 [2:0] MCS 001 010 011 100 000 Description PLL Lock Status. PLL lock status bit. When one PLL is locked. PLL Not Locked PLL Locked PLL Unlock Automute. When set to 1, mutes the ADC output if PLL becomes unlocked. No Automatic Mute on PLL Unlock Automatic Mute with PLL Unlock Reserved. PLL Clock Source Select. Selecting input clock source for PLL. MCLK Used for PLL Input LRCLK Used for PLL Input; Only Supported for Sample Rates > 32 kHz Master Clock Select. MCS bits determine the frequency multiplication ratio of the PLL. It must be set based on the input MCLK frequency and sample rate. 256 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other sample rates) 384 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other sample rates) 512 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other sample rates) 768 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other sample rates) 128 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other sample rates) Rev. C | Page 38 of 68 Reset 0x0 Access R 0x1 RW 0x0 0x0 RW RW 0x1 RW Data Sheet Bits Bit Name ADAU1977 Settings 101 110 111 Description Reserved Reserved Reserved Reset Access Reset 0x0 Access R 0x2 RW 0x0 RW 0x1 RW 0x0 R 0x1 RW 0x0 R DC-TO-DC BOOST CONVERTER CONTROL REGISTER Address: 0x02, Reset: 0x4A, Name: BST_CONTROL Table 28. Bit Descriptions for BST_CONTROL Bits 7 Bit Name BST_GOOD Settings 0 1 [6:5] FS_RATE 00 01 10 11 4 BOOST_SW_FREQ 0 1 3 OV_EN 0 1 2 BOOST_OV 0 1 1 OC_EN 0 1 0 BOOST_OC 0 1 Description Boost Converter Output Status. Boost Converter Output Not Stabilized Boost Converter Output Good Sample Rate Control for Boost Switching Frequency. 8 kHz/16 kHz/32 kHz/64 kHz/128 kHz fS 11.025 kHz/22.05 kHz/44.1 kHz/88.2 kHz/176.4 kHz fS 12 kHz/24 kHz/48 kHz/96 kHz/192 kHz fS Reserved Boost Regulator Switching Frequency. 1.5 MHz Switching Frequency 3 MHz Switching Frequency Overvoltage Fault Protection Enable. Disable Enable Boost Converter Overvoltage Fault Status. Normal Operation Overvoltage Fault Overcurrent Fault Protection Enable. Disable Enable Boost Converter Overcurrent Fault Status. Normal Operation Boost Overcurrent Protection Active Rev. C | Page 39 of 68 ADAU1977 Data Sheet MICBIAS AND BOOST CONTROL REGISTER Address: 0x03, Reset: 0x7D, Name: MB_BST_CONTROL Table 29. Bit Descriptions for MB_BST_CONTROL Bits [7:4] Bit Name MB_VOLTS Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 3 MB_EN 0 1 2 BOOST_EN 0 1 1 MRCV 0 1 Description MICBIAS Output Voltage. 5.0 V 5.5 V 6.0 V 6.5 V 7.0 V 7.5 V 8.0 V 8.5 V 9.0 V Reserved Reserved Reserved Reserved Reserved Reserved Reserved MICBIAS Enable. MICBIAS Powered Down MICBIAS Enabled Boost Enable. Boost Off Boost On Boost Fault Manual Recovery. Normal Operation Attempt Manual Boost Fault Recovery Rev. C | Page 40 of 68 Reset 0x7 Access RW 0x1 RW 0x1 RW 0x0 W Data Sheet Bits 0 Bit Name BOOST_RCVR ADAU1977 Settings 0 1 Description Boost Recovery Mode. Automatic Fault Recovery Manual Fault Recovery; Use MRCV to Recover Reset 0x1 Access RW Reset 0x0 Access RW 0x0 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW BLOCK POWER CONTROL AND SERIAL PORT CONTROL REGISTER Address: 0x04, Reset: 0x3F, Name: BLOCK_POWER_SAI Table 30. Bit Descriptions for BLOCK_POWER_SAI Bits 7 Bit Name LR_POL Settings 0 1 6 BCLKEDGE 0 1 5 LDO_EN 0 1 4 VREF_EN 0 1 3 ADC_EN4 0 1 2 ADC_EN3 0 1 1 ADC_EN2 0 1 0 ADC_EN1 0 1 Description Sets LRCLK Polarity. LRCLK Low then High LRCLK High then Low Sets the Bit Clock Edge on Which Data Changes. Data Changes on Falling Edge Data Changes on Rising Edge LDO Regulator Enable. LDO Powered Down LDO Enabled Voltage Reference Enable. Voltage Reference Powered Down Voltage Reference Enabled ADC Channel 3 Enable. ADC Channel Powered Down ADC Channel Enabled ADC Channel 3 Enable. ADC Channel Powered Down ADC Channel Enabled ADC Channel 2 Enable. ADC Channel Powered Down ADC Channel Enabled ADC Channel 1 Enable. ADC Channel Powered Down ADC Channel Enabled Rev. C | Page 41 of 68 ADAU1977 Data Sheet SERIAL PORT CONTROL REGISTER1 Address: 0x05, Reset: 0x02, Name: SAI_CTRL0 Table 31. Bit Descriptions for SAI_CTRL0 Bits [7:6] Bit Name SDATA_FMT Settings 00 01 10 11 [5:3] SAI 000 001 010 011 100 [2:0] FS 000 001 010 011 100 Description Serial Data Format. I2S Data Delayed from Edge of LRCLK by 1 BCLK Left Justified Right Justified, 24-Bit Data Right Justified, 16-Bit Data Serial Port Mode. Stereo (I2S, LJ, RJ) TDM2 TDM4 TDM8 TDM16 Sampling Rate. 8 kHz to 12 kHz 16 kHz to 24 kHz 32 kHz to 48 kHz 64 kHz to 96 kHz 128 kHz to 192 kHz Rev. C | Page 42 of 68 Reset 0x0 Access RW 0x0 RW 0x2 RW Data Sheet ADAU1977 SERIAL PORT CONTROL REGISTER2 Address: 0x06, Reset: 0x00, Name: SAI_CTRL1 Table 32. Bit Descriptions for SAI_CTRL1 Bits 7 Bit Name SDATA_SEL Settings 0 1 [6:5] SLOT_WIDTH 00 01 10 11 4 DATA_WIDTH 0 1 3 LR_MODE 0 1 2 SAI_MSB 0 1 1 BCLKRATE 0 1 0 SAI_MS 0 1 Description SDATAOUTx Pin Selection in TDM4 or Greater Modes. SDATAOUT1 used for output SDATAOUT2 used for output Number of BCLKs per Slot in TDM Mode. 32 BCLKs per TDM slot 24 BCLKs per TDM slot 16 BCLKs per TDM slot Reserved Output Data Bit Width. 24-bit data 16-bit data Sets LRCLK Mode. 50% duty cycle clock Pulse—LRCLK is a single BCLK cycle wide pulse Sets Data to be Input/Output either MSB or LSB First. MSB first data LSB first data Sets the Number of Bit Clock Cycles per Data Channel Generated When in Master Mode. 32 BCLKs/channel 16 BCLKs/channel Sets the Serial Port into Master or Slave Mode. LRCLK/BCLK Slave LRCLK/BCLK Master Rev. C | Page 43 of 68 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1977 Data Sheet CHANNEL MAPPING FOR OUTPUT SERIAL PORTS REGISTER Address: 0x07, Reset: 0x10, Name: SAI_CMAP12 Table 33. Bit Descriptions for SAI_CMAP12 Bits [7:4] Bit Name CMAP_C2 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Channel 2 Output Mapping. Slot 1 for Channel Slot 2 for Channel Slot 3 for Channel (on SDATAOUT2 in stereo modes) Slot 4 for Channel (on SDATAOUT2 in stereo modes) Slot 5 for Channel (TDM8+ only) Slot 6 for Channel (TDM8+ only) Slot 7 for Channel (TDM8+ only) Slot 8 for Channel (TDM8+ only) Slot 9 for Channel (TDM16 only) Slot 10 for Channel (TDM16 only) Slot 11 for Channel (TDM16 only) Slot 12 for Channel (TDM16 only) Slot 13 for Channel (TDM16 only) Slot 14 for Channel (TDM16 only) Slot 15 for Channel (TDM16 only) Slot 16 for Channel (TDM16 only) Rev. C | Page 44 of 68 Reset 0x1 Access RW Data Sheet Bits [3:0] Bit Name CMAP_C1 ADAU1977 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Channel 1 Output Mapping. If CMAP is set to a slot that doesn’t exist for a given serial mode, then that channel will not be driven. For example, if CMAP is set to Slot 9 and the serial format is I2S, then that channel will not be driven. If more than one channel is set to the same slot, only the lowest channel number will be driven; other channels will not be driven. Slot 1 for Channel Slot 2 for Channel Slot 3 for Channel (on SDATAOUT2 in stereo modes) Slot 4 for Channel (on SDATAOUT2 in stereo modes) Slot 5 for Channel (TDM8+ only) Slot 6 for Channel (TDM8+ only) Slot 7 for Channel (TDM8+ only) Slot 8 for Channel (TDM8+ only) Slot 9 for Channel (TDM16 only) Slot 10 for Channel (TDM16 only) Slot 11 for Channel (TDM16 only) Slot 12 for Channel (TDM16 only) Slot 13 for Channel (TDM16 only) Slot 14 for Channel (TDM16 only) Slot 15 for Channel (TDM16 only) Slot 16 for Channel (TDM16 only) Rev. C | Page 45 of 68 Reset 0x0 Access RW ADAU1977 Data Sheet CHANNEL MAPPING FOR OUTPUT SERIAL PORTS REGISTER Address: 0x08, Reset: 0x32, Name: SAI_CMAP34 Table 34. Bit Descriptions for SAI_CMAP34 Bits [7:4] Bit Name CMAP_C4 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Channel 4 Output Mapping. Slot 1 for Channel Slot 2 for Channel Slot 3 for Channel (on SDATAOUT2 in stereo modes) Slot 4 for Channel (on SDATAOUT2 in stereo modes) Slot 5 for Channel (TDM8+ only) Slot 6 for Channel (TDM8+ only) Slot 7 for Channel (TDM8+ only) Slot 8 for Channel (TDM8+ only) Slot 9 for Channel (TDM16 only) Slot 10 for Channel (TDM16 only) Slot 11 for Channel (TDM16 only) Slot 12 for Channel (TDM16 only) Slot 13 for Channel (TDM16 only) Slot 14 for Channel (TDM16 only) Slot 15 for Channel (TDM16 only) Slot 16 for Channel (TDM16 only) Rev. C | Page 46 of 68 Reset 0x3 Access RW Data Sheet Bits [3:0] Bit Name CMAP_C3 ADAU1977 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Channel 3 Output Mapping. Slot 1 for Channel Slot 2 for Channel Slot 3 for Channel (on SDATAOUT2 in stereo modes) Slot 4 for Channel (on SDATAOUT2 in stereo modes) Slot 5 for Channel (TDM8+ only) Slot 6 for Channel (TDM8+ only) Slot 7 for Channel (TDM8+ only) Slot 8 for Channel (TDM8+ only) Slot 9 for Channel (TDM16 only) Slot 10 for Channel (TDM16 only) Slot 11 for Channel (TDM16 only) Slot 12 for Channel (TDM16 only) Slot 13 for Channel (TDM16 only) Slot 14 for Channel (TDM16 only) Slot 15 for Channel (TDM16 only) Slot 16 for Channel (TDM16 only) Rev. C | Page 47 of 68 Reset 0x2 Access RW ADAU1977 Data Sheet SERIAL OUTPUT DRIVE AND OVERTEMPERATURE PROTECTION CONTROL REGISTER Address: 0x09, Reset: 0xF0, Name: SAI_OVERTEMP Table 35. Bit Descriptions for SAI_OVERTEMP Bits 7 Bit Name SAI_DRV_C4 Settings 0 1 6 SAI_DRV_C3 0 1 5 SAI_DRV_C2 0 1 4 SAI_DRV_C1 0 1 3 DRV_HIZ 0 1 2 OT_MCRV 0 1 1 OT_RCVR 0 1 Description Channel 4 Serial Output Drive Enable. Channel Not Driven on Serial Output Port Channel Driven on Serial Output Port; Slot Determined by CMAP Channel 3 Serial Output Drive Enable. Channel Not Driven on Serial Output Port Channel Driven on Serial Output Port; Slot Determined by CMAP Channel 2 Serial Output Drive Enable. Channel Not Driven on Serial Output Port Channel Driven on Serial Output Port; Slot Determined by CMAP Channel 1 Serial Output Drive Enable. Channel Not Driven on Serial Output Port Channel Driven on Serial Output Port; Slot Determined by CMAP Select Whether to Tristate Unused SAI Channels or to Actively Drive These Data Slots. Unused Outputs Driven Low Unused Outputs High-Z Overtemperature Manual Recovery Attempt. Normal Operation Attempt Manual Overtemperature Recovery Overtemperature Manual Recovery. Automatic Recovery from Overtemperature Fault Manual Recovery from Overtemperature Fault, Must Set OT_MCRV Register Rev. C | Page 48 of 68 Reset 0x1 Access RW 0x1 RW 0x1 RW 0x1 RW 0x0 RW 0x0 W 0x0 RW Data Sheet Bits 0 Bit Name OT ADAU1977 Settings 0 1 Description Overtemperature Status. Normal Operation Overtemperature Fault Reset 0x0 Access R Reset 0xA0 Access RW POST ADC GAIN CHANNEL 1 CONTROL REGISTER Address: 0x0A, Reset: 0xA0, Name: POSTADC_GAIN1 Table 36. Bit Descriptions for POSTADC_GAIN1 Bits [7:0] Bit Name PADC_GAIN1 Settings 00000000 00000001 00000010 ... 10011111 10100000 10100001 ... 11111110 11111111 Description Channel 1 Post ADC Gain. +60 dB Gain +59.625 dB Gain +59.25 dB Gain ... +0.375 dB Gain 0 dB Gain −0.375 dB Gain ... −35.625 dB Gain Mute Rev. C | Page 49 of 68 ADAU1977 Data Sheet POST ADC GAIN CHANNEL 2 CONTROL REGISTER Address: 0x0B, Reset: 0xA0, Name: POSTADC_GAIN2 Table 37. Bit Descriptions for POSTADC_GAIN2 Bits [7:0] Bit Name PADC_GAIN2 Settings 00000000 00000001 00000010 ... 10011111 10100000 10100001 ... 11111110 11111111 Description Channel 2 Post ADC Gain. +60 dB Gain +59.625 dB Gain +59.25 dB Gain ... +0.375 dB Gain 0 dB Gain −0.375 dB Gain ... −35.625 dB Gain Mute Rev. C | Page 50 of 68 Reset 0xA0 Access RW Data Sheet ADAU1977 POST ADC GAIN CHANNEL 3 CONTROL REGISTER Address: 0x0C, Reset: 0xA0, Name: POSTADC_GAIN3 Table 38. Bit Descriptions for POSTADC_GAIN3 Bits [7:0] Bit Name PADC_GAIN3 Settings 00000000 00000001 00000010 ... 10011111 10100000 10100001 ... 11111110 11111111 Description Channel 3 Post ADC Gain. +60 dB Gain +59.625 dB Gain +59.25 dB Gain ... +0.375 dB Gain 0 dB Gain −0.375 dB Gain ... −35.625 dB Gain Mute Rev. C | Page 51 of 68 Reset 0xA0 Access RW ADAU1977 Data Sheet POST ADC GAIN CHANNEL 4 CONTROL REGISTER Address: 0x0D, Reset: 0xA0, Name: POSTADC_GAIN4 Table 39. Bit Descriptions for POSTADC_GAIN4 Bits [7:0] Bit Name PADC_GAIN4 Settings 00000000 00000001 00000010 ... 10011111 10100000 10100001 ... 11111110 11111111 Description Channel 4 Post ADC Gain. +60 dB Gain +59.625 dB Gain +59.25 dB Gain ... +0.375 dB Gain 0 dB Gain −0.375 dB Gain ... −35.625 dB Gain Mute Rev. C | Page 52 of 68 Reset 0xA0 Access RW Data Sheet ADAU1977 HIGH-PASS FILTER AND DC OFFSET CONTROL REGISTER AND MASTER MUTE Address: 0x0E, Reset: 0x02, Name: MISC_CONTROL Table 40. Bit Descriptions for MISC_CONTROL Bits [7:6] Bit Name SUM_MODE Settings 00 01 10 11 5 4 RESERVED MMUTE 0 1 [3:1] 0 RESERVED DC_CAL 0 1 Description Channel Summing Mode Control for Higher SNR. Normal 4-Channel Operation 2-Channel Summing Operation (See the ADC Summing Modes Section) 1-Channel Summing Operation (See the ADC Summing Modes Section) Reserved Reserved. Master Mute. Normal Operation All Channels Muted Reserved. DC Calibration Enable. Normal Operation Perform DC Calibration Rev. C | Page 53 of 68 Reset 0x0 Access RW 0x0 0x0 RW RW 0x1 0x0 RW RW ADAU1977 Data Sheet DIAGNOSTICS CONTROL REGISTER Address: 0x10, Reset: 0x0F, Name: DIAG_CONTROL Table 41. Bit Descriptions for DIAG_CONTROL Bits [7:4] 3 Bit Name RESERVED DIAG_EN4 Settings 0 1 2 DIAG_EN3 0 1 1 DIAG_EN2 0 1 0 DIAG_EN1 0 1 Description Reserved. Diagnostics Enable Channel 4. Diagnostics Disabled Diagnostics Enabled Diagnostics Enable Channel 3. Diagnostics Disabled Diagnostics Enabled Diagnostics Enable Channel 2. Diagnostics Disabled Diagnostics Enabled Diagnostics Enable Channel 1. Diagnostics Disabled Diagnostics Enabled Rev. C | Page 54 of 68 Reset 0x0 0x1 Access RW RW 0x1 RW 0x1 RW 0x1 RW Data Sheet ADAU1977 DIAGNOSTICS REPORT REGISTER CHANNEL 1 Address: 0x11, Reset: 0x00, Name: DIAG_STATUS1 Table 42. Bit Descriptions for DIAG_STATUS1 Bits 7 6 Bit Name RESERVED MIC_SHORT1 Settings 0 1 5 MICH_OPEN1 0 1 4 MICH_SB1 0 1 3 MICH_SG1 0 1 2 MICH_SMB1 0 1 1 MICL_SB1 0 1 0 MICL_SG1 0 1 Description Reserved. Mic Terminals Shorted. Normal Operation Mic Terminals Shorted Mic Open Connection. Normal Operation Mic Open Connection Mic High Shorted to Supply. Normal Operation Mic High Shorted to Supply Mic High Shorted to Ground. Normal Operation Mic High Shorted to Ground Mic High Shorted to MICBIAS. Normal Operation Mic High Shorted to MICBIAS Mic Low Shorted to Supply. Normal Operation Mic Low Shorted to Supply Mic Low Shorted to Ground. Normal Operation Mic Low Shorted to Ground Rev. C | Page 55 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1977 Data Sheet DIAGNOSTICS REPORT REGISTER CHANNEL 2 Address: 0x12, Reset: 0x00, Name: DIAG_STATUS2 Table 43. Bit Descriptions for DIAG_STATUS2 Bits 7 6 Bit Name RESERVED MIC_SHORT2 Settings 0 1 5 MIC_OPEN2 0 1 4 MICH_SB2 0 1 3 MICH_SG2 0 1 2 MICH_SMB2 0 1 1 MICL_SB2 0 1 0 MICL_SG2 0 1 Description Reserved. Mic Terminals Shorted. Normal Operation Mic Terminals Shorted Mic Open Connection. Normal Operation Mic Open Connection Mic High Shorted to Supply. Normal Operation Mic High Shorted to Supply Mic High Shorted to Ground. Normal Operation Mic High Shorted to Ground Mic High Shorted to MICBIAS. Normal operation Mic High Shorted to MICBIAS Mic Low Shorted to Supply. Normal Operation Mic Low Shorted to Supply Mic Low Shorted to Ground. Normal Operation Mic Low Shorted to Ground Rev. C | Page 56 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet ADAU1977 DIAGNOSTICS REPORT REGISTER CHANNEL 3 Address: 0x13, Reset: 0x00, Name: DIAG_STATUS3 Table 44. Bit Descriptions for DIAG_STATUS3 Bits 7 6 Bit Name RESERVED MIC_SHORT3 Settings 0 1 5 MIC_OPEN3 0 1 4 MICH_SB3 0 1 3 MICH_SG3 0 1 2 MICH_SMB3 0 1 1 MICL_SB3 0 1 0 MICL_SG3 0 1 Description Reserved. Mic Terminals Shorted. Normal Operation Mic Terminals Shorted Mic Open Connection. Normal Operation Mic Open Connection Mic High Shorted to Supply. Normal Operation Mic High Shorted to Supply Mic High Shorted to Ground. Normal Operation Mic High Shorted to Ground Mic High Shorted to MICBIAS. Normal Operation Mic High Shorted to MICBIAS Mic Low Shorted to Supply. Normal Operation Mic Low Shorted to Supply Mic Low Shorted to Ground. Normal Operation Mic Low Shorted to Ground Rev. C | Page 57 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1977 Data Sheet DIAGNOSTICS REPORT REGISTER CHANNEL 4 Address: 0x14, Reset: 0x00, Name: DIAG_STATUS4 Table 45. Bit Descriptions for DIAG_STATUS4 Bits 7 6 Bit Name RESERVED MIC_SHORT4 Settings 0 1 5 MIC_OPEN4 0 1 4 MICH_SB4 0 1 3 MICH_SG4 0 1 2 MICH_SMB4 0 1 1 MICL_SB4 0 1 0 MICL_SG4 0 1 Description Reserved. Mic Terminals Shorted. Normal Operation Mic Terminals Shorted Mic Open Connection. Normal Operation Mic Open Connection Mic High Shorted to Supply. Normal Operation Mic High Shorted to Supply Mic High Shorted to Ground. Normal Operation Mic High Shorted to Ground Mic High Shorted to MICBIAS. Normal Operation Mic High Shorted to MICBIAS Mic Low Shorted to Supply. Normal Operation Mic Low Shorted to Supply Mic Low Shorted to Ground. Normal Operation Mic Low Shorted to Ground Rev. C | Page 58 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet ADAU1977 DIAGNOSTICS INTERRUPT PIN CONTROL REGISTER 1 Address: 0x15, Reset: 0x20, Name: DIAG_IRQ1 Table 46. Bit Descriptions for DIAG_IRQ1 Bits 7 6 Bit Name RESERVED IRQ_RESET Settings 0 1 5 IRQ_DRIVE 0 1 4 IRQ_POL 0 1 3 DIAG_MASK4 0 1 2 DIAG_MASK3 0 1 1 DIAG_MASK2 0 1 0 DIAG_MASK1 0 1 Description Reserved. FAULT Pin Reset. Normal Operation Reset FAULT Pin FAULT Pin Drive Options. FAULT Pin Always Driven FAULT Pin Only Driven During Fault, Otherwise High-Z FAULT Pin Polarity. Faults Set FAULT Pin Low Faults Set FAULT Pin High FAULT Pin Mask for All Channel 4 Faults. Faults on Channel 4 Trigger FAULT Pin Faults on Channel 4 Do Not Trigger FAULT Pin FAULT Pin Mask for All Channel 3 Faults. Faults on Channel 3 Trigger FAULT Pin Faults on Channel 3 Do Not Trigger FAULT Pin FAULT Pin Mask for All Channel 2 Faults. Faults on Channel 2 Trigger FAULT Pin Faults on Channel 2 Do Not Trigger FAULT Pin FAULT Pin Mask for All Channel 1 Faults. Faults on Channel 1 Trigger FAULT Pin Faults on Channel 1 Do Not Trigger FAULT Pin Rev. C | Page 59 of 68 Reset 0x0 0x0 Access RW RW 0x1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1977 Data Sheet DIAGNOSTICS INTERRUPT PIN CONTROL REGISTER 2 Address: 0x16, Reset: 0x00, Name: DIAG_IRQ2 Table 47. Bit Descriptions for DIAG_IRQ2 Bits 7 Bit Name BST_FAULT_MASK Settings 0 1 6 MIC_SHORT_MASK 0 1 5 MIC_OPEN_MASK 0 1 4 MICH_SB_MASK 0 1 3 MICH_SG_MASK 0 1 1 MICL_SB_MASK 0 1 0 MICL_SG_MASK 0 1 Description FAULT Pin Mask for Boost Faults. Boost Faults Assert FAULT Pin Boost Faults Do Not Assert FAULT Pin FAULT Pin Mask for Mic Terminal Short Fault. Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic Open Connection Fault. Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic High Short to Supply Fault. Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic High Short to Ground Fault. Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic Low Short to Supply Fault. Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic Low Short to Ground Fault. Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin Rev. C | Page 60 of 68 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Data Sheet ADAU1977 DIAGNOSTICS ADJUSTMENTS REGISTER 1 Address: 0x17, Reset: 0x00, Name: DIAG_ADJUST1 Table 48. Bit Descriptions for DIAG_ADJUST1 Bits [7:6] Bit Name SHT_T_TRIP Settings 00 01 10 11 [5:4] SHT_M_TRIP 00 01 10 11 [3:2] SHT_G_TRIP 00 01 10 11 [1:0] SHT_B_TRIP 00 01 10 11 Description Short Fault to Other Terminal Trip Point Adjust. 0.465 × MICBIAS to 0.535 × MICBIAS 0.483 × MICBIAS to 0.517 × MICBIAS 0.429 × MICBIAS to 0.571 × MICBIAS Reserved Short Fault to Mic Bias Trip Point Adjust. 0.95 × MICBIAS 0.9 × MICBIAS 0.85 × MICBIAS 0.975 × MICBIAS Short Fault to Ground Trip Point Adjust. 0.2 × VREF 0.133 × VREF 0.1 × VREF 0.266 × VREF Short Fault to Supply/Battery Trip Point Adjust. 0.95 × VBAT 0.9 × VBAT 0.85 × VBAT 0.975 × VBAT Rev. C | Page 61 of 68 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW ADAU1977 Data Sheet DIAGNOSTICS ADJUSTMENTS REGISTER 2 Address: 0x18, Reset: 0x20, Name: DIAG_ADJUST2 Table 49. Bit Descriptions for DIAG_ADJUST2 Bits [7:6] [5:4] Bit Name RESERVED FAULT_TO Settings 00 01 10 11 3 2 RESERVED HYST_SM_EN 0 1 1 HYST_SG_EN 0 1 0 HYST_SB_EN 0 1 Description Reserved. Fault Timeout Adjust. No Fault Timeout Period (That Is, the Time That the Fault Needs to Persist Before Being Reported) 50 ms Fault Timeout Period 100 ms Fault Timeout Period (Default) 150 ms Fault Timeout Period Reserved. Hysteresis Short to MICBIAS Enable. Disable Enable Hysteresis Short to Ground Enable. Disable Enable Hysteresis Short to Battery Enable. Disable Enable Rev. C | Page 62 of 68 Reset 0x0 0x2 Access RW RW 0x0 0x0 RW RW 0x0 RW 0x0 RW Data Sheet ADAU1977 ADC CLIPPING STATUS REGISTER Address: 0x19, Reset: 0x00, Name: ASDC_CLIP Table 50. Bit Descriptions for ASDC_CLIP Bits [7:4] 3 Bit Name RESERVED ADC_CLIP4 Settings 0 1 2 ADC_CLIP3 0 1 1 ADC_CLIP2 0 1 0 ADC_CLIP1 0 1 Description Reserved. ADC Channel 4 Clip Status. Normal Operation ADC Channel Clipping ADC Channel 3 Clip Status. Normal Operation ADC Channel Clipping ADC Channel 2 Clip Status. Normal Operation ADC Channel Clipping ADC Channel 1 Clip Status. Normal Operation ADC Channel Clipping Rev. C | Page 63 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R ADAU1977 Data Sheet DIGITAL DC HIGH-PASS FILTER AND CALIBRATION REGISTER Address: 0x1A, Reset: 0x00, Name: DC_HPF_CAL Table 51. Bit Descriptions for DC_HPF_CAL Bits 7 Bit Name DC_SUB_C4 Settings 0 1 6 DC_SUB_C3 0 1 5 DC_SUB_C2 0 1 4 DC_SUB_C1 0 1 3 DC_HPF_C4 0 1 2 DC_HPF_C3 0 1 1 DC_HPF_C2 0 1 0 DC_HPF_C1 0 1 Description Channel 4 DC Subtraction from Calibration. No DC Subtraction DC Value from DC Calibration Is Subtracted Channel 3 DC Subtraction from Calibration. No DC Subtraction DC Value from DC Calibration Is Subtracted Channel 2 DC Subtraction from Calibration. No DC Subtraction DC Value from DC Calibration Is Subtracted Channel 1 DC Subtraction from Calibration. No DC Subtraction DC Value from DC Calibration Is Subtracted Channel 4 DC High-Pass Filter Enable. HPF Off HPF On Channel 3 DC High-Pass Filter Enable. HPF Off HPF On Channel 2 DC High-Pass Filter Enable. HPF Off HPF On Channel 1 DC High-Pass Filter Enable. HPF Off HPF On Rev. C | Page 64 of 68 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Data Sheet ADAU1977 APPLICATIONS CIRCUIT +14.4V AVDDx AVDD2 DIAGNOSTICS C1 TO C8 = 1000pF R1 TO R4 TYP = 500Ω ±0.1% BG REF PLL AGND2 AGND2 PGND AGND1 AGND2 AGND3 DGND VREF AGNDx MB_GND C18 10µF C19 0.1µF I2C/SPI CONTROL PLL_FILT R4 MCLKIN C1 C2 C3 C4 C5 C6 C7 C8 R2 SCL/CCLK SDA/COUT ADDR1/CIN ADDR0/CLATCH FAULT PD/RESET R13 R16 IOVDD R15 AGND3 AGND1 TO DSP R11 ADC VBAT LRCLK BCLK SDATAOUT1 SDATAOUT2 R12 ADC C7 0.1µF R9 ADC REXT +1.8V OR +3.3V R10 ADC ATTENUATOR 14dB MIC1 VAC = 2V DIFF MIC2 VAC = 2V DIFF LINE1 VCM = 7V, VAC = 10V DIFF LINE2 VCM = 7V, VAC = 10V DIFF C16 10µF MLCC X7R C15 0.1µF IOVDD SERIAL AUDIO PORT 4.7µH SW PGND AIN1+ AIN1– AIN2+ AIN2– AIN3+ AIN3– AIN4+ AIN4– DVDD ADAU1977 PROGRAMMABLE GAIN DECIMATOR/HPF DC CALIBRATION PROG BIAS 3.3V TO 1.8V REGULATOR SA_MODE R3 C14 0.1µF BOOST CONVERTER IOUT 50mA 5V TO 9V C9 10µF ELECTROLYTIC 1nF MAX MLCC R1 C13 0.1µF AVDD1 AVDD3 MICBIAS VBOOST_IN C10 10µF MLCC X7R VBOOST_OUT C11 0.1µF 10µF MLCC X7R C12 0.1µF AVDD1 AVDD3 AVDD2 VBAT (LOAD DUMP SUPRESSED) +3.3V MICROCONTROLLER R14 C21 C20 R17 +3.3V (AVDD2) NOTES 1. R9, R10 = TYPICAL 2kΩ. 2. R11 THROUGH R14 USED FOR SETTING THE DEVICE IN I 2C MODE. 3. R15, R16 = TYPICAL 47kΩ. 4. PLL LOOP FILTER: R17 C20 C21 LRCLK MCLK 4.87kΩ 2200pF 39nF 1kΩ 390pF 5600pF 5. FOR MORE INFORMATIONABOUT CALCUL ATING THEVALUE OF REXT, SEE THE POWER-ON RESET SEQUENCE SECTION. Figure 46. Typical Application Schematic—Two Microphones, Two Line Inputs, I2C and I2S Mode Rev. C | Page 65 of 68 10296-046 PLL INPUT OPTION ADAU1977 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 31 40 30 0.50 BSC 1 TOP VIEW 0.80 0.75 0.70 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.05 3.90 SQ 3.75 EXPOSED PAD 21 0.45 0.40 0.35 PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 47. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm × 6 mm Body, Very Very Thin Quad (CP-40-14) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADAU1977WBCPZ ADAU1977WBCPZ-R7 ADAU1977WBCPZ-RL EVAL-ADAU1977Z 1 2 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 40-Lead LFCSP_WQ 40-Lead LFCSP_WQ, 7” Tape and Reel 40-Lead LFCSP_WQ, 13” Tape and Reel Evaluation Board Package Option CP-40-14 CP-40-14 CP-40-14 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADAU1977W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. C | Page 66 of 68 Data Sheet ADAU1977 NOTES Rev. C | Page 67 of 68 ADAU1977 Data Sheet NOTES ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10296-0-1/14(C) Rev. C | Page 68 of 68