RTG4 FPGA PCIe Data Plane Demo using Two
Channel Fabric DMA - Libero SoC v11.7
DG0622 Demo Guide
Contents
1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA . . . . . . . . . . 6
2.1
2.2
2.3
2.4
2.5
2.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.2
Demo Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.3
Demo Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3.1
Host PC Memory to LSRAM (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3.2
LSRAM to Host PC Memory (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3.3
Host PC Memory to DDR Memory (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3.4
DDR Memory to Host PC Memory (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.3.5
LSRAM to DDR Memory (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.3.6
DDR Memory to LSRAM (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.4
Throughput Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Setting Up the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1
Programming the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.2
Connecting RTG4 Development Kit to Host PC PCIe Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.3
Drivers Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.4
Installing PCIe_Demo Application GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Running the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3 Appendix: Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 Appendix: Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5 Appendix: Silk Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1
7.2
7.3
7.4
7.5
7.6
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1
Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.3
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Demo Design Files Top Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PCIe Data Plane Demo Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
FlashPro - New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FlashPro Project Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FlashPro- Programmer Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RTG4 Development Kit Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Device Manager - PCIe Device Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Prompt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jungo Driver Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Install this Driver Software Anyway Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Completed Successfully Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Installing PCIe_Demo Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCIe_Demo Application Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Successful Installation of PCIe_Demo Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device Manager - PCIe Device Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PCIe_Demo Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PCIe Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Demo Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PCIe Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PCIe Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read and Writes to Scratchpad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DMA Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DMA Transactions between Host PC Memory and LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA between Host PC Memory and LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DMA between Host PC Memory and LSRAM - Loop Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DMA between Host PC Memory and LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DMA between Host PC Memory and LSRAM - Loop Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DMA between Host PC Memory and LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DMA between Host PC Memory and LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DMA between Host PC Memory and DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DMA between LSRAM and DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Workaround for Link Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Hot Reset Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Top View - RTG4 Development Kit Silk Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Tables
Table 1.
Table 2.
Table 3.
Table 4.
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RTG4 Development Kit Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Throughput Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Preface
1
Preface
1.1
Purpose
This demo is for RTG4™ field programmable gate array (FPGA) device. It provides instructions on how
to use the corresponding reference design.
1.2
Intended Audience
This demo guide is intended for:
•
•
1.3
FPGA designers
System-level designers
References
The following documents are referred in this demo guide:
•
•
•
UG0567: RTG4 FPGA High-Speed Serial Interfaces User Guide
UG0573: RTG4 FPGA High-Speed DDR Interfaces User Guide
Libero SoC User Guide
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
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RTG4 FPGA PCIe Data Plane Demo using
Two Channel Fabric DMA
2.1
Introduction
This demo highlights the high-speed data transfer capability of the RTG4 devices through the PCIe
interface. To achieve high-speed data transfer, an advanced extensible interface (AXI) based direct
memory access (DMA) controller is implemented in the FPGA fabric. An application, PCIe_Demo that
runs in the host PC is provided for setting up and initiating the DMA transactions from the RTG4 PCIe
endpoint to the host PC device. Drivers for connecting the host PC to the RTG4 PCIe endpoint are
provided as part of the demo deliverables.
The high-speed serial interface (SERDESIF) available in the RTG4 devices provides a fully hardened
PCIe endpoint implementation, and is compliant with the PCIe Base Specification Revision 2.0,1.1 and
1.0. For more information about this, refer to the UG0567: RTG4 FPGA High-Speed Serial Interface User
Guide.
This demo demonstrates the performance of the PCIe and DDR controller of the RTG4 devices.
2.2
Design Requirements
Table 1 • Design Requirements
Design Requirements
Description
Hardware Requirements
RTG4 Development Kit:
• 12 V adapter
• PCI Edge Card Ribbon Cable
Rev A (Die: RT4G150_ES)
Host PC with 8 GB RAM and PCIe 2.0 Gen1 compliant slot with 64-bit Windows 7 Operating System
x4 or higher width.
Software Requirements
Libero® System-on-Chip (SoC)
v11.7
FlashPro programming software
v11.7
PCIe_Demo Application
–
2.3
Demo Design
2.3.1
Introduction
The demo design files are available for download from the following path in the Microsemi website:
http://soc.microsemi.com/download/rsc/?f=rt4g_dg0622_liberov11p7_df
The demo design files include:
•
•
•
•
•
Drivers_64bitOS
GUI
Libero Project
Programming files
Readme.txt file
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
Figure 1 shows the top-level structure of the design files. Refer to readme.txt file for the complete
directory structure.
Figure 1 • Demo Design Files Top Level Structure
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Figure 2 on page 8 shows the demo design. The PCIe core in the RTG4 devices supports both AXI and
AMBA® high-performance bus (AHB) Master and Slave interfaces. This demo design uses the AXI
Master and Slave interfaces to achieve maximum bandwidth. The PCIe_Demo application on the host
PC initiates the DMA transfers, and the embedded PCIe core in the RTG4 device initiates the AXI
transactions through the AXI master interface to the DMA controller in the FPGA fabric. The DMA
controller has two independent channels that share the AXI read/write channels of the PCIe AXI slave
interface and FDDR AXI slave interface. The DMA controller in the FPGA fabric initiates the DMA
channels depending on the type of the DMA transfer. Each channel has a timer to calculate the
throughput. It has 4 KB of LSRAM buffer.
DMA channel 0 handles the following DMA transfers:
•
•
•
Host PC memory to LSRAM
Host PC memory to DDR memory
LSRAM to DDR memory
DMA channel 1 handles the following DMA transfers:
•
•
•
LSRAM to host PC memory
DDR memory to host PC memory
DDR memory to LSRAM
Revision 3
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
Figure 2 • PCIe Data Plane Demo Block Diagram
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The FDDR controller is configured to access the DDR3 memory in x32 mode. The FDDR clock is
configured to 320 MHz (640 Mbps DDR) with a 80 MHz DDR_FIC clock for an aggregate memory
bandwidth of 1280 Mbps. The PCIe AXI interface clock and fabric DMA controller clock are configured to
80 MHz.
2.3.2
Demo Design Features
The following are the demo design features:
•
•
•
•
•
•
•
•
•
•
•
DMA data transfers between the host PC memory and the LSRAM
DMA data transfers between the host PC memory and the DDR memory
DMA data transfers between the DDR memory and the LSRAM
Displays throughput for each DMA data transfer
Enables continuous DMA transfers for observing throughput variations.
Displays the PCIe link enable/disable, negotiated link width, and link speed on the PCIe_Demo
application.
Displays the position of DIP Switches on the RTG4 Development Kit on the PCIe_Demo application.
Displays the PCIe Configuration Space on the PCIe_Demo application.
Controls LEDs on the board according to the command from the PCIe_Demo application.
Enables read and write operations to scratchpad register in the FPGA fabric.
Interrupts the host PC, when the Push button is pressed. The PCIe_Demo application displays the
count value of the number of interrupts sent from the board.
Revision 3
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
2.3.3
Demo Design Description
The demo design supports six types of data transfers. The following sections describe the process of
each data transfer:
•
•
•
•
•
•
Host PC Memory to LSRAM (Read)
LSRAM to Host PC Memory (Write)
Host PC Memory to DDR Memory (Read)
DDR Memory to Host PC Memory (Write)
LSRAM to DDR Memory (Write)
DDR Memory to LSRAM (Read)
2.3.3.1 Host PC Memory to LSRAM (Read)
Data transfer from PC memory to the LSRAM block occurs in the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
PCIe_Demo application sets up the Fabric DMA controller through the PCIe link. This includes DMA
direction, address, and size (4 KB).
Fabric DMA controller initiates a 16 beat AXI burst (128 bytes) read transaction to the PCIe AXI
slave interface.
The PCIe core sends the memory read (MRd) transaction layer packets (TLP) to the host PC.
The host PC returns a completion (CplD) TLP to the PCIe link.
This returned data completes the AXI read initiated by the Fabric DMA controller.
This data is stored in the LSRAM.
The Fabric DMA controller repeats this process (from Step 2 to 6) until the 4 KB size of data transfer
is completed.
The Fabric DMA controller provides the DMA completion status and the number of clock cycles
consumed to complete the DMA transaction to the PCIe_Demo application.
2.3.3.2 LSRAM to Host PC Memory (Write)
Data transfer from the LSRAM to PC memory occurs in the following sequence:
1.
2.
3.
4.
5.
PCIe_Demo application sets up the Fabric DMA controller through the PCIe link. This includes DMA
direction, address, and size (4 KB).
Fabric DMA controller reads the LSRAM data and initiates an AXI 16 beat burst write transaction to
PCIe AXI slave interface.
The PCIe core sends a memory write (MWr) TLP to the host PC.
The Fabric DMA controller repeats this process (Step 2 and 3) until the 4 KB size of data transfer is
completed.
The Fabric DMA controller provides the DMA completion status and the number of clock cycles
consumed to complete the DMA transaction to the PCIe_Demo application.
2.3.3.3 Host PC Memory to DDR Memory (Read)
Data transfer from the PC memory to the DDR memory occurs in the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
PCIe_Demo application sets up the Fabric DMA controller through the PCIe link. This includes DMA
direction, address, and size (4 KB).
Fabric DMA controller initiates 16 beat AXI burst (128 bytes) read transaction to the PCIe AXI
interface.
The PCIe core sends a memory read (MRd) transaction layer packets (TLP) to the host PC.
The host PC returns a completion data (CplD) TLP to the PCIe link.
This returned data completes the AXI read initiated by the Fabric DMA controller.
This data is stored in the dual port LSRAM.
The LSRAM data is written to the DDR controller through the AXI interface as an AXI 16 beat burst
write transaction. The reads from the host PC memory and the writes to the DDR memory occur
independent of each other for achieving high throughput. Empty flags are generated in the Fabric
DMA controller to avoid reading unknown data from the LSRAM.
The Fabric DMA controller repeats this process (from Step 2 to 7) until the 4 KB size of data transfer
is completed.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
9.
The Fabric DMA controller provides the DMA completion status and the number of clock cycles
consumed to complete the DMA transaction to the PCIe_Demo application.
2.3.3.4 DDR Memory to Host PC Memory (Write)
Data transfer from the DDR memory to the PC memory occurs in the following sequence:
1.
2.
3.
4.
5.
6.
7.
PCIe_Demo application sets up the Fabric DMA controller through the PCIe link. This includes DMA
direction, address, and size (4 KB).
The Fabric DMA controller initiates a 16 beat burst (128 bytes) AXI read transaction from the DDR
through the FDDR controller.
The data is stored in the dual port LSRAM.
The LSRAM data is written to the PCIe core as an AXI 16 beat burst write transaction. The reads
from the DDR memory and writes to host PC memory occur independent of each other for achieving
high throughput. Empty flags are generated in the Fabric DMA controller to avoid reading unknown
data from the LSRAM.
The PCIe core sends a memory write (MWr) TLP to the host PC.
The Fabric DMA controller repeats this process (from Step 2 to 5) until the 4 KB size of data transfer
is completed.
The Fabric DMA controller provides the DMA completion status and the number of clock cycles
consumed to complete the DMA transaction to the PCIe_Demo application.
2.3.3.5 LSRAM to DDR Memory (Write)
Data transfer from the LSRAM to the DDR memory occurs in the following sequence:
1.
2.
3.
4.
PCIe_Demo application sets up the Fabric DMA controller through the PCIe link. This includes DMA
direction, address, and size (4 KB).
The LSRAM data is written to the DDR controller through AXI interface as an AXI 16 beat burst write
transaction.
The Fabric DMA controller repeats this process (Step 2) until the 4 KB size of data transfer is
completed.
The Fabric DMA controller provides the DMA completion status and the number of clock cycles
consumed to complete the DMA transaction to the PCIe_Demo application for display.
2.3.3.6 DDR Memory to LSRAM (Read)
Data transfer from the DDR memory to the LSRAM occurs in the following sequence:
1.
2.
3.
4.
5.
2.3.4
PCIe_Demo application sets up the Fabric DMA controller through the PCIe link. This includes DMA
direction, address, and size (4 KB).
The Fabric DMA controller initiates a 16 beat burst AXI read transaction of the DDR through the
FDDR controller.
The data is stored in the dual port LSRAM.
The Fabric DMA controller repeats this process (Step 2 and 3) until the 4 KB size of data transfer is
completed.
The Fabric DMA controller provides the DMA completion status and the number of clock cycles
consumed to complete the DMA transaction to the PCIe_Demo application for display.
Throughput Calculation
This demo implements a timer to measure the throughput of DMA transfers. The throughput measured
includes all of the overhead of the AXI, PCIe, and DMA controller transactions.
The demo design implements following steps to measure throughput:
1.
2.
3.
4.
5.
Setup the DMA controller for the complete transfer.
Start the timer and the DMA controller.
Initiate the data transfer for the requested number of bytes.
Wait until the DMA transfer is completed.
Record the number of clock cycles used for Steps 2-4.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
To arrive at a realistic system performance, the throughput calculation takes into account all the
overheads during a transfer.
EQ 1 Throughput = Transfer Size (Byte) / (Number of clock cycles taken for a transfer * Clock Period)
2.4
Setting Up the Demo Design
The following steps describe how to setup the hardware demo for the RTG4 Development Kit:
1.
Connect the jumpers on the RTG4 Development Kit, as shown in Table 2.
Table 2 shows the jumper settings.
Table 2 • RTG4 Development Kit Jumper Settings
Jumper
Pin (From)
Pin (To)
Comments
J11, J17, J19, J23, J26, J21, J32, J27
1
2
Default
J16
2
3
Default
J33
1
3
2
4
Default
"Appendix: Silk Screen" on page 43 provides the RTG4 development kit silk screen to identify the
jumper locations on board.
Note: Ensure that the power supply switch, SW6 is switched OFF while connecting the jumpers on the RTG4
Development Kit board.
2.
3.
4.
Connect the host PC to the J47 connector using the USB cable.
Connect the USB cable (mini USB to Type A USB cable) to J47 of the RTG4 Development Kit board
and other end of the cable to the USB port of the host PC.
Switch ON the power supply switch, SW6.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
2.4.1
Programming the Demo Design
The following steps describe how to program the demo design:
1.
2.
3.
4.
5.
6.
7.
Download the demo design from:
http://soc.microsemi.com/download/rsc/?f=rt4g_dg0622_liberov11p7_df
Launch the FlashPro software.
Click New Project.
In the New Project window, enter the project name.
Click Browse and navigate to the location where the project needs to be saved.
Select Single device as the Programming mode.
Click OK to save the project.
Figure 3 • FlashPro - New Project
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
8.
9.
Click Configure Device.
Click Browse and navigate to the location where the PCIE_EP_DMA.stp file is located, and select
the file. The default location is:
<download_folder>\rt4g_dg0622_liberov11p6_df\ProgrammingFile\
Figure 4 • FlashPro Project Configuration
10. Click PROGRAM to start programming the device. Wait until the Programmer Status is changed to
RUN PASSED (highlighted in Figure 5).
Figure 5 • FlashPro- Programmer Status
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
2.4.2
Connecting RTG4 Development Kit to Host PC PCIe Slot
The following steps describe how to connect the RTG4 Development Kit board to the host PC:
1.
2.
After successful programming, shut down the host PC.
Connect the J230 - PCIe Edge connector of the RTG4 Development Kit to host PC's PCIe slot
through the PCI Edge Card Ribbon Cable.
Note: Ensure that the host PC is switched OFF while inserting the PCIe Edge Connector. Else, the PCIe device
may not be detected properly. The host PC may wake-up after inserting the PCIe Edge connector, as the
RTG4 devices do not support cold sparing.
Figure 6 shows the board setup for the host PC in which the RTG4 Development Kit is connected to the
host PC PCIe slot.
Figure 6 • RTG4 Development Kit Setup
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
3.
Switch ON the host PC and check the Device Manager of the Host PC for PCIe Device. Figure 7
shows the example Device Manager window. If the device is not detected, power cycle the RTG4
Development Kit and click scan for hardware changes (highlighted in Figure 7) in the Device
Manager window.
Figure 7 • Device Manager - PCIe Device Detection
Note: If the device is still not detected, check if the BIOS version in the host PC is latest, and if PCI is enabled
in the host PC BIOS.
2.4.3
Drivers Installation
The PCIe demo uses a driver framework provided by Jungo WinDriverPro. To install the PCIe drivers on
the host PC, use the following steps:
1.
Extract the PCIe_Demo.rar to C:\ drive. The PCIe_Demo.rar is located at:
<Download Folder>\rt4g_dg0622_liberov11p6_df\Drivers_64bitOS\PCIe_Demo.rar
2. Run the batch file Jungo_KP_install.bat located at C:\PCIe_Demo\DriverInstall\
Note: Installing these drivers require administration rights.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
3.
To run the batch file C:\PCIe_Demo\DriverInstall\Jungo_KP_install.bat, open command prompt and
select Run as administrator, as shown in Figure 8.
Figure 8 • Command Prompt
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
4.
Navigate to C:\ Drive and execute Jungo_KP_install.bat. in command prompt and press Enter. A
Windows Security dialog box is displayed and click Install, as shown in Figure 9.
Figure 9 • Jungo Driver Installation
5.
Click Install this driver software anyway, as shown in Figure 10.
Figure 10 • Install this Driver Software Anyway Window
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
Completed successfully message is displayed, as shown in the Figure 11.
Figure 11 • Completed Successfully Message
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
2.4.4
Installing PCIe_Demo Application GUI
The PCIe_Demo application is a simple GUI that runs on the host PC to communicate with the RTG4
PCIe endpoint device. It provides PCIe link status, driver information and demo controls. The
PCIe_Demo application invokes the PCIe driver installed on the host PC and provides commands to the
driver according to the selection made.
The following steps describe how to install the PCIe_Demo application:
1.
Go to
<Download Folder>\rt4g_dg0622_liberov11p6_df\GUI, extract PCIe_Demo_GUI_Installer.rar,
and double-click setup.exe. Do not change the default options and click Next.
Figure 12 • Installing PCIe_Demo Application
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
2.
Click Next to start the installation.
Figure 13 • PCIe_Demo Application Installation
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
3.
Click Finish to complete the installation.
Figure 14 shows that the installation has been successfully completed.
Figure 14 • Successful Installation of PCIe_Demo Application
4.
5.
6.
Shut down the host PC.
Power cycle the RTG4 Development Kit.
Restart the host PC.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
2.5
Running the Design
The following steps describe about how to run the demo design:
1.
Check the host PC Device Manager for the drivers. If the device is not detected, power cycle the
RTG4 Development Kit and click scan for hardware changes (highlighted in Figure 15) in Device
Manager window.
Figure 15 shows an example Device Manager window.
Figure 15 • Device Manager - PCIe Device Detection
Note: If a warning appears on the DEVICE or WinDriver in the Device Manager, uninstall them and start from
Step 1 of driver installation.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
2.
Invoke the PCIe_Demo application from All Programs > PCIe Demo > PCIe Demo GUI.
Figure 16 shows the PCIe_Demo launch window.
Figure 16 • PCIe_Demo Application
3.
Click Connect (highlighted in Figure 16). The application detects and displays the connected Kit,
demo design, and PCIe link.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
Figure 17 shows the example messages after the connection is established.
Figure 17 • PCIe Device Information
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
4.
Click Demo Controls to display the LEDs options and DIP switch positions, as shown in Figure 18.
Figure 18 • Demo Controls
5.
6.
7.
8.
9.
Click LED buttons to switch ON or OFF the LEDs on the board.
Click Start LED ON/OFF Walk.The LEDs on the board blink.
Click Stop LED ON/OFF Walk.The LEDs stop blinking.
Change the DIP switch positions on the board and observe the same being reflected in Switch
Module.
Click Enable Interrupt Session to enable the PCIe interrupt.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
10. Press the Push button, SW1 on the RTG4 Development Kit board. Observe the interrupt count on
the Interrupt Counter field in PCIe_Demo application, as shown in Figure 19.
Figure 19 • PCIe Interrupt
11. Click Clear/Disable Interrupts to clear and disable the PCIe interrupts.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
12. Click Config Space to view the details about the PCIe configuration space.
Figure 20 shows the PCIe configuration space.
Figure 20 • PCIe Configuration Space
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
13. Click PCIe R/W to execute read and writes to a 32-bit scratchpad register using BAR1 space.
Figure 21 shows the PCIe R/W panel.
Figure 21 • Read and Writes to Scratchpad Register
14. Click Fabric DMA to perform the DMA operations.
Three types of DMA transactions are possible:
•
•
•
Between host PC memory and LSRAM
Between host PC memory and DDR3 memory
Between LSRAM and DDR3 memory
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
For each operation, Transfer Type can be selected as Read, Write, or Read/Write, as shown in
Figure 22. It has Loop Count field to execute the DMA operation in a loop.
Figure 22 • DMA Operations
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
15. Select the type of DMA transfer as Host PC Memory - - > LSRAM and Transfer Type as Read to
execute the DMA transactions from Host PC to LSRAM. Click Start Transfer.
Figure 23 shows the Fabric DMA panel.
Figure 23 • DMA Transactions between Host PC Memory and LSRAM
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
After completion of data transfer, the throughput is displayed, as shown in Figure 24.
Figure 24 • DMA between Host PC Memory and LSRAM
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
16. Enter 10 as Loop Count and click Loop Transfer to perform 10 sequential DMA transactions. After
completion of data transfer, the PCIE_DEMO application displays the throughputs, as shown in
Figure 25. The average throughput is also logged. The log file is stored in the host PC at
C:\PCIe_Demo\DriverInstall.
Figure 25 • DMA between Host PC Memory and LSRAM - Loop Transfer
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
17. Select the type of DMA transfer as Host PC Memory < - - LSRAM and Transfer Type as Write to
execute the DMA transactions from LSRAM to host PC.
18. Click Start Transfer to perform a single DMA transaction. After completion of data transfer the
throughput is displayed, as shown in Figure 26.
Figure 26 • DMA between Host PC Memory and LSRAM
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
19. Enter 10 as the Loop Count and click Loop Transfer to perform 10 repeated DMA transactions.
After completion of data transfer, the throughput is displayed, as shown in Figure 27.
Figure 27 • DMA between Host PC Memory and LSRAM - Loop Transfer
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
20. Select Transfer Type as Read/Write to perform simultaneous read and writes. Click Start Transfer
to perform a single DMA transaction. After completion of data transfer, the throughput is displayed,
as shown in Figure 28.
Figure 28 • DMA between Host PC Memory and LSRAM
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
21. Enter 10 as the Loop Count and click Loop Transfer to perform 10 sequential DMA transactions.
After completion of data transfer, the throughput is displayed, as shown in Figure 29.
Figure 29 • DMA between Host PC Memory and LSRAM
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
22. Select the type of DMA transfer as Host PC Memory <--> DDR and Transfer Type as Read/Write
to perform simultaneous read and writes. Click Loop Transfer to perform 10 repeated DMA
transactions.The Transfer Type can be selected as Read or Write also. After completion of data
transfer, the throughput is displayed, as shown in Figure 30.
Figure 30 • DMA between Host PC Memory and DDR
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
23. Select the type of DMA transfer as LSRAM to DDR and Transfer Type as Read/Write to perform
simultaneous read and writes. Click Loop Transfer to perform 10 repeated DMA transactions. After
completion of data transfer, the throughput is displayed, as shown in Figure 31.
The Transfer Type can be selected as Read or Write.
Figure 31 • DMA between LSRAM and DDR
24. Click Exit to quit the demo.
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RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA
2.6
Summary
This demo shows how to implement a PCIe Data Plane Design using AXI based fabric DMA controller.
The Throughput for data transfers is depends on the Host PC system configuration and the type of PCIe
slots used.
Table 3 shows the throughput values observed on the HP Workstation Z220 PCIe slot 4.
Table 3 • Throughput Summary
Throughput in Mbyte/sec
X1 Lane
Gen1
DMA Transfer Type
Host PC to LSRAM
DDR to LSRAM
Host PC to DDR
Read
Single xfer
180
Loop xfer (50)
177
Write
237
236
R/W
180/237
180/236
Read
577
571
Write
585
582
R/W
575/585
570/580
Read
178
178
Write
232
232
R/W
177/232
177/231
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Appendix: Known Issues
3
Appendix: Known Issues
The following steps describe about known issues:
1.
The PCIe root ports can enable or disable the link by configuring the link control register of the PCIe
endpoint. If the PCIe root ports disable the link, the RTG4 PCIe endpoint LTSSM may be held in link
disable or polling compliance states. This issue will be fixed in a future RTG4 silicon version. The
demo design includes a workaround, as shown in Figure 32.
The LTSSM_DISABLE_DETECT logic monitors the state of the LTSSM. If it does not change from
LTSSM_DISABLE (6'b010000) state for a time period greater than 1 ms, the logic issues a corereset pulse and resets the core.
The LTSSM_POLLING_COMPLIANCE_DETECT logic also monitors the state of the LTSSM. If it
does not change from LTSSM_POLLING_COMPLIANCE (6'b000011) state for a time period greater
than 1 ms, the logic issues a core-reset pulse to reset the core.
Figure 32 • Workaround for Link Enable/Disable
2.
The PCIe reset (fundamental reset or in-band reset) causes the endpoint device state machines,
hardware logic, port states, and configuration registers (except for the sticky registers) to initialize
the default conditions. During a host initiated PCIe reset process, the SERDES PCIe endpoint reset
must be generated in a proper sequence, and the endpoint device must be reinitialized correctly.
This will be handled automatically in a future Libero release.
If the PCIe endpoint is not reset properly, corrupt data may be passed through the PCIe link.
The demo design implements proper endpoint reset, as shown in Figure 33 on page 41. It detects
the hot reset, and resets the SERDES core and AXI interface using the SERDES soft reset register
through the CoreABC IP module.
The logic performs the following operations:
a. The HOTRESET_DETECT logic detects the hot reset from the root port by monitoring the
LTSSM[5] signal from SERDES block and generates HOTRESET.
b. The GPIO_IN[0] of the CoreGPIO module is connected to the HOTRESET signal.The GPIO_IN[1]
is connected to the PCIE_L2P2_ACTIVE signal from the SERDES block.
c. The CoreGPIO generates an interrupt to the CoreABC IP module on the positive edge of the
HOTRESET signal or the negative edge of the PCIE_L2P2_ACTIVE signal.
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Appendix: Known Issues
d. The CoreGPIO interrupt is connected to IO_IN[0] of the CoreABC IP module. The CoreABC
monitors IO_IN[0]. If it is high, it resets the SERDES core and AXI interface using the SERDES soft
reset register.
Figure 33 • Hot Reset Detection Block
3.
PCIe X4 designs enumerate as x1 designs on RTG4 ES device. In the demo design, PCIe is
configured for x1 link width. It will be fixed in a future RTG4 silicon version.
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Appendix: Register Details
4
Appendix: Register Details
Table 4 shows the registers used to interface with the Fabric DMA controller. These registers are in
BAR1 address space.
Table 4 • Register Details
Register Name
Register Address
Description
PC_BASE_ADDR
0x8028
Host PC memory base address provided by the driver.
DMA_DIR
0x8008
DMA direction:
Direction
Register Value
1. PCIe DDR memory
2. DDR PCIe memory
0x11AA0001
0x11AA0002
3. LSRAM DDR memory
0x11AA0003
4. DDR LSRAM memory
0x11AA0004
5. PCIe LSRAM memory
6. LSRAM PCIe memory
0x11AA0005
0x11AA0006
To reset the DMA, the register value is 0x11AA0007.
Notes:
1. Before initiating DMA transactions, reset the DMA with the
register value, 0X11AA0007.
2. The DMA transactions 1 and 2, 3 and 4, or 5 and 6 can be
performed simultaneously by writing the corresponding values
one after other.
DMA_CH0_STATUS
0x8100
DMA Channel-0 status:
• DMA_CH0_STATUS[31]
1: DMA operation completed
0: DMA operation not completed
• DMA_CH0_STATUS[15:0] CLK count
DMA_CH1_STATUS
0x8108
DMA Channel-1 status:
• DMA_CH1_STATUS[31]
1: DMA operation completed
0: DMA operation not completed
• DMA_CH1_STATUS[15:0] CLK count
RW_REG
0x0
Scratchpad register for PCIe R/W.
LED_CTRL
0xA0
LEDs control register.
SWITCH_STATUS
0x90
DIP switch status.
Note: For the DDR memory, the source memory address is fixed as 0x0100_0000 and the destination memory
address is fixed as 0x0000_0000.
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Appendix: Silk Screen
5
Appendix: Silk Screen
Figure 34 shows the top-view of the RTG4 Development Kit silk screen.
Figure 34 • Top View - RTG4 Development Kit Silk Screen
J1
J2
SERDES TEST TRACE-5/8/5 MILS
LAYER-L14 LENGTH-5460 MILS
J3
J5
J4
J6
SERDES TEST TRACE-3.5/8/3.5 MILS
LAYER-L12 LENGTH-7206 MILS
J9 12V/5A
2.5V
1.8V
1.5V
1.2V
B1
Revision 3
J17 SWT
C19
D3
R24
R30
C23 R25 R21
GND TP15
C26
J25
GA1 J24
U4
R6
TP84
VDDPLL1
A40
GND
TMS
TDO
TDI
J23
R34
R35
C30
TRST_L
TCK
U12
GND
TP29
FTDI PROG MODE
RMT
J32
D8
R69
C71
SEL
C73
R76
J34
U17
R50
JTAG PROG MODE
D4 R48
R49
R54
C61
U23
C70
U18
R88
C91
C81
U28
R79 R82 R85
R86
C80
C79
C83
C85
C88
C92
TP57
R93
0P75V_REG_FDDR0
3P3V_LDO
2P5V
1P2V_SERDES_IO
R119
R120
R121
0P75V_REG_FDDR0
0P75V_REG_FDDR1
DS13
DS14
DS15
DS16
DS17
DS18
R115
R116
R117
R118
DS12
VDD_REG
1P5V_REG
R111
R112
R113
R114
DS8
TP79
VCCIO_HPC1_VADJ
VCCIO_HPC2_VADJ
1P8V
1P0V_PHY
TP65
TP68
DS9
DS10
DS11
J57
REFCLK_N
GND
J50
SERDES5_TX0_P
GND
J49
R102
R104 SERDES5_RX0_P
1P2V_REG
R74
R78
D9
A1
C95
TP66
TP63
TP72
TP77
C111
TP81
TP82
R123 GND TP80
GND
TP67
R108 R99 R106 R97
R109 R100
R98
R103
R107
R105
TP71
TP56
TP61
GND
GND
TP60
C100
C102 R94
REFCLK_P
J48
TP64
TP58
C98
J27
C35
R37
C45 TP30
1P2V_SERDES_IO C68
TP50
U27
GND
R92
J58
SERDES5_RX0_N
J59
SERDES5_TX0_N
C87
C89
C93
GND
C101
C104
C105
C106
C109
GND
TP54
Y4 125MHz
J54
SERDES_VREF2
J53
SERDES_VREF1
C77
C78
C82
C86
GND
U29
R83
TP46
GND C76
J33
VCCIO_HPC1_VADJ
A1
U6
U9
R60
1P2V_SERDES_IO
A1
GND R75
GND
TP51
U22
A1
TP45
TP42
TP52
D10
CON1
C62
U19
C57
C58
C56
U20
C60
C69
A1
U24
S0_PRSNT
U32
C107 C108
J55 R110
R122
D5
C54
TP35 TP36
AF7 AE7
0P75V_REG_FDDR1
3P3V R101
U10
A1
U15
C53
C52
GND
C64 C55
R58
R59
D11 R87
R90
R91
C99
C97
TP69
2P5V
C40
C47
C49
3P3V_LDO
2P5V
C36
U16
U13
U11
C44
C33
C42
3.3V
2.5V TP18
C29 1.8V
1.5V
1.2V GA0
J22 FP4 HEADER FTDI-JTAG
FTDI-SPI
SLAVE
C34
R42 C46
C50
3
OFF
R13 J19 L1 C15
R18
C11
VPP TP19
Y2 50MHz
6
RMTC12C8
U8
9
A1
C24
VCCIO_HPC1_VIO
_B_M2C_FMC
C32
TP27
AE35 TP28
A1
A1
3P3V_LDO
R184
2
19
1
J26 TRACE ETM HEADER 1
J20
AF35
A1
10
R19
20
TP83
R11
R36
C27
TP53
1P5V_REG
19
R15
R7
D2
R33
A1
R137
B32
U33
D1
20
A
J18 1
RVI HEADER
2
B
C74
TP59
R138
R139
R135
L2
U7
R14
C13
C17
A1
C59 R55
R61
C65 TP34 1P0V_PHY
TP37
R89
TP76 F33
GND
C110
R95
R23
R27
R29
R32
R31
C25
C28
C31
C103
BD2
U30
C38
C75
R84
R73
1P8V
U31
I2C0_SDA
CR2
R96
5V0_FT DS7
R43
R45
R46
R47
R51
U26
R345
R344 C94
C96
J51
J52
5
J47
PO_LED0
T34 PO_LED3
R56R57
R62 R63
R64
Dd7 J35
Dd6 J36
Dd4 J37
Dd2 J38
J46
C90
1
100MHz
Y1
RT4G_DEVELOPMENT_KIT REV A
R22
DVP-102-000418-001
R26
R28
SW6 ON
1
R70
R9
W33
U35
VCCIO_HPC2_VADJ
R36
U14
J31
Y3
25MHZ
12V_PWR_EN
J41 J42 J43
PWREN# Dd5
CR1
GND
U3
TP7
TP5
VCCIO_HPC2_VADJ 5P0V
2
MDC
C72
R77
Dd3
C37
J39
U25
J44
C38
J45 J40
GND
X1
R80
C84
R81
U21
J21
C41
R65
R66
1
R67
R68
D7
C63
C18
T33
A1
C66
C67
PHY
TRSTN
TMS
TCK
R71
R72
TDI
TP43 TDO
GND
TP49
GND
VCCIO_HPC2_VIO
_B_M2C_FMC
DS6
LED8 LED7 LED6 LED5 LED4 LED3
TC24
R38
R39
R41
R52 HSDACP
R53
J11
A1
B1
J12 HPC2-PARTIALLY POPULATED FMC
A40
C10
V30
C39
C43
C48
R40 C51
R44 HSDACN
D6
J10
SW7 DEVRST
C6
W34
MDIO
C37
A1
J29
DS4
DS5
J28
TC4
TC5 TC1
TC6 TC2
TC7
TC8 TC3
TC9
R17
J30
DS1
L
R136
R12
R16
C5
C9
SW5 ON-H LED1
LED2
AA33
VDD_REG
Y31
A1
A1 A
A
W31
TP16 C14 R20
W30
VDD CURRENT SENSE
B
B1 B
V33
SW4 AB32 SW3 AB30 B1
V34
A1 A
A
A1
U34
W36
B
B1 L
ON-H
B1 B
PO_LED2
SW2 AB31
SW1 AA30 CONFIG1
R10
C7
U5
J15
W35
DS2
RESET
LED9
3P3V
J13
R2
R3
R4
R5
GA1
GA0
J16
TP14
3P3V TP12
1.2V 1.0V
R8
1
DS3
R1
GND
TP1
12P0V
TP4
TP9
TP10
TP11
TP13
J14
3P3V
K1
TCK
GND
TMS
TRST_L
TDO
TP2 TDI
GND TP3
HPC1-FULLY POPULATED FMC
K40
U2
TP8
GND
U1
5P0V
J8
J7
TP78
J56
GND
3P3V
A1
K1
43
Revision History
6
Revision History
The following table shows important changes made in this document for each revision.
Revision
Changes
Revision 3
(April 2016)
Updated the document for Libero v11.7 software release (SAR 78192).
Revision 2
(October 2015)
Updated the document for Libero v11.6 software release (SAR 71422).
Revision 1
(June 2015)
Initial release
Revision 3
44
Product Support
7
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
7.1
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
7.2
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
7.3
Technical Support
For Microsemi SoC Products Support, visit
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.
7.4
Website
You can browse a variety of technical and non-technical information on the Microsemi SoC Products
Group home page, at http://www.microsemi.com/products/fpga-soc/fpga-and-soc.
7.5
Contacting the Customer Technical Support
Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
7.5.1
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected].
7.5.2
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Revision 3
45
Product Support
7.5.3
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Visit About Us for sales office listings and
corporate contacts.
7.6
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes
in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web
page.
Revision 3
46
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world's standard for time; voice
processing devices; RF solutions; discrete components; enterprise storage and communication
solutions, security technologies and scalable anti-tamper products; Ethernet Solutions; Powerover-Ethernet ICs and midspans; as well as custom design capabilities and services.
Microsemi is headquartered in Aliso Viejo, Calif, and has approximately 4,800 employees
globally. Learn more at www.microsemi.com.
Microsemi Corporate
Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
© 2016 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
50200622-3/4.16