LG0623: RTG4 FPGA Fabric Lab Guide

RTG4 FPGA Fabric
LG0623 Lab Guide
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50200623-2/6.16
Revision History
1
Revision History
The following table shows important changes made in this document for each revision.
Revision
Changes
Revision 2
(June 2016)
Updated the document for Libero SoC v11.7 software release (SAR 79550).
Revision 1
(June 2015)
Initial release.
Revision 2
3
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 RTG4 FPGA Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1
RTG4 Device Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.3
Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4
Extracting the Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Step 1: Creating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1
Launching Libero SoC Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1.1
Making Connections in the Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Step 2: Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Step 3: Synthesize the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Step 4: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Step 5: Entering Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Step 6: Layout and Timing Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.7.1
Layout Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.7.2
Timing Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Step 7: Programming the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Step 8: Running the Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1
3.2
3.3
3.4
3.5
3.6
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 2
39
39
39
39
39
39
39
39
40
4
Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Demo Design Files Top Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Libero SoC Project Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Libero SoC New Project Details Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Project Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Selection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device I/O Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Imported HDL source files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Use Enhanced Constraint Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Design Hierarchy Tab with Imported Files (VHDL shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Opening the SmartDesign Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Entering SmartDesign Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock & Management Category of the Libero SoC IP Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Configuring the RTG4 Fabric CCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Macro Library Category of the Libero SoC IP Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IP Catalog Search Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SmartDesign Canvas After Adding Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Renaming the Top Level Port PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Modifying Top Level Port Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SmartDesign Canvas After Connecting the Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Setting Fabric_Top as the Root Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Importing the testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Importing the testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Testbenches in the RTG4_Fabric project (VHDL shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Selecting user_testbench for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Importing the Simulation Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Testbench and Simulation Files (VHDL shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Location of the Libero SoC Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Libero SoC Project Settings Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Simulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Launching Pre-Synthesis Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ModelSim Waveform Window (VHDL results shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Design Flow - Synthesize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Opening the I/O Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Constraint Manager Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O Editor with Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Edit Timing Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Constraint Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Create Clock Constraint Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clock Constraint Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Entering the Clock Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Constraints Editor with Clock Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Running Layout and Verifying Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Design Flow Tab after Layout and Timing Report Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Timing Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RTG4 Development Kit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Launching Programming Software from Design Flow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Selecting Programming Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Programming Messages in Libero SoC Log Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Design Flow window after Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision 2
5
Tables
Table 1
Table 2
Table 3
Table 4
Table 5
State of SW7, SW2, and SW1 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SmartDesign Port Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision 2
6
RTG4 FPGA Fabric
2
RTG4 FPGA Fabric
2.1
Introduction
This lab guide demonstrates how to implement a basic RTG4™ field programmable gate array (FPGA)
fabric design using SmartDesign. The design drives LEDs on the RTG4 Development Kit board with
different patterns based on the state of SW7, SW2, and SW1 switches (see Table 1).
Table 1 • State of SW7, SW2, and SW1 Switches
Reset Switch (SW7)
User Switch (SW2)
User Switch (SW1)
LED[8:1] Behavior
Pressed
Do not care
Do not care
Off
Released
Released
Released
Toggle LED[6:5] and LED[4:3]
Red and Green LEDs
Released
Released
Pressed
Shift left
Released
Pressed
Released
Shift right
Released
Pressed
Pressed
Toggle LED[8:7] and LED[2:1]
Orange and Yellow LEDs
After completing this lab guide, you will be familiar with the following:
•
•
•
•
2.1.1
Creating a Libero® System-on-Chip (SoC) project
Implementing an RTG4 fabric design with SmartDesign
Simulating the design
Making pin assignments, running layout, and programming the RTG4 silicon
RTG4 Device Components
This lab guide uses the RTG4 FPGA fabric and the fabric clock conditioning circuit (CCC).
2.1.2
Design Requirements
Table 2 lists the hardware and software design requirements.
Table 2 • Design Requirements
Design Requirements
Description
Hardware Requirements
RTG4 FPGA Development Kit
-
Software Requirements
Libero® System-on-Chip (SoC)
v11.7
ModelSim
10.4c
Synplify Pro
J 2015.03M SP1-2
FlashPro Programming Software
v11.7
Revision 2
7
RTG4 FPGA Fabric
2.1.3
Demo Design
The demo design files are available for download from the following path in the Microsemi website:
http://soc.microsemi.com/download/rsc/?f=rt4g_lg0623_liberov11p7_df
The demo design files include:
•
•
•
Source_files
Solution
readme.txt
Figure 1 shows the top-level structure of the design files. For further details, refer to the readme.txt
file.
Figure 1 •
Demo Design Files Top Level Structure
GRZQORDGBIROGHU!
UWJBOJBOLEHURYSBGI
6RXUFHBILOHV
6ROXWLRQ
UHDGPHW[W
2.1.4
Extracting the Source Files
1.
2.
3.
Download design files from
http://soc.microsemi.com/download/rsc/?f=rt4g_lg0623_liberov11p7_df
Extract rt4g_lg0623_liberov11p7_df.rar to extract the required lab files to the <C:, D:, or
E:>\Microsemiprj folder on the HDD of the PC.
Ensure that the RTG4_Fabric_tutorial folder contains a Source_files sub-folder, which is
extracted.
Revision 2
8
RTG4 FPGA Fabric
2.2
Step 1: Creating the Design
Create the fabric design using SmartDesign by using the source files provided in the Source_files folder.
2.2.1
Launching Libero SoC Software
1.
Figure 2 •
Click Start > Programs > Microsemi > Libero SoC v11.7 or click the shortcut on the desktop. The
Libero SoC Project Manager is displayed as shown in Figure 2.
Libero SoC Project Manager
Revision 2
9
RTG4 FPGA Fabric
2.
Figure 3 •
Libero SoC New Project Details Dialog Box
3.
4.
Figure 4 •
Click New under Projects to create a new project, or click Project > New Project from the Libero
SoC software menu. The New Project wizard is displayed as shown in Figure 3.
Enter the following information in the Project Details page of the New Project dialog box as shown
in Figure 4:
•
Project Name: RTG4_Fabric
•
Project Location: <C:, D:, or E:>\Microsemiprj\RTG4_Fabric_tutorial (depending on where you
extracted the source files)
•
Preferred HDL Type: Verilog or VHDL
•
Enable Block Creation: Leave Unchecked (default)
Click Next
Project Details
Revision 2
10
RTG4 FPGA Fabric
5.
•
•
•
•
•
•
Figure 5 •
Device Selection Settings
6.
•
•
•
Figure 6 •
Enter the following information in the Device Selection page of the New Project dialog box and
click Next:
Family: RTG4
Die: RT4G150_ES
Package: 1657 CG
Speed: STD
Core Voltage: 1.2
Range: MIL
Enter the following information in the Device Settings page of the New Project dialog box and click
Next:
Default I/O Technology: LVCMOS 2.5 V (default)
Reserve Pins for Probes: Check (default)
Reserve Pins for SPI: Leave Unchecked (default)
Device I/O Settings
Revision 2
11
RTG4 FPGA Fabric
The Add HDL Source Files page is displayed as shown in Figure 7.
Figure 7 •
Imported HDL source files
7.
8.
9.
Click Import File to import the provided VHDL and Verilog source file into the project.
Enter the following information in the Import Files dialog box and click Open:
•
Files Type: HDL Source Files (*.vhd *.v *.h)
•
File Name: LED_ctrl.vhd (for VHDL projects) or LED_ctrl.v (for Verilog projects)
•
File Location: <C:, D:, or E>\Microsemiprj\RTG4_Fabric_tutorial\Source_files
Click Finish.
Revision 2
12
RTG4 FPGA Fabric
10. Click Use Enhanced Constraint Flow (see Figure 8).
Figure 8 •
Use Enhanced Constraint Flow
The LED_ctrl (LED_ctrl.vhd) file is displayed on the Libero Design Hierarchy tab (see Figure 9).
Figure 9 •
Design Hierarchy Tab with Imported Files (VHDL shown)
11. Open the SmartDesign canvas by selecting File > New > SmartDesign or by double-clicking
Create SmartDesign under Create Design in the Design Flow tab.
Revision 2
13
RTG4 FPGA Fabric
Figure 10 • Opening the SmartDesign Canvas
12. Enter Fabric_Top in the Create New SmartDesign dialog box then click OK. For Verilog designs,
the name is case sensitive.
Figure 11 • Entering SmartDesign Name
13. Drag-and-drop the LED_ctrl component from the Design Hierarchy tab in the SmartDesign
canvas.
This design uses a Fabric CCC to generate the 500 kHz internal clock. The CCC reference clock is
the 50 MHz crystal oscillator on the RTG4 Development Kit. In the following steps, configure the
CCC to output a 500 kHz clock.
14. Expand Clock & Management in the IP catalog.
Figure 12 • Clock & Management Category of the Libero SoC IP Catalog
15. Drag-and-drop an instance of the RTG4 CCC v1.1.208 component in the SmartDesign canvas.
16. Double-click the RTG4FCCC_0 component in the SmartDesign canvas to open the RTG4 CCC
Configurator.
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17. Select the Basic tab in the FAB CCC configurator. Enter the following:
•
Reference Clock: Enter 50 MHz
Select FPGA Fabric Input 0 from the drop-down menu
•
GL0: Select
Enter Frequency as 0.5 MHz
Figure 13 • Configuring the RTG4 Fabric CCC
18. Click OK to save the changes.
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19. Expand Macro Library in the Libero SoC IP catalog.
Figure 14 • Macro Library Category of the Libero SoC IP Catalog
20. Drag-and-drop an instance of AND2, INBUF, and SYSRESET in the SmartDesign Canvas.
Note: Type part of the macro name followed by * in the IP Catalog search field to find macros from the list.
When finished, change the field to * to display the entire catalog.
Figure 15 • IP Catalog Search Field
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21. After adding the components, the SmartDesign is displayed as shown in Figure 16. Drag the
components to improve the appearance of the canvas, if required.
Note: Expand the canvas area by selecting View > Maximize Work Area or click the
icon on the tool bar.
Figure 16 • SmartDesign Canvas After Adding Components
2.2.1.1
Making Connections in the Canvas
Connect the components in the SmartDesign canvas to complete the design. SmartDesign in the Libero
SoC software has a connection mode that supports click, drag, and release to make connections.
1.
2.
3.
Select SmartDesign > Connection Mode from the Libero SoC software or click the Connection
Mode icon
.
Connect the GL0 port of RTG4FCCC_0 component to the CLK port of the LED_ctrl_0 component as
follows:
•
Click and drag-and-drop the GL0 port of the RTG4FCCC_0 component in the CLK port of the
LED_ctrl_0 component.
Repeat the previous step to make the following connections listed in Table 3:
Table 3 • SmartDesign Port Connections
From
To
Component
Port
Component
Port
RTG4FCCC_0
LOCK
AND2_0
A
SYSRESET_0
POWER_ON_RESET_N
AND2_0
B
AND2_0
Y
LED_ctrl_0
RESETn
INBUF-0
Y
RTG4FCCC_0
CLK0
4.
5.
6.
Select SmartDesign > Connection Mode from the Libero SoC menu to exit the connection mode.
Promote the following ports to the top-level. Right-click on the port and select Promote to Top
Level:
•
LED_ctrl_0: PB_SW1
•
LED_ctrl_0: PB_SW2
•
LED_ctrl: LED[7:0]
Rename the top-level PAD CLK_50 port by right-clicking the port and selecting Rename Top Level
Pin.
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7.
Enter CLK_50 as name in the Rename Top Level Port dialog box as shown in Figure 18.
Figure 17 • Renaming the Top Level Port PAD
Figure 18 • Modifying Top Level Port Names
8.
9.
Click OK to save the top level port name.
After making the connections, the SmartDesign canvas is displayed as shown in Figure 19. You can
drag-and-drop the components or use the SmartDesign Auto Arrange feature to improve the
appearance of the canvas.
Figure 19 • SmartDesign Canvas After Connecting the Ports
10. Save the design (File > Save Fabric_Top).
11. Generate the design by clicking SmartDesign > Generate Component or by clicking the Generate
Component on the SmartDesign toolbar.
12. Restore the work area from View > Restore Work Area, if you have expanded the work area earlier.
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13. Ensure that 'Fabric_Top' was generated successfully. message appears in the Libero Message
window.
14. Close the design from File > Close Fabric_Top.
2.3
Step 2: Simulating the Design
A testbench, ModelSim macro, and wave format files are provided as part of the source files. The
LED_ctrl module/entity contains a 19-bit counter. To accelerate the simulation of the design, some of the
counter bits are forced high in the ModelSim macro file.
Note: With the slow clock rate, that is 500 kHz, simulation takes a long time.
1.
Ensure that Fabric_Top is in bold font in the Libero Design Hierarchy window. If it does not, select
Fabric_Top, right-click and select Set As Root.
Figure 20 • Setting Fabric_Top as the Root Level
2.
Expand Verify Pre-Synthesized Design in the Design Flow window. Right-click Simulate and
select Import Files...
Figure 21 • Importing the testbench
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3.
Enter the following in the Import Files dialog box and click Open:
•
Look in: <C:, D:, or E:>\Microsemiprj\RTG4_Fabric_tutorial\Source_files
•
Files of type: HDL Stimulus Files (*.vhd *.v)
•
File name: user_testbench.vhd (for VHDL projects) or user_testbench.v (for Verilog
projects)
Figure 22 • Importing the testbench
4. Select the Stimulus Hierarchy tab. The testbench .hdl file will be displayed.
Note: If user_testbench.v or user_testbench.vhd is not visible in the Stimulus Hierarchy tab, the file is not
imported as an HDL stimulus file. Re-import the file as described in step 3 and step 4.
Figure 23 • Testbenches in the RTG4_Fabric project (VHDL shown)
5.
Right-click user_testbench.v or user_testbench.vhd and select Set as active stimulus to use the
testbench you imported for simulation. A waveform symbol will be displayed next to the testbench
name to indicate it is the active stimulus.
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Figure 24 • Selecting user_testbench for Simulation
6.
7.
Import the ModelSim macro and Wave format files by right-clicking Simulate under Verify PreSynthesized Design in the Design Flow window and selecting Import Files.
Enter the following in the Import Files dialog box and click Open:
•
Look in: <C: or D: or E:>\Microsemiprj\RTG4_Fabric_tutorial\Source_files
•
Files of type: Simulation Files (*.mem *.bfm *.dat *.txt *.do)
•
File name: Hold the shift key and select vhdl_run.do and vhdl_wave.do (VHDL projects)
OR vlog_run.do and vlog_wave.do (Verilog projects)
Figure 25 • Importing the Simulation Files
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The testbench and simulation files are visible on the Libero SoC Files tab under Stimulus and
Simulation, respectively.
Figure 26 • Testbench and Simulation Files (VHDL shown)
8.
9.
Open the ModelSim macro file (vhdl_run.do or vlog_run.do) in the Libero SoC editor by
double-clicking the filename on the Files tab.
Locate the variable PROJECT_DIR online 11 of vhdl_run.do or vlog_run.do and confirm that it
matches the location of the Libero SoC fabric tutorial. The location is displayed at the top of the
Libero SoC GUI (do not include RTG4_Fabric.prjx). Edit the path if required.
Figure 27 • Location of the Libero SoC Project
10. Locate the variable INSTALL_DIR online 12 of vhdl_run.do or vlog_run.do and confirm that it
matches the location of the Libero SoC RTG4_Launch installation. Edit the path if required.
11. Save the file after making the changes (File > Save vhdl_run.do or File > Save vlog_run.do).
12. The vhdl_run.do/vlog_run.do file contains the force-freeze command to force the counter bits
in LED_ctrl to high, This command helps to speed up the simulation.
13. Close the editor from File > Close vhdl_run.do or File > Close vlog_run.do.
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14. Open the Libero SoC project settings from Project > Project Settings.
Figure 28 • Libero SoC Project Settings Dialog Box
15.
16.
17.
•
•
•
Select Do File under Simulation Options in the Project Settings Dialog box.
Uncheck Use automatic DO file check box.
Click browse next to User defined DO file, enter the following information and click Open:
Look in: <C: or D: or E:>\Microsemiprj\RTG4_Fabric_tutorial\RTG4_Fabric\simulation
Files of type:*.do
File name:vhdl_run.do (VHDL projects) or vlog_run.do (Verilog projects)
The ModelSim macro file (vhdl_run.do or vlog_run.do) calls the Wave format file (vhdl_wave.do or
vlog_wave.do), and hence do not require any separate settings for the Wave Format file.
Figure 29 • Simulation Options
18. Click Save and Close to close the Project Settings dialog box by saving the project settings.
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19. Expand Verify Pre-Synthesized Design in the Design Flow window. Right-click Simulate and select
Open Interactively to launch ModelSim in GUI mode.
Figure 30 • Launching Pre-Synthesis Simulation
20. The simulation runs for 2.5 ms. When finished, the waveform window is displayed as shown in
Figure 31.
Figure 31 • ModelSim Waveform Window (VHDL results shown)
21. Scroll in the window. The LED port represents the LED driver (1 = LED off; 0 = LED on). The
PB_SW1 and PB_SW2 ports represent the switch inputs (0 = switch pressed; 1 = switch released).
The DEVRST_N input represents the Reset (SW7 input).
22. Ensure that the LED output (LED) matches the description in Table 1 on page 7.
23. Close the ModelSim simulator by File > Quit. Click Yes when asked if you want to quit.
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2.4
Step 3: Synthesize the Design
In the Design Flow window, expand the Implement Design and right-click Synthesize and select Run
as shown in Figure 32.
Figure 32 • Design Flow - Synthesize
2.5
Step 4: Pin Assignments
1.
In the Design Flow window, expand Constraints. Right-click Manage Constraints and select Open
Manage Constraints View.
Figure 33 • Opening the I/O Editor
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2.
In the Constraint Manager window, select the I/O Attributes tab and click Edit with I/O Editor (see
Figure 34).
Figure 34 • Constraint Manager Window
The I/O Editor is displayed as shown in Figure 35.
Figure 35 • I/O Editor
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3.
Make the pin assignments listed in the Table 4. In I/O Editor, go to Pin Number column and click
Unassigned in the Pin Number column to see the available I/O pins. Accept the default settings for
all other options.
Table 4 • Pin Assignments
Port Name
I/O Standard
Pin No
Pin Name
CLK_50
LVCMOS25
AA39
MSIOD73PB1/GB12_23
LED[0]
LVCMOS25
W35
MSIOD62PB1
LED[1]
LVCMOS25
W34
MSIOD46PB1
LED[2]
LVCMOS25
V30
MSIOD47PB1
LED[3]
LVCMOS25
W33
MSIOD46NB1
LED[4]
LVCMOS25
T33
MSIOD38PB1
LED[5]
LVCMOS25
U35
MSIOD41NB1
LED[6]
LVCMOS25
R36
MSIOD37PB1
LED[7]
LVCMOS25
T34
MSIOD38NB1
PB_SW1
LVCMOS25
AA30
MSIOD68NB1
PB_SW2
LVCMOS25
AB31
MSIOD65PB1
Figure 36 shows the I/O Attribute Editor after assigning the pins.
Figure 36 • I/O Editor with Pin Assignments
4.
5.
Select File > Commit and Check from the I/O Attribute Editor menu. Ensure that the I/O Editor
Log window has no errors.
Close the I/O Attribute Editor using File > Exit.
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RTG4 FPGA Fabric
2.6
Step 5: Entering Timing Constraints
1.
In the Constraint Manager window, select the Timing tab, click Edit with Constraint Editor > Edit
Timing Verification Constraints, as shown in Figure 37.
Figure 37 • Edit Timing Constraint
The Constraint Editor window is displayed as shown in Figure 38.
Figure 38 • Constraint Editor
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RTG4 FPGA Fabric
2.
3.
Click Constraints > Clock to add a Clock constraint. The Create Clock Constraint dialog box is
displayed as shown in Figure 39.
Click Browse, as shown in Figure 39.
Figure 39 • Create Clock Constraint Dialog Box
4.
It opens the Select Source Pins for Clock Constraint window. Select the
RTG4FCCC_0/CCC_INST/GL0 pin, click Add and click OK (see Figure 40).
Figure 40 • Clock Constraint Window
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5.
Enter the following information in the Create Clock Constraint dialog box and click OK:
•
Frequency: 0.5 MHz
Figure 41 • Entering the Clock Constraint
The clock constraint is displayed in the Constraints Editor (see Figure 42).
Figure 42 • Constraints Editor with Clock Constraint
6.
Close the Constraints Editor (File > Exit). Click Yes when prompted to save the changes.
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RTG4 FPGA Fabric
2.7
Step 6: Layout and Timing Verification
2.7.1
Layout Verification
Expand Verify Post Layout Implementation on the Design Flow tab. Right-click Verify Timing and
select Run. Place-and-Route tool is executed and a timing report is generated.
Figure 43 • Running Layout and Verifying Timing
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A green check mark is displayed in the Design Flow window next to Place and Route and Verify Timing
indicating that layout is completed without any errors and a timing report is generated.
Figure 44 • Design Flow Tab after Layout and Timing Report Generation
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2.7.2
Timing Verification
•
•
The timing reports are in the Reports tab.
Maximum Delay Analysis is contained in the Fabric_Top_max_timing_slow_1.14V_125C.xml report.
Minimum Delay Analysis is contained in the Fabric_Top_min_timing_fast_1.26V_-55C.xml report.
Both the reports are available in the Reports window.
Figure 45 • Timing Reports
•
Timing violations can quickly be identified by looking at the timing violations reports as
Fabric_Top_max_timing_violations_slow_1.14V_125C.xml or
Fabric_Top_min_timing_violations_fast_1.26V_-55C.xml.
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2.8
Step 7: Programming the Design
Run FlashPro in batch mode to program the RT4G150_ES on the RTG4 Development Kit board.
Figure 46 • RTG4 Development Kit Board
1.
2.
3.
Ensure that the board is powered OFF using SW6 switch. Also ensure that AC input connector is not
connected to JP before connecting the cable or changing the jumper connections.
Plug the AC adapter to the J9 connector and plug into a 120 V AC outlet.
Before programming (and powering up) the RTG4 Development Kit board, ensure that the jumpers
are positioned as show in Table 5.
Table 5 • Jumper Settings
Jumper
Location
Purpose
Settings
J16
Above SW3
Select VDD core voltage
2-3 installed
J17
Below J9 AC connector
Select either SW6 input or signal
ENABLE_FT4232 from FT4232H
chip
1-2 installed
J19
Below J9 AC connector
J21
To the right of the dip switch bank
J23
To the right of the FP4 programming header
J26
Below ETM Trace header
J28
Below the dip switch bank
J32
To the left of the FMC connector (HPC1)
J33
Below FP4 programming header
4.
1-2 installed
Bank 7 supply voltage
1-2 installed
1-2 installed
Bank 2 supply voltage
1-2 installed
1-2 installed
Enable FlashPro5 for
programming
1-2 installed
1-2 installed
3-4 installed
Connect USB cable (mini USB to Type A USB cable) to J47 of the RTG4 Development Kit board and
other end of the cable to the USB port of the Host PC.
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5.
6.
Move the SW6 switch to the ON position, towards the J9 AC input connector.
Expand Program Design in the Design Flow window. Right-click Run PROGRAM Action and select
Configure Action/Procedures.
Figure 47 • Launching Programming Software from Design Flow Window
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RTG4 FPGA Fabric
7.
Confirm the following settings in the Select Action and Procedures dialog box and click OK:
•
Action: Program
•
Procedures: DO_VERIFY checked
Figure 48 • Selecting Programming Actions
8.
9.
Right-click Run PROGRAM Action and select Run to begin programming.
FlashPro5 runs in batch mode and programs the device. Once the board is programmed,
programming message is displayed in the Libero SoC log window. Programmer number will differ
from board to board.
Note: Interruption in the programming sequence may damage the device.
10. The following message must be visible in the Reports view under Program Device when the device
is programmed successfully. Programmer number will be different from device to device:
•
programmer E200YR6XLL: Chain programming PASSED.
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Figure 49 • Programming Messages in Libero SoC Log Window
A green check mark is displayed next to Program Design and Run PROGRAM Action in the Design Flow
window to indicate programming is completed successfully.
Figure 50 • Design Flow window after Programming
11. Close Libero SoC from Project > Exit.
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2.9
Step 8: Running the Application
1.
2.
3.
4.
Reset the board by holding the SW7 reset switch. The LEDs must be in OFF position.
Release SW7 and observe the pattern of the LEDs. LEDs [6:5] and LEDs [4:3] (the Red and Green
LEDs) must be toggled.
Press and hold SW1 switch and observe the pattern of the LEDs. Release SW1 switch and press
SW2 switch and observe the pattern of the LEDs. Press and hold SW1 and SW2 switches together.
The LED pattern must match the description in Table 1 on page 7.
When finished, change SW6 switch to the OFF position and power OFF the board.
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Product Support
3
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
3.1
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
3.2
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
3.3
Technical Support
For Microsemi SoC Products Support, visit
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.
3.4
Website
You can browse a variety of technical and non-technical information on the Microsemi SoC Products
Group home page, at http://www.microsemi.com/products/fpga-soc/fpga-and-soc.
3.5
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
3.5.1
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected].
3.5.2
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
3.5.3
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Visit About Us for sales office listings and
corporate contacts.
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Product Support
3.6
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes
in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web
page.
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