EMC1186 DATA SHEET (08/15/2013) DOWNLOAD

EMC1186
Dual Channel 1°C Temperature Sensor with Hardware
Thermal Shutdown and 1.8V SMBus Communications
PRODUCT FEATURES
Datasheet
General Description
Applications
The EMC1186 is a high accuracy, low cost, 1.8V System
Management Bus (SMBus) compatible temperature sensor.
Advanced features such as Resistance Error Correction (REC),
Beta Compensation (to support CPU diodes requiring the
BJT/transistor model including 65nm and lower geometry
processors) and automatic diode type detection combine to
provide a robust solution for complex environmental monitoring
applications. The ability to communicate at 1.8V SMBus levels
provides compatible I/O for the advanced processors found in
today’s tablet and smartphone applications.
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Features
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Support for diodes requiring the BJT/transistor model
— Supports 65nm and lower geometry CPU thermal
diodes
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Additionally, the EMC1186provides a hardware programmable
system shutdown feature that is programmed at part power-up
via two pull-up resistor values and that cannot be masked or
corrupted through the SMBus.
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REC automatically eliminates the temperature error caused by
series resistance allowing greater flexibility in routing thermal
diodes. Frequency hopping* and analog filters ensure remote
diode traces can be as far as eight (8) inches without degrading
the signal. Beta Compensation eliminates temperature errors
caused by low, variable beta transistors common in today's fine
geometry processors. The automatic beta detection feature
monitors the external diode/transistor and determines the
optimum sensor settings for accurate temperature
measurements regardless of processor technology. This frees
the user from providing unique sensor configurations for each
temperature monitoring application. These advanced features
plus ±1°C measurement accuracy provide a low-cost, highly
flexible and accurate solution for critical temperature monitoring
applications.
EMC1186
Hardware Thermal Shutdown
— triggers dedicated SYS_SHDN pin
— hardware configured range 77°C to 112°C in 1°C steps
— cannot be disabled or modified by software
The EMC1186 monitors two temperature channels (one
external and one internal), providing ±1°C accuracy for both
external and internal diode temperatures.
Switchi
ng
Current
Notebook Computers
Desktop Computers
Industrial
Embedded applications
Pin and register compatible with EMC1422
Automatically determines external diode type and
optimal settings
Resistance Error Correction
Frequency hops the remote sample frequency to reject
DC converter and other coherent noise sources*
Consecutive Alert queue to further reduce false Alerts
Up to 1 External Temperature Monitors
— 25°C typ, ±1°C max accuracy (20°C < TDIODE < 110°C)
— 0.125°C resolution
— Supports up to 2.2nF diode filter capacitor
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Internal Temperature Monitor
— ±1°C accuracy
— 0.125°C resolution
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3.3V Supply Voltage
1.8V SMBus operation
Programmable temperature limits for ALERT (85°C
default high limit and 0°C default low limit)
Available in small 8-pin 2mm x 3mm TDFN RoHS
compliant package
VDD = 3.3V
SYS_SHDN Limit
Internal
Temperature
Register
Internal
Temp
Diode
Low Limit Registers
High Limit Registers
Thermal
diode
SMBus Interface
External
Temperature
Register(s)
Digital Mux
Digital Mux
DN1
ΔΣADC
Limit Comparator
CPU
Analog
Mux
DP1
1.8V – 3.3V
VDD
Conversion Rate Register
Host
EMC1186
DP1
SMCLK
DN1
Internal
SMDATA
Diode
SMBus
Interface
ALERT
SMCLK
Configuration Register
Status
Registers
Interupt
Masking
SYS_SHDN
SMDATA
Power Control
ALERT
SYS_SHDN
GND
* Technology covered under the US patent 7,193,543.
SMSC EMC1186
Revision 1.0 (07-11-13)
DATASHEET
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Ordering Information:
SMBUS
ADDRESS
ORDERING NUMBER
PACKAGE
FEATURES
EMC1186-1-AC3-TR
8-pin TDFN 2mm x 3mm
(RoHS compliant)
Two temperature sensors, hardware set
system shutdown, ALERT and SYS_SHDN
pins, fixed SMBus address
1001_100(r/w)
EMC1186-2-AC3-TR
8-pin TDFN 2mm x 3mm
(RoHS compliant)
Two temperature sensors, hardware set
system shutdown, ALERT and THERM pins,
fixed SMBus address
1001_101(r/w)
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.
Copyright © 2013 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.0 (07-11-13)
2
DATASHEET
SMSC EMC1186
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table of Contents
Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 SMBus Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 4 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3 SMBus Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.6 SMBus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.7 SMBus and I2C Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
13
13
14
14
14
14
15
15
15
15
16
Chapter 5 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Conversion Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 .SYS_SHDN Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Hardware Thermal Shutdown Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 ALERT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1 ALERT Pin Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2 ALERT Pin Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 ALERT and SYS_SHDN Pin Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2 Resistance Error Correction (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.3 Programmable External Diode Ideality Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 Consecutive Alerts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Temperature Measurement Results and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
18
19
20
20
20
20
21
21
21
22
22
22
22
24
Chapter 6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 Data Read Interlock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Configuration Register 03h / 09h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Conversion Rate Register 04h / 0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMSC EMC1186
3
DATASHEET
27
27
28
29
Revision 1.0 (07-11-13)
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
6.5 Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Scratchpad Registers 11h and 12h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 Software Thermal Shutdown Configuration Register 1Dh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Hardware Thermal Shutdown Limit Register 1Eh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Channel Mask Register 1Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Consecutive ALERT Register 22h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 External Diode Ideality Factor Registers 27h to 31h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Filter Control Register 40h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 SMSC ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
30
31
31
32
32
33
34
36
37
37
37
Chapter 7 Typical Operating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 9 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision 1.0 (07-11-13)
4
DATASHEET
SMSC EMC1186
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
List of Figures
Figure 1.1
Figure 2.1
Figure 4.1
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 8.1
Figure 8.3
Figure 8.2
Figure 8.4
Figure 8.5
EMC1186 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
EMC1186 Pin Diagram, TDFN-8 2mm x 3mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System Diagram for EMC1186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Diagram of Hardware Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Isolating ALERT and SYS_SHDN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Temperature Filter Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Temperature Filter Impulse Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2mm x 3mm TDFN Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2mm x 3mm TDFN Package PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2mm x 3mm TDFN Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
EMC1186-1 8-Pin TDFN Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
EMC1186-2 8-Pin TDFN Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SMSC EMC1186
5
DATASHEET
Revision 1.0 (07-11-13)
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
List of Tables
Table 2.1 EMC1186 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5.1 Supply Current vs. Conversion Rate for EMC1186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5.2 SYS_SHDN Threshold Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6.3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6.4 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6.5 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6.6 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6.7 Scratchpad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6.8 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6.9 Software Thermal Shutdown Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6.10 Hardware Thermal Shutdown Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 6.11 Channel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 6.12 Consecutive ALERT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6.13 Consecutive Alert / Therm Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6.14 Ideality Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6.15 Ideality Factor Look-Up Table (Diode Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6.16 Substrate Diode Ideality Factor Look-Up Table (BJT Model) . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6.17 Filter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6.18 FILTER Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6.19 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6.20 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6.21 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision 1.0 (07-11-13)
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DATASHEET
SMSC EMC1186
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 1 Block Diagram
VDD
EMC1186
Switching
Current
SYS_SHDN Limit
Internal
Temperature
Register
Low Limit Registers
High Limit Registers
Internal
Temp Diode
SMBus Interface
External
Temperature
Register(s)
Digital Mux
DN1
ΔΣ ADC
Limit Comparator
Analog
Mux
DP1
Digital Mux
Conversion Rate Register
SMCLK
Configuration Register
Status Registers
Interupt Masking
SMDATA
ALERT
SYS_SHDN
GND
Figure 1.1 EMC1186 Block Diagram
SMSC EMC1186
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 2 Pin Description
EM C1186
VDD
1
DP
2
8
SM CLK
7
SM DATA
Exposed pad
DN
3
6
ALERT
SYS_SHDN
4
5
G ND
Figure 2.1 EMC1186 Pin Diagram, TDFN-8 2mm x 3mm
The pin types are described Table 2.2.
Table 2.1 EMC1186 Pin Description
PIN NUMBER
NAME
1
VDD
2
DP
External diode positive (anode) connection
AIO
3
DN
External diode negative (cathode) connection
AIO
4
SYS_SHDN
5
GND
6
ALERT
7
SMDATA
SMBus Data input/output - requires pull-up
resistor
8
SMCLK
SMBus Clock input - requires pull-up resistor
Bottom Pad
Exposed Pad
Revision 1.0 (07-11-13)
FUNCTION
Power supply
Active low system shutdown output signal requires pull-up resistor which selects the
Hardware Thermal Shutdown Limit
Ground
TYPE
Power
OD (5V)
Power
Active low digital ALERT output signal requires pull-up resistor
Not internally connected, but recommend
grounding.
8
DATASHEET
OD (5V)
DIOD (5V)
DI (5V)
-
SMSC EMC1186
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table 2.2 Pin Types
PIN TYPE
Power
AIO
DI
DESCRIPTION
This pin is used to supply power or ground to the device.
Analog Input / Output -This pin is used as an I/O for analog signals.
Digital Input - This pin is used as a digital input. This pin is 5V tolerant.
DIOD
Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as
an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant.
OD
Open Drain Digital Output - This pin is used as a digital output. It is open drain and
requires a pull-up resistor. This pin is 5V tolerant.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 3 Electrical Specifications
3.1
Absolute Maximum Ratings
Table 3.1 Absolute Maximum Ratings
DESCRIPTION
RATING
UNIT
Supply Voltage (VDD)
-0.3 to 4.0
V
Voltage on 5V tolerant pins (V5VT_pin)
-0.3 to 5.5
V
0 to 3.6
V
-0.3 to VDD +0.3
V
Operating Temperature Range
-40 to +125
°C
Storage Temperature Range
-55 to +150
°C
Voltage on 5V tolerant pins (|V5VT_pin - VDD|) (see Note 3.1)
Voltage on any other pin to Ground
Lead Temperature Range
Refer to JEDEC Spec. J-STD-020
Package Thermal Characteristics for DFN-10
Thermal Resistance (θj-a)
ESD Rating, All pins HBM
77.1
°C/W
2000
V
Note: Stresses at or above those listed could cause permanent damage to the device. This is a stress
rating only and functional operation of the device at any other condition above those indicated
in the operation sections of this specification is not implied.
Note 3.1
3.2
For the 5V tolerant pins that have a pull-up resistor (SMCLK, SMDATA,SYS_SHDN, and
ALERT), the pull-up voltage must not exceed 3.6V when the device is unpowered.
Electrical Specifications
Table 3.2 Electrical Specifications
VDD = 3.0V to 3.6V, TA = -40°C to 125°C, all typical values at TA = 27°C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
DC Power
Supply Voltage
VDD
Supply Current
IDD
Revision 1.0 (07-11-13)
3.0
3.3
3.6
V
200
410
µA
0.0625 conversion / sec, dynamic
averaging disabled
215
425
µA
1 conversion / sec, dynamic
averaging disabled
325
465
µA
4 conversions / sec, dynamic
averaging disabled
10
DATASHEET
SMSC EMC1186
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table 3.2 Electrical Specifications (continued)
VDD = 3.0V to 3.6V, TA = -40°C to 125°C, all typical values at TA = 27°C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
890
1050
1120
UNITS
CONDITIONS
µA
4 conversions / sec, dynamic
averaging enabled
µA
> 16 conversions / sec, dynamic
averaging enabled
Internal Temperature Monitor
Temperature Accuracy
±0.25
Temperature Resolution
±1
°C
-5°C < TA < 100°C
±2
°C
-40°C < TA < 125°C
0.125
°C
External Temperature Monitor
Temperature Accuracy
Temperature Resolution
±0.25
±1
°C
+20°C < TDIODE < +110°C
0°C < TA < 100°C
±0.5
±2
°C
-40°C < TDIODE < 127°C
0.125
°C
ms
Conversion Time all
Channels
tCONV
150
Capacitive Filter
CFILTER
2.2
2.7
nF
default settings
Connected across external diode
ALERT and SYS_SHDN pins
Output Low Voltage
VOL
Leakage Current
ILEAK
3.3
0.4
±5
V
ISINK = 8mA
µA
ALERT and SYS_SHDN pins
Device powered or unpowered
TA < 85°C
pull-up voltage < 3.6V
SMBus Electrical Characteristics
Table 3.3 SMBus Electrical Specifications
VDD = 3.0 to 3.6V, TA = -40°C to 125°C, all typical values are at TA = 27°C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBus Interface
Input High Voltage
VIH
1.4
VDD
V
5V Tolerant. Voltage threshold
based on 1.8V operation
Input Low Voltage
VIL
-0.3
0.8
V
5V Tolerant. Voltage threshold
based on 1.8V operation
Leakage Current
ILEAK
±5
µA
Powered or unpowered
TA < 85°C
SMSC EMC1186
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Revision 1.0 (07-11-13)
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table 3.3 SMBus Electrical Specifications (continued)
VDD = 3.0 to 3.6V, TA = -40°C to 125°C, all typical values are at TA = 27°C unless otherwise noted.
CHARACTERISTIC
SYMBOL
Hysteresis
MIN
TYP
MAX
50
Input Capacitance
CIN
Output Low Sink Current
IOL
UNITS
CONDITIONS
mV
5
pF
8.2
15
mA
SMDATA = 0.4V
SMBus Timing
Clock Frequency
fSMB
Spike Suppression
tSP
Bus Free Time Stop to
Start
tBUF
1.3
µs
Hold Time: Start
tHD:STA
0.6
µs
Setup Time: Start
tSU:STA
0.6
µs
Setup Time: Stop
tSU:STO
0.6
µs
Data Hold Time
tHD:DAT
0
µs
When transmitting to the master
Data Hold Time
tHD:DAT
0.3
µs
When receiving from the master
Data Setup Time
tSU:DAT
100
ns
Clock Low Period
tLOW
1.3
µs
Clock High Period
tHIGH
0.6
µs
Clock/Data Fall time
tFALL
300
ns
Min = 20+0.1CLOAD ns
Clock/Data Rise time
tRISE
300
ns
Min = 20+0.1CLOAD ns
Capacitive Load
CLOAD
400
pF
per bus line
Timeout
tTIMEOUT
35
ms
Disabled by default
Revision 1.0 (07-11-13)
10
25
400
kHz
50
ns
12
DATASHEET
SMSC EMC1186
Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 4 System Management Bus Interface Protocol
4.1
Communications Protocol
The EMC1186 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 4.1.
For the first 15ms after power-up the device may not respond to SMBus communications.
.
T LOW
T HD:STA
T HIGH
T SU:STO
T FALL
SMCLK
T RISE
T HD:STA
T SU:DAT
T HD:DAT
T SU:STA
SMDATA
TBUF
S
P
S
S - Start Condition
P - Stop Condition
P
Figure 4.1 SMBus Timing Diagram
4.1.1
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
4.1.2
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD / WR bit
is a logic ‘1’, the SMBus Host is reading data from the client device.
The EMC1186-1 SMBus address is hard coded to 1001_100(r/w).
The EMC1186-2 SMBus address is hard coded to 1001_101(r/w).
4.1.3
SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
4.1.4
SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives. This is done by the client device
pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to the
Write Byte protocol.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the
SMBus data line high after the 8th data bit has been sent.
4.1.5
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the device detects an SMBus Stop bit
and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.
4.1.6
SMBus Timeout
The EMC1186 supports SMBus Timeout. If the clock line is held low for longer than tTIMEOUT, the
device will reset its SMBus protocol. This function can be enabled by setting the TIMEOUT bit (see
Section 6.11, "Consecutive ALERT Register 22h").
4.1.7
SMBus and I2C Compatibility
The EMC1186 is compatible with SMBus and I2C. The major differences between SMBus and I2C
devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For
information on using the EMC1186 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave
Devices in I2C Systems.
1. EMC1186 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz.
2. Minimum frequency for SMBus communications is 10kHz.
3. The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This
timeout functionality is disabled by default in the EMC1186 and can be enabled by writing to the
TIMEOUT bit. I2C does not have a timeout.
4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
Attempting to communicate with the EMC1186 SMBus interface with an invalid slave address or invalid
protocol will result in no response from the device and will not affect its register contents. Stretching
of the SMCLK signal is supported, provided other devices on the SMBus control the timing.
4.2
SMBus Protocols
The device supports Send Byte, Read Byte, Write Byte, Receive Byte, and the Alert Response Address
as valid protocols as shown below.
All of the below protocols use the convention in Table 4.1.
Table 4.1 Protocol Format
Revision 1.0 (07-11-13)
DATA SENT
TO DEVICE
DATA SENT TO
THE HOST
# of bits sent
# of bits sent
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
4.2.1
Write Byte
The Write Byte is used to write one byte of data to the registers, as shown in Table 4.2.
Table 4.2 Write Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
REGISTER
DATA
ACK
STOP
1 -> 0
YYYY_YYY
0
0
XXh
0
XXh
0
0 -> 1
4.2.2
Read Byte
The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.3.
Table 4.3 Read Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
START
SLAVE
ADDRESS
RD
ACK
REGISTER
DATA
NACK
STOP
1 -> 0
YYYY_
YYY
0
0
XXh
0
1 -> 0
YYYY_
YYY
1
0
XX
1
0 -> 1
4.2.3
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address
location. No data is transferred during the Send Byte protocol as shown in Table 4.4.
Table 4.4 Send Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
STOP
1 -> 0
YYYY_YYY
0
0
XXh
0
0 -> 1
4.2.4
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address
pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads
of the same register as shown in Table 4.5.
Table 4.5 Receive Byte Protocol
START
SLAVE
ADDRESS
RD
ACK
REGISTER DATA
NACK
STOP
1 -> 0
YYYY_YYY
1
0
XXh
1
0 -> 1
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
4.3
Alert Response Address
The ALERT output can be used as a processor interrupt or as an SMBus Alert.
When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA)
to the general address of 0001_100xb. All devices with active interrupts will respond with their client
address as shown in Table 4.6.
Table 4.6 Alert Response Address Protocol
START
ALERT
RESPONSE
ADDRESS
RD
ACK
DEVICE
ADDRESS
NACK
STOP
1 -> 0
0001_100
1
0
YYYY_YYY
1
0 -> 1
The EMC1186 will respond to the ARA in the following way:
1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication
from the device was not prematurely stopped due to a bus contention event).
2. Set the MASK_ALL bit to clear the ALERT pin.
APPLICATION NOTE: The ARA does not clear the Status Register and if the MASK_ALL bit is cleared prior to the
Status Register being cleared, the ALERT pin will be reasserted.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 5 Product Description
The is an SMBus temperature sensor with Hardware Thermal Shutdown. The EMC1186 monitors one
internal diode and one externally connected temperature diode.
Thermal management is performed in cooperation with a host device. This consists of the host reading
the temperature data of both the external and internal temperature diodes of the EMC1186 and using
that data to control the speed of one or more fans.
The EMC1186 has two levels of monitoring. The first provides a maskable ALERT signal to the host
when the measured temperatures exceeds user programmable limits. This allows the EMC1186 to be
used as an independent thermal watchdog to warn the host of temperature hot spots without direct
control by the host. The second level of monitoring asserts the SYS_SHDN pin when the External
Diode 1 temperature exceeds a hardware specified threshold temperature. Additionally, the internal
diode can be configured to assert the SYS_SHDN pin when the measured temperature exceeds user
programmable limits.
Figure 5.1 shows a system level block diagram of the EMC1186.
VDD = 3.3V
1.8V – 3.3V
VDD
CPU
Thermal
diode
Host
EMC1186
DP1
DN1
Internal
Diode
SMCLK
SMDATA
SMBus
Interface
ALERT
SYS_SHDN
Power
Control
Figure 5.1 System Diagram for EMC1186
5.1
Conversion Rates
The EMC1186 may be configured for different conversion rates based on the system requirements.
The conversion rate is configured as described in Section 6.4. The default conversion rate is 4
conversions per second. Other available conversion rates are shown in Table 6.5, "Conversion Rate".
5.2
Dynamic Averaging
Dynamic averaging causes the EMC1186 to measure the external diode channels for an extended time
based on the selected conversion rate. This functionality can be disabled for increased power savings
at the lower conversion rates (see Section 6.3, "Configuration Register 03h / 09h"). When dynamic
averaging is enabled, the device will automatically adjust the sampling and measurement time for the
external diode channels. This allows the device to average 2x or 16x longer than the normal 11 bit
operation (nominally 21ms per channel) while still maintaining the selected conversion rate. The
benefits of dynamic averaging are improved noise rejection due to the longer integration time as well
as less random variation of the temperature measurement.
When enabled, the dynamic averaging applies when a one-shot command is issued. The device will
perform the desired averaging during the one-shot operation according to the selected conversion rate.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
When enabled, the dynamic averaging will affect the average supply current based on the chosen
conversion rate as shown in Table 5.1.
Table 5.1 Supply Current vs. Conversion Rate for EMC1186
AVERAGE SUPPLY CURRENT
(TYPICAL)
AVERAGING FACTOR (BASED ON
11-BIT OPERATION)
CONVERSION RATE
ENABLED
(DEFAULT)
DISABLED
ENABLED
(DEFAULT)
DISABLED
1 / 16 sec
210uA
200uA
16x
1x
1 / 8 sec
265uA
200uA
16x
1x
1 / 4 sec
330uA
200uA
16x
1x
1 / 2 sec
395uA
200uA
16x
1x
1 / sec
460uA
215uA
16x
1x
4 / sec (default)
890uA
325uA
8x
1x
8 / sec
1010uA
630uA
4x
1x
16 / sec
1120uA
775uA
2x
1x
32 / sec
1200uA
1050uA
1x
1x
64 / sec
1400uA
1100uA
0.5x
0.5x
5.3
.SYS_SHDN
Output
The SYS_SHDN output is asserted independently of the ALERT output and cannot be masked. If the
External Diode 1 temperature exceeds the Hardware Thermal Shutdown Limit for the programmed
number of consecutive measurements, the SYS_SHDN pin is asserted.
The Hardware Thermal Shutdown Limit is defined at power-up via the pull-up resistors on the
SYS_SHDN and ALERT pins as shown in Table 5.2. This limit cannot be modified or masked via
software.
In addition to External Diode 1 channel triggering the SYS_SHDN pin when the measured temperature
exceeds to the Hardware Thermal Shutdown Limit, each of the measurement channels can be
configured to assert the SYS_SHDN pin when they exceed the corresponding THERM Limit.
When the SYS_SHDN pin is asserted, it will not release until the External Diode 1 temperature drops
below the Hardware Thermal Shutdown Limit minus 10°C and all other measured temperatures drop
below the THERM Limit minus the THERM Hysteresis value (when linked to SYS_SHDN).
Figure 5.2 shows a block diagram of the interaction between the input channels and the SYS_SHDN
pin.
Revision 1.0 (07-11-13)
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Hardware Thermal Shutdown
SMBus
Traffic
Internal Diode
Temperature
Conversion
and THERM
Limit
Compare
Software
Shutdown Enable
H/W Thermal
Shutdown Sensor
3.3V
Temperature
Conversion
SW_SHDN
3.3V
SYS_SHDN
HW_SHDN
ALERT
Function
Select
Figure 5.2 Block Diagram of Hardware Thermal Shutdown
5.4
Hardware Thermal Shutdown Limit
The Hardware Thermal Shutdown Limit temperature is determined by pull-up resistors on the
SYS_SHDN and ALERT pins shown in Table 5.2.
Table 5.2 SYS_SHDN Threshold Temperature
SYS_SHD
PULL-UP
ALERT
PULL-UP
4.7K OHM
±10%
6.8K OHM
±10%
10K OHM
±10%
15K OHM
±10%
22K OHM
±10%
33K OHM
±10%
4.7K OHM ±10%
77°C
83°C
89°C
95°C
101°C
107°C
6.8K OHM ±10%
78°C
84°C
90°C
96°C
102°C
108°C
10K OHM ±10%
79°C
85°C
91°C
97°C
103°C
109°C
15K OHM ±10%
80°C
86°C
92°C
98°C
104°C
110°C
22K OHM ±10%
81°C
87°C
93°C
99°C
105°C
111°C
33K OHM ±10%
82°C
88°C
94°C
100°C
106°C
112°C
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
5.5
ALERT Output
The ALERT pin is an open drain output and requires a pull-up resistor to VDD and has two modes of
operation: interrupt mode and comparator mode. The mode of the ALERT output is selected via the
ALERT / COMP bit in the Configuration Register (see Section 6.3).
5.5.1
ALERT Pin Interrupt Mode
When configured to operate in interrupt mode, the ALERT pin asserts low when an out of limit
measurement (> high limit or < low limit) is detected on any diode or when a diode fault is detected,
functioning as any standard ALERT in on the SMBus. The ALERT pin will remain asserted as long
as an out-of-limit condition remains. Once the out-of-limit condition has been removed, the ALERT pin
will remain asserted until the appropriate status bits are cleared.
The ALERT pin can be masked by setting the MASK_ALL bit. Once the ALERT pin has been masked,
it will be de-asserted and remain de-asserted until the MASK_ALL bit is cleared by the user. Any
interrupt conditions that occur while the ALERT pin is masked will update the Status Register normally.
There are also individual channel masks (see Section 6.10).
The ALERT pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave
to communicate an error condition to the master. One or more ALERT outputs can be hard-wired
together.
5.5.2
ALERT Pin Comparator Mode
When the ALERT pin is configured to operate in comparator mode, it will be asserted if any of the
measured temperatures exceeds the respective high limit. The ALERT pin will remain asserted until
all temperatures drop below the corresponding high limit minus the Therm Hysteresis value.
When the ALERT pin is asserted in comparator mode, the corresponding high limit status bits will be
set. Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is
deasserted, the status bits will be automatically cleared.
The MASK_ALL bit will not block the ALERT pin in this mode; however, the individual channel masks
(see Section 6.10) will prevent the respective channel from asserting the ALERT pin.
5.6
ALERT and SYS_SHDN Pin Considerations
Because of the decode method used to determine the Hardware Thermal Shutdown Limit, it is
important that the pull-up resistance on both the ALERT and SYS_SHDN pins be within the tolerances
shown in Table 5.2. Additionally, the pull-up resistor on the ALERT and SYS_SHDN pins must be
connected to the same 3.3V supply that drives the VDD pin.
For 15ms after power up, the ALERT and SYS_SHDN pins must not be pulled low or the Hardware
Thermal Shutdown Limit will not be decoded properly. If the system requirements do not permit these
conditions, the ALERT and SYS_SHDN pins must be isolated from their respective busses during this
time.
One method of isolating the ALERT pin is shown in Figure 5.3.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
+ 3 .3 V
VDD
1
DP
2
DN
SYS_SHDN
8
4 .7 K 33K
SM CLK
7
SM DATA
3
6
ALER T
4
5
GND
EM C1186
+ 2 .5 - 5 V
22K
S h a re d A le rt
+ 3 .3 V
4 .7 K 33K
+ 2 .5 - 5 V
22K
S h a re d S Y S _ S H D N
Figure 5.3 Isolating ALERT and SYS_SHDN Pin
5.7
Temperature Measurement
The EMC1186 can monitor the temperature of one externally connected diodes.
The device contains programmable High, Low, and Therm limits for all measured temperature
channels. If the measured temperature goes below the Low limit or above the High limit, the ALERT
pin can be asserted (based on user settings).
5.7.1
Beta Compensation
The EMC1186 is configured to monitor the temperature of basic diodes (e.g., 2N3904) or CPU thermal
diodes. For External Diode 1, it automatically detects the type of external diode (CPU diode or diode
connected transistor) and determines the optimal setting to reduce temperature errors introduced by
beta variation. Compensating for this error is also known as implementing the transistor or BJT model
for temperature measurement.
For discrete transistors configured with the collector and base shorted together, the beta is generally
sufficiently high such that the percent change in beta variation is very small. For example, a 10%
variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute
approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction
is used for temperature measurement and the collector is tied to the substrate, the proportional beta
variation will cause large error. For example, a 10% variation in beta for two forced emitter currents
with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C.
5.7.2
Resistance Error Correction (REC)
Parasitic resistance in series with the external diodes will limit the accuracy obtainable from
temperature measurement devices. The voltage developed across this resistance by the switching
diode currents cause the temperature measurement to read higher than the true temperature.
Contributors to series resistance are PCB trace resistance, on die (i.e. on the processor) metal
resistance, bulk resistance in the base and emitter of the temperature transistor. Typically, the error
caused by series resistance is +0.7°C per ohm. The EMC1186 automatically corrects up to 100 ohms
of series resistance.
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Datasheet
5.7.3
Programmable External Diode Ideality Factor
The EMC1186 is designed for external diodes with an ideality factor of 1.008. Not all external diodes,
processor or discrete, will have this exact value. This variation of the ideality factor introduces error in
the temperature measurement which must be corrected for. This correction is typically done using
programmable offset registers. Since an ideality factor mismatch introduces an error that is a function
of temperature, this correction is only accurate within a small range of temperatures. To provide
maximum flexibility to the user, the EMC1186 provides a 6-bit register for each external diode where
the ideality factor of the diode used is programmed to eliminate errors across all temperatures.
APPLICATION NOTE: When monitoring a substrate transistor or CPU diode and beta compensation is enabled, the
Ideality Factor should not be adjusted. Beta Compensation automatically corrects for most
ideality errors.
5.8
Diode Faults
The EMC1186 detects an open on the DP and DN pins, and a short across the DP and DN pins. For
each temperature measurement made, the device checks for a diode fault on the external diode
channel(s). When a diode fault is detected, the ALERT pin asserts (unless masked, see Section 5.9)
and the temperature data reads 00h in the MSB and LSB registers (note: the low limit will not be
checked). A diode fault is defined as one of the following: an open between DP and DN, a short from
VDD to DP, or a short from VDD to DN.
If a short occurs across DP and DN or a short occurs from DP to GND, the low limit status bit is set
and the ALERT pin asserts (unless masked). This condition is indistinguishable from a temperature
measurement of 0.000°C (-64°C in extended range) resulting in temperature data of 00h in the MSB
and LSB registers.
If a short from DN to GND occurs (with a diode connected), temperature measurements will continue
as normal with no alerts.
5.9
Consecutive Alerts
The EMC1186 contain multiple consecutive alert counters. One set of counters applies to the ALERT
pin and the second set of counters applies to the SYS_SHDN pin. Each temperature measurement
channel has a separate consecutive alert counter for each of the ALERT and SYS_SHDN pins. All
counters are user programmable and determine the number of consecutive measurements that a
temperature channel(s) must be out-of-limit or reporting a diode fault before the corresponding pin is
asserted.
See Section 6.11, "Consecutive ALERT Register 22h" for more details on the consecutive alert
function.
5.10
Digital Filter
To reduce the effect of noise and temperature spikes on the reported temperature, the External Diode
1 channel uses a programmable digital filter. This filter can be configured as Level 1, Level 2, or
Disabled (default) (see Section 6.13). The typical filter performance is shown in Figure 5.4 and
Figure 5.5.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Filter Step Response
Temperature (C)
90
Disabled
80
70
Level1
Level2
60
50
40
30
20
10
0
0
2
4
6
8
10
12
14
Samples
Figure 5.4 Temperature Filter Step Response
Filter Impulse Response
90
Temperature (C)
80
Disabled
70
60
50
Level1
40
Level2
30
20
10
0
0
2
4
6
8
10
12
14
Samples
Figure 5.5 Temperature Filter Impulse Response
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
5.11
Temperature Measurement Results and Data
The temperature measurement results are stored in the internal and external temperature registers.
These are then compared with the values stored in the high and low limit registers. Both external and
internal temperature measurements are stored in 11-bit format with the eight (8) most significant bits
stored in a high byte register and the three (3) least significant bits stored in the three (3) MSB
positions of the low byte register. All other bits of the low byte register are set to zero.
The EMC1186 has two selectable temperature ranges. The default range is from 0°C to +127°C and
the temperature is represented as binary number able to report a temperature from 0°C to +127.875°C
in 0.125°C steps.
The extended range is an extended temperature range from -64°C to +191°C. The data format is a
binary number offset by 64°C. The extended range is used to measure temperature diodes with a large
known offset (such as AMD processor diodes) where the diode temperature plus the offset would be
equivalent to a temperature higher than +127°C.
Table 5.3 shows the default and extended range formats.
Table 5.3 Temperature Data Format
TEMPERATURE (°C)
DEFAULT RANGE 0°C TO 127°C
EXTENDED RANGE -64°C TO 191°C
Diode Fault
000 0000 0000
000 0000 0000
-64
000 0000 0000
000 0000 0000
-1
000 0000 0000
001 1111 1000
0
000 0000 0000
010 0000 0000
0.125
000 0000 0001
010 0000 0001
1
000 0000 1000
010 0000 1000
64
010 0000 0000
100 0000 0000
65
010 0000 1000
100 0000 1000
127
011 1111 1000
101 1111 1000
127.875
011 1111 1111
101 1111 1111
128
011 1111 1111
110 0000 0000
190
011 1111 1111
111 1111 0000
191
011 1111 1111
111 1111 1000
>= 191.875
011 1111 1111
111 1111 1111
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 6 Register Description
The registers shown in Table 6.1 are accessible through the SMBus. An entry of ‘-’ indicates that the
bit is not used and will always read ‘0’.
Table 6.1 Register Set in Hexadecimal Order
REGISTER
ADDRESS
R/W
REGISTER NAME
FUNCTION
DEFAULT
VALUE
00h
R
Internal Diode Data
High Byte
Stores the integer data for the
Internal Diode
00h
01h
R
External Diode 1
Data High Byte
Stores the integer data for External
Diode 1
00h
03h
R/W
Configuration
Controls the general operation of
the device (mirrored at address
09h)
00h
Page 28
04h
R/W
Conversion Rate
Controls the conversion rate for
updating temperature data
(mirrored at address 0Ah)
06h
(4/sec)
Page 29
05h
R/W
Internal Diode High
Limit
Stores the 8-bit high limit for the
Internal Diode (mirrored at address
0Bh)
55h
(85°C)
06h
R/W
Internal Diode Low
Limit
Stores the 8-bit low limit for the
Internal Diode (mirrored at address
0Ch)
00h
(0°C)
07h
R/W
External Diode 1
High Limit High Byte
Stores the integer portion of the
high limit for External Diode 1
(mirrored at register 0Dh)
55h
(85°C)
08h
R/W
External Diode 1 Low
Limit High Byte
Stores the integer portion of the
low limit for External Diode 1
(mirrored at register 0Eh)
00h
(0°C)
09h
R/W
Configuration
Controls the general operation of
the device (mirrored at address
03h)
0Ah
R/W
Conversion Rate
Controls the conversion rate for
updating temperature data
(mirrored at address 04h)
PAGE
Page 27
Page 29
SMSC EMC1186
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DATASHEET
00h
06h
(4/sec)
Page 28
Page 29
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table 6.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS
R/W
REGISTER NAME
FUNCTION
DEFAULT
VALUE
0Bh
R/W
Internal Diode High
Limit
Stores the 8-bit high limit for the
Internal Diode (mirrored at address
05h)
55h
(85°C)
0Ch
R/W
Internal Diode Low
Limit
Stores the 8-bit low limit for the
Internal Diode (mirrored at address
06h)
00h
(0°C)
55h
(85°C)
PAGE
Page 29
0Dh
R/W
External Diode 1
High Limit High Byte
Stores the integer portion of the
high limit for External Diode 1
(mirrored at register 07h)
0Eh
R/W
External Diode 1 Low
Limit High Byte
Stores the integer portion of the
low limit for External Diode 1
(mirrored at register 08h)
00h
(0°C)
10h
R
External Diode 1
Data Low Byte
Stores the fractional data for
External Diode 1
00h
Page 27
11h
R/W
Scratchpad
Scratchpad register for software
compatibility
00h
Page 30
12h
R/W
Scratchpad
Scratchpad register for software
compatibility
00h
Page 30
13h
R/W
External Diode 1
High Limit Low Byte
Stores the fractional portion of the
high limit for External Diode 1
00h
14h
R/W
External Diode 1 Low
Limit Low Byte
Stores the fractional portion of the
low limit for External Diode 1
00h
19h
R/W
External Diode 1
Therm Limit
Stores the 8-bit critical temperature
limit for External Diode 1
55h
(85°C)
Page 31
1Dh
R/W
SYS_SHDN
Configuration
Controls which software channels,
if any, are linked to the
SYS_SHDN pin
00h
Page 31
1Eh
R
Hardware Thermal
Shutdown Limit
When read, returns the selected
Hardware Thermal Shutdown Limit
N/A
Page 32
1Fh
R/W
Channel Mask
Register
Controls the masking of individual
channels
00h
Page 32
20h
R/W
Internal Diode Therm
Limit
Stores the 8-bit critical temperature
limit for the Internal Diode
55h
(85°C
21h
R/W
Therm Hysteresis
Stores the 8-bit hysteresis value
that applies to all Therm limits
0Ah
(10°C)
22h
R/W
Consecutive ALERT
Controls the number of out-of-limit
conditions that must occur before
an interrupt is asserted
70h
Page 33
27h
R/W
External Diode 1
Ideality Factor
Stores the ideality factor for
External Diode 1
12h
(1.008)
Page 34
Page 29
Page 31
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Datasheet
Table 6.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS
R/W
REGISTER NAME
FUNCTION
DEFAULT
VALUE
PAGE
29h
R
Internal Diode Data
Low Byte
Stores the fractional data for the
Internal Diode
00h
Page 27
40h
R/W
Filter Control
Controls the digital filter setting for
the External Diode 1 channel
00h
Page 36
FDh
R
Product ID
Stores a fixed value that identifies
the device
22h
Page 37
FEh
R
Manufacturer ID
Stores a fixed value that
represents SMSC
5Dh
Page 37
FFh
R
Revision
Stores a fixed value that
represents the revision number
07h
Page 37
6.1
Data Read Interlock
When any temperature channel high byte register is read, the corresponding low byte is copied into
an internal ‘shadow’ register. The user is free to read the low byte at any time and be guaranteed that
it will correspond to the previously read high byte. Regardless if the low byte is read or not, reading
from the same high byte register again will automatically refresh this stored low byte data.
6.2
Temperature Data Registers
Table 6.2 Temperature Data Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
00h
R
Internal Diode
High Byte
128
64
32
16
8
4
2
1
00h
29h
R
Internal Diode
Low Byte
0.5
0.25
0.125
-
-
-
-
-
00h
01h
R
External Diode
1 High Byte
128
64
32
16
8
4
2
1
00h
10h
R
External Diode
1 Low Byte
0.5
0.25
0.125
-
-
-
-
-
00h
As shown in Table 6.2, all temperatures are stored as an 11-bit value with the high byte representing
the integer value and the low byte representing the fractional value left justified to occupy the MSBits.
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Bit 0 - HWSD - This bit is set when the External Diode 1 Temperature exceeds the Hardware Thermal
Shutdown Limit set by the pull-up resistors on the ALERT and SYS_SHDN pins. When set, this bit will
assert the SYS_SHDN pin.
6.3
Configuration Register 03h / 09h
Table 6.3 Configuration Register
ADDR
R/W
REGISTER
B7
B6
R/W
Configuration
MASK_
ALL
RUN/
STOP
03h
09h
B5
B4
B3
B2
B1
ALERT/
COMP
RECD1
-
RANGE
DAVG_
DIS
B0
DEFAULT
00h
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.

‘0’ - (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the
ALERT pin will be asserted.

‘1’ - The ALERT pin is masked. It will not be asserted for any interrupt condition unless it is
configured in comparator mode. The Status Registers will be updated normally.
Bit 6 - RUN / STOP - Controls Active/Standby modes.

‘0’ (default) - The device is in Active mode and converting on all channels.

‘1’ - The device is in Standby mode and not converting.
Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.

‘0’ (default) - The ALERT acts as an Alert pin and has interrupt behavior as described in
Section 5.5.1.

‘1’ - The ALERT acts as a THERM pin and has comparator behavior as described in Section 5.5.2.
In this mode the MASK_ALL bit is ignored.
Bit 4 - RECD1 - Disables the Resistance Error Correction (REC) for External Diode 1.

‘0’ (default) - REC is enabled for External Diode 1.

‘1’ - REC is disabled for External Diode 1.
Bit 2 - RANGE - Configures the measurement range and data format of the temperature channels.

‘0’ (default) - The temperature measurement range is 0°C to +127.875°C and the data format is
binary.

‘1’ -The temperature measurement range is -64°C to +191.875°C and the data format is offset
binary (see Table 5.3).
Bit 1 - DAVG_DIS - Disables the dynamic averaging feature on all temperature channels.

‘0’ (default) - The dynamic averaging feature is enabled. All temperature channels will be converted
with an averaging factor that is based on the conversion rate as shown in Table 6.5.

‘1’ - The dynamic averaging feature is disabled. All temperature channels will be converted with a
maximum averaging factor of 1x (equivalent to 11-bit conversion). For higher conversion rates, this
averaging factor will be reduced as shown in Table 6.5.
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6.4
Conversion Rate Register 04h / 0Ah
Table 6.4 Conversion Rate Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
R/W
Conversion
Rate
-
-
-
-
04h
0Ah
B3
B2
B1
B0
DEFAULT
06h
(4/sec)
CONV[3:0]
The Conversion Rate Register controls how often the temperature measurement channels are updated
and compared against the limits. This register is fully accessible at either address.
Bits 3-0 - CONV[3:0] - Determines the conversion rate as shown in Table 6.5.
Table 6.5 Conversion Rate
CONV[3:0]
HEX
3
2
1
0
CONVERSIONS / SECOND
0h
0
0
0
0
1
1h
0
0
0
1
1
2h
0
0
1
0
1
3h
0
0
1
1
1
4h
0
1
0
0
1
5h
0
1
0
1
2
6h
0
1
1
0
4 (default)
7h
0
1
1
1
8
8h
1
0
0
0
16
9h
1
0
0
1
32
Ah
1
0
1
0
64
Bh - Fh
6.5
All others
1
Limit Registers
Table 6.6 Temperature Limit Registers
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
R/W
Internal Diode
High Limit
128
64
32
16
8
4
2
1
55h
(85°C)
05h
0Bh
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Datasheet
Table 6.6 Temperature Limit Registers (continued)
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
R/W
Internal Diode
Low Limit
128
64
32
16
8
4
2
1
00h
(0°C)
R/W
External
Diode 1 High
Limit High
Byte
128
64
32
16
8
4
2
1
55h
(85°C)
R/W
External
Diode 1 High
Limit Low
Byte
0.5
0.25
0.125
-
-
-
-
-
00h
R/W
External
Diode 1 Low
Limit High
Byte
128
64
32
16
8
4
2
1
00h
(0°C)
R/W
External
Diode 1 Low
Limit Low
Byte
0.5
0.25
0.125
-
-
-
-
-
00h
06h
0Ch
07h
0Dh
13h
08h
0Eh
14h
The device contains both high and low limits for all temperature channels. If the measured temperature
exceeds the high limit, then the corresponding status bit is set and the ALERT pin is asserted.
Likewise, if the measured temperature is less than or equal to the low limit, the corresponding status
bit is set and the ALERT pin is asserted.
The data format for the limits must match the selected data format for the temperature so that if the
extended temperature range is used, the limits must be programmed in the extended data format.
The limit registers with multiple addresses are fully accessible at either address.
6.6
Scratchpad Registers 11h and 12h
Table 6.7 Scratchpad Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
11h
R/W
Scratchpad
7
6
5
4
3
2
1
0
00h
12h
R/W
Scratchpad
7
6
5
4
3
2
1
0
00h
The Scratchpad Registers are Read / Write registers that are used for place holders to be software
compatible with legacy programs. Reading from the registers will return what is written to them.
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6.7
Therm Limit Registers
Table 6.8 Therm Limit Registers
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
19h
R/W
External
Diode 1
Therm Limit
128
64
32
16
8
4
2
1
55h
(85°C)
20h
R/W
Internal Diode
Therm Limit
128
64
32
16
8
4
2
1
55h
(85°C)
21h
R/W
Therm
Hysteresis
128
64
32
16
8
4
2
1
0Ah
(10°C)
The Therm Limit Registers are used to determine whether a critical thermal event has occurred. If the
measured temperature exceeds the Therm Limit, the SYS_SHDN pin will be asserted (if the
corresponding measurement channel is linked to the SYS_SHDN pin - see Section 6.8, "Software
Thermal Shutdown Configuration Register 1Dh"). The limit setting must match the chosen data format
of the temperature reading registers.
6.8
Software Thermal Shutdown Configuration Register 1Dh
Table 6.9 Software Thermal Shutdown Configuration Register
ADDR.
1Dh
R/W
REGISTER
B7
B6
B5
B4
R/W
Software
Thermal
Shutdown
Configuration
-
-
-
-
B3
B2
-
-
B1
B0
DEFAULT
EXTSYS
INTSYS
00h
The Software Thermal Shutdown Configuration Register controls whether any of the software channels
will assert the SYS_SHDN pin. If a channel is enabled, the temperature is compared against the
corresponding Therm Limit. If the measured temperature exceeds the Therm Limit, the SYS_SHDN
pin is asserted. This functionality is in addition to the Hardware Shutdown circuitry.
Bit 1 - EXT1SYS - configures the External Diode 1 channel to assert the SYS_SHDN pin based on its
Therm Limit.

‘0’ (default) - The External Diode 1 channel is not linked to the SYS_SHDN pin. If the temperature
exceeds the Therm Limit, the E1THERM status bit is set but the SYS_SHDN pin is not asserted.

‘1’ - The External Diode 1 channel is linked to the SYS_SHDN pin. If the temperature exceeds its
Therm Limit, the E1THERM status bit is set and the SYS_SHDN pin is asserted. It will remain
asserted until the temperature drops below its Therm Limit minus the Therm Hysteresis.
Bit 0 - INTSYS - Configures the Internal Diode channel to assert the SYS_SHDN pin based on its
Therm Limit.

‘0’ (default) - The Internal Diode channel is not linked to the SYS_SHDN pin. If the temperature
exceeds its Therm Limit, the ITHERM status bit is set but the SYS_SHDN pin is not asserted.

‘1’ - The Internal Diode channel is linked to the SYS_SHDN pin. If the temperature exceeds its
Therm Limit, the ITHERM status bit is set and the SYS_SHDN pin is asserted. It will remain
asserted until the temperature drops below its Therm Limit minus the Therm Hysteresis.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
6.9
Hardware Thermal Shutdown Limit Register 1Eh
Table 6.10 Hardware Thermal Shutdown Limit Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
1Eh
R
Hardware
Thermal
Shutdown Limit
128
64
32
16
8
4
2
1
N/A
This read only register returns the Hardware Thermal Shutdown Limit selected by the value of the pullup resistors on the ALERT and SYS_SHDN pins. The data represents the hardware set temperature
in °C using the active temperature setting set by the RANGE bit in the Configuration Register. See
Table 5.3, "Temperature Data Format" for the data format.
When the External Diode 1 Temperature exceeds this limit, the SYS_SHDN pin is asserted and will
remain asserted until the External Diode 1 Temperature drops below this limit minus 10°C.
6.10
Channel Mask Register 1Fh
Table 6.11 Channel Mask Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
1Fh
R/W
Channel
Mask
-
-
-
-
-
-
EXT
MASK
INT
MASK
00h
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads a diode fault or out of limit error. The
channel mask does not mask the SYS_SHDN pin.
Bit 1 - EXTMASK - Masks the ALERT pin from asserting when the External Diode channel is out of
limit or reports a diode fault.

‘0’ (default) - The External Diode channel will cause the ALERT pin to be asserted if it is out of
limit or reports a diode fault.

‘1’ - The External Diode channel will not cause the ALERT pin to be asserted if it is out of limit or
reports a diode fault.
Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out
of limit.

‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out of limit.

‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out of limit.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
6.11
Consecutive ALERT Register 22h
Table 6.12 Consecutive ALERT Register
ADDR.
R/W
REGISTER
B7
22h
R/W
Consecutive
ALERT
TIME
OUT
B6
B5
B4
CTHRM[2:0]
B3
B2
B1
CALRT[2:0]
B0
DEFAULT
-
70h
The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must
be detected in consecutive measurements before the ALERT or SYS_SHDN pin is asserted.
Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality.
An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in
consecutive measurements will increment the consecutive alert counter. The counters will also be reset
if no out-of-limit condition or diode fault condition occurs in a consecutive reading.
When the ALERT pin is configured as an interrupt, when the consecutive alert counter reaches its
programmed value, the following will occur: the STATUS bit(s) for that channel and the last error
condition(s) (i.e. EHIGH,) will be set to ‘1’, the ALERT pin will be asserted, the consecutive alert
counter will be cleared, and measurements will continue.
When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore diode
fault and low limit errors and only increment if the measured temperature exceeds the High Limit.
Additionally, once the consecutive alert counter reaches the programmed limit, the ALERT pin will be
asserted, but the counter will not be reset. It will remain set until the temperature drops below the High
Limit minus the Therm Hysteresis value.
For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1186 device, the high
limits are set at 70°C, and none of the channels are masked, the ALERT pin will be asserted after the
following four measurements:
1. Internal Diode reads 71°C and the external diode reads 69°C. Consecutive alert counter for INT is
incremented to 1.
2. Both the Internal Diode and the External Diode read 71°C. Consecutive alert counter for INT is
incremented to 2 and for EXT1 is set to 1.
3. The External Diode reads 71°C and the Internal Diode reads 69°C. Consecutive alert counters
for INT is cleared and EXT is incremented to 2.
4. The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for
INT is set to 1, and EXT1 is incremented to 3.
5. The Internal Diode reads 71°C and the external diodes read 71°C. Consecutive alert counter for
INT is incremented to 2, and EXT1 is incremented to 4. The appropriate status bits are set for
EXT1 and the ALERT pin is asserted. EXT1 counter is reset to 0 and all other counters hold the
last value until the next temperature measurement.
Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.

‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely
without the device resetting its SMBus protocol.

‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than tTIMEOUT,
the device will reset the SMBus protocol.
Bits 6-4 CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the
corresponding Therm Limit and Hardware Thermal Shutdown Limit before the SYS_SHDN pin is
asserted. All temperature channels use this value to set the respective counters. The consecutive
THERM counter is incremented whenever any of the measurements exceed the corresponding Therm
Limit or if the External Diode 1 measurement exceeds the Hardware Thermal Shutdown Limit.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
If the temperature drops below the Therm Limit or Hardware Thermal Shutdown Limit, the counter is
reset. If the programmed number of consecutive measurements exceed the Therm Limit or Hardware
Thermal Shutdown Limit, and the appropriate channel is linked to the SYS_SHDN pin, the SYS_SHDN
pin will be asserted low.
Once the SYS_SHDN pin is asserted, the consecutive Therm counter will not reset until the
corresponding temperature drops below the appropriate limit minus the corresponding hysteresis.
The bits are decoded as shown in Table 6.13. The default setting is 4 consecutive out of limit
conversions.
Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of
limit condition or diode fault before the ALERT pin is asserted. All temperature channels use this value
to set the respective counters. The bits are decoded as shown in Table 6.13. The default setting is 1
consecutive out of limit conversion.
Table 6.13 Consecutive Alert / Therm Settings
6.12
NUMBER OF CONSECUTIVE OUT OF LIMIT
MEASUREMENTS
2
1
0
0
0
0
1
(default for CALRT[2:0])
0
0
1
2
0
1
1
3
1
1
1
4
(default for CTHRM[2:0])
External Diode Ideality Factor Registers 27h to 31h
Table 6.14 Ideality Configuration Registers
ADDR.
R/W
REGISTER
B7
B6
27h
R/W
External
Diode 1
Ideality
Factor
-
-
B5
B4
B3
B2
IDEALITY1[5:0]
B1
B0
DEFAULT
12h
These registers store the ideality factors that are applied to the external diodes. Table 6.15 defines
each setting and the corresponding ideality factor. Beta Compensation and Resistance Error Correction
automatically correct for most diode ideality errors; therefore, it is not recommended that these settings
be updated without consulting SMSC.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table 6.15 Ideality Factor Look-Up Table (Diode Model)
SETTING
FACTOR
SETTING
FACTOR
SETTING
FACTOR
08h
0.9949
18h
1.0159
28h
1.0371
09h
0.9962
19h
1.0172
29h
1.0384
0Ah
0.9975
1Ah
1.0185
2Ah
1.0397
0Bh
0.9988
1Bh
1.0200
2Bh
1.0410
0Ch
1.0001
1Ch
1.0212
2Ch
1.0423
0Dh
1.0014
1Dh
1.0226
2Dh
1.0436
0Eh
1.0027
1Eh
1.0239
2Eh
1.0449
0Fh
1.0040
1Fh
1.0253
2Fh
1.0462
10h
1.0053
20h
1.0267
30h
1.0475
11h
1.0066
21h
1.0280
31h
1.0488
12h
1.0080
22h
1.0293
32h
1.0501
13h
1.0093
23h
1.0306
33h
1.0514
14h
1.0106
24h
1.0319
34h
1.0527
15h
1.0119
25h
1.0332
35h
1.0540
16h
1.0133
26h
1.0345
36h
1.0553
17h
1.0146
27h
1.0358
37h
1.0566
For CPU substrate transistors that require the BJT transistor model, the ideality factor behaves slightly
differently than for discrete diode-connected transistors. Refer to Table 6.16 when using a CPU
substrate transistor.
Table 6.16 Substrate Diode Ideality Factor Look-Up Table (BJT Model)
SETTING
FACTOR
SETTING
FACTOR
SETTING
FACTOR
08h
0.9869
18h
1.0079
28h
1.0291
09h
0.9882
19h
1.0092
29h
1.0304
0Ah
0.9895
1Ah
1.0105
2Ah
1.0317
0Bh
0.9908
1Bh
1.0120
2Bh
1.0330
0Ch
0.9921
1Ch
1.0132
2Ch
1.0343
0Dh
0.9934
1Dh
1.0146
2Dh
1.0356
0Eh
0.9947
1Eh
1.0159
2Eh
1.0369
0Fh
0.9960
1Fh
1.0173
2Fh
1.0382
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table 6.16 Substrate Diode Ideality Factor Look-Up Table (BJT Model) (continued)
SETTING
FACTOR
SETTING
FACTOR
SETTING
FACTOR
10h
0.9973
20h
1.0187
30h
1.0395
11h
0.9986
21h
1.0200
31h
1.0408
12h
1.0000
22h
1.0213
32h
1.0421
13h
1.0013
23h
1.0226
33h
1.0434
14h
1.0026
24h
1.0239
34h
1.0447
15h
1.0039
25h
1.0252
35h
1.0460
16h
1.0053
26h
1.0265
36h
1.0473
17h
1.0066
27h
1.0278
37h
1.0486
APPLICATION NOTE: When measuring a 65nm Intel CPU, the Ideality Setting should be the default 12h. When
measuring a 45nm Intel CPU, the Ideality Setting should be 15h.
Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel exceeds its programmed high limit.
Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.
Bit 1 - ELOW - This bit is set when the External Diode channel drops below its programmed low limit.
Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.
Bit 1 - ETHERM - This bit is set when the External Diode channel exceeds its programmed Therm
Limit. When set, this bit will assert the THERM pin.
Bit 0- ITHERM - This bit is set when the Internal Diode channel exceeds its programmed Therm Limit.
When set, this bit will assert the THERM pin.
6.13
Filter Control Register 40h
Table 6.17 Filter Configuration Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
40h
R/W
Filter Control
-
-
-
-
-
-
B1
B0
DEFAULT
FILTER[1:0]
00h
The Filter Configuration Register controls the digital filter on the External Diode 1 channel.
Bits 1-0 - FILTER[1:0] - Control the level of digital filtering that is applied to the External Diode 1
temperature measurement as shown in Table 6.18. See Figure 5.4 and Figure 5.5 for examples on the
filter behavior.
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Table 6.18 FILTER Decode
FILTER[1:0]
6.14
1
0
AVERAGING
0
0
Disabled (default)
0
1
Level 1
1
0
Level 1
1
1
Level 2
Product ID Register
Table 6.19 Product ID Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FDh
R
Product ID
0
0
1
0
0
0
1
0
22h
The Product ID Register holds a unique value that identifies the device.
6.15
SMSC ID Register
Table 6.20 Manufacturer ID Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FEh
R
SMSC ID
0
1
0
1
1
1
0
1
5Dh
The Manufacturer ID register contains an 8-bit word that identifies the SMSC as the manufacturer of
the EMC1186.
6.16
Revision Register
Table 6.21 Revision Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FFh
R
Revision
0
0
0
0
0
1
1
1
07h
The Revision register contains an 8-bit word that identifies the die revision.
SMSC EMC1186
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 7 Typical Operating Curves
Tem perature Error vs. Am bient Tem perature
(2N3904, TDIODE = 42.5°C, VDD = 3.3V)
1.0
1.0
0.8
0.8
0.6
Temperature Error (°C)
Temperature Error (°C)
Tem perature Error vs. Filter Capacitor
(2N3904, TA = 27°C, TDIODE = 27°C, VDD = 3.3V)
0.5
0.3
0.0
-0.3
-0.5
-0.8
-1.0
0
1000
2000
3000
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
4000
-1.0
-40 -25 -10
Filter Capacitor (pF)
Temperature Error (°C)
Temperature Error (°C)
Revision 1.0 (07-11-13)
5
4
Beta Compensation
Disabled
3
2
1
0
Beta Compensation Enabled
-1
20
110 125
95 110 125
Temperature Error vs. CPU Temperature
Typical 65nm CPU from major vendor
(TA = 27°C, VDD = 3.3V, BETA = 011, CFILTER = 470pF)
Tem perature Error vs. External Diode Tem perature
(2N3904, TA = 42.5°C, VDD = 3.3V)
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -25 -10 5
20 35 50 65 80 95
External Diode Tem perature (°C)
5
20 35 50 65 80
Am bient Tem perature (°C)
40
60
80
100
120
CPU Temperature (°C)
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Tem perature Error vs. Am bient Tem perature
(2N3904, TDIODE = 27°C, VDD = 3.3V)
120
0.8
100
80
REC Disabled
0.6
60
0.4
40
0.2
20
REC Enabled
0.0
0
50
100
Series R (Ohm)
2.0
0
200
150
EXT2 - APD
1.5
Temperature Error (°C)
1.0
Temperature Error (°C)
REC Disabled
Temperature Error (°C)
REC Enabled
Temperature Error vs. Series Resistance
EXT3 - APD
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-40 -25 -10
5
20 35 50 65 80
Am bient Tem perature (°C)
95 110 125
S upply Curre nt vs. Conve rsion Ra te
1200
1100
1000
Supply Current (uA
900
800
Dy namic
A v eraging
Enabled
700
Dy namic
A v eraging
Dis abled
600
500
400
300
200
1
2
4
8
16
32
64
Conve rsion Ra te
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 8 Package Information
Figure 8.1 2mm x 3mm TDFN Package Drawing
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Figure 8.2 2mm x 3mm TDFN Package Dimensions
Figure 8.3 2mm x 3mm TDFN Package PCB Land Pattern
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
8.1
Package Markings
The EMC1186 devices will be marked as shown in Figure 8.4 and Figure 8.5.
TOP
LINE 1: Preface, First digit of Device Code
E 4
LINE 2: Second digit of Device Code, Revision
0 R
PIN 1
BOTTOM
BOTTOM MARKING IS NOT ALLOWED
Figure 8.4 EMC1186-1 8-Pin TDFN Package Markings
TOP
LINE 1: Preface, First digit of Device Code
E 4
LINE 2: Second digit of Device Code, Revision
1 R
PIN 1
BOTTOM
BOTTOM MARKING IS NOT ALLOWED
Figure 8.5 EMC1186-2 8-Pin TDFN Package Markings
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Dual Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications
Datasheet
Chapter 9 Datasheet Revision History
Table 9.1 Customer Revision History
REVISION LEVEL & DATE
Rev. 1.0 (07-11-13)
SMSC EMC1186
SECTION/FIGURE/ENTRY
CORRECTION
Formal document release
43
DATASHEET
Revision 1.0 (07-11-13)